Shift register, drive circuit, drive method, and display device

Abstract

The present disclosure provides a shift register, a driving circuit, a driving method and a display device, and relates to the technical field of display. The shift register comprises a first control circuit configured to control the potential of a first node under the control of a first clock signal from a first clock terminal; a gating circuit configured to control the potential of the first node under the control of a plurality of gate signals from a plurality of gate terminals; an input circuit configured to control the potential of a second node under the control of the potential of the first node and a second clock signal from a second clock terminal; a second control circuit configured to control the potential of a third node under the control of the potential of the second node; and an output circuit configured to output a scan signal under the control of the potentials of the second node and the third node.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a driving method, and a display device. Background Technology

[0002] To achieve a good balance between power consumption and high refresh rates, displays typically employ local high refresh rate (DRPR) technology. This technology requires the driver circuitry to have flexible activation capabilities. Common shift register driver circuits offer limited driving capabilities for displays and cannot adjust in real time according to the image, thus failing to meet the more flexible high refresh rate requirements of displays. Summary of the Invention

[0003] This disclosure provides a shift register, a driving circuit, a driving method, and a display device.

[0004] According to a first aspect, this disclosure provides a shift register, comprising: a first control circuit configured to control the potential of a first node under the control of a first clock signal from a first clock terminal; a gating circuit configured to control the potential of the first node under the control of a plurality of gating signals from a plurality of gating terminals; an input circuit configured to control the potential of a second node under the control of the potential of the first node and a second clock signal from a second clock terminal; a second control circuit configured to control the potential of a third node under the control of the potential of the second node; and an output circuit configured to output a scan signal under the control of the potentials of the second node and the third node.

[0005] According to an embodiment of the present disclosure, the gating circuit controls the potential of the first node under the control of multiple gating signals from multiple gating terminals. The gating circuit is configured to: control the potential of the first node to remain at a second level under the control of a first level of the multiple gating signals; and pull down the potential of the first node under the control of the second level of any one of the multiple gating signals.

[0006] According to embodiments of this disclosure, the gating circuit is further configured to: control the potential of the first node to remain at a second level under the control of a first level of the third node; and pull down the potential of the first node under the control of a second level of the third node.

[0007] According to an embodiment of this disclosure, a first control circuit controls the potential of a first node under the control of a first clock signal from a first clock terminal. The first control circuit is configured to: charge the first node with a first voltage of a first power supply under the control of a second level of the first clock signal, thereby controlling the potential of the first node to be at the second level; and maintain the potential of the first node at the second level when the first clock signal is at the first level.

[0008] According to embodiments of this disclosure, the shift register further includes: a pull-down circuit configured to: pull down the potential of the third node under the control of the potential of the first node and the second clock signal; and pull down the potential of the second node under the control of the second level of the third node.

[0009] According to embodiments of this disclosure, the shift register further includes: a reset circuit configured to reset the fourth node by a second voltage of a second power supply under the control of a first clock signal; and to reset the potential of the second node under the control of the potential of the first node and the potential of the fourth node.

[0010] According to embodiments of this disclosure, the shift register further includes a third control circuit electrically connected to the input circuit, the third control circuit being configured to control the voltage supplied to the input circuit under the control of a first voltage of a first power supply.

[0011] According to embodiments of the present disclosure, the output circuit includes a plurality of output terminals configured to output a plurality of scan signals for driving a plurality of sub-pixel units.

[0012] According to an embodiment of this disclosure, the gating circuit includes a tenth transistor, a twelfth transistor, and a plurality of gating transistors; wherein the control electrode of the tenth transistor and the control electrode of the twelfth transistor are electrically connected to a third node, the first electrode of the tenth transistor and the first electrode of the twelfth transistor are electrically connected to a first node, and the second electrode of the tenth transistor and the second electrode of the twelfth transistor are electrically connected to the first electrode of the plurality of gating transistors; the control electrodes of the plurality of gating transistors are respectively electrically connected to a plurality of gating terminals, and the second electrodes of the plurality of gating transistors are electrically connected to a first clock terminal.

[0013] According to an embodiment of this disclosure, the first control circuit includes a first transistor, an eleventh transistor, a thirteenth transistor, a first capacitor, and a second capacitor; wherein the control electrode of the first transistor is electrically connected to a first clock terminal, the first electrode of the first transistor is electrically connected to a first power supply, and the second electrode of the first transistor is electrically connected to the control electrode of the eleventh transistor; the first electrode of the eleventh transistor is electrically connected to the first power supply, and the second electrode of the eleventh transistor is electrically connected to a first node; the control electrode of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the first power supply, and the second electrode of the thirteenth transistor is electrically connected to a gating circuit; the first terminal of the first capacitor is electrically connected to the control electrode of the eleventh transistor, and the second terminal of the first capacitor is electrically connected to the first node; and the first terminal of the second capacitor is electrically connected to the first power supply, and the second terminal of the second capacitor is electrically connected to the first node.

[0014] According to embodiments of this disclosure, the second node includes a first sub-node and a second sub-node, and the second control circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor; wherein the control electrode and the first electrode of the fifteenth transistor are electrically connected to a third power supply, and the second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor; the control electrode of the sixteenth transistor is electrically connected to the third power supply, and the second electrode of the sixteenth transistor is electrically connected to the control electrode of the eighteenth transistor; the control electrode of the seventeenth transistor is electrically connected to the first sub-node, the first electrode of the seventeenth transistor is electrically connected to the control electrode of the eighteenth transistor, and the second electrode of the seventeenth transistor is electrically connected to a fourth power supply; the first electrode of the eighteenth transistor is electrically connected to the third power supply, and the second electrode of the eighteenth transistor is electrically connected to the third node; the control electrode of the nineteenth transistor is electrically connected to the second sub-node, the first electrode of the nineteenth transistor is electrically connected to the third node, and the second electrode of the nineteenth transistor is electrically connected to the second power supply.

[0015] According to embodiments of this disclosure, the second node includes a first sub-node and a second sub-node, and the second control circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor; wherein the control electrode and the first electrode of the fifteenth transistor are electrically connected to a first clock terminal, and the second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor; the control electrode of the sixteenth transistor is electrically connected to the first clock terminal, and the second electrode of the sixteenth transistor is electrically connected to the control electrode of the eighteenth transistor; the control electrode of the seventeenth transistor is electrically connected to the second sub-node, the first electrode of the seventeenth transistor is electrically connected to the control electrode of the eighteenth transistor, and the second electrode of the seventeenth transistor is electrically connected to the second electrode of the fifteenth transistor; the first electrode of the eighteenth transistor is electrically connected to the second electrode of the fifteenth transistor, and the second electrode of the eighteenth transistor is electrically connected to a first power supply; and the control electrode of the nineteenth transistor is electrically connected to the first sub-node, the first electrode of the nineteenth transistor is electrically connected to the second electrode of the seventeenth transistor, and the second electrode of the nineteenth transistor is electrically connected to a second power supply.

[0016] According to embodiments of this disclosure, the second node includes a first sub-node and a second sub-node, and the input circuit includes a fourteenth transistor, a twenty-second transistor, and a twenty-fifth transistor; wherein, the control electrode of the fourteenth transistor is electrically connected to a second clock terminal, the first electrode of the fourteenth transistor is electrically connected to a first power supply, and the second electrode of the fourteenth transistor is electrically connected to a fourth node; the control electrode of the twenty-second transistor is electrically connected to the first node, the first electrode of the twenty-second transistor is electrically connected to the fourth node, and the second electrode of the twenty-second transistor is electrically connected to the first sub-node; and the control electrode of the twenty-fifth transistor is electrically connected to the first node, the first electrode of the twenty-fifth transistor is electrically connected to the fourth node, and the second electrode of the twenty-fifth transistor is electrically connected to the second sub-node.

[0017] According to embodiments of this disclosure, the second node includes a first sub-node and a second sub-node, and the pull-down circuit includes a twentieth transistor, a twenty-first transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-sixth transistor, a twenty-seventh transistor, and a twenty-eighth transistor; wherein, the control electrode of the twentieth transistor is electrically connected to the first node, the first electrode of the twentieth transistor is electrically connected to the third node, and the second electrode of the twentieth transistor is electrically connected to the first electrode of the twenty-first transistor; the control electrode of the twenty-first transistor is electrically connected to a first clock terminal, and the second electrode of the twenty-first transistor is electrically connected to a second power supply; the control electrodes of the twenty-third transistor, the twenty-fourth transistor, the twenty-sixth transistor, and the twenty-seventh transistor are electrically connected to the third node; the twenty-third transistor and the twenty-fourth transistor are connected in series, the first electrode of the twenty-third transistor is electrically connected to the first sub-node, and the second electrode of the twenty-fourth transistor is electrically connected to the second power supply; the twenty-sixth transistor and the twenty-seventh transistor are connected in series, the first electrode of the twenty-sixth transistor is electrically connected to the second sub-node, and the second electrode of the twenty-seventh transistor is electrically connected to the second power supply; and the control electrode of the twenty-eighth transistor is electrically connected to the first sub-node, the first electrode of the twenty-eighth transistor is electrically connected to the second electrode of the twenty-third transistor and the second electrode of the twenty-sixth transistor, and the second electrode of the twenty-eighth transistor is electrically connected to the first power supply.

[0018] According to an embodiment of this disclosure, the reset circuit includes a 29th transistor and a 30th transistor; wherein the 29th transistor and the 30th transistor are connected in series, the control electrode of the 29th transistor and the 30th transistor are electrically connected to a first clock terminal, the first electrode of the 29th transistor is electrically connected to a fourth node, and the second electrode of the 30th transistor is electrically connected to a second power supply.

[0019] According to a second aspect, this disclosure provides a driving circuit including M driving unit groups, each driving unit group including a plurality of shift registers as provided in any embodiment of this disclosure; wherein the m-th driving unit group is electrically connected to a first gating terminal group, the (m+1)-th driving unit group is electrically connected to a second gating terminal group, the gating signal output by the first gating terminal group is opposite to the gating signal output by the second gating terminal group, 1≤m<M, and M is a positive integer.

[0020] According to embodiments of this disclosure, the number of first gating terminals included in the first gating terminal group is the same as the number of second gating terminals included in the second gating terminal group, and the number of first gating terminals is the same as the number of gating transistors included in the shift register.

[0021] According to embodiments of this disclosure, the multiple shift registers included in the m-th drive unit group are connected in the same way as the multiple gating terminals included in the first gating terminal group, and the multiple shift registers included in the (m+1)-th drive unit group are connected in the same way as the multiple second gating terminals included in the second gating terminal group.

[0022] According to a third aspect, this disclosure provides a display device, including a display panel; and a driving circuit as provided in the embodiments of this disclosure; wherein the display panel includes a plurality of sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

[0023] According to the fourth aspect, this disclosure provides a driving method applied to a shift register provided in the embodiments of this disclosure, comprising: in a gating phase, controlling multiple gating signals to be at a first level; and in a non-gating phase, controlling at least one of the multiple gating signals to be at a second level. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure;

[0025] Figure 2 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0026] Figure 3 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0027] Figure 4A This is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0028] Figure 4B This is a simulation diagram of the voltage in a shift register according to an embodiment of the present disclosure;

[0029] Figure 4C This is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0030] Figure 5 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0031] Figure 6 This is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0032] Figure 7 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0033] Figure 8A This is a schematic diagram of the drive circuit according to an embodiment of the present disclosure;

[0034] Figure 8B This is a signal timing diagram of the driving circuit according to an embodiment of the present disclosure;

[0035] Figure 9A This is a schematic diagram of the structure of a drive circuit according to another embodiment of the present disclosure;

[0036] Figure 9B This is a signal timing diagram of a drive circuit according to another embodiment of the present disclosure;

[0037] Figure 9C This is a timing diagram of the gating signal according to an embodiment of the present disclosure;

[0038] Figure 10 This is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure;

[0039] Figure 11 This is a flowchart of a driving method according to an embodiment of the present disclosure. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. In the following description, some specific embodiments are used for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0041] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0042] Furthermore, in the description of the embodiments disclosed herein, the terms "connected" or "connected to" can refer to two components being directly connected, or to two components being connected via one or more other components. Additionally, these two components can be connected or coupled via wired or wireless means.

[0043] The source and drain of the switching transistor used in this embodiment are symmetrical, so their source and drain can be interchanged. In this embodiment, according to its function, the control electrode can be called the control electrode, one of the source and drain is called the first electrode, and the other of the source and drain is called the second electrode.

[0044] It should be noted that in the description of the embodiments of this disclosure, the symbol SCOUT can represent either a scan signal or the output terminal of the scan signal. Similarly, the symbol GVDD can represent either a power supply or the voltage provided by the power supply, the symbol VGL can represent either a power supply or the voltage provided by the power supply, and the symbol VGH can represent either a power supply or the voltage provided by the power supply. For example, power supplies VGL and LVGL can provide low voltages, while power supplies VGH and GVDD can provide high levels. The following embodiments are the same, and similar parts will not be described again.

[0045] Figure 1 This is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure.

[0046] like Figure 1 As shown, the shift register 100 includes a first control circuit 110, a gating circuit 120, an input circuit 130, a second control circuit 140, and an output circuit 150.

[0047] In this embodiment of the disclosure, the first control circuit 110 is electrically connected to the first clock terminal CLK1, the gating circuit 120 is electrically connected to multiple gating terminals D0, D1, ..., Dn, the input circuit 130 is electrically connected to the second clock terminal CLK2, and the output circuit 150 is electrically connected to the output terminal SCOUT.

[0048] The first control circuit 110, the gating circuit 120, and the input circuit 130 are electrically connected to the first node P. The input circuit 130, the second control circuit 140, and the output circuit 150 are electrically connected to the second node QN. The second control circuit 140 and the output circuit are electrically connected to the third node QB.

[0049] In this embodiment, the first control circuit 110 is configured to control the potential of the first node P under the control of a first clock signal CLK1 from the first clock terminal CLK1. The gating circuit 120 is configured to control the potential of the first node P under the control of multiple gating signals D0, D1, ..., Dn from multiple gating terminals D0, D1, ..., Dn. The input circuit 130 is configured to control the potential of the second node QN under the control of the potential of the first node P and a second clock signal CLK2 from the second clock terminal CLK2. The second control circuit 140 is configured to control the potential of the third node QB under the control of the potential of the second node QN. The output circuit 150 is configured to output a scan signal SCOUT from the output terminal SCOUT under the control of the potentials of the second node QN and the third node QB.

[0050] In this embodiment, when all multiple selection signals D0-Dn are low and the first clock signal at the first clock terminal is low, the first node P is high, and the circuit is in the selection phase. When the second clock signal at the second clock terminal is high, the input circuit controls the second node QN to be high, while the second control circuit 140 controls the third node QB to be low, ensuring normal output from the output circuit.

[0051] When at least one of the multiple strobe signals is high, the potential of the first node P becomes low, and at this time the shift register 100 is in the non-strobe stage.

[0052] When the shift register is in the non-gated stage, the second control circuit 140 controls the second node QB to be low and the third node QB to be high, enabling the shift register 100 to output a low voltage during the non-gated stage. When the shift register is in the gated stage, the second control circuit 140 controls the second node to be low and the third node QB to be low, enabling the shift register output circuit 150 to output normally, achieving the reverse potential action of the second node QN and the third node QB.

[0053] In this embodiment, when all gating signals are low, the first node P remains high, causing the second node QN to be high, thus ensuring normal output from the output circuit 150, and the shift register 100 remains in the gating phase. When one of the gating signals is high, the potential of the first node P is pulled low, causing the second node QN to be low, the output of the output circuit 150 SCOUT stops outputting, and the shift register 100 enters the non-gating phase.

[0054] According to embodiments of this disclosure, the control of the first node by the strobe signal can directly determine whether the shift register is in the strobe stage, resulting in a simple structure. In a driving circuit including multiple shift registers, any shift register can be selected by the strobe signal, providing flexible activation capability.

[0055] In embodiments of this disclosure, the first level can be a low level, and the second level can be a high level. Under the control of the low levels of multiple gating signals, the gating circuit 120 controls the potential of the first node P to remain at a high level, and the shift register 100 is in the gating stage. When any of the multiple gating signals is at a high level, the gating circuit 120 controls the potential of the first node P to be pulled down from a high level to a low level, and the shift register 100 is in the non-gating stage.

[0056] In the embodiments of this disclosure, when the third node QB is low, the gating circuit 120 controls the potential of the first node P to remain high under the control of the low level of the third node QB. When the third node QB is high, the potential of the first node P is pulled down to low under the control of the high level of the third node QB.

[0057] Under the control of the low level of the third node QB, the gating circuit 120 is in the cutoff state, which can control the potential of the first node P to remain at a high level, thus avoiding leakage caused by the electrical connection between the first node P and the first clock terminal CLK1.

[0058] In embodiments of this disclosure, under the control of a high level of the first clock signal CLK1, the first control circuit 110 charges the first node P through the first voltage VGH of the first power supply VGH, causing the potential of the first node P to be high. When the first clock signal CLK1 is low, the first control circuit 110 maintains the potential of the first node P at a low level.

[0059] In this embodiment of the disclosure, the output circuit 150 may include a plurality of output terminals SCOUT1, SCOUT2, ..., SCOUTn, which are configured to output a plurality of scan signals SCOUT1, SCOUT2, ..., SCOUTn to drive multi-row sub-pixel units.

[0060] Figure 2 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0061] like Figure 2 As shown, the shift register 200 includes a first control circuit 210, a gating circuit 220, an input circuit 230, a second control circuit 240, an output circuit 250, a pull-down circuit 260, and a reset circuit 270.

[0062] In the embodiments disclosed herein, the first control circuit 210, the gating circuit 220, the input circuit 230, the second control circuit 240, and the output circuit 250 are similar in structure to the first control circuit 110, the gating circuit 120, the input circuit 130, the second control circuit 140, and the output circuit 150 described above, and will not be repeated for the sake of brevity.

[0063] In the embodiments of this disclosure, the pull-down circuit 260 is electrically connected to the second clock terminal CLK2, and the reset circuit 270 is electrically connected to the first clock terminal CLK1 and the second power supply LVGL.

[0064] In the embodiments of this disclosure, the first control circuit 210, the gating circuit 220, the input circuit 230, and the pull-down circuit 260 are electrically connected to the first node P; the input circuit 230, the second control circuit 240, the output circuit 250, and the pull-down circuit 260 are electrically connected to the second node QN; the second control circuit 240, the output circuit 250, and the pull-down circuit 260 are electrically connected to the third node QB; and the reset circuit 270 and the input circuit 230 are electrically connected to the fourth node Q.

[0065] It should be noted that this disclosure does not limit the number of output terminals.

[0066] In the embodiments of this disclosure, when the first node P is at a high level and the second clock signal CLK2 is at a high level, the pull-down circuit 260, under the control of the first node P and the second clock signal CLK2, controls the potential of the third node QB to be pulled down to a low level. Under the control of the low level of the third node QB, the potential of the second node QN is pulled down to a low level.

[0067] When the output circuit 250 is outputting normally, the pull-down circuit 260 controls the potential of the second node QB to be low, thereby preventing the second node QB from coupling to a high potential and causing noise in the scanning signal.

[0068] In the embodiments of this disclosure, under the control of the high level of the first clock signal, the reset circuit 270 resets the fourth node Q through the second voltage LVGL of the second power supply LVGL, controlling the fourth node Q to be at a low level. At this time, the first node P is at a high level. Under the control of the high level of the first node P and the low level of the fourth node, the reset circuit resets the potential of the second node QN, controlling the second node QN to be at a low level.

[0069] Under the control of the first clock signal CLK1, the reset circuit 270 resets the fourth node Q in the initial stage. At the same time, when the shift register is in the strobe stage, the reset circuit 270 can continuously reset the fourth node Q.

[0070] Figure 3 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0071] like Figure 3 As shown, the shift register 300 includes a first control circuit 310, a gating circuit 320, an input circuit 330, a second control circuit 340, an output circuit 350, a pull-down circuit 360, and a reset circuit 370.

[0072] In this embodiment, the first control circuit 310 includes a first transistor T1, an eleventh transistor T11, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2. The gating circuit 320 includes second to ninth transistors T2-T9, a tenth transistor T10, and a twelfth transistor T12 connected in parallel, wherein the second to ninth transistors T2-T9 can be gating transistors. The input circuit 330 includes a fourteenth transistor T14, a twenty-second transistor T22, and a twenty-fifth transistor T25. The second control circuit 340 includes a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19. The output circuit 350 includes a thirty-first transistor T31, a thirty-second transistor T32, a thirty-third transistor T33, and a thirty-fourth transistor T34. The pull-down circuit 360 includes the twentieth transistor T20, the twenty-first transistor T21, the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-sixth transistor T26, the twenty-seventh transistor T27, and the twenty-eighth transistor T28. The reset circuit 370 includes the twenty-ninth transistor T29 and the thirtieth transistor T30. The first transistor T1 to the thirty-fourth transistor T34 are all N-type transistors.

[0073] In this embodiment of the disclosure, the second node QN may include a first child node Q1 and a second child node Q2.

[0074] In this embodiment of the disclosure, the control electrode of the first transistor T1 is electrically connected to the first clock terminal CLK1, the first electrode of the first transistor T1 is electrically connected to the first power supply VGH, and the second electrode of the first transistor T1 is electrically connected to the control electrode of the eleventh transistor T11.

[0075] The control electrode of the eleventh transistor T11 is electrically connected to the first terminal of the first capacitor C1. The first terminal of the eleventh transistor T11 is electrically connected to the first power supply VGH. The second terminal of the eleventh transistor T11 is electrically connected to the first node P. The second terminal of the first capacitor C1 is electrically connected to the first node P.

[0076] The control electrode of the thirteenth transistor T13 is connected to the first node P, the first electrode of the thirteenth transistor T13 is connected to the first power supply VGH, and the second electrode of the thirteenth transistor T13 is connected to the gating circuit 120.

[0077] The first terminal of the second capacitor C2 is electrically connected to the first power supply VGH, and the second terminal of the second capacitor C2 is electrically connected to the first node P.

[0078] The control terminals of the second to ninth transistors T2-T9 are electrically connected to the selection terminals D0-D7 of the first selection terminal group, respectively. The second terminals of the second to ninth transistors T2-T9 are electrically connected to the first clock segment CLK1. The first terminals of the second to ninth transistors T2-T9 are electrically connected to the second terminals of the tenth transistor T10 and the twelfth transistor T12.

[0079] The control terminals of the tenth and twelfth transistors are electrically connected to the third node QB, and the first terminals of the tenth transistor T10 and the twelfth transistor T12 are electrically connected to the first node P.

[0080] The control electrode of the fourteenth transistor T14 is connected to the second clock terminal CLK2, the first electrode of the fourteenth transistor T14 is connected to the first power supply VGH, and the second electrode of the fourteenth transistor T14 is connected to the fourth node Q.

[0081] The control electrode of the 22nd transistor T22 is electrically connected to the first node P, the first electrode of the 22nd transistor T22 is electrically connected to the fourth node Q, and the second electrode of the 22nd transistor T22 is electrically connected to the first sub-node Q1.

[0082] The control electrode of the 25th transistor T25 is connected to the first node P, the first electrode of the 25th transistor T25 is connected to the fourth node Q, and the second electrode of the 25th transistor is connected to the second sub-node Q2.

[0083] The control electrode and first electrode of the fifteenth transistor T15 are electrically connected to the third power supply GVDD, and the second electrode of the fifteenth transistor T15 is electrically connected to the first electrode of the sixteenth transistor T16.

[0084] The control electrode of the sixteenth transistor T16 is electrically connected to the third power supply GVDD, and the second electrode of the sixteenth transistor T16 is electrically connected to the control electrode of the eighteenth transistor T18.

[0085] The control electrode of the seventeenth transistor T17 is electrically connected to the first sub-node Q1, the first electrode of the seventeenth transistor T17 is electrically connected to the control electrode of the eighteenth transistor T18, and the second electrode of the seventeenth transistor T17 is electrically connected to the fourth power supply VGL.

[0086] The first terminal of the eighteenth transistor T18 is electrically connected to the third power supply GVDD, and the second terminal of the eighteenth transistor T18 is electrically connected to the third node QB.

[0087] The control electrode of the nineteenth transistor T19 is connected to the second sub-node Q2, the first electrode of the nineteenth transistor T19 is connected to the third node QB, and the second electrode of the nineteenth transistor T19 is connected to the second power supply LVGL.

[0088] The control electrode of the twentieth transistor T20 is electrically connected to the first node P, the first electrode of the twentieth transistor T20 is electrically connected to the third node QB, and the second electrode of the twentieth transistor T20 is electrically connected to the first electrode of the twenty-first transistor T21.

[0089] The control electrode of the 21st transistor T21 is connected to the first clock terminal CLK1, and the second electrode of the 21st transistor T21 is connected to the second power supply LVGL.

[0090] The control terminals of transistors T23, T24, T26, and T27 are electrically connected to the third node QB.

[0091] The 23rd transistor T23 and the 24th transistor T24 are connected in series. The first terminal of the 23rd transistor T23 is electrically connected to the first sub-node Q1, and the second terminal of the 24th transistor T24 is electrically connected to the second power supply LVGL.

[0092] The twenty-sixth transistor T26 and the twenty-seventh transistor T27 are connected in series. The first terminal of the twenty-sixth transistor T26 is electrically connected to the second sub-node Q2, and the second terminal of the twenty-seventh transistor T27 is electrically connected to the second power supply LVGL.

[0093] The control electrode of the twenty-eighth transistor T28 is electrically connected to the first sub-node Q1, the first electrode of the twenty-eighth transistor T28 is electrically connected to the second electrode of the twenty-third transistor T23 and the second electrode of the twenty-sixth transistor T26, and the second electrode of the twenty-eighth transistor T28 is electrically connected to the first power supply VGH.

[0094] The 29th transistor T29 and the 30th transistor T30 are connected in series. The control electrode of the 29th transistor T29 and the 30th transistor T30 is electrically connected to the first clock terminal CLK1. The first electrode of the 29th transistor T29 is electrically connected to the fourth node Q. The second electrode of the 30th transistor T30 is electrically connected to the second power supply LVGL.

[0095] In this embodiment of the disclosure, the control electrode of the thirty-first transistor T31 is electrically connected to the first sub-node Q1, the first electrode of the thirty-first transistor T31 is electrically connected to the clock terminal CLKE1, and the second electrode of the thirty-first transistor T31 is electrically connected to the first output terminal SCOUT(1).

[0096] The control electrode of the 32nd transistor T32 is electrically connected to the third node QB, the first electrode of the 32nd transistor T32 is connected to the fourth power supply VGL, and the second electrode of the 32nd transistor T32 is electrically connected to the first output terminal SCOUT(1).

[0097] The first end of the third capacitor C3 is connected to the first sub-node Q1, and the second end of the third capacitor C3 is connected to the first output terminal SCOUT(1).

[0098] The control electrode of the 33rd transistor T33 is connected to the second sub-node Q2, the first electrode of the 33rd transistor T33 is connected to the clock terminal CLKE2, and the second electrode of the 33rd transistor T33 is connected to the second output terminal SCOUT(2).

[0099] The control electrode of the 34th transistor T34 is connected to the third node QB, the first electrode of the 34th transistor T34 is connected to the fourth power supply VGL, and the second electrode of the 34th transistor T34 is connected to the second output terminal SCOUT(2).

[0100] The first terminal of the fourth capacitor C4 is electrically connected to the second sub-node Q2, and the second terminal of the fourth capacitor C2 is electrically connected to the second output terminal SCOUT(2).

[0101] It should be noted that this disclosure does not limit the number of output terminals.

[0102] Figure 4A and Figure 4C yes Figure 3 Signal timing diagram of the intermediate shift register, Figure 4A and Figure 4C The timing waveforms of each signal in each stage of the forward and reverse scanning processes are shown respectively. Figure 4B This is a simulation diagram of the voltage in a shift register according to an embodiment of the present disclosure.

[0103] The following is based on Figure 3 Taking the structure of the shift register shown as an example, combined with... Figure 4A and Figure 4C The signal timing diagram shown describes the operation of the shift register provided in the embodiments of this disclosure. The forward and reverse scan operations of the shift register each include five stages.

[0104] For example, Figure 4A The signal timing of shift register 300 during the forward scan process is shown in the five stages S1-S5. Figure 4A The signal timing provided to the first-stage shift register in a cascaded series of shift registers is shown.

[0105] Before the forward scan begins, the first clock signal CLK1 outputs a high level, causing the potential of the first node P to become high. The 29th transistor T29 and the 30th transistor T30 are then turned on. The fourth node Q, the first child node Q1, and the second child node Q2 are reset via the 30th transistor T30, the 29th transistor T29, the 25th transistor T25, and the 22nd transistor T22, respectively. During the forward scan, when the first clock signal CLK1 is high, the same reset effect can be achieved for the aforementioned nodes.

[0106] In the first stage S1, the first clock signal CLK1 changes from high to low, the strobe signals D0-D7 are low, the second clock signal is low, and clock signals CLKE1 and CLKE2 are low. The first voltage VGH is high, the second voltage LVGL is low, the third voltage GVDD is high, and the fourth voltage VGL is low, wherein the second voltage LVGL is lower than the fourth power supply voltage VGL. Since the threshold voltage Vth of the transistor is prone to negative drift, leading to leakage, when the second voltage LVGL is lower than the fourth voltage VGL, it can make the transistor's Vgs(LVGL-VGL) in the off state negative.

[0107] When the first clock signal CLK1 is high, the first transistor T1 is turned on under the control of the first clock signal CLK1. Since the first voltage VGH is high, the high level is provided to the first terminal of the first capacitor C1 through the first transistor T1, thereby charging the first capacitor C1. The first capacitor C1 stores the high level, making the potential of the first node P high.

[0108] Under the control of the third voltage GVDD, the fifteenth transistor T15, the sixteenth transistor T16, and the eighteenth transistor T18 are turned on, making the third node QB high.

[0109] Under the control of the high level of the third node QB, transistors T23, T24, T26, and T27 are turned on. Under the control of the second voltage LVGL, a low level is provided to the first child node Q1 through transistors T24 and T23, keeping the first child node Q1 at a low level. A low level is also provided to the second child node Q2 through transistors T27 and T26, keeping the second child node at a low level.

[0110] Under the control of the high level of the first node P, the twenty-second transistor T22 is turned on, and the low level is provided to the fourth node Q through the twenty-second transistor T22, so that the potential of the fourth node Q is kept low.

[0111] Under the control of the strobe signals D0-D7, the second transistor T2 to the ninth transistor T9 are turned off, and the potential of the first node P will not be reduced due to the influence of the second transistor T2 to the ninth transistor T9, and the potential of the first node P remains at a high level.

[0112] When the first clock signal CLK1 changes from high level to low level, the first transistor T1 is turned off under the control of the first clock signal CLK1. Since the first capacitor C1 remains at a high potential, the eleventh transistor T11 remains on, so that the first voltage VGH is provided to the first node P, and the first node P remains at a high level.

[0113] In the second stage S2, the first clock signal CLK1 is at a low level, and the second clock signal CLK2 changes from a low level to a high level.

[0114] Under the control of the second clock signal CLK2, the fourteenth transistor T14 is turned on, and the first voltage VGH is provided to the fourth node Q through the fourteenth transistor T14, making the potential of the fourth node Q high.

[0115] Under the control of the high level of the first node P, the twenty-second transistor T22 and the twenty-fifth transistor T25 are turned on. The first voltage VGH is provided to the first child node Q1 through the twenty-second transistor T22, and the first voltage VGH is provided to the second child node Q2 through the twenty-fourth transistor T24, so that the potentials of the first child node Q1 and the second child node Q2 are high.

[0116] Under the control of the high level of the first sub-node Q1 and the second sub-node Q2, the seventeenth transistor T17 and the nineteenth transistor T19 are turned on. The fourth voltage VGL is supplied to the eighteenth transistor T18 through the seventeenth transistor T17, and under the control of the fourth voltage VGL, the eighteenth transistor T18 is turned off.

[0117] Under the control of the second clock signal CLK2, the twenty-first transistor T21 is turned on. Under the control of the high level of the first node P, the twentieth transistor T20 is turned on. At this time, the low level of the second voltage LVGL is provided to the third node QB through the twentieth transistor T20 and the first transistor T21, causing the potential of the third node QB to be pulled low.

[0118] In this embodiment, when the select terminals D0-D7 are all low and the first clock signal CLK1 is low, the first and second terminals of transistors T2-T9 are both low. However, since the threshold voltage Vth is usually negative, without the tenth transistor T10 and the twelfth transistor T12, transistors T2-T9 may not be completely turned off, resulting in Vgs being less than 0. This would cause the potential of the first node P to become low under the influence of the first clock signal CLK1. The tenth transistor T10 and the twelfth transistor T12 in the shift register of this disclosure are turned off under the control of the low potential of the third node QB, avoiding leakage caused by the fourth node Q being connected to a low potential through transistors T2-T9.

[0119] Furthermore, when the first sub-node Q1 and the second sub-node Q2 are high, transistors T17 and T19 are turned on. Since transistors T15, T16, and T18 are relatively small, when T17 is on, the control electrode of T18 drops to a negative voltage, operating in the saturation region. When T19 is on, it operates in the linear region. Therefore, controlling the third node QB to a low level achieves the effect of voltage inversion.

[0120] In the third stage S3, the first clock signal CLK1 and the second clock signal CLK2 remain at a low level.

[0121] Under the control of the second clock signal CLK2, the potentials of the fourth node Q, the first child node Q1, and the second child node Q2 remain high, while the third node QB is low. Under the control of the high level of the first child node Q1, the thirty-first transistor T31 is turned on, and the clock signal CLKE1 is provided to the first output terminal SCOUT(1) through the thirty-first transistor T31. Therefore, the first scan signal SCOUT(1) of the first output terminal SCOUT(1) is the same as the clock signal CLKE1. Under the control of the high level of the second child node Q2, the thirty-third transistor T33 is turned on, and the clock signal CLKE2 is provided to the second output terminal SCOUT(2) through the thirty-third transistor T33. Therefore, the second scan signal SCOUT(2) of the second output terminal SCOUT(2) is the same as the clock signal CLKE2.

[0122] Due to the bootstrap effect of the third capacitor C3 and the fourth capacitor C4, after the thirty-first transistor T31 and the thirty-third transistor T33 are turned on, the third capacitor C3 continues to charge the first sub-node Q1, and the fourth capacitor C4 continues to charge the second sub-node, causing the potentials of the first sub-node Q1 and the second sub-node Q2 to rise further.

[0123] At the end of the third stage S3, as the first capacitor C1 finishes discharging, the potential of the first node P becomes low under the control of the low level of the first clock signal CLK1. The gating stage of the shift register ends, and the first output terminal SCOUT(1) and the second output terminal SCOUT(2) stop outputting.

[0124] In the embodiments of this disclosure, when the clock signal CLKE1 goes high, the thirtieth transistor T31 is turned on. Due to the presence of the third capacitor C3, the twenty-third transistor T23 and the twenty-fourth transistor T24 of this disclosure can prevent the first child node Q1 from being coupled to a high potential and causing noise to the output. The twenty-sixth transistor T26 and the twenty-seventh transistor T27 have the same effect on the second child node Q2, and will not be described again.

[0125] In the fourth stage S4, the first clock signal is at a high level.

[0126] Under the control of the first clock signal, the twenty-ninth transistor T29 and the thirtieth transistor T30 are turned on. The second voltage LVGL is provided to the fourth node Q through the thirtieth transistor T30 and the twenty-ninth transistor T29, causing the potential of the fourth node Q to drop to a low level.

[0127] Under the control of the first clock signal, the first transistor T1 is turned on, and the first voltage VGH is provided to the first node P through the first transistor T1, making the potential of the first node P high, and at the same time recharging the first capacitor C1 that was discharged in the third stage S3. At this time, the twenty-second transistor T22 and the twenty-fifth transistor T25 are turned on, and the potentials of the first child node Q1 and the second child node Q2 are reduced to low.

[0128] Under the control of the low level of the first child node Q1 and the second child node Q2, the seventeenth transistor T17 and the nineteenth transistor T19 are turned off, and the eighteenth transistor T18 is turned on. The third voltage GVDD is provided to the third node QB through the eighteenth transistor T18, making the potential of the third node QB high.

[0129] In the fifth stage S5, the strobe signal D0 of the strobe terminal D0 is at a high level, and the first clock signal CLK1 is at a low level.

[0130] Under the control of the strobe signal D0, the second transistor T2 is turned on. Under the control of the high level of the third node QB, the tenth transistor T10 is turned on, and the first clock signal CLK1 is provided to the first node P through the second transistor T2 and the tenth transistor T10, causing the potential of the first node P to become low.

[0131] Under the control of the low level of the first node P, the twenty-second transistor T22 and the twenty-fifth transistor T25 are turned off, causing the potential of the first child node Q1 and the second child node Q2 to drop to a low level, and the thirty-first transistor T31 and the thirty-third transistor T33 are turned off.

[0132] Under the control of the first clock signal and the strobe signal D0, the shift register is in the non-strobe stage at this time.

[0133] In this embodiment, the shift register is selected using a total of 12 signals: D0-D7, CLK1 and CLK2, and CLKE1 and CLKE2, resulting in a simplified architecture. Each shift register can provide two scan signals. In a GOA unit composed of two shift registers provided in this embodiment, the eight strobe signals can support 1024 rows of selection. If the number of rows needs to be increased, each additional strobe signal can support double the number of rows.

[0134] Figure 4B This is a simulation diagram of the voltage in the shift register according to an embodiment of this disclosure.

[0135] like Figure 4B As shown, the simulated waveforms of each signal potential in each stage of the shift register provided in this embodiment of the present disclosure are... Figure 4A The timing waveforms described are similar. For the sake of brevity, further details will not be provided.

[0136] Figure 4C This is a signal timing diagram of a shift register according to another embodiment of the present disclosure.

[0137] Figure 4C The timing diagram shows the signals supplied to the last stage shift register in a cascaded series of shift registers. Third clock signal CLK3 and fourth clock signal CLK4 are supplied to the last stage shift register. Clock signals CLKE3 and CLKE4 are supplied to the first stage shift register.

[0138] Timing of the fourth clock signal CLK4 and Figure 4A The timing of the first clock signal CLK1 is shown to be the same. The timing of the third clock signal CLK3 is the same as... Figure 4A The timing of the second clock signal CLK2 is shown to be the same. The timing of clock signal CLKE4 is the same as... Figure 4A The timing of clock signal CLKE1 is shown to be the same. The timing of clock signal CLKE3 is the same as... Figure 4A The timing of the clock signal CLKE2 shown is the same.

[0139] The control of the last-stage shift register by the fourth clock signal CLK4 can be referred to the control of the first-stage shift register by the first clock signal CLK1 described earlier, and the control of the last-stage shift register by the third clock signal CLK3 can be referred to the control of the first-stage shift register by the second clock signal CLK2 described earlier.

[0140] The control of the last stage shift register by clock signal CLKE4 can be referred to the control of the first stage shift register by clock signal CLKE1 described earlier, and the control of the last stage shift register by clock signal CLKE3 can be referred to the control of the first stage shift register by clock signal CLKE2 described earlier.

[0141] When the last shift register is the 512th stage, the scan signals of outputs SCOUT(1023) and SCOUT(1024) are respectively... Figure 4A The first scan signal SCOUT(1) and the second scan signal SCOUT(2) output by the first-stage shift register are shown.

[0142] During the reverse scan process, the timing of each signal in the five stages S1-S5 of the last stage shift register is consistent with... Figure 4A The descriptions are similar, so I will not repeat them for the sake of brevity.

[0143] Figure 5 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0144] like Figure 5 As shown, the shift register 500 includes a first control circuit 510, a gating circuit 520, an input circuit 530, a second control circuit 540, an output circuit 550, a pull-down circuit 560, and a reset circuit 570.

[0145] In the embodiments disclosed herein, the first control circuit 510, the gating circuit 520, the input circuit 530, the second control circuit 540, the pull-down circuit 560, and the reset circuit 570 are structurally similar to the first control circuit 310, the gating circuit 320, the input circuit 330, the second control circuit 340, the pull-down circuit 360, and the reset circuit 370 described above, and will not be repeated for the sake of brevity.

[0146] In this embodiment of the disclosure, the second node QN may include a first child node Q1, a second child node Q2, a third child node Q3, and a fourth child node Q4.

[0147] In this embodiment, the output circuit 550, based on the control circuit 350 described above, further includes a 35th transistor T35, a 36th transistor T36, a 37th transistor T37, a 38th transistor T38, a 39th transistor T39, a 40th transistor T40, a 41st transistor T41, a 42nd transistor T42, a 43rd transistor T43, a 44th transistor T44, a 5th capacitor C5, and a 6th capacitor C6. All of the 35th transistors T35 to T44 are N-type transistors.

[0148] The control terminal of the 35th transistor T35 is electrically connected to the first node P, the first electrode of the 35th transistor T35 is electrically connected to the fourth node Q, and the second electrode of the 35th transistor T35 is electrically connected to the third sub-node Q3.

[0149] The thirty-sixth transistor T36 and the thirty-seventh transistor T37 are connected in series. The control terminals of the thirty-sixth transistor T36 and the thirty-seventh transistor T37 are electrically connected to the third node QB. The second terminal of the thirty-sixth transistor T36 is electrically connected to the third sub-node Q3. The second terminal of the thirty-seventh transistor T37 is electrically connected to the second power supply LVGL.

[0150] The control electrode of the thirty-eighth transistor T38 is electrically connected to the third sub-node Q3, the first electrode of the thirty-eighth transistor T38 is electrically connected to the clock terminal CLKE3, and the second electrode of the thirty-eighth transistor T38 is electrically connected to the third output terminal SCOUT(3).

[0151] The control electrode of the 39th transistor T39 is connected to the third node QB, the first electrode of the 39th transistor T39 is connected to the fourth power supply VGL, and the second electrode of the 39th transistor T39 is connected to the third output terminal SCOUT (3).

[0152] The control terminal of the 40th transistor T40 is electrically connected to the first node P, the first electrode of the 40th transistor T40 is electrically connected to the fourth node Q, and the second electrode of the 35th transistor T35 is electrically connected to the third sub-node Q3.

[0153] Transistor T41 (41) and transistor T42 (42) are connected in series. The control terminals of transistors T41 and T42 are electrically connected to the fourth sub-node Q4. The second terminal of transistor T41 is electrically connected to the fourth sub-node Q4. The second terminal of transistor T42 is electrically connected to the second power supply LVGL.

[0154] The control electrode of the forty-third transistor T43 is connected to the fourth child node Q4, the first electrode of the forty-third transistor T43 is connected to the clock terminal CLKE4, and the second electrode of the forty-third transistor T43 is connected to the fourth output terminal SCOUT(4).

[0155] The control electrode of the forty-fourth transistor T44 is electrically connected to the third node QB, the first electrode of the forty-fourth transistor T44 is electrically connected to the fourth power supply VGL, and the second electrode of the forty-fourth transistor T44 is electrically connected to the fourth output terminal SCOUT(4).

[0156] Figure 6 This is a signal timing diagram of a shift register according to another embodiment of the present disclosure.

[0157] like Figure 6 As shown, Figure 6 The timing waveforms of each signal in each stage of the forward scan of shift register 500 are shown.

[0158] The following is based on Figure 5 Taking the structure of the shift register 500 shown as an example, combined with... Figure 6 The signal timing diagram shown describes the process of the shift register provided in the embodiments of this disclosure. The timing changes of the first clock signal CLK1, the second clock signal CLK2, the clock signal CLKE1, the clock signal CLKE2, the first child node Q1, the second child node Q2, the first node P, the third node QB, and the fourth node Q are similar to the timing changes of the signals described above, and will not be repeated for the sake of brevity.

[0159] In the first stage S1, the timing changes of each signal in shift register 500 are similar to those described above, and will not be repeated here for the sake of brevity.

[0160] In the second stage S2, the second clock signal CLK2 changes from low level to high level.

[0161] Under the control of the high level of the first node P, the thirty-fifth transistor T35 and the fortieth transistor T40 are turned on. The first voltage VGH is provided to the third child node Q3 through the thirty-fifth transistor T35, and to the fourth child node Q4 through the fortieth transistor T40, so that the potentials of the third child node Q3 and the fourth child node Q4 are high.

[0162] Under the control of the high levels of the first sub-node Q1 and the fourth sub-node Q4, the seventeenth transistor T17 and the nineteenth transistor T19 are turned on. The fourth voltage VGL is supplied to the eighteenth transistor T18 through the seventeenth transistor T17, and under the control of the fourth voltage VGL, the eighteenth transistor T18 is turned off.

[0163] In the third stage S3, the first clock signal CLK1 and the second clock signal CLK2 remain at a low level.

[0164] Under the control of the second clock signal CLK2, the potentials of the fourth node Q, the third sub-node Q3, and the fourth sub-node Q4 remain high, while the third node QB is low. Under the control of the high level of the third sub-node Q3, the thirty-eighth transistor T38 is turned on, and the clock signal CLKE3 is provided to the third output terminal SCOUT(3) through the thirty-eighth transistor T38. Therefore, the third scan signal SCOUT(3) of the third output terminal SCOUT(3) is the same as the clock signal CLKE3. Under the control of the high level of the fourth sub-node Q4, the forty-third transistor T43 is turned on, and the clock signal CLKE4 is provided to the output terminal SCOUT(4) through the forty-third transistor T43. Therefore, the fourth scan signal SCOUT(4) of the fourth output terminal SCOUT(4) is the same as the clock signal CLKE4.

[0165] Due to the bootstrap effect of the fifth capacitor C5 and the sixth capacitor C6, after the thirty-eighth transistor T38 and the forty-third transistor T43 are turned on, the fifth capacitor C5 continues to charge the third sub-node Q3, and the sixth capacitor C6 continues to charge the fourth sub-node Q4, causing the potentials of the third sub-node Q3 and the fourth sub-node Q4 to rise further.

[0166] In the fourth stage S4, the first clock signal is at a high level.

[0167] Under the control of the first clock signal, the twenty-ninth transistor T29 and the thirtieth transistor T30 are turned on. The second voltage LVGL is provided to the fourth node Q through the thirtieth transistor T30 and the twenty-ninth transistor T29, causing the potential of the fourth node Q to drop to a low level.

[0168] Under the control of the first clock signal, the first transistor T1 is turned on, and the first voltage VGH is provided to the first node P through the first transistor T1, making the potential of the first node P high, and at the same time recharging the first capacitor C1 that was discharged in the third stage S3. At this time, the thirty-fifth transistor T35 and the fortieth transistor T40 are turned on, and the potentials of the third child node Q3 and the fourth child node Q4 are reduced to low.

[0169] Under the control of the low levels of the first child node Q1 and the fourth child node Q4, the seventeenth transistor T17 and the nineteenth transistor T19 are turned off, and the eighteenth transistor T18 is turned on. The third voltage GVDD is provided to the third node QB through the eighteenth transistor T18, making the potential of the third node QB high.

[0170] In the fifth stage S5, the strobe signal D0 of the strobe terminal D0 is at a high level, and the first clock signal CLK1 is at a low level.

[0171] Under the control of the strobe signal D0, the second transistor T2 is turned on. Under the control of the high level of the third node QB, the tenth transistor T10 is turned on, and the first clock signal is provided to the first node P through the second transistor T2 and the tenth transistor T10, causing the potential of the first node P to become low.

[0172] Under the control of the low level of the first node P, the thirty-fifth transistor T35 and the fortieth transistor T40 are turned off, causing the potential of the third child node Q2 and the fourth child node Q4 to drop to a low level, and the thirty-eighth transistor T38 and the forty-third transistor T43 are turned off.

[0173] Under the control of the first clock signal and the strobe signal D0, the shift register is in the non-strobe stage at this time. Figure 7 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0174] like Figure 7 As shown, the shift register 700 includes a first control circuit 710, a gating circuit 720, an input circuit 730, a second control circuit 740, an input circuit 750, a pull-down circuit 760, a reset circuit 770, and a third control circuit 780.

[0175] In the embodiments of this disclosure, the first control circuit 710, the gating circuit 720, the input circuit 750 and the reset circuit 770 are similar in structure to the first control circuit 510, the gating circuit 520, the input circuit 550 and the reset circuit 570 described above, and will not be repeated for the sake of brevity.

[0176] In this embodiment of the disclosure, the second control circuit 740 also includes the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, and the nineteenth transistor T19, just like the second control circuit 540 described above. However, the connection method of the fifteenth transistor T15 to the nineteenth transistor T19 is different from that of the second control circuit 540.

[0177] In this embodiment, the input circuit 730 further includes a forty-fifth transistor T45 in addition to the input circuit 530 described above. The pull-down circuit 760 further includes a forty-sixth transistor T46 and a forty-seventh transistor T47 in addition to the second pull-down circuit 560 described above. The third control circuit 780 includes a forty-eighth transistor T48 and a forty-ninth transistor T49. All transistors from the forty-fifth transistor T45 to the forty-ninth transistor T49 are N-type transistors.

[0178] The control electrode and the first electrode of the fifteenth transistor T15 are electrically connected to the first clock terminal CLK1, and the second electrode of the fifteenth transistor T15 is electrically connected to the first electrode of the sixteenth transistor T16.

[0179] The control electrode of the sixteenth transistor T16 is electrically connected to the first clock terminal CLK1, and the second electrode of the sixteenth transistor T16 is electrically connected to the control electrode of the eighteenth transistor T18.

[0180] The control electrode of the seventeenth transistor T17 is electrically connected to the second sub-node Q2, the first electrode of the seventeenth transistor T17 is electrically connected to the control electrode of the eighteenth transistor T18, and the second electrode of the seventeenth transistor T17 is electrically connected to the second electrode of the fifteenth transistor T15.

[0181] The first terminal of the eighteenth transistor T18 is electrically connected to the second terminal of the fifteenth transistor T15, and the second terminal of the eighteenth transistor T18 is electrically connected to the first power supply VGH.

[0182] The control electrode of the nineteenth transistor T19 is electrically connected to the first sub-node Q1, the first electrode of the nineteenth transistor T19 is electrically connected to the second electrode of the seventeenth transistor T17, and the second electrode of the nineteenth transistor T19 is electrically connected to the second power supply LVGL.

[0183] The forty-fifth transistor T45 is connected in series with the fourteenth transistor T14. The control electrode of the forty-fifth transistor T45 is electrically connected to the second clock terminal CLK2, and the second electrode of the forty-fifth transistor T45 is electrically connected to the first power supply VGH.

[0184] The forty-sixth transistor T46 is connected in series with the twentieth transistor T20 and the twenty-first transistor T21. The control electrode of the forty-sixth transistor T46 is electrically connected to the first node P.

[0185] The forty-seventh transistor T47 is connected in series with the twenty-eighth transistor T28. The control electrode of the forty-seventh transistor T47 is electrically connected to the first node P, and the second electrode of the forty-seventh transistor T47 is electrically connected to the first power supply VGH.

[0186] Transistor T48 (48th) and transistor T49 (49th) are connected in series. The control terminals of transistors T48 and T49 are electrically connected to the first power supply VGH. The second terminal of transistor T48 is electrically connected to the first terminal of transistor T14 (44th), and the second terminal of transistor T49 is electrically connected to the first power supply VGH.

[0187] The shift register 700 disclosed herein employs a second control circuit 740 with a different structure from shift registers 300 and 500. It uses an AC inverter and designates the eighteenth transistor T18 as a critical path to prevent leakage current, thereby avoiding leakage caused by negative drift of Vth when the potential of the third node QB is high. The forty-eighth transistor T48 and forty-nine transistor T49 added to the third control circuit 780 in shift register 700 can effectively prevent leakage current caused by the input circuit being turned off.

[0188] When shift register 700 is in the non-gated stage, the third node QB needs to remain at a high level. When the first clock signal CLK1 is low, if there is no eighteenth transistor T18, the Vgs of the sixteenth transistor T16, the seventeenth transistor T17, the nineteenth transistor T19, and the twentieth transistor T20 are all 0. If Vth experiences negative drift, all of the above transistors will turn on, causing the potential of the third node QB to drop rapidly. When the eighteenth transistor T18 is added, it can be ensured that the sixteenth transistor T16, the nineteenth transistor T19, and the twenty-first transistor T21 are completely turned off, eliminating leakage paths and keeping the potential of the third node QB more stable.

[0189] Figure 8A This is a schematic diagram of the structure of a driving circuit according to an embodiment of the present disclosure.

[0190] like Figure 8A As shown, the driving circuit 800 includes M driving unit groups, and each driving unit group may include multiple shift registers as described in the embodiments of this disclosure. For example, driving unit group 810 includes shift register GOA1 and shift register GOA2. It should be noted that... Figure 8A The structure of each drive unit group in the drive circuit 800, which includes two shift registers, is shown only schematically. Each drive unit group includes two shift registers, and the drive circuit 800 includes a total of 2M shift registers. The 2M shift registers include shift register GOA1, shift register GOA2, shift register GOA3, ..., shift register GOA2M.

[0191] In this embodiment of the disclosure, the multiple gating terminals may include multiple first gating terminals D0-D7 of the first gating terminal group and multiple second gating terminals D0'-D7' of the second gating terminal group. The shift registers in the m-th driving unit group are all electrically connected to the first gating terminal group, and the shift registers in the (m+1)-th driving unit group are all electrically connected to the second gating terminal group. The gating signal output by the first gating terminal group is opposite to the gating signal output by the second gating terminal group, where 1 ≤ m < M, and M is a positive integer greater than 1.

[0192] In this embodiment of the disclosure, the two shift registers in each drive unit group are electrically connected to different clock signals. For example, drive unit group 810 includes shift register GOA1 and shift register GOA2. Shift register GOA1 is electrically connected to the first clock terminal CLK1, the second clock terminal CLK2, and clock terminals CLKE1 and CLKE2. Shift register GOA2 is electrically connected to the third clock terminal CLK3, the fourth clock terminal CLK4, and clock terminals CLKE3 and CLKE4. Each shift register includes two output terminals.

[0193] In this embodiment, the shift register can be any one of the shift registers 100, 200, and 300 mentioned above. Further details will not be provided here.

[0194] In the embodiments of this disclosure, the 2M shift registers do not need to be cascaded, and the output signal is not controlled by other shift registers. When applied to the drive circuit 800, it can realize the output of random frame displacement signals.

[0195] In embodiments of this disclosure, the number of first gating terminals in the first gating terminal group is the same as the number of second gating terminals in the second gating terminal group, and the number of first gating terminals is the same as the number of gating transistors included in the shift register. For example, the first gating terminal group includes 8 gating terminals D0-D7, and the second gating terminal group includes 8 gating terminals D0'-D7'.

[0196] Each gate in the gate group controls one gate transistor. This disclosure does not limit the number of gates and gate transistors; the number of gates and gate transistors can be set according to actual needs.

[0197] In the embodiments of this disclosure, the multiple shift registers included in the m-th drive unit group are connected in the same way as the multiple first strobe terminals included in the first strobe terminal group, and the multiple shift registers included in the (m+1)-th drive unit group are connected in the same way as the multiple second strobe terminals included in the second strobe terminal group.

[0198] For example, a driver unit group may include two shift registers, and the shift registers within the group are connected to the strobe terminals in the same way. For two adjacent driver unit groups, the connection methods between the shift registers and the strobe terminals of the different driver unit groups are different.

[0199] like Figure 8AAs shown, the shift registers of the first drive unit group 810 are all electrically connected to the first strobe terminals D0-D7 of the first strobe terminal group, and the shift registers of the second drive unit group are all electrically connected to the second strobe terminals D0'-D7' of the second strobe terminal group. The levels of the first strobe terminals D0-D7 and the second strobe terminals D0'-D7' are opposite. When the strobe signal output by the first strobe terminal group is high, the strobe signal output by the second strobe terminal group is low. Conversely, when the strobe signal output by the first strobe terminal group is low, the strobe signal output by the second strobe terminal group is high.

[0200] Figure 8B This is a signal timing diagram of a drive circuit according to an embodiment of the present disclosure.

[0201] like Figure 8B As shown, Figure 8B The timing waveforms of each signal in each stage of the forward scan operation of the drive circuit 800 are shown.

[0202] According to embodiments of this disclosure, Figure 8B The signal changes of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, the clock signals CLKE1, CLKE2, CLKE3 and CLKE4, the first strobe terminals D0-D7 of the first strobe terminal group, the first node P, the first child node Q1, the second child node Q2, the third node QB, the fourth node Q, the first scan signal SCOUT(1) and the second scan signal SCOUT(2) are shown.

[0203] Figure 8B The timing changes of the first scan signal SCOUT(1), the second scan signal SCOUT(2), the first node P, the first child node Q1, the second child node Q2, the third node QB, and the fourth node Q shown are similar to the timing changes of the signals described above, and will not be repeated for the sake of brevity.

[0204] In this embodiment of the disclosure, the fourth clock terminal CLK4 connected to the shift register GOA2 described above has a similar function to the first clock terminal CLK1 connected to the shift register GOA1 described above. The third clock terminal CLK3 connected to the shift register GOA2 described above has a similar function to the second clock terminal CLK2 connected to the shift register GOA1 described above. The clock terminals CLKE3 and CLKE4 connected to the shift register GOA2 described above have a similar function to the clock terminals CLKE1 and CLKE2 connected to the shift register GOA1 described above. For the sake of brevity, these will not be described in detail again.

[0205] Figure 9A This is a schematic diagram of the structure of a drive circuit according to another embodiment of the present disclosure.

[0206] like Figure 9A As shown, the driving circuit 900 includes M driving unit groups, and each driving unit group may include multiple shift registers as described in the embodiments of this disclosure. For example, driving unit group 910 includes shift register GOA1 and shift register GOA2. It should be noted that... Figure 9A The structure of each drive unit group in the drive circuit 900, comprising two shift registers, is shown only schematically. Each drive unit group includes two shift registers, and the drive circuit 900 includes 2M shift registers. The 2M shift registers include shift register GOA1, shift register GOA2, shift register GOA3, ..., shift register GOA2M.

[0207] In this embodiment of the disclosure, the connection method between the shift register and the strobe terminal in each drive unit group is similar to the connection method in the drive circuit 800 described above, and will not be repeated for the sake of brevity.

[0208] In this embodiment of the disclosure, the shift registers in the first drive unit group 910 include shift register GOA1 and shift register GOA2. Shift register GOA1 is electrically connected to the first clock terminal CLK1, the second clock terminal CLK2, and clock terminals CLKE1, CLKE2, CLKE3, and CLKE4. Shift register GOA2 is electrically connected to the third clock terminal CLK3, the fourth clock terminal CLK4, and clock terminals CLKE5, CLKE6, CLKE7, and CLKE8. Each shift register includes four output terminals.

[0209] In this embodiment of the disclosure, the shift register can be either the shift register 500 or the shift register 700 mentioned above, and will not be described again here.

[0210] Figure 9B This is a signal timing diagram of a drive circuit according to another embodiment of the present disclosure.

[0211] like Figure 9B As shown, Figure 9B The timing waveforms of each signal in each stage of the forward scan operation of the drive circuit 900 are shown.

[0212] According to embodiments of this disclosure, Figure 9BThe signal changes of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, clock signals CLKE1-CLKE8, the first strobe terminals D0-D7 of the first strobe terminal group, the first node P, the first child node Q1, the second child node Q2, the third node QB, the fourth node Q, the first scan signal SCOUT(1), the second scan signal SCOUT(2), the third scan signal SCOUT(3), and the fourth scan signal SCOUT(4) are shown.

[0213] Figure 9B The clock signals CLK1, CLK2, CLKE1, CLKE2, CLKE3, CLKE4, Q1, Q2, Q3, Q4, P, QB, and Q4 described above are related to the clock signals CLK1, CLK2, CLKE1, CLKE2, CLKE3, CLKE4, Q1, Q2, Q3, Q4, P, QB, and Q4. Figure 6 The timing changes of each signal are similar, so they will not be elaborated further for the sake of simplicity.

[0214] In this embodiment of the disclosure, the relationships between the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 are respectively as follows: Figure 8B The descriptions are similar, so I will not repeat them for the sake of brevity.

[0215] The clock terminals CLKE1 and CLKE4 connected to the shift register GOA1 described above have similar functions to the clock terminals CLK5 and CLKE8 connected to the shift register GOA2 described above, and will not be repeated for the sake of brevity.

[0216] Figure 9C This is a timing diagram of the strobe signal according to an embodiment of the present disclosure. Figure 9C The timing of the gating signals output from the plurality of first gating terminals D0-D7 and the plurality of second gating terminals D0'-D7' electrically connected to the driving circuits 800 and 900 described above is shown.

[0217] In this embodiment of the disclosure, when the first strobe signal is at a first level, the corresponding second strobe signal is at a second level. For example, when the first strobe signal D0 is at a low level, the corresponding second strobe signal D0' is at a high level. When the first strobe signal D1 is at a low level, the corresponding second strobe signal D1' is at a high level.

[0218] The pulse width of Dx is twice the pulse width of Dx-1, where x is an integer. The value of x provided in this specification ranges from 0 to 7. For example, the pulse width of the first strobe signal D1 is twice the pulse width of the first strobe signal D0. The pulse width of the second strobe signal D1' is twice the pulse width of the second strobe signal D0'.

[0219] In this embodiment, the number of gating transistors in the shift register can be set according to requirements, and the number of gating signals is set accordingly based on the number of gating transistors. The control terminal of the x-th gating transistor in the shift register is selectively connected to either the gating terminal Dx or the gating terminal Dx'. The connection method between the shift register and the gating signal terminal is the same within the same driving unit group.

[0220] Figure 10 This is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure.

[0221] like Figure 10 As shown, the display device 1000 includes a display panel 1010 and a driving circuit 1020.

[0222] In this embodiment of the disclosure, the display panel 1010 includes a plurality of sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

[0223] In this embodiment, the driving circuit 1020 may be the driving circuit 800 and driving circuit 900 described above, and will not be repeated here.

[0224] It should be noted that the number of subpixel units included in the display panel 1010 is for illustrative purposes only, and this disclosure does not limit the number of subpixel units.

[0225] The driving circuit 1020 includes multiple shift registers that support gating, each shift register being connected to sub-pixel units in a different row. When it is necessary to refresh the sub-pixel units in a certain row, the driving circuit can select the corresponding shift register to refresh the specified row of sub-pixel units.

[0226] Figure 11 This is a flowchart of a driving method according to an embodiment of the present disclosure.

[0227] like Figure 11 As shown, the driving method may include operations S1110-S1120.

[0228] In the embodiments of this disclosure, the driving method can be applied to the shift registers 100, 200, 300, 500 and 700 described above.

[0229] During operation of S1110, in the gating phase, multiple gating signals are controlled to be at the first level.

[0230] In operation S1120, during the non-gating phase, at least one of the multiple gating signals is controlled to be at the second level.

[0231] In this embodiment of the disclosure, operations S1110-S1120 are similar to those performed by shift registers 300, 500 and 700 as described above, and will not be repeated here.

[0232] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0233] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0234] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A shift register, comprising: The first control circuit is configured to control the potential of the first node under the control of a first clock signal from a first clock terminal; The gating circuit is configured to control the potential of the first node under the control of multiple gating signals from multiple gating terminals, and to control the potential of the first node to remain at a second level under the control of a first level of a third node; Under the control of the second level of the third node, the potential of the first node is pulled down; The input circuit is configured to control the potential of the second node under the control of the potential of the first node and a second clock signal from the second clock terminal; The second control circuit is configured to control the potential of the third node under the control of the potential of the second node; The output circuit is configured to output a scan signal under the control of the potentials of the second node and the third node.

2. The shift register according to claim 1, wherein, The gating circuit controls the potential of the first node under the control of multiple gating signals from multiple gating terminals, and the gating circuit is configured as follows: Under the control of the first level of the plurality of gating signals, the potential of the first node is maintained at the second level; as well as Under the control of the second level of any one of the plurality of gating signals, the potential of the first node is pulled down.

3. The shift register according to claim 1, wherein, The first control circuit, under the control of a first clock signal from a first clock terminal, controls the potential of the first node. The first control circuit is configured to: Under the control of the second level of the first clock signal, the first node is charged by the first voltage of the first power supply, and the potential of the first node is controlled to the second level. as well as When the first clock signal is at the first level, the potential of the first node is kept at the second level.

4. The shift register according to claim 1, further comprising: The pull-down circuit is configured as follows: Under the control of the potential of the first node and the second clock signal, the potential of the third node is pulled down; as well as Under the control of the second level of the third node, the potential of the second node is pulled down.

5. The shift register according to claim 1, further comprising: The reset circuit is configured to reset the fourth node by means of the second voltage of the second power supply under the control of the first clock signal; as well as The potential of the second node is reset under the control of the potential of the first node and the potential of the fourth node.

6. The shift register according to claim 1, further comprising: A third control circuit is electrically connected to the input circuit, and the third control circuit is configured to control the voltage supplied to the input circuit under the control of a first voltage of a first power supply.

7. The shift register according to claim 1, wherein, The output circuit includes multiple output terminals, which are configured to output multiple scan signals, which are used to drive multiple rows of sub-pixel units.

8. The shift register according to claim 1, wherein, The gating circuit includes a tenth transistor, a twelfth transistor, and multiple gating transistors; The control terminals of the tenth transistor and the twelfth transistor are electrically connected to the third node, the first terminals of the tenth transistor and the twelfth transistor are electrically connected to the first node, and the second terminals of the tenth transistor and the twelfth transistor are electrically connected to the first terminals of the plurality of gate transistors. The control electrode of the plurality of gating transistors is electrically connected to the plurality of gating terminals, and the second electrode of the plurality of gating transistors is electrically connected to the first clock terminal.

9. The shift register according to claim 1, wherein, The first control circuit includes a first transistor, an eleventh transistor, a thirteenth transistor, a first capacitor, and a second capacitor; Wherein, the control electrode of the first transistor is electrically connected to the first clock terminal, the first electrode of the first transistor is electrically connected to the first power supply, and the second electrode of the first transistor is electrically connected to the control electrode of the eleventh transistor. The first electrode of the eleventh transistor is electrically connected to the first power supply, and the second electrode of the eleventh transistor is electrically connected to the first node; The control electrode of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the first power supply, and the second electrode of the thirteenth transistor is electrically connected to the gating circuit. The first terminal of the first capacitor is electrically connected to the control electrode of the eleventh transistor, and the second terminal of the first capacitor is electrically connected to the first node; and The first terminal of the second capacitor is electrically connected to the first power source, and the second terminal of the second capacitor is electrically connected to the first node.

10. The shift register according to claim 1, wherein, The second node includes a first sub-node and a second sub-node, and the second control circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor; The control electrode and the first electrode of the fifteenth transistor are electrically connected to the third power supply, and the second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor. The control electrode of the sixteenth transistor is electrically connected to the third power supply, and the second electrode of the sixteenth transistor is electrically connected to the control electrode of the eighteenth transistor; The control electrode of the seventeenth transistor is electrically connected to the first sub-node, the first electrode of the seventeenth transistor is electrically connected to the control electrode of the eighteenth transistor, and the second electrode of the seventeenth transistor is electrically connected to the fourth power supply. The first electrode of the eighteenth transistor is electrically connected to the third power supply, and the second electrode of the eighteenth transistor is electrically connected to the third node; The control electrode of the nineteenth transistor is electrically connected to the second sub-node, the first electrode of the nineteenth transistor is electrically connected to the third node, and the second electrode of the nineteenth transistor is electrically connected to the second power supply.

11. The shift register according to claim 1, wherein, The second node includes a first sub-node and a second sub-node, and the second control circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor; The control electrode and the first electrode of the fifteenth transistor are electrically connected to the first clock terminal, and the second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor. The control electrode of the sixteenth transistor is electrically connected to the first clock terminal, and the second electrode of the sixteenth transistor is electrically connected to the control electrode of the eighteenth transistor; The control electrode of the seventeenth transistor is electrically connected to the first sub-node, the first electrode of the seventeenth transistor is electrically connected to the second power supply, and the second electrode of the seventeenth transistor is electrically connected to the first electrode of the nineteenth transistor; The first terminal of the eighteenth transistor is electrically connected to the second terminal of the fifteenth transistor, and the second terminal of the eighteenth transistor is electrically connected to a first power supply; and The control electrode of the nineteenth transistor is electrically connected to the fourth sub-node, and the second electrode of the nineteenth transistor is electrically connected to the control electrode of the eighteenth transistor.

12. The shift register according to claim 1, wherein, The second node includes a first sub-node and a second sub-node, and the input circuit includes a fourteenth transistor, a twenty-second transistor, and a twenty-fifth transistor; The control electrode of the fourteenth transistor is electrically connected to the second clock terminal, the first electrode of the fourteenth transistor is electrically connected to the first power supply, and the second electrode of the fourteenth transistor is electrically connected to the fourth node. The control electrode of the 22nd transistor is electrically connected to the first node, the first electrode of the 22nd transistor is electrically connected to the fourth node, and the second electrode of the 22nd transistor is electrically connected to the first child node; and The control electrode of the 25th transistor is electrically connected to the first node, the first electrode of the 25th transistor is electrically connected to the fourth node, and the second electrode of the 25th transistor is electrically connected to the second sub-node.

13. The shift register according to claim 4, wherein, The second node includes a first sub-node and a second sub-node, and the pull-down circuit includes a twentieth transistor, a twenty-first transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-sixth transistor, a twenty-seventh transistor, and a twenty-eighth transistor; Wherein, the control electrode of the twentieth transistor is electrically connected to the first node, the first electrode of the twentieth transistor is electrically connected to the third node, and the second electrode of the twentieth transistor is electrically connected to the first electrode of the twentieth eleventh transistor; The control electrode of the 21st transistor is electrically connected to the second clock terminal, and the second electrode of the 21st transistor is electrically connected to the second power supply. The control terminals of the 23rd transistor, the 24th transistor, the 26th transistor, and the 27th transistor are electrically connected to the third node; The 23rd transistor and the 24th transistor are connected in series. The first terminal of the 23rd transistor is electrically connected to the first sub-node, and the second terminal of the 24th transistor is electrically connected to the second power supply. The 26th transistor and the 27th transistor are connected in series, with the first terminal of the 26th transistor electrically connected to the second sub-node and the second terminal of the 27th transistor electrically connected to the second power supply; and The control electrode of the 28th transistor is electrically connected to the first sub-node, the first electrode of the 28th transistor is electrically connected to the second electrode of the 23rd transistor and the second electrode of the 26th transistor, and the second electrode of the 28th transistor is electrically connected to the first power supply.

14. The shift register according to claim 5, wherein, The reset circuit includes a twenty-ninth transistor and a thirtieth transistor; The 29th transistor and the 30th transistor are connected in series. The control electrodes of the 29th transistor and the 30th transistor are electrically connected to the first clock terminal. The first electrode of the 29th transistor is electrically connected to the fourth node. The second electrode of the 30th transistor is electrically connected to the second power supply.

15. A driving circuit comprising M driving unit groups, each driving unit group comprising a plurality of shift registers as described in any one of claims 1-14; in, The m-th drive unit group is electrically connected to the first gating terminal group, and the (m+1)-th drive unit group is electrically connected to the second gating terminal group. The gating signal output by the first gating terminal group is opposite to the gating signal output by the second gating terminal group, 1≤m<M, where M is a positive integer greater than 1.

16. The driving circuit according to claim 15, wherein, The number of first gating terminals in the first gating terminal group is the same as the number of second gating terminals in the second gating terminal group, and the number of first gating terminals is the same as the number of gating transistors in the shift register.

17. The driving circuit according to claim 15, wherein, The multiple shift registers included in the m-th drive unit group are connected in the same way as the multiple first strobe terminals included in the first strobe terminal group, and the multiple shift registers included in the (m+1)-th drive unit group are connected in the same way as the multiple second strobe terminals included in the second strobe terminal group.

18. A display device, comprising: Display panel; as well as The driving circuit as described in any one of claims 15-17; The display panel includes multiple sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

19. A driving method applied to a shift register as described in any one of claims 1-14, comprising: During the gating phase, all of the multiple gating signals are controlled to be at the first level; During the non-gating phase, at least one of the plurality of gating signals is controlled to be at the second level.

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