A method for fabricating a semiconductor device

Abstract

This invention discloses a method for fabricating a semiconductor device. The method includes: providing a substrate; fabricating an epitaxial structure on one side of the substrate; and fabricating a gate and a gate connection structure on the side of the epitaxial structure away from the substrate, wherein the gate connection structure is electrically connected to at least a portion of the gate. The semiconductor device fabrication method provided by this invention, by fabricating a gate connection structure that is electrically connected to at least a portion of the gate, can reduce the influence of gate resistance, improve gain, and reduce leakage current.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor device. Background Technology

[0002] Gallium nitride semiconductor materials have significant advantages such as large bandgap, high electron saturation drift velocity, high breakdown field strength, and high temperature resistance. Compared with first-generation semiconductor silicon and second-generation semiconductor gallium arsenide, they are more suitable for manufacturing high-temperature, high-voltage, high-frequency, and high-power electronic devices, and have broad application prospects. They have become a hot research topic in the semiconductor industry.

[0003] In the field of 5G communication, the bandwidth and high frequency requirements for semiconductor radio frequency devices are very high. Gate structure design and manufacturing process are closely related to the frequency characteristics of semiconductor devices, directly affecting their operating frequency. Therefore, gate structure design is particularly important in the design and fabrication of semiconductor devices, playing a crucial role in their reliability and operational stability.

[0004] For gallium nitride (GaN) RF power amplifiers, achieving a balance between improving the power and gain characteristics of the device is a requirement of application circuits and a goal pursued by GaN RF chips. Specifically, in traditional integrated circuit GaN RF chip designs, the gate power supply is located on one side of the device, while the power supply on the other side of the gate is reduced due to the gate resistance, resulting in a significant decrease in gain. Therefore, how to improve the gain of the semiconductor device while simultaneously increasing its bandwidth and high-frequency performance, thus achieving a performance balance for the power amplifier, has become an urgent problem to be solved. Summary of the Invention

[0005] This invention provides a method for fabricating a semiconductor device to reduce the influence of gate resistance, improve gain, and reduce leakage current.

[0006] This invention provides a method for fabricating a semiconductor device, comprising:

[0007] Provide substrate;

[0008] An epitaxial structure is fabricated on one side of the substrate;

[0009] A gate and a gate connection structure are formed on the side of the epitaxial structure away from the substrate, the gate connection structure being electrically connected to at least a portion of the gate.

[0010] Optionally, a gate and gate connection structure are fabricated on the side of the epitaxial structure away from the substrate, including:

[0011] A gate and a gate connection structure are fabricated on the side of the epitaxial structure away from the substrate using the same process; the gate connection structure includes a first gate connection portion and a second gate connection portion that are interconnected. Along the thickness direction of the semiconductor device, the first gate connection portion does not overlap with the gate, and the second gate connection portion is electrically connected to the gate.

[0012] Optionally, before fabricating the gate and gate connection structure on the side of the epitaxial structure away from the substrate, the method further includes:

[0013] A source electrode is fabricated on the side of the epitaxial structure away from the substrate;

[0014] Along the thickness direction of the semiconductor device, the first gate connection portion overlaps with and is insulated from the source; or, the first gate connection portion is located on the side of the source away from the gate.

[0015] Optionally, the semiconductor device includes an active region and a passive region surrounding the active region;

[0016] The second gate connection portion is located in the active region;

[0017] Alternatively, the gate includes a first gate portion and a second gate portion that are interconnected, the second gate portion being located in the passive region, the second gate connection portion being located in the passive region, and the second gate connection portion being electrically connected to the second gate portion.

[0018] Optionally, a gate and gate connection structure are fabricated on the side of the epitaxial structure away from the substrate, including:

[0019] The source and gate electrodes are respectively fabricated on the side of the epitaxial structure away from the substrate;

[0020] A first dielectric layer is formed on the side of the gate away from the substrate;

[0021] A gate connection structure and a source field plate are fabricated using the same process on the side of the first dielectric layer away from the substrate. The gate connection structure is electrically connected to the gate, and the source field plate is electrically connected to the source.

[0022] Optionally, the thickness of the gate connection structure is greater than the thickness of the first dielectric layer;

[0023] The thickness of the source field plate is greater than the thickness of the first dielectric layer.

[0024] Optionally, the semiconductor device includes an active region and a passive region surrounding the active region;

[0025] The source field plate includes a field plate body and a field plate connecting part that are connected to each other, and the field plate connecting part is electrically connected to the source electrode.

[0026] The gate connection structure includes a first gate connection portion and a second gate connection portion that are interconnected, and the second gate connection portion is electrically connected to the gate.

[0027] Optionally, the semiconductor device includes an active region and a passive region surrounding the active region;

[0028] A gate and gate connection structure are fabricated on the side of the epitaxial structure away from the substrate, including:

[0029] The same process is used to fabricate a source and gate connection structure on the side of the epitaxial structure away from the substrate; the gate connection structure includes a first gate connection portion and a second gate connection portion that are interconnected, the second gate connection portion being located in the passive region;

[0030] A second dielectric layer is prepared on the side of the source and gate connection structure away from the substrate;

[0031] A gate is fabricated on the side of the second dielectric layer away from the substrate. The gate includes a first gate portion and a second gate portion that are interconnected. The second gate portion is located in the passive region. The second gate portion is electrically connected to the second gate connection portion.

[0032] Optionally, a gate and gate connection structure are fabricated on the side of the epitaxial structure away from the substrate, including:

[0033] A gate is fabricated on the side of the epitaxial structure away from the substrate;

[0034] A third dielectric layer is prepared on the side of the gate away from the substrate;

[0035] The gate connection structure and gate pad are fabricated using the same process on the side of the third dielectric layer away from the substrate; the gate connection structure is electrically connected to the gate, and the gate pad is electrically connected to the gate.

[0036] Optionally, a gate and gate connection structure are fabricated on the side of the epitaxial structure away from the substrate, including:

[0037] A gate is fabricated on the side of the epitaxial structure away from the substrate;

[0038] A fourth dielectric layer is prepared on the side of the gate away from the substrate;

[0039] A gate connection structure is formed on the side of the fourth dielectric layer away from the substrate, and the gate connection structure is electrically connected to the gate.

[0040] Optionally, along the thickness direction of the semiconductor device, the gate and the gate connection structure at least partially overlap.

[0041] The semiconductor device fabrication method provided in this invention involves fabricating a gate and a gate connection structure on the side of the epitaxial structure away from the substrate. The gate connection structure is electrically connected to at least a portion of the gate, thereby reducing gate resistance, increasing gate gain, and reducing leakage current. Attached Figure Description

[0042] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0043] Figure 2 A schematic flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention;

[0044] Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0045] Figure 4 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0046] Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0047] Figure 6 A schematic flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention;

[0048] Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0049] Figure 8 for Figure 7 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line A-A';

[0050] Figure 9 A schematic flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention;

[0051] Figure 10 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0052] Figure 11 for Figure 10 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line B-B';

[0053] Figure 12 A schematic flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention;

[0054] Figure 13 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0055] Figure 14 for Figure 13 A schematic diagram of the cross-sectional structure of the provided semiconductor device along the section line C-C';

[0056] Figure 15 A schematic flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention;

[0057] Figure 16 for Figure 13 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line C-C';

[0058] Figure 17 This is a schematic flowchart of another method for fabricating a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0059] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0060] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a method for fabricating a semiconductor device includes:

[0061] S101, Provide substrate.

[0062] For example, the substrate material can be one or a combination of sapphire, silicon carbide, silicon, gallium arsenide, gallium nitride, or aluminum nitride, or other materials suitable for growing gallium nitride. The substrate can be prepared by atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, organometallic chemical vapor deposition, low-pressure chemical vapor deposition, high-density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical-chemical vapor deposition, rapid thermochemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.

[0063] S102. An epitaxial structure is prepared on one side of the substrate.

[0064] For example, the epitaxial structure can be formed from one or more group III-V nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride, and a two-dimensional electron gas can be formed in the epitaxial structure. The growth methods of the epitaxial structure include metal-organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, and liquid phase epitaxy, etc., and the embodiments of the present invention are not limited thereto.

[0065] S103. A gate and a gate connection structure are fabricated on the side of the epitaxial structure away from the substrate, and the gate connection structure is electrically connected to at least a portion of the gate.

[0066] For example, the semiconductor device provided in this embodiment of the invention can be a single-cell structure or a multi-cell structure, and this embodiment of the invention does not limit this. If the semiconductor device is a single-cell structure, the semiconductor device may include a source-gate-drain basic structure; if the semiconductor device is a multi-cell structure, the semiconductor device may include multiple source-gate-drain basic structures. The gate may extend along a first direction, and the multiple gates may be arranged along a second direction, which may be in the same plane as the first direction and perpendicular to the first direction.

[0067] Furthermore, the fabrication method provided in this embodiment of the invention can also fabricate a gate connection structure on the side of the epitaxial structure away from the substrate. The gate connection structure is electrically connected to at least a portion of the gate. Since the gate resistance affects the charging and discharging speed of the junction capacitance, and thus affects the switching speed of the semiconductor device, that is, the smaller the gate resistance, the faster the switching speed of the semiconductor device. By electrically connecting the gate connection structure to at least a portion of the gate, the gate resistance can be reduced, thereby improving the switching speed of the semiconductor device.

[0068] The semiconductor device fabrication method provided in this invention, by fabricating a gate connection structure on the side of the epitaxial structure away from the substrate, and electrically connecting the gate connection structure to at least a portion of the gate, can reduce the influence of gate resistance, improve gain, and reduce leakage current.

[0069] Optional, Figure 2 This is a schematic flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 2 The fabrication method shown provides a detailed explanation of how to fabricate the gate and gate connection structure. For example... Figure 2 As shown, the method for fabricating a semiconductor device includes:

[0070] S201, Provide a substrate.

[0071] S202, Prepare an epitaxial structure on one side of the substrate.

[0072] S203. The gate and gate connection structure are fabricated on the side of the epitaxial structure away from the substrate using the same process.

[0073] Specifically, the gate connection structure includes a first gate connection portion and a second gate connection portion that are interconnected. Along the thickness direction of the semiconductor device, the first gate connection portion does not overlap with the gate, and the second gate connection portion is electrically connected to the gate.

[0074] For example, the gate and gate connection structures can be fabricated using the same process, such as using the same masking process to simultaneously fabricate the gate and gate connection structures, thus simplifying the fabrication process. Furthermore, using the same process to fabricate the gate and gate connection structures ensures that they are disposed in the same layer, maintaining a simple semiconductor device structure.

[0075] Furthermore, Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Figure 4 A schematic diagram of another semiconductor device provided in an embodiment of the present invention, such as... Figure 3 and Figure 4 As shown, the first gate connection portion 1401 and the second gate connection portion 1402 of the gate connection structure 140 are interconnected. Along the thickness direction of the semiconductor device, the first gate connection portion 1401 does not overlap with the gate 130, and the second gate connection portion 1402 is electrically connected to the gate 130. Specifically, the first gate connection portion 1401 has a large area and serves as the main adjustment structure for the gain of the gate 130, optimizing the electric field of the gate 130, reducing the resistance of the gate 130, and increasing the gain of the gate 130. The second gate connection portion 1402 serves as the connection portion between the gate 130 and the gate connection structure 140, ensuring a normal connection between the gate 130 and the gate connection structure 140, and ensuring a reduction in the resistance of the gate 130. Along the thickness direction of the semiconductor device 10, the gate 130 and the first gate connection portion 1401 do not overlap, that is, along the second direction (e.g., ... Figure 3 and Figure 4 (As shown in the X direction) The first gate portion 1301 and the first gate connection portion 1401 do not overlap, i.e., they are staggered. Since the resistance of the gate 130 affects the charging and discharging speed of the junction capacitance, and thus affects the switching speed of the semiconductor device 10, i.e., the smaller the resistance of the gate 130, the faster the switching speed of the semiconductor device 10, the resistance of the gate 130 can be reduced and the switching speed of the semiconductor device 10 can be improved by electrically connecting the second gate connection portion 1402 in the gate connection structure 140 to the gate 130.

[0076] Based on the above embodiments, continue to refer to Figure 3As shown, the semiconductor device 10 includes an active region aa and a passive region bb surrounding the active region aa; the gate 130 includes a first gate portion 1301 and a second gate portion 1302 connected to each other, the second gate portion 1302 is located in the passive region bb, the second gate connection portion 1402 is located in the passive region bb, and the second gate connection portion 1402 is electrically connected to the second gate portion 1302.

[0077] Specifically, the active region aa can be understood as the region beneath which a two-dimensional electron gas, electrons, or holes exist. Its operating state and characteristics are affected by external circuits, and it is the active operating region of the semiconductor device 10. The passive region bb participates in the operation of the semiconductor device 10, but its operating state is not affected by external circuits. For example, the electrode lead-out structure of the active region aa can be set in the passive region bb, and the passive region bb can be set around the active region aa.

[0078] The gate 130 includes a first gate portion 1301 and a second gate portion 1302 that are interconnected. The gate connection structure 140 includes a first gate connection portion 1401 and a second gate connection portion 1402 that are interconnected. The first gate portion 1301 includes a portion located in the active region aa that forms a Schottky contact with the epitaxial structure 120, and a portion extending along the first direction Y to connect with the gate pad 170. The first gate portion 1301 serves as the gate 130 structure of the semiconductor device 10, controlling the on / off state of the gate 130 in the semiconductor device 10, thereby controlling the operating state of the semiconductor device 10. The first gate connection portion 1401 is located in the active region aa and has a large area; as the main adjustment structure for gate gain, it can reduce gate resistance and increase gate gain. The second gate portion 1302 and the second gate connection portion 1402 are both located in the passive region bb and serve as connection portions between the gate 130 and the gate connection structure 140, ensuring normal connection between the gate 130 and the gate connection structure 140 and reducing the resistance of the gate 130. Furthermore, the second gate portion 1302 and the second gate connection portion 1402 are electrically connected in the passive region bb, ensuring that the arrangement of the semiconductor device 10 in the active region aa will not affect the normal operation and performance of the active region aa, thus ensuring the stability of the semiconductor device 10. Moreover, since the passive region bb has a large arrangement space, the second gate portion 1302 and the second gate connection portion 1402 located in the passive region bb can have a large degree of design freedom, facilitating improved connection stability between the second gate portion 1302 and the second gate connection portion 1402.

[0079] Based on the above embodiments, continue to refer to Figure 4As shown, the semiconductor device 10 includes an active region aa and a passive region bb surrounding the active region aa. The second gate connection portion 1402 is located in the active region aa, that is, the gate connection structure 140 and the gate 130 are electrically connected in the active region aa rather than the passive region bb. In this way, while ensuring the reduction of gate resistance, the improvement of switching speed and the improvement of gain, the semiconductor device structure can be kept small, which is conducive to realizing the miniaturized design of the semiconductor device.

[0080] Based on the above embodiments, Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention, combined with... Figure 3 , Figure 4 and Figure 5 It can be understood that, in the preparation method provided in the embodiments of the present invention, before preparing the gate and gate connection structure on the side of the epitaxial structure away from the substrate using the same process, it may further include: preparing the source on the side of the epitaxial structure away from the substrate, and the source and the epitaxial structure forming an ohmic structure.

[0081] Specifically, the source can be connected to the back side of the semiconductor device through a source via. For example, the source via can penetrate the substrate and the epitaxial structure, that is, it can be connected to the source through the source signal input electrode (not shown in the figure) located on the side of the substrate away from the epitaxial structure. In other words, the source is electrically connected to the source signal input electrode through the source via.

[0082] Continue to refer Figure 3 and Figure 4 As shown, along the thickness direction of the semiconductor device 10, the first gate connection portion 1401 overlaps with and is insulated from the source 150.

[0083] For example, continue to refer to Figure 3 and Figure 4 The first gate connection portion 1401 can be located above the source 150 and overlap with the projection of the source 150. On the one hand, the overlap between the first gate connection portion 1401 and the source 150 will not affect the output of the gate 130 signal. On the other hand, the overlap between the first gate connection portion 1401 and the source 150 can reduce the area of ​​the semiconductor device 10. Furthermore, the first gate connection portion 1401 can be located above the source via, which can ensure the stability of the source via region, thereby enabling the semiconductor device 10 to operate normally.

[0084] Continue to refer Figure 5 As shown, the first gate connection portion 1401 is located on the side of the source 150 away from the gate 130.

[0085] For example, continue to refer to Figure 5For a multi-cell semiconductor device, along the second direction X, the first gate connection portion 1401 is located on the side of the source 150 away from the gate 130, and the first gate connection portion 1401 is located between two adjacent sources 150. Two adjacent transistor cells share the same first gate connection portion 1401. Thus, the semiconductor device 10 is no longer arranged with adjacent transistor cells sharing one source, but rather with drain 180, gate 130, source 150, gate connection structure 140, source 150, gate 130, and drain 180. That is, adjacent transistor cells share one first gate connection portion 1401, and each cell has a source 150, a gate 130, and a drain 180. This can reduce the influence of gate resistance, improve gain, and reduce leakage current.

[0086] For example, continue to refer to Figure 5 Along the second direction X, the first gate connection portion 1401 and the two adjacent source electrodes 150 maintain a certain distance and are equally spaced.

[0087] It should be noted that, Figure 5 Taking a semiconductor device with a multi-cell structure as an example, it can be understood that a semiconductor device may also include only a single-cell structure. In this case, the first gate connection portion may also be located on the side of the source far away from the gate in the second direction X, which will not be elaborated here.

[0088] Figure 6 This is a schematic flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 6 The fabrication method shown provides a detailed explanation of how to fabricate the gate and gate connection structure. For example... Figure 6 As shown, the method for fabricating a semiconductor device includes:

[0089] S301, Provide substrate.

[0090] S302. An epitaxial structure is prepared on one side of the substrate.

[0091] S303. The source and gate are fabricated on the side of the epitaxial structure away from the substrate, respectively.

[0092] S304. A first dielectric layer is prepared on the side of the gate away from the substrate.

[0093] S305. On the side of the first dielectric layer away from the substrate, a gate connection structure and a source field plate are fabricated using the same process. The gate connection structure is electrically connected to the gate, and the source field plate is electrically connected to the source.

[0094] Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 8 for Figure 7The provided schematic diagram shows the cross-sectional structure of the semiconductor device along section line A-A', combined with... Figure 7 and Figure 8 As shown, in the fabrication method provided in this embodiment of the invention, a source 150 and a drain 180 are first fabricated on one side of the epitaxial structure 120, and both the source 150 and the drain 180 form an ohmic structure with the epitaxial structure 120. Then, a gate 130 is fabricated on the side of the epitaxial structure 120 away from the substrate 110, between the source 150 and the drain 180, and the gate located in the active region aa forms a Schottky structure with the epitaxial structure 120.

[0095] Next, a first dielectric layer 210 is fabricated on the side of the source 150 and gate 130 away from the substrate 110. The first dielectric layer 210 covers the source 150 and gate 130, and a first connection via K1 and a second connection via K2 can be fabricated in the first dielectric layer 210 using the same mask process. The first connection via K1 exposes a portion of the gate 130, and the second connection via K2 exposes a portion of the source 150. Exemplarily, the first dielectric layer 210 can be made of materials such as silicon dioxide, silicon nitride, and aluminum oxide. The fabrication method of the first dielectric layer 210 includes physical vapor deposition and chemical vapor deposition. The first dielectric layer 210 can cover the electrode structure.

[0096] Next, the gate connection structure 140 and the source field plate 160 are fabricated on the side of the first dielectric layer 210 away from the substrate 110 using the same process. The gate connection structure 140 is electrically connected to the gate 130 through the first connection via K1, and the source field plate 160 is electrically connected to the source 150 through the second connection via K2.

[0097] The first connection via K1 exposes a portion of the gate 130, allowing the growth of a gate connection structure 140 within this exposed area. The gate connection structure 140 is electrically connected to the gate 130 via K1. This reduces the resistance of the gate 130, increases gain, and improves connection stability, thereby ensuring the performance of the semiconductor device. Furthermore, the second connection via K2 exposes a portion of the source 150, allowing the growth of a source field plate 160 within this exposed area. The source field plate 160 is electrically connected to the source 150 via K2. This reduces the resistance of the source 150 and improves connection stability, further ensuring the performance of the semiconductor device. Moreover, the gate connection structure 140 and the source field plate 160 are co-layered and fabricated in the same process. This simplifies the process flow, avoids unnecessary film layers, simplifies masking, and facilitates thinner semiconductor device designs.

[0098] It should also be noted that the first dielectric layer in the embodiments of the present invention may refer to a single dielectric layer or multiple dielectric layers, and the embodiments of the present invention do not limit this.

[0099] In summary, the fabrication method provided by the embodiments of the present invention simplifies the process flow by using the same material to fabricate the gate connection structure and the source field plate in the same process, thereby avoiding the setting of redundant film layers and simplifying the masking process. On the other hand, it is beneficial to realize the thinner and lighter design of semiconductor devices.

[0100] Further reference Figure 8 As shown, the thickness of the gate connection structure 140 is greater than the thickness of the first dielectric layer 210; the thickness of the source field plate 160 is greater than the thickness of the first dielectric layer 210. This arrangement can reduce the gate parasitic capacitance, thereby ensuring the working performance of the semiconductor device.

[0101] Further reference Figure 7 and then Figure 8 As shown, the semiconductor device 10 includes an active region aa and an unreacted region bb surrounding the active region aa; the source field plate 160 includes a field plate body 1601 and a field plate connection portion 1602, the field plate connection portion 1602 being electrically connected to the source 150 through a second connection via K2; the gate connection structure 140 includes a first gate connection portion 1401 and a second gate connection portion 1402 connected to each other, the second gate connection portion 1402 being electrically connected to the gate 130 through the first connection via K1; the field plate connection portion 1602 is offset from the first connection via K1; the second gate connection portion 1402 is offset from the second connection via.

[0102] Specifically, the field plate connection portion 1602 is electrically connected to the source electrode 150 through the second connection via, thereby realizing the electrical connection between the source field plate 160 and the source electrode 150. Furthermore, the field plate connection portion 1602 is staggered from the first connection via K1, meaning the projections do not overlap, preventing the field plate connection portion 1602 from overlapping with the gate connection structure 140, thus avoiding mutual interference. In addition, the second gate connection portion 1402 is staggered from the second connection via K2, thus preventing mutual interference between the source field plate 160 and the second gate connection portion 1402 in the gate connection structure 140, thereby ensuring the operating performance of the semiconductor device 10.

[0103] It should be noted that, Figure 7Taking the second gate connection portion 1402 located in the passive region as an example, it can be understood that the second gate connection portion 1402 can be located in the active region aa or the passive region bb. Regardless of whether the second gate connection portion 1402 is located in the active region aa or the passive region bb, the second gate connection portion 1402 is staggered from the second connection via K2 to avoid mutual interference between the source field plate 160 and the gate connection structure 140.

[0104] Optional, continue to refer to Figure 7 As shown, the semiconductor device 10 includes an active region aa and a passive region bb surrounding the active region aa;

[0105] The gate connection structure 140 includes a first gate connection portion 1401 and a second gate connection portion 1402 that are connected to each other. The second gate connection portion 1402 is electrically connected to the gate 130 through a first connection via K1.

[0106] The second gate connection portion 1402 is located in the passive region bb; the total opening area of ​​the second connection via K2 is S1, and the area of ​​the source is S2; wherein S1 / S2≥50%.

[0107] Specifically, the source field plate 160 is electrically connected to the source 150 through the second connection via K2. The total opening area S1 of the second connection via K2 and the area S2 of the source 150 satisfy S1 / S2≥50%, that is, the total opening area of ​​the second connection via K2 is greater than half of the area of ​​the source 150. This allows for a larger exposed area of ​​the source 150 on the first dielectric layer 210, enabling the exposed source metal to be electrically connected to the source field plate 160 over a large area through the second connection via K2. This achieves the function of the source field plate on the one hand, and ensures connection stability on the other.

[0108] Figure 9 This is a schematic flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 10 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 11 for Figure 10 The provided schematic diagram shows the cross-sectional structure of the semiconductor device along section line B-B', combined with... Figure 9 , Figure 10 and Figure 11 As shown, the method for fabricating a semiconductor device provided in this embodiment of the invention includes:

[0109] S401, Provide substrate.

[0110] S402. An epitaxial structure is prepared on one side of the substrate.

[0111] S403. The source and gate connection structure are fabricated on the side of the epitaxial structure away from the substrate using the same process; the gate connection structure includes a first gate connection portion and a second gate connection portion that are interconnected, and the second gate connection portion is located in the passive region.

[0112] For example, the gate connection structure 140 and the source 150 are disposed in the same layer and fabricated in the same process. This simplifies the process flow, avoids the setting of extra film layers, simplifies the mask process, and facilitates the realization of thinner and lighter semiconductor devices.

[0113] Furthermore, the gate connection structure 140 includes a first gate connection portion 1401 and a second gate connection portion 1402 that are interconnected. Since the gate connection structure 140 needs to be electrically connected to the gate 130, the second gate connection portion 1402 can be located in the passive region bb. In this way, when the second gate connection portion 1402 is electrically connected to the gate 130, a short circuit will not be caused between the gate connection structure 140 and the source 150.

[0114] S404. A second dielectric layer is prepared on the side of the source and gate connection structure away from the substrate.

[0115] For example, a second dielectric layer 220 is formed on the side of the source 150 and the gate connection structure 140 away from the substrate 110. The second dielectric layer 220 can cover the source 150 and the gate connection structure 140. Furthermore, a third connection via K3 can be formed in the second dielectric layer 220. The third connection via K3 exposes a portion of the second gate connection portion, facilitating the subsequent electrical connection of the gate 130 to the second gate connection portion 1402 through the third connection via K3.

[0116] Furthermore, the second dielectric layer 220 can be made of materials such as silicon dioxide, silicon nitride, and aluminum oxide. The preparation methods for the second dielectric layer 220 include physical vapor deposition and chemical vapor deposition.

[0117] S405. A gate is fabricated on the side of the second dielectric layer away from the substrate. The gate includes a first gate portion and a second gate portion that are interconnected. The second gate portion is located in the passive region. The second gate portion is electrically connected to the second gate connection portion.

[0118] Specifically, the gate 130 includes a first gate portion 1301 and a second gate portion 1302 that are interconnected. The second gate portion 1302 is electrically connected to the second gate connection portion 1402 through a third connection via K3. This achieves the electrical connection between the gate 130 and the gate connection portion 140, which helps to reduce the gate impedance and improve the performance of the semiconductor device.

[0119] It should be noted that the second dielectric layer in the embodiments of the present invention may refer to a single dielectric layer or multiple dielectric layers, and the embodiments of the present invention do not limit this.

[0120] In summary, the fabrication method provided by the embodiments of the present invention, by using the same process to fabricate the source and gate connection structure on the side of the epitaxial structure away from the substrate, can simplify the process flow, avoid the setting of extra film layers, simplify the mask process, and facilitate the realization of thinner and lighter semiconductor device designs.

[0121] Figure 12 This is a schematic flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 13 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 14 for Figure 13 The provided schematic diagram shows the cross-sectional structure of the semiconductor device along section line C-C', combined with... Figure 12-14 As shown, the preparation method provided in this embodiment of the invention includes:

[0122] S501, Provides a substrate.

[0123] S502, Prepare an epitaxial structure on one side of the substrate.

[0124] S503. A gate is fabricated on the side of the epitaxial structure away from the substrate.

[0125] S504. A third dielectric layer is prepared on the side of the gate away from the substrate.

[0126] For example, a third dielectric layer 230 is prepared on the side of the gate 130 away from the substrate 110, and the third dielectric layer 230 can cover the gate 130. Furthermore, a fourth connection via K4 and a fifth connection via K5 can be prepared in the third dielectric layer 230, both of which expose a portion of the gate 130, facilitating the subsequent electrical connection between the gate connection structure 140 and the gate field plate 170 and the gate 130 through the fourth connection via K4 and the fifth connection via K5.

[0127] Furthermore, the third dielectric layer 230 can be made of materials such as silicon dioxide, silicon nitride, and aluminum oxide. The preparation methods for the third dielectric layer 230 include physical vapor deposition and chemical vapor deposition.

[0128] S505. The gate connection structure and gate pad are fabricated using the same process on the side of the third dielectric layer away from the substrate; the gate connection structure is electrically connected to the gate, and the gate pad is electrically connected to the gate.

[0129] For example, the gate connection structure 140 and the gate pad 170 can be set in the same layer and fabricated in the same process. This can simplify the process flow, avoid the setting of extra film layers, simplify the mask process, and facilitate the realization of thinner and lighter semiconductor devices.

[0130] It should be noted that when the gate connection structure and the gate pad are disposed in the same layer and fabricated in the same process, the gate connection structure and the gate can be connected in the passive region or in the active region. This embodiment of the invention does not limit this. Figure 13 Taking the connection between the gate connection structure 140 and the gate 130 in the passive region bb as an example, the gate 130 includes a first gate portion 1301 and a second gate portion 1302 that are connected to each other, and the second gate portion 1302 is located in the passive region bb; correspondingly, the gate connection structure 140 includes a first gate connection portion 1401 and a second gate connection portion 1402 that are connected to each other, and the second gate connection portion 1402 is located in the passive region. The second gate connection portion 1402 is electrically connected to the second gate portion 1302 in the passive region through the fourth connection via K4.

[0131] It should also be noted that the gate connection structure and the gate pad are disposed in the same layer and fabricated in the same process, and the gate connection structure and the gate pad can be made of the same material. Figure 13 In order to distinguish between the gate connection structure and the gate pad, different fillers are used for the gate connection structure and the gate pad. This is only to distinguish the different results, not to limit the materials.

[0132] It should also be noted that the third dielectric layer in the embodiments of the present invention may refer to a single dielectric layer or multiple dielectric layers, and the embodiments of the present invention do not limit this.

[0133] In summary, the fabrication method provided by the embodiments of the present invention, by using the same process to fabricate the gate connection structure and gate pad, can simplify the process flow, avoid the setting of redundant film layers, simplify the mask process, and facilitate the realization of thinner and lighter semiconductor device designs.

[0134] Continue to refer Figure 13 and Figure 14 As shown, the semiconductor device 10 includes an active region aa and a passive region bb surrounding the active region aa; the fourth connection via K4 and the fifth connection via K5 are located on opposite sides of the passive regions bb of the active region aa. This ensures a simple connection relationship between the gate 130 and the gate pad 170 and the gate connection structure 140, avoiding complex via fabrication processes when connecting on the same side.

[0135] Figure 15This is a schematic flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 16 for Figure 13 The provided schematic diagram shows another cross-sectional structure of the semiconductor device along section line C-C', combined with... Figure 15 and Figure 16 As shown, the preparation method provided in this embodiment of the invention includes:

[0136] S601, Provides a substrate.

[0137] S602. An epitaxial structure is prepared on one side of the substrate.

[0138] S603. A gate is fabricated on the side of the epitaxial structure away from the substrate.

[0139] S604. A fourth dielectric layer is prepared on the side of the gate away from the substrate.

[0140] For example, a fourth dielectric layer 240 is formed on the side of the gate 130 away from the substrate 110, and the fourth dielectric layer 240 can cover the gate 130. Furthermore, a sixth connection via K6 can be formed in the fourth dielectric layer 240, and the sixth connection via K6 exposes part of the gate 130, so that the subsequent gate connection structure 140 can be electrically connected to the gate 130 through the sixth connection via K6.

[0141] Furthermore, the fourth dielectric layer 240 can be made of materials such as silicon dioxide, silicon nitride, and aluminum oxide. The preparation methods for the fourth dielectric layer 240 include physical vapor deposition and chemical vapor deposition.

[0142] S605. A gate connection structure is fabricated on the side of the fourth dielectric layer away from the substrate, and the gate connection structure is electrically connected to the gate.

[0143] For example, a gate connection structure 140 is fabricated on the side of the fourth dielectric layer 240 away from the substrate 110. The gate connection structure 140 is electrically connected to the gate 130 through a sixth connection via K6, thereby reducing gate resistance, reducing leakage current, and improving the performance of the semiconductor device.

[0144] It should be noted that the fourth dielectric layer in the embodiments of the present invention may refer to a single dielectric layer or a multilayer dielectric layer, and the embodiments of the present invention do not limit it in this regard.

[0145] In summary, the preparation method provided by the embodiments of the present invention can independently prepare the gate connection structure, reducing the film layer and process limitations of the gate connection structure, increasing the degree of freedom in preparing the gate connection structure, reducing the difficulty in preparing the gate connection structure, and improving the preparation efficiency.

[0146] Based on the above embodiments, continue to refer to Figure 13As shown, along the thickness direction of the semiconductor device, the gate 130 and the gate connection structure 140 overlap at least partially, thereby reducing the area of ​​the semiconductor device along the second direction X and realizing the miniaturization design of the semiconductor device.

[0147] It should be noted that continued reference is necessary. Figure 3 , Figure 4 , Figure 5 , Figure 1 , Figure 10 and Figure 13 As shown, the fabrication method provided in this embodiment of the invention may further include fabricating a drain 180 and a drain pad 190. The drain 180 and the drain pad 190 are electrically connected in the passive region bb, facilitating the provision of a drain signal to the drain 180 through the drain pad 190. Furthermore, the drain 180 can be fabricated in the same process and co-layered with the source 150, and the drain pad 190 can be fabricated in the same process and co-layered with the gate pad 170, ensuring a simple semiconductor device fabrication process and a simple film layer configuration.

[0148] Optional, Figure 17 This is a schematic flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 17 As shown, the method for fabricating a semiconductor device includes:

[0149] S701, provides a substrate.

[0150] S702. A nucleation layer is prepared on one side of the substrate.

[0151] For example, continue to refer to Figure 4 The nucleation layer 1201 can be made of aluminum nitride and is located between the substrate 110 and the buffer layer 1202, serving to bond the semiconductor material layer that needs to be grown next.

[0152] S1003. Prepare a buffer layer on the side of the nucleation layer away from the substrate.

[0153] For example, continue to refer to Figure 8 , Figure 11 , Figure 14 and Figure 16 The buffer layer 1202 is located on one side of the substrate. The material of the buffer layer 1202 can be gallium nitride, and the buffer layer 1202 can include iron atoms, which is beneficial to achieve the high resistance performance of the buffer layer 1202, ensuring that it can block vertical leakage current and improve the pinch-off performance of semiconductor devices.

[0154] S704. Prepare a channel layer on the side of the buffer layer away from the substrate.

[0155] For example, continue to refer to Figure 8 , Figure 11 , Figure 14 and Figure 16 The channel layer 1203 can be a group III nitride, such as Al. x Ga 1－x N, where 0 ≤ x < 1, means that the energy at the interface between the channel layer 1203 and the barrier layer 1204, i.e., the energy at the conduction band edge of the channel layer 1203, is less than the energy at the conduction band edge of the barrier layer 1204. For example, x = 0 indicates that the channel layer 1203 is GaN. The channel layer 1203 can also be other Group III nitrides, such as InGaN or AlInGaN. The channel layer 1203 can be undoped or unintentionally doped. The channel layer 1203 can also be a multilayer structure, such as a combination of a superlattice, GaN, or AlGaN.

[0156] S705. A barrier layer is prepared on the side of the channel layer away from the substrate, and the barrier layer and the channel layer form a heterojunction structure.

[0157] For example, continue to refer to Figure 8 , Figure 11 , Figure 14 and Figure 16 The barrier layer 1204 can be AlN, AlInN, AlGaN, or AlInGaN. The barrier layer 1204 has sufficient thickness and a sufficiently high Al composition to create a significant carrier concentration at the interface between the channel layer 1203 and the barrier layer 1204. For example, the thickness of the barrier layer 1204 can be 20 nm, and the Al doping concentration can be 25%.

[0158] For example, continue to refer to Figure 4 The channel layer 1203 may include GaN, while the barrier layer 1204 may include AlGaN. That is, the material of the barrier layer 1204 has a higher band gap than the material of the channel layer 1203, and the channel layer 1204 may also have a greater electron affinity than the barrier layer 1204. Due to the band gap difference between the barrier layer 1204 and the channel layer 1203, and the piezoelectric effect at the interface between the barrier layer 1204 and the channel layer 1203, a two-dimensional electron gas (2DEG) is formed between the channel layer 1203 and the barrier layer 1204.

[0159] Understandably, epitaxial structures can also include a cap layer, which is located on the surface of the barrier layer away from the substrate. The cap layer can reduce surface states, reduce surface leakage current in subsequent semiconductor devices, and suppress current collapse, thereby improving the performance and reliability of the epitaxial structure and semiconductor devices.

[0160] S706. A gate and a gate connection structure are prepared on the side of the epitaxial structure away from the substrate, wherein the gate connection structure is electrically connected to at least a portion of the gate.

[0161] The semiconductor device fabrication method provided in this invention ensures the complete fabrication of the semiconductor device epitaxial structure by sequentially fabricating a core layer, a buffer layer, a channel layer, and a barrier layer on one side of the substrate. Furthermore, by fabricating a gate connection structure on the side of the gate away from the substrate, the gate connection structure is electrically connected to at least a portion of the gate, which reduces the influence of the gate resistance, improves the gain, maintains an optimized gate electric field, and reduces leakage current.

[0162] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; An epitaxial structure is fabricated on one side of the substrate; A gate and a gate connection structure are fabricated on the side of the epitaxial structure away from the substrate, the gate connection structure being electrically connected to at least a portion of the gate; The semiconductor device includes an active region and a passive region surrounding the active region; the semiconductor device also includes a drain and a gate pad; The gate connection structure includes a first gate connection portion and a second gate connection portion that are interconnected; the first gate connection portion extends along a first direction and includes a portion located in the passive region and a portion located in the active region, wherein the first gate connection portion located in the passive region is electrically connected to a gate pad; the second gate connection portion extends along a second direction, and a gap is included between the gate and the drain along the second direction; the orthographic projection of the gate connection structure on the substrate and the orthographic projection of the gap on the substrate do not overlap; The second direction is in the same plane as the first direction and is perpendicular to the first direction.

2. The preparation method according to claim 1, characterized in that, A gate and gate connection structure are fabricated on the side of the epitaxial structure away from the substrate, including: The same process is used to fabricate a gate and a gate connection structure on the side of the epitaxial structure away from the substrate; along the thickness direction of the semiconductor device, the first gate connection portion does not overlap with the gate, and the second gate connection portion is electrically connected to the gate.

3. The preparation method according to claim 2, characterized in that, Before fabricating the gate and gate connection structure on the side of the epitaxial structure away from the substrate, the method further includes: A source electrode is fabricated on the side of the epitaxial structure away from the substrate; Along the thickness direction of the semiconductor device, the first gate connection portion overlaps with and is insulated from the source; or, the first gate connection portion is located on the side of the source away from the gate.

4. The preparation method according to claim 2, characterized in that, The second gate connection portion is located in the active region; Alternatively, the gate includes a first gate portion and a second gate portion that are interconnected, the second gate portion being located in the passive region, the second gate connection portion being located in the passive region, and the second gate connection portion being electrically connected to the second gate portion.

5. The preparation method according to claim 1, characterized in that, A gate and gate connection structure are fabricated on the side of the epitaxial structure away from the substrate, including: The source and gate electrodes are respectively fabricated on the side of the epitaxial structure away from the substrate; A first dielectric layer is formed on the side of the gate away from the substrate; A gate connection structure and a source field plate are fabricated using the same process on the side of the first dielectric layer away from the substrate. The gate connection structure is electrically connected to the gate, and the source field plate is electrically connected to the source.

6. The preparation method according to claim 5, characterized in that, The thickness of the gate connection structure is greater than the thickness of the first dielectric layer; The thickness of the source field plate is greater than the thickness of the first dielectric layer.

7. The preparation method according to claim 5, characterized in that, The semiconductor device includes an active region and a passive region surrounding the active region; The source field plate includes a field plate body and a field plate connecting part that are connected to each other, and the field plate connecting part is electrically connected to the source electrode. The gate connection structure includes a first gate connection portion and a second gate connection portion that are interconnected, and the second gate connection portion is electrically connected to the gate.

8. The preparation method according to claim 1, characterized in that, A gate and gate connection structure are fabricated on the side of the epitaxial structure away from the substrate, including: The same process is used to fabricate a source and gate connection structure on the side of the epitaxial structure away from the substrate; the gate connection structure includes a first gate connection portion and a second gate connection portion that are interconnected, the second gate connection portion being located in the passive region; A second dielectric layer is prepared on the side of the source and gate connection structure away from the substrate; A gate is fabricated on the side of the second dielectric layer away from the substrate. The gate includes a first gate portion and a second gate portion that are interconnected. The second gate portion is located in the passive region. The second gate portion is electrically connected to the second gate connection portion.

9. The preparation method according to claim 1, characterized in that, A gate and gate connection structure are fabricated on the side of the epitaxial structure away from the substrate, including: A gate is fabricated on the side of the epitaxial structure away from the substrate; A third dielectric layer is prepared on the side of the gate away from the substrate; The gate connection structure and gate pad are fabricated using the same process on the side of the third dielectric layer away from the substrate; the gate connection structure is electrically connected to the gate, and the gate pad is electrically connected to the gate.

10. The preparation method according to claim 1, characterized in that, A gate and gate connection structure are fabricated on the side of the epitaxial structure away from the substrate, including: A gate is fabricated on the side of the epitaxial structure away from the substrate; A fourth dielectric layer is prepared on the side of the gate away from the substrate; A gate connection structure is formed on the side of the fourth dielectric layer away from the substrate, and the gate connection structure is electrically connected to the gate.

11. The preparation method according to claim 10, characterized in that, Along the thickness direction of the semiconductor device, the gate and the gate connection structure at least partially overlap.

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