A semiconductor device

Abstract

The embodiment of the present application discloses a semiconductor device, which comprises a gate located on the side of an epitaxial structure far from a substrate; the gate extends along a first direction, and the gate comprises a first gate subpart and a second gate subpart connected with each other; at least one gate connecting structure is located on the side of the gate far from the substrate; the gate connecting structure comprises a first gate connecting subpart and a second gate connecting subpart connected with each other, and the second gate connecting subpart is located in a passive region; along the thickness direction of the semiconductor device, the first gate connecting subpart at least partially overlaps with the first gate subpart, the second gate connecting subpart at least partially overlaps with the second gate subpart, and the second gate connecting subpart is electrically connected with at least part of the second gate subpart. The semiconductor device provided by the present application can reduce the influence of the gate resistance, improve the gain, and improve the switching speed of the device by electrically connecting the gate connecting structure with at least part of the gate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor device. Background Technology

[0002] Gallium nitride (GaN), a semiconductor material, has become a research hotspot due to its large bandgap, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity. In electronic devices, GaN is more suitable than silicon and gallium arsenide for manufacturing high-temperature, high-frequency, high-voltage, and high-power devices, showing broad application prospects and thus becoming a current research focus in the semiconductor industry.

[0003] In the field of 5G communication, the bandwidth and high frequency requirements for semiconductor radio frequency devices are very high. Gate structure design and manufacturing process are closely related to the frequency characteristics of semiconductor devices, directly affecting their operating frequency. Therefore, gate structure design is particularly important in the design and fabrication of semiconductor devices, playing a crucial role in their reliability and operational stability.

[0004] For gallium nitride (GaN) RF power amplifiers, achieving a balance between improving the power and gain characteristics of the device is a requirement of application circuits and a goal pursued by GaN RF chips. Specifically, in traditional integrated circuit GaN RF chip designs, the gate power supply is located on one side of the device, while the power supply on the other side of the gate is reduced due to the gate resistance, resulting in a significant decrease in gain. Therefore, how to improve the gain of the semiconductor device while simultaneously increasing its bandwidth and high-frequency performance, thus achieving a performance balance for the power amplifier, has become an urgent problem to be solved. Summary of the Invention

[0005] This invention provides a semiconductor device that reduces the influence of gate resistance, thereby improving gain and device switching speed.

[0006] This invention provides a semiconductor device including an active region and a passive region surrounding the active region;

[0007] The semiconductor device further includes:

[0008] Substrate;

[0009] An epitaxial structure is located on one side of the substrate;

[0010] A gate is located on the side of the epitaxial structure away from the substrate; the gate extends along a first direction, which is parallel to the plane of the substrate; the gate includes a first gate portion and a second gate portion connected to each other, the first gate portion forming a Schottky contact with the epitaxial structure, and the second gate portion being located in the passive region;

[0011] At least one gate connection structure is located on the side of the gate away from the substrate; the gate connection structure includes a first gate connection portion and a second gate connection portion connected to each other, the second gate connection portion being located in the passive region; along the thickness direction of the semiconductor device, the first gate connection portion at least partially overlaps with the first gate portion, the second gate connection portion at least partially overlaps with the second gate portion, and the second gate connection portion is electrically connected to at least a portion of the second gate portion.

[0012] Optionally, the area of ​​the gate connection structure is larger than the area of ​​the gate.

[0013] Optionally, the area of ​​the gate connection structure is S1, and the area of ​​the gate is S2;

[0014] Where S1 / S2≥1.5.

[0015] Optionally, the gate connection structure covers the gate along the thickness direction of the semiconductor device.

[0016] Optionally, the second gate portion includes a first sub-portion and a second sub-portion, wherein the first sub-portion is located on the side of the second sub-portion away from the active region and along a second direction, and the size of the first sub-portion is larger than the size of the second sub-portion; the second direction intersects the first direction and is parallel to the plane of the substrate.

[0017] The second gate connection portion is electrically connected to the first sub-portion.

[0018] Optionally, the semiconductor device further includes a source electrode and a source field plate;

[0019] The source field plate is located between the film layer containing the gate and the film layer containing the gate connection structure.

[0020] Optionally, the size of the second gate portion along the first direction is larger than the size of the source field plate in the passive region, and the size of the second gate connection portion is larger than the size of the source field plate in the passive region.

[0021] Optionally, the semiconductor device further includes a first dielectric layer located between the film layer containing the source field plate and the film layer containing the gate, and a second dielectric layer located between the film layer containing the source field plate and the film layer containing the gate connection structure.

[0022] Along the thickness direction of the semiconductor device, the source field plate overlaps with the first gate, and the thickness d1 of the first dielectric layer satisfies d1≥300nm;

[0023] And / or, the source field plate overlaps with the first gate connection structure, and the thickness d2 of the second dielectric layer satisfies d2≥300nm.

[0024] Optionally, the gate connection structure is electrically connected to the gate via a connecting post;

[0025] The connecting post includes a first connecting post portion located in the first dielectric layer and a second connecting post portion located in the second dielectric layer;

[0026] The first connecting post portion and the second connecting post portion are integrally formed and integrally formed with the gate connection structure; or, the first connecting post portion is integrally formed with the source field plate, and the second connecting post portion is integrally formed with the gate connection structure.

[0027] Optionally, the semiconductor device further includes a gate pad, which is located in the passive region on the first side of the active region along the first direction, and the first gate portion and the first gate connection portion are both electrically connected to the gate pad.

[0028] The first gate connection portion is disposed on the same layer as the gate pad.

[0029] The semiconductor device provided in this embodiment of the invention reduces gate resistance, increases gate gain, and improves device switching speed by providing at least one gate connection structure in the semiconductor device and electrically connecting it to at least a portion of the gate. Furthermore, the first gate connection portion at least overlaps with the first gate portion, which reduces the area of ​​the semiconductor device, ensuring a compact semiconductor device structure and facilitating miniaturized device design. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0031] Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line A-A';

[0032] Figure 3 yes Figure 1 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line B-B';

[0033] Figure 4 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0034] Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0035] Figure 6 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0036] Figure 7 yes Figure 6 A schematic diagram of the cross-sectional structure of the provided semiconductor device along the section line F-F';

[0037] Figure 8 yes Figure 6 A schematic diagram of the cross-sectional structure of the provided semiconductor device along the section line E-E';

[0038] Figure 9 yes Figure 6 A schematic diagram of another cross-sectional structure of the provided semiconductor device along the section line E-E'. Detailed Implementation

[0039] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0040] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line A-A'. Figure 3 yes Figure 1 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line B-B'. (See diagram below.) Figures 1-3 As shown, the semiconductor device 10 includes: an active region aa and a passive region bb surrounding the active region aa; the semiconductor device 10 also includes: a substrate 110; an epitaxial structure 120 located on one side of the substrate 110; a gate 130 located on the side of the epitaxial structure 120 away from the substrate 110; the gate 130 is along a first direction (e.g., Figure 1 Extending along the Y direction shown in the figure, the first direction Y and the second direction X intersect and are both parallel to the plane where the substrate 110 is located; the gate 130 includes a first gate portion 1301 and a second gate portion 1302 that are interconnected, the first gate portion 1301 forms a Schottky contact with the epitaxial structure 120, and the second gate portion 1302 is located in the passive region bb; at least one gate connection structure 140 is located on the side of the gate 130 away from the substrate 110; the gate connection structure 140 includes a first gate connection portion 1401 and a second gate connection portion 1402 that are interconnected, and the second gate connection portion 1402 is located in the passive region bb; along the thickness direction of the semiconductor device (e.g., Figure 2(as shown in the Z direction), the first gate connection portion 1401 and the first gate portion 1301 at least partially overlap, the second gate connection portion 1402 and the second gate portion 1302 at least partially overlap, and the second gate connection portion 1402 is electrically connected to at least a portion of the second gate portion 1302.

[0041] For details, please refer to [link / reference]. Figure 1 The active region aa can be understood as the region beneath which a two-dimensional electron gas, electrons, or holes exist. Its operating state and characteristics are affected by external circuits, and it is the active operating region of the semiconductor device 10. The passive region bb participates in the operation of the semiconductor device 10, but its operating state is not affected by external circuits. For example, the electrode lead-out structure of the active region aa can be set in the passive region bb, and the passive region bb can be set around the active region aa.

[0042] For example, refer to Figure 1 and Figure 2 The substrate 110 in the semiconductor device 10 can be formed from one of the following materials: silicon, sapphire, silicon carbide, and gallium arsenide. The epitaxial structure 120 located on one side of the substrate 110 can be formed from one or more of the following group III-V nitrides: gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride.

[0043] It should be noted that, Figure 1 The example given is a semiconductor device 10 that includes multiple gates 130. It can be understood that the semiconductor device 10 may also include only one gate 130, i.e., a single-cell structure with a source 150, a gate 130, and a drain 180.

[0044] For example, continue to refer to Figure 1 and Figure 2At least one gate connection structure 140 can be made of a conductive metal, which can be a low-resistance conductive material to facilitate the reduction of the gate 130 resistance. Specifically, the gate 130 includes a first gate portion 1301 and a second gate portion 1302 that are interconnected. The first gate portion 1301 forms a Schottky contact with the epitaxial structure 140, and the second gate portion 1302 is located in the passive region bb. As the gate 130 structure of the semiconductor device 10, it controls the on / off state of the gate 130 in the semiconductor device 10, thereby controlling the operating state of the semiconductor device 10. The first gate connection portion 1401 is located in the active region aa and has a large area. As the main adjustment structure for the gate 130 gain, it reduces the gate 130 resistance and increases the gate 130 gain. The second gate portion 1302 and the second gate connection portion 1402 are both located in the passive region bb and serve as the connection portions between the gate 130 and the gate connection structure 140, ensuring normal connection between the gate 130 and the gate connection structure 140 and reducing the gate 130 resistance. Furthermore, the second gate connection portion 1402 is electrically connected to at least a portion of the second gate portion 1302, which can reduce the resistance of the gate 130, thereby reducing the impact of the gate 130 resistance, improving gain, and increasing the device switching speed. In addition, along the thickness direction Z of the semiconductor device 10, the first gate connection portion 1401 and the first gate portion 1301 at least partially overlap, and the second gate connection portion 1402 and the second gate portion 1302 at least partially overlap. This facilitates the electrical connection between the second gate connection portion 1402 and at least a portion of the second gate portion 1302, and also reduces the area of ​​the semiconductor device 10, ensuring a compact structure and facilitating miniaturized device design.

[0045] In summary, the semiconductor device provided by the embodiments of the present invention, by providing at least one gate connection structure in the semiconductor device and electrically connecting at least a portion of the second gate portion through the second gate connection portion, can reduce gate resistance, increase gate gain, and improve device switching speed. Furthermore, the fact that the first gate connection portion and the first gate portion at least overlap can reduce the area of ​​the semiconductor device, ensuring a compact semiconductor device structure and facilitating miniaturized device design.

[0046] Optional, continue to refer to Figure 1 and Figure 3 At least a portion of the second gate portion 1302 is electrically connected to the second gate connection portion 1402 via a connection via M; along the second direction X, the size of the connection via M is smaller than the size of the second gate portion 1302 and the size of the second gate connection portion 1402.

[0047] Specifically, at least a portion of the second gate portion 1302 and the second gate connection portion 1402 are electrically connected through a connection via M. This means that the second gate portion 1302 and the second gate connection portion 1402 are electrically connected in the passive region bb. This ensures that the arrangement of the semiconductor device 10 in the active region aa will not affect the normal operation and performance of the active region aa, thus guaranteeing the stability of the semiconductor device 10. Furthermore, since the passive region bb has a large arrangement space, the electrical connection between the second gate portion 1302 and the second gate connection portion 1402 in the passive region bb through the connection via M allows for greater design freedom in the passive region bb, facilitating improved connection stability between the second gate portion 1302 and the second gate connection portion 1402.

[0048] Specifically, along the second direction X, the size of the connecting via M is smaller than the size of the second gate portion 1302 and the size of the second gate connection portion 1402, which can ensure that the second gate connection portion 1402 and the second gate portion 1302 are fully electrically connected, further reducing the resistance of the gate 130 and reducing the leakage current of the gate 130.

[0049] Optional, continue to refer to Figure 1 The area of ​​the gate connection structure 140 is larger than the area of ​​the gate 130.

[0050] Specifically, the area of ​​the gate connection structure 140 is larger than the area of ​​the gate 130. This can be understood as the product of the dimensions of the gate connection structure 140 along the first direction Y and the second direction X being greater than the product of the dimensions of the gate 130 along the first direction Y and the second direction X. Since the area of ​​the gate connection structure 140 is larger, its resistance is smaller. By forming an electrical connection between the gate connection structure 140 and the gate 130, the resistance of the gate 130 can be reduced, thereby increasing the gain of the semiconductor device 10.

[0051] Optional, continue to refer to Figure 1 The area of ​​the gate connection structure 140 is S1, and the area of ​​the gate 130 is S2; wherein, S1 / S2≥1.5.

[0052] Specifically, when the area S1 of the gate connection structure 140 and the area S2 of the gate 130 satisfy S1 / S2≥1.5, the gate 130 is electrically connected to the gate 130, which can significantly reduce the resistance of the gate 130 and further improve the gain and the switching speed of the semiconductor device 10.

[0053] Optional, Figure 4 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, such as... Figure 4 As shown, along the thickness direction of the semiconductor device, the gate connection structure 140 covers the gate 130.

[0054] For example, the gate connection structure 140 can be located above the gate 130 and overlap with the projection of the gate. Specifically, the projection of the gate connection structure 140 covers the projection of the gate 130, that is, the gate connection structure 140 covers the gate 130. This is beneficial to the electrical connection between the gate connection structure 140 and the gate 130, improving the stability of the electrical connection and thus ensuring the normal performance of the semiconductor device 10. On the other hand, it can reduce the size of the active region aa along the second direction X, thereby realizing the miniaturization of the semiconductor device 10.

[0055] Optional, Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention. For example... Figure 5 As shown, the second gate portion 1302 includes a first sub-portion 13021 and a second sub-portion 13022. The first sub-portion 13021 is located on the side of the second sub-portion 13022 away from the active region aa and along the second direction X. The size of the first sub-portion 13021 is larger than the size of the second sub-portion 13022. The second direction X intersects the first direction Y and is parallel to the plane where the substrate 110 is located. The second gate connection portion 1402 is electrically connected to the first sub-portion 13021.

[0056] For details, please refer to [link / reference]. Figure 5 The second gate portion 1302 includes a first sub-portion 13021 and a second sub-portion 13022. The first sub-portion 13021 is located on the side of the second sub-portion 13022 away from the active region aa and along the second direction X. The size of the first sub-portion 13021 is larger than the size of the second sub-portion 13022. The second gate connection portion 1402 is electrically connected to the first sub-portion 13021. That is, the connection position between the second gate connection portion 1402 and the second gate portion 1302 is set in the wider part of the second gate portion 1302. On the one hand, it can improve the connection stability, which is conducive to a more robust connection and a more stable structure. On the other hand, it can reduce the connection resistance and connection difficulty between the second gate connection portion 1402 and the second gate portion 1302.

[0057] Optional, Figure 6 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention. For example... Figure 6 As shown, the semiconductor device 10 also includes a source 150 and a source field plate 160; the source field plate 160 is located between the film layer where the gate 130 is located and the film layer where the gate connection structure 140 is located.

[0058] For example, continue to refer to Figure 6The source field plate 160 overlaps with the side of the gate 130 near the drain 180, thus extending the source field plate 160 towards the gate 130. This further increases the modulation effect of the source field plate 160 on the electric field, reduces the electric field accumulation on the side of the gate 130 near the drain 180, reduces the probability of breakdown on the side of the gate 130 near the drain 180, and increases the reliability of the semiconductor device 10. For example, the source field plate 160 may include an interconnected field plate body 1601 and a field plate branch 1602. One end of the field plate branch 1602 is electrically connected to the field plate body 1601, and the other end of the field plate branch 1602 is electrically connected to the source 150, thereby realizing the electrical connection between the source field plate 160 and the source 150.

[0059] Furthermore, Figure 7 yes Figure 6 The provided diagram shows the cross-sectional structure of the semiconductor device along section line F-F'. (Continue to refer to...) Figure 6 and Figure 7 The source field plate 160 is located between the film layer where the source 150 is located and the film layer where the gate 130 is located. In other words, the gate 130, the source field plate 160 and the gate connection structure 140 are all set in different layers. This can ensure a greater degree of freedom in setting different structures in the active region aa, and can reduce mutual interference.

[0060] It should be noted that continued reference is necessary. Figure 1 and Figure 2 The source 150 can be connected to the back side of the semiconductor device 10 through a source via C. For example, the source via C can penetrate the substrate 110 and the epitaxial structure 120, that is, it is connected to the source 150 through the source signal input electrode D located on the side of the substrate 110 away from the epitaxial structure 120. In other words, the source 150 is electrically connected to the source signal input electrode D through the source via C. Furthermore, the first gate connection portion 1401 can be located above the source via C, which ensures the stability of the source via C region, thereby enabling the semiconductor device 10 to operate normally.

[0061] Optional, continue to refer to Figure 6 Along the first direction Y, the size of the second gate portion 1302 is greater than the size of the source field plate 160 in the passive region bb, and the size of the second gate connection portion 1402 is greater than the size of the source field plate 160 in the passive region bb.

[0062] For details, please refer to [link / reference]. Figure 6Along the first direction Y, the size of the second gate portion 1302 is larger than the size of the source field plate 160 in the passive region bb, and the size of the second gate connection portion 1402 is larger than the size of the source field plate 160 in the passive region bb. In other words, along the first direction Y, the extension length of the second gate portion 1302 and the second gate connection portion 1402 in the passive region bb is greater than the extension length of the source field plate 160 in the passive region bb. That is, the influence of the source field plate 160 covering the gate 130 does not need to be considered, and the size and position of the source field plate 160 and the gate connection structure 140 can be freely designed, thereby improving the connection stability between the gate connection structure 140 and the gate 130, and thus optimizing the device performance.

[0063] Optional, Figure 8 yes Figure 6 A schematic diagram of the cross-sectional structure of the provided semiconductor device along the section line E-E'. (See diagram below.) Figure 6 and Figure 8 As shown, the semiconductor device 10 further includes a first dielectric layer 210 located between the source field plate 160 film layer and the gate 130 film layer, and a second dielectric layer 220 located between the source field plate 160 film layer and the gate connection structure 140 film layer; along the thickness direction Z of the semiconductor device 10, the source field plate 160 overlaps with the first gate portion 1301, and the thickness d1 of the first dielectric layer 210 satisfies d1≥300nm; and / or, the source field plate 160 overlaps with the first gate connection portion 1401, and the thickness d2 of the second dielectric layer 220 satisfies d2≥300nm.

[0064] For details, please refer to [link / reference]. Figure 6 and Figure 8 The source field plate 160, gate 130, and gate connection structure 140 are located in different film layers to avoid mutual interference. Furthermore, along the thickness direction Z of the semiconductor device 10, the source field plate 160 overlaps with the first gate portion 1301, and the thickness d1 of the first dielectric layer 210 satisfies d1≥300nm. This reduces the parasitic capacitance between the source field plate 160 and the first gate portion 1301, thereby reducing the impact on the performance of the semiconductor device 10 and ensuring normal device operation. (Continue to refer to...) Figure 6 and Figure 8 The source field plate 160 overlaps with the first gate connection portion 1401, and the thickness d2 of the second dielectric layer 220 satisfies d2≥300nm. This reduces the parasitic capacitance between the source field plate 160 and the first gate connection portion 1401, thereby reducing the impact on the performance of the semiconductor device 10 and ensuring normal device operation. Furthermore, by overlapping the source field plate 160 with the first gate portion 1301, and / or by overlapping the source field plate 160 with the first gate connection portion 1401, the area of ​​the semiconductor device 10 can be reduced, achieving device miniaturization.

[0065] It should be noted that, Figure 8 Only the technical solution shown is an example where the source field plate 160 overlaps with both the first gate portion 1301 and the first gate connection portion 1401. Optionally, when the source field plate 160 overlaps with the first gate portion 1301, the thickness d1 of the first dielectric layer satisfies d1≥300nm; or, when the source field plate 160 overlaps with the first gate connection portion 1401, the thickness d2 of the second dielectric layer satisfies d2≥300nm. That is, under the condition that the source field plate 160 overlaps with the first gate portion 1301 or the source field plate 160 overlaps with the first gate connection portion 1401, increasing the thickness of the first dielectric layer 210 or the second dielectric layer 220 can reduce parasitic capacitance, thereby reducing the impact on the performance of the semiconductor device 10 and ensuring normal device operation.

[0066] Optional, continue to refer to Figure 6 and Figure 8 The gate connection structure 140 is electrically connected to the gate 130 via a connecting post 200. The connecting post 200 includes a first connecting post portion 201 located in the first dielectric layer 210 and a second connecting post portion 202 located in the second dielectric layer 220. The first connecting post portion 201 and the second connecting post portion 202 are integrally disposed and integrally disposed with the gate connection structure 140. Alternatively, the first connecting post portion 201 is integrally disposed with the source field plate 160, and the second connecting post portion 202 is integrally disposed with the gate connection structure 140.

[0067] Specifically, the gate connection structure 140 and the gate 130 are electrically connected via the connecting post 200, which can improve connection stability and thus reduce the resistance of the gate 130. Further, in the first dielectric layer 210, the gate 130 is electrically connected via the first connecting post portion 201 of the connecting post 200, and then electrically connected via the first connecting post portion 201 to the second connecting post portion 202 located in the second dielectric layer 220, thereby realizing the electrical connection between the gate connection structure 140 and the gate 130 via the connecting post 200. As one possible implementation, refer to... Figure 8 The first connecting post portion 201 and the second connecting post portion 202 are integrally formed with the gate connection structure 140, which simplifies the process flow of the semiconductor device 10 and helps improve process reliability. As another feasible implementation, Figure 9 yes Figure 6 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line E-E'. (See diagram below.) Figure 9As shown, the first connecting post portion 201 is integrally formed with the source field plate 160, and the second connecting post portion 202 is integrally formed with the gate connection structure 140. Specifically, before forming the source field plate 160, an opening is formed in the first dielectric layer 210 above the gate 130 to expose the gate 130. During the formation of the source field plate 160, an electrical connection is formed between the first connecting post portion 201 and the gate 130 at the opening in the first dielectric layer 210. Then, a second dielectric layer 220 is deposited, and another opening is formed above the gate 130. Finally, the second connecting post portion 202 is filled above the second dielectric layer 220 and into the opening to form the gate connection structure 140. That is, the connecting post 200 is not integrally formed, but is formed by two steps, namely, the first connecting post portion 201 is integrally formed with the source field plate 160, and the second connecting post portion 202 is integrally formed with the gate connection structure 140.

[0068] Optional, continue to refer to Figure 1 The semiconductor device 10 also includes a gate pad 170. Along the first direction, the gate pad 170 is located in the passive region bb on the first side of the active region aa. The first gate portion 1301 and the first gate connection portion 1401 are both electrically connected to the gate pad 170. The first gate connection portion 1401 is disposed on the same layer as the gate pad 170.

[0069] For example, continue to refer to Figure 1 Along the first direction Y, the gate 130 in the active region aa can be connected to the gate pad 170 in the passive region bb through the gate interconnect metal. The first gate portion 1301 can receive the gate voltage signal through the gate pad 170 to ensure the normal operation of the semiconductor device 10. Specifically, the first gate connection portion 1401 is disposed on the same layer as the gate pad 170. This simplifies the process flow, avoids the setting of redundant film layers and simplifies the mask process, and facilitates the realization of a thinner and lighter design for the semiconductor device 10.

[0070] Optional, continue to refer to Figure 1 The semiconductor device 10 also includes a drain 180 and a drain pad 190 connected to each other; the drain 180 forms an ohmic contact with the epitaxial structure 120; along the first direction Y, the drain pad 180 is located on the second side of the active region aa; along the first direction Y, the second gate connection portion 1402 is located between the active region aa and the drain pad 190.

[0071] For example, continue to refer to Figure 1The drain 180 in the active region aa can be connected to the drain pad 190 in the passive region bb through the drain interconnect metal. Specifically, along the first direction Y, the drain pad 190 is located on the second side of the active region aa, that is, the drain 180 can receive the drain voltage signal through the drain pad 190 to ensure the normal operation of the semiconductor device 10.

[0072] Furthermore, along the first direction Y, the second gate connection portion 1402 is located between the active region aa and the drain pad 190, which can further reduce the area of ​​the passive region bb, thereby reducing the area of ​​the semiconductor device 10 and enabling the device to be miniaturized.

[0073] Optional, continue to refer to Figure 2 The epitaxial structure 120 includes a nucleation layer 1201, a buffer layer 1202, a channel layer 1203, and a barrier layer 1204 stacked together; the channel layer 1203 and the barrier layer 1204 form a heterojunction structure.

[0074] For example, continue to refer to Figure 2 The nucleation layer 1201 can be made of aluminum nitride and is located between the substrate 110 and the buffer layer 1202, serving to bond the semiconductor material layer that needs to be grown next.

[0075] For example, continue to refer to Figure 2 The buffer layer 1202 is located on one side of the substrate 110. The material of the buffer layer 1202 can be gallium nitride, and the buffer layer 1202 can include iron atoms, which is beneficial to achieve the high resistance performance of the buffer layer 1202, ensuring that it can block vertical leakage current and improve the pinch-off performance of semiconductor devices.

[0076] For example, continue to refer to Figure 2 The channel layer 1203 can be a group III nitride, such as Al. x Ga 1－x N, where 0 ≤ x < 1, means that the energy at the interface between the channel layer 1203 and the barrier layer 1204, i.e., the energy at the conduction band edge of the channel layer 1203, is less than the energy at the conduction band edge of the barrier layer 1204. For example, x = 0 indicates that the channel layer 1203 is GaN. The channel layer 1203 can also be other Group III nitrides, such as InGaN or AlInGaN. The channel layer 1203 can be undoped or unintentionally doped. The channel layer 1203 can also be a multilayer structure, such as a combination of a superlattice, GaN, or AlGaN.

[0077] For example, continue to refer to Figure 2The barrier layer 1204 can be AlN, AlInN, AlGaN, or AlInGaN. The barrier layer 1204 has sufficient thickness and a sufficiently high Al composition to create a significant carrier concentration at the interface between the channel layer 1203 and the barrier layer 1204.

[0078] For example, continue to refer to Figure 2 The channel layer 1203 may include GaN, while the barrier layer 1204 may include AlGaN. That is, the material of the barrier layer 1204 has a higher band gap than the material of the channel layer 1203, and the channel layer 1203 may also have a greater electron affinity than the barrier layer 1204. Due to the band gap difference between the barrier layer 1204 and the channel layer 1203, and the piezoelectric effect at the interface between the two layers, a two-dimensional electron gas (2DEG) is formed between the channel layer 1203 and the barrier layer 1204.

[0079] It is understood that the epitaxial structure 120 may also include a cap layer located on the surface of the barrier layer 1204 away from the substrate 110. The cap layer can reduce surface states, reduce surface leakage current in subsequent semiconductor devices, and suppress current collapse, thereby improving the performance and reliability of the epitaxial structure 120 and the semiconductor device 10.

[0080] It should be understood that the embodiments of the present invention, from the perspective of semiconductor device design, can reduce the influence of gate resistance and improve gain and reduce leakage current by setting at least one gate connection structure. The semiconductor devices include, but are not limited to: high-power high-electron-mobility transistors (HEMTs) operating under high-voltage and high-current conditions; silicon-on-insulator (SOI) transistors; gallium arsenide (GaAs)-based transistors; and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), and metal-insulator-semiconductor heterojunction field-effect transistors (MESFETs). A MISHFET (Missile Field-Effect Transistor) or other field-effect transistors. The at least one gate connection structure provided in the semiconductor device of this invention can be widely used in the manufacturing of semiconductor devices such as radio frequency microwaves and power electronics. It is particularly advantageous for gallium nitride electronic devices with large bandgap, high electron mobility, high breakdown field strength, and good thermal conductivity, and can better meet the high-performance requirements of rapidly developing fields such as electronic communications.

[0081] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises an active region and a passive region surrounding the active region; The semiconductor device further comprises: a substrate; an epitaxial structure on one side of the substrate; a gate on a side of the epitaxial structure away from the substrate; the gate extends along a first direction, which is parallel to the plane in which the substrate lies; the gate comprises a first gate subpart and a second gate subpart connected to each other, the first gate subpart forms a Schottky contact with the epitaxial structure, and the second gate subpart is located in the passive region; at least one gate connection structure on a side of the gate away from the substrate; the gate connection structure comprises a first gate connection subpart and a second gate connection subpart connected to each other, and the second gate connection subpart is located in the passive region; along the thickness direction of the semiconductor device, the first gate connection subpart at least partially overlaps with the first gate subpart, the second gate connection subpart at least partially overlaps with the second gate subpart, and the second gate connection subpart is electrically connected to at least part of the second gate subpart; wherein the area of the gate connection structure is greater than the area of the gate; The gate connection structure covers the gate along the extension direction of the gate; wherein the extension direction of the gate connection structure is consistent with the extension direction of the gate.

2. The semiconductor device according to claim 1, wherein The area of the gate connection structure is S1, and the area of the gate is S2; wherein S1 / S2≥1.

5.

3. The semiconductor device of claim 1, wherein the second gate subpart comprises a first sub-subpart and a second sub-subpart, the first sub-subpart is located on a side of the second sub-subpart away from the active region, and along a second direction, the size of the first sub-subpart is greater than the size of the second sub-subpart; the second direction intersects the first direction and is parallel to the plane in which the substrate lies; The second gate connection subpart is electrically connected to the first sub-subpart.

4. The semiconductor device of claim 1, wherein The semiconductor device further comprises a source and a source field plate; The source field plate is located between the film layer in which the gate is located and the film layer in which the gate connection structure is located.

5. The semiconductor device of claim 4, wherein, Along the first direction, the size of the second gate subpart is greater than the size of the source field plate in the passive region, and the size of the second gate connection subpart is greater than the size of the source field plate in the passive region.

6. The semiconductor device of claim 4, wherein, The semiconductor device further comprises a first dielectric layer between the film layer in which the source field plate is located and the film layer in which the gate is located, and a second dielectric layer between the film layer in which the source field plate is located and the film layer in which the gate connection structure is located; Along the thickness direction of the semiconductor device, the source field plate overlaps with the first gate subpart, and the thickness d1 of the first dielectric layer satisfies d1≥300nm; And / or, the source field plate overlaps with the first gate connection subpart, and the thickness d2 of the second dielectric layer satisfies d2≥300nm.

7. The semiconductor device of claim 6, wherein, The gate connection structure and the gate are electrically connected through a connecting column; The connecting column comprises a first connecting column subpart in the first dielectric layer and a second connecting column subpart in the second dielectric layer; The first connecting column part and the second connecting column part are integrally arranged with the gate connecting structure; or the first connecting column part is integrally arranged with the source field plate, and the second connecting column part is integrally arranged with the gate connecting structure.

8. The semiconductor device of claim 1, wherein The semiconductor device further comprises a gate pad, in the first direction, the gate pad is located in the passive region on the first side of the active region, and the first gate part and the first gate connecting part are both electrically connected with the gate pad. The first gate connecting part is arranged in the same layer as the gate pad.

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