A redundant self-recovery latch resistant to multiple nodes and clock signal single event upset

Abstract

The present invention relates to a redundant self-recovery latch resistant to multi-node and clock signal single particle upsets, comprising an input circuit, a first latch circuit, a second latch circuit, an output circuit, a first clock signal circuit CLK1, and a second clock signal circuit CLK2. The present invention makes the clock signal circuit redundant and divides it into two identical clock signal circuits CLK1 and CLK2. The working states of the first latch circuit and the second latch circuit are controlled by the clock signals of the two clock signal circuits. By adding a redundant latch circuit and a redundant transmission circuit, the latch can resist multi-node single particle upsets and has the ability to self-recover; the redundant clock signal circuit enables the latch to resist clock signal single particle upsets.

Description

Technical Field

[0001] The present invention relates to a novel latch, in particular to a redundant self-recovery latch resistant to multi-node and clock signal single particle upset, belonging to the technical field of circuit-level radiation-resistant reinforcement. Background Art

[0002] In aerospace and some specialized military applications, electronic equipment must function properly in environments with significant radiation exposure, making the radiation resistance of electronic components increasingly important. Furthermore, space radiation exposure is a major cause of aircraft failures, making the radiation resistance of integrated circuits a key design parameter for aerospace electronics.

[0003] Due to the complexity of the radiation environment, integrated circuits may experience various radiation effects, including total dose effects, single-event upsets (SEEs), single-event latch-up, and single-event gate breakdown. A SEE occurs when a single high-energy particle impacts a semiconductor device, generating charge that is collected by sensitive nodes, causing the logic state of the storage circuit to flip. With the advancement of process nodes, issues such as reduced charge storage at sensitive nodes and the single-event impact trajectory covering multiple devices are impacting the integrated circuit's ability to withstand SEEs. Consequently, radiation hardening technologies to address SEEs will become a key research focus.

[0004] The traditional DICE structure, a widely used single-event upset (SING)-resistant structure, is resistant to single-node SINGs. Two pairs of transistors form a sensitive node pair. When a SING occurs at any node, the remaining unaffected nodes can recover the data at the node where the SING occurred, preventing the data from being latched. However, the DICE structure has its drawbacks: 1. It is not immune to SINGs introduced from the clock side; 2. As device sizes shrink, a single high-energy particle can affect multiple nodes, rendering the DICE structure incapable of immunizing against multiple SINGs. Furthermore, when multiple nodes experience SINGs, the DICE structure will latch erroneous data and be unable to recover the data on its own. Summary of the Invention

[0005] The technology of the present invention solves the problem: based on circuit-level design reinforcement, the DICE structure is improved to provide a redundant self-recovery latch with significantly improved resistance to multi-node and clock signal single-event upsets.

[0006] The technical solution of the present invention is:

[0007] A redundant self-recovery latch resistant to multi-node and clock signal single event upsets, comprising:

[0008] An input circuit receives an external data signal D, flips the data signal D, obtains a data signal D1 and transmits the data signal D1 to the first latch circuit and the second latch circuit;

[0009] A first clock signal circuit CLK1 receives an external clock signal CLK, inverts the clock signal CLK to obtain a first clock signal CLKN1 and a clock signal CLKNN1, and transmits the obtained signals to a first latch circuit and a second latch circuit to control the working states of the first latch circuit and the second latch circuit;

[0010] The second clock signal circuit CLK2 receives an external clock signal CLK, inverts the clock signal CLK to obtain a second clock signal CLKN2 and a clock signal CLKNN2, and transmits the obtained clock signals to the first latch circuit to control the working state of the first latch circuit;

[0011] The first latch circuit is controlled by the first clock signal CLKN1 and the clock signal CLKNN1, as well as the second clock signal CLKN2 and the clock signal CLKNN2. When the clock signal CLK is at a high level, the first latch circuit receives the data signal D1 transmitted by the input circuit in real time. The first latch circuit is in a transparent state and performs inversion processing on the data signal D1 to obtain a data signal D2 and transmits it to the output circuit. When the clock signal CLK is at a low level, the first latch circuit does not receive the data signal D1 transmitted by the input circuit. The first latch circuit is in a latched state and latches the data signal D1 transmitted by the input circuit last received when the clock signal CLK is at a high level, performs inversion processing on the data signal D2 and transmits it to the output circuit.

[0012] The second latch circuit is controlled by the first clock signal CLKN1 and the clock signal CLKNN1. When the clock signal CLK is at a high level, the second latch circuit receives the data signal D1 transmitted by the input circuit in real time. The second latch circuit is in a transparent state and inverts the data signal D1 to obtain a data signal D3 and transmits it to the output circuit. When the clock signal CLK is at a low level, the second latch circuit does not receive the data signal D1 transmitted by the input circuit. The second latch circuit is in a latched state and latches the data signal D1 transmitted by the input circuit last received when the clock signal CLK is at a high level, inverts the data signal D3 and transmits it to the output circuit.

[0013] The output circuit receives the data signal D2 transmitted by the first latch circuit and the data signal D3 transmitted by the second latch circuit, flips the data signals D2 and D3, obtains a data signal Q and outputs it externally.

[0014] In the redundant self-recovery latch resistant to multiple nodes and clock signal single event upset, at least one of the following conditions is satisfied:

[0015] The levels of the clock signals CLKN1 and CLKN2 are synchronized;

[0016] The high and low levels of the clock signals CLKNN1 and CLKNN2 are synchronized.

[0017] In the redundant self-recovery latch resistant to multiple nodes and clock signal single event upset, when the clock signal CLK is at a low level, the clock signals CLKN1 and CLKN2 are at a high level, and the clock signals CLKNN1 and CLKNN2 are at a low level.

[0018] In the above redundant self-recovery multi-node and clock signal single event upset resistant latch, the first clock signal circuit CLK1 includes an inverter INV5 and an inverter INV6;

[0019] The inverter INV5 includes a PMOS transistor p27 and an NMOS transistor n27, wherein the source of the PMOS transistor p27 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p27 receives the clock signal CLK; the source of the NMOS transistor n27 is grounded, the gate of the NMOS transistor n27 receives the clock signal CLK, and the drain of the NMOS transistor n27 is connected to the drain of the PMOS transistor p27 to form a common node N11. The common node N11 serves as an output end and outputs the clock signal CLKN1.

[0020] The inverter INV6 includes a PMOS transistor p28 and an NMOS transistor n28, wherein the source of the PMOS transistor p28 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p28 receives the clock signal CLKN1 output from the common node N11; the source of the NMOS transistor n28 is grounded, and the gate of the NMOS transistor n28 receives the clock signal CLKN1 from the common node N11. The drain of the NMOS transistor n28 is connected to the drain of the PMOS transistor p28 to form a common node N12. The common node N12 serves as an output end to output the clock signal CLKNN1.

[0021] In the above redundant self-recovery multi-node and clock signal single event upset resistant latch, the second clock signal circuit CLK2 includes an inverter INV7 and an inverter INV8;

[0022] The inverter INV7 includes a PMOS transistor p29 and an NMOS transistor n29, wherein the source of the PMOS transistor p29 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p29 receives the clock signal CLK; the source of the NMOS transistor n29 is grounded, the gate of the NMOS transistor n29 receives the clock signal CLK, and the drain of the NMOS transistor n29 is connected to the drain of the PMOS transistor p29 to form a common node N13. The common node N13 serves as an output end and outputs the clock signal CLKN2.

[0023] The inverter INV8 includes a PMOS transistor p30 and an NMOS transistor n30, wherein the source of the PMOS transistor p30 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p30 receives the clock signal CLKN2 output from the common node N13; the source of the NMOS transistor n30 is grounded, and the gate of the NMOS transistor n30 receives the clock signal CLKN2 from the common node N13; the drain of the NMOS transistor n30 is connected to the drain of the PMOS transistor p30 to form a common node N14, and the common node N14 serves as an output end to output the clock signal CLKNN2.

[0024] In the above redundant self-recovery latch resistant to multiple nodes and clock signal single event upset, the input circuit includes an inverter INV1;

[0025] The inverter INV1 includes a PMOS transistor p1 and an NMOS transistor n1, wherein the source of the PMOS transistor p1 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p1 receives the data signal D transmitted from the outside; the source of the NMOS transistor n1 is grounded, the gate of the NMOS transistor n1 receives the data signal D transmitted from the outside, and the drain of the NMOS transistor n1 is connected to the drain of the PMOS transistor p1 to form a common node DN. The common node DN serves as an output end to output the data signal D1.

[0026] In the above redundant self-recovery multi-node and clock signal single event upset resistant latch, the first latch circuit includes a clock-controlled transmission unit C1, a clock-controlled transmission unit C4, a clock-controlled transmission unit C5 and an inverter INV2;

[0027] The clock-controlled transmission unit C1 includes a PMOS transistor p2, a PMOS transistor p3, an NMOS transistor n2, and an NMOS transistor n3, wherein the source of the PMOS transistor p2 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p2 receives the data signal D1 output from the common node DN; the source of the PMOS transistor p3 is connected to the drain of the PMOS transistor p2, and the gate of the PMOS transistor p3 receives the clock signal CLKN1 output from the common node N11; the source of the NMOS transistor n2 is grounded, and the gate of the NMOS transistor n2 receives the data signal D1 output from the common node DN; the source of the NMOS transistor n3 is connected to the drain of the NMOS transistor n2, and the gate of the NMOS transistor n3 receives the clock signal CLKNN1 output from the common node N12; the drain of the NMOS transistor n3 is connected to the drain of the PMOS transistor p3, forming a common node N5;

[0028] The clock-controlled transmission unit C4 includes a PMOS transistor p8, a PMOS transistor p9, an NMOS transistor n8, and an NMOS transistor n9, wherein the source of the PMOS transistor p8 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p8 receives the signal of the common node N5; the source of the PMOS transistor p9 is connected to the drain of the PMOS transistor p8, and the gate of the PMOS transistor p9 receives the clock signal CLKNN1 output from the common node N12; the source of the NMOS transistor n8 is grounded, and the gate of the NMOS transistor n8 receives the signal of the common node N5; the source of the NMOS transistor n9 is connected to the drain of the NMOS transistor n8, and the gate of the NMOS transistor n9 receives the clock signal CLKN1 output from the common node N11; the drain of the NMOS transistor n9 is connected to the drain of the PMOS transistor p9, forming a common node N6, and the common node N6 serves as an output end to output the data signal D2;

[0029] The clock-controlled transmission unit C5 includes a PMOS transistor p10, a PMOS transistor p11, an NMOS transistor n10, and an NMOS transistor n11, wherein the source of the PMOS transistor p10 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p10 receives the signal of the common node N5; the source of the PMOS transistor p11 is connected to the drain of the PMOS transistor p10, the gate of the PMOS transistor p11 receives the clock signal CLKN2 output from the common node N13, and the drain of the PMOS transistor p11 is connected to the common node N6; the source of the NMOS transistor n10 is grounded, and the gate of the NMOS transistor n10 receives the signal of the common node N5; the source of the NMOS transistor n11 is connected to the drain of the NMOS transistor n10, the gate of the NMOS transistor n11 receives the clock signal CLKNN2 output from the common node N14, and the drain of the NMOS transistor n11 is connected to the common node N6;

[0030] The inverter INV2 includes a PMOS transistor p12 and an NMOS transistor n12, wherein the source of the PMOS transistor p12 is connected to the power supply voltage VDD, the gate of the PMOS transistor p12 receives the signal of the common node N6, and the drain of the PMOS transistor p12 is connected to the common node N5; the source of the NMOS transistor n12 is grounded, the gate of the NMOS transistor n12 receives the signal of the common node N6; and the drain of the NMOS transistor n12 is connected to the common node N5.

[0031] In the redundant self-recovery latch resistant to multiple nodes and clock signal single event upset, the driving capability of the clock-controlled transmission unit C1 is greater than that of the inverter INV2, and the driving capability of the inverter INV2 is greater than that of the clock-controlled transmission unit C4.

[0032] In the above redundant self-recovery multi-node and clock signal single event upset resistant latch, the second latch circuit includes a clock-controlled transmission unit C2, a clock-controlled transmission unit C3, a DICE structure, a C unit C6, an inverter INV3, an inverter INV4 and a C unit C7;

[0033] The clock-controlled transmission unit C2 includes a PMOS transistor p4, a PMOS transistor p5, an NMOS transistor n4, and an NMOS transistor n5, wherein the source of the PMOS transistor p4 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p4 receives the data signal D1 output from the common node DN; the source of the PMOS transistor p5 is connected to the drain of the PMOS transistor p4, and the gate of the PMOS transistor p5 receives the clock signal CLKN1 output from the common node N11; the source of the NMOS transistor n4 is grounded, and the gate of the NMOS transistor n4 receives the data signal D1 output from the common node DN; the source of the NMOS transistor n5 is connected to the drain of the NMOS transistor n4, and the gate of the NMOS transistor n5 receives the clock signal CLKNN1 output from the common node N12; the drain of the NMOS transistor n5 is connected to the drain of the PMOS transistor p5, forming a common node N4;

[0034] The clock-controlled transmission unit C3 includes a PMOS transistor p6, a PMOS transistor p7, an NMOS transistor n6, and an NMOS transistor n7, wherein the source of the PMOS transistor p6 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p6 receives the data signal D1 output from the common node DN; the source of the PMOS transistor p7 is connected to the drain of the PMOS transistor p6, and the gate of the PMOS transistor p7 receives the clock signal CLKN1 output from the common node N11; the source of the NMOS transistor n6 is grounded, and the gate of the NMOS transistor n6 receives the data signal D1 output from the common node DN; the source of the NMOS transistor n7 is connected to the drain of the NMOS transistor n6, and the gate of the NMOS transistor n7 receives the clock signal CLKNN1 output from the common node N12; the drain of the NMOS transistor n7 is connected to the drain of the PMOS transistor p7, forming a common node N2;

[0035] The DICE structure includes a transmission unit C9, a clock-controlled transmission unit C10, a transmission unit C11, and a clock-controlled transmission unit C12. The transmission unit C9 includes a PMOS transistor p21 and an NMOS transistor n21, wherein the source of the PMOS transistor p21 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p21 receives a signal from the common node N4; the source of the NMOS transistor n21 is grounded, the gate of the NMOS transistor n21 receives a signal from the common node N2, and the drain of the NMOS transistor n21 is connected to the drain of the PMOS transistor p21 to form a common node N1; the clock-controlled transmission unit C10 includes a PMOS transistor p22, a PMOS transistor p23, NMOS transistor n22 and NMOS transistor n23, wherein the source of PMOS transistor p22 is connected to the power supply voltage VDD, and the gate of PMOS transistor p22 receives the signal of common node N1; the source of PMOS transistor p23 is connected to the drain of PMOS transistor p22, the gate of PMOS transistor p23 receives the clock signal CLKNN1 output from common node N12, and the drain of PMOS transistor p23 is connected to common node N2; the source of NMOS transistor n22 is grounded, and the gate of NMOS transistor n22 receives the signal of common node N3; the source of NMOS transistor n23 is connected to the drain of NMOS transistor n22, and the gate of NMOS transistor n23 receives the clock signal output from common node N11 CLKN1, the drain of the NMOS transistor n23 is connected to the common node N2; the transmission unit C11 includes a PMOS transistor p24 and an NMOS transistor n24, wherein the source of the PMOS transistor p24 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p24 receives the signal of the common node N2; the source of the NMOS transistor n24 is grounded, the gate of the NMOS transistor n24 receives the signal of the common node N4, and the drain of the NMOS transistor n24 is connected to the drain of the PMOS transistor p24 to form a common node N3; the clock-controlled transmission unit C12 includes a PMOS transistor p25, a PMOS transistor p26, an NMOS transistor n25 and an NMOS transistor n26, wherein the PMOS transistor The source of PMOS transistor p25 is connected to the power supply voltage VDD, and the gate of PMOS transistor p25 receives the signal of common node N3; the source of PMOS transistor p26 is connected to the drain of PMOS transistor p25, the gate of PMOS transistor p26 receives the clock signal CLKNN1 output from common node N12, and the drain of PMOS transistor p26 is connected to common node N4; the source of NMOS transistor n25 is grounded, and the gate of NMOS transistor n25 receives the signal of common node N1; the source of NMOS transistor n26 is connected to the drain of NMOS transistor n25, the gate of NMOS transistor n26 receives the clock signal CLKN1 output from common node N11, and the drain of NMOS transistor n26 is connected to common node N4;

[0036] The C unit C6 includes a PMOS transistor p13, a PMOS transistor p14, an NMOS transistor n13, and an NMOS transistor n14, wherein the source of the PMOS transistor p13 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p13 receives the signal of the common node N3; the source of the PMOS transistor p14 is connected to the drain of the PMOS transistor p13, and the gate of the PMOS transistor p14 receives the signal of the common node N1; the source of the NMOS transistor n13 is grounded, and the gate of the NMOS transistor n13 receives the signal of the common node N3; the source of the NMOS transistor n14 is connected to the drain of the NMOS transistor n13, and the gate of the NMOS transistor n14 receives the signal of the common node N1; the drain of the NMOS transistor n14 is connected to the drain of the PMOS transistor p14, forming a common node N7;

[0037] The inverter INV3 includes a PMOS transistor p15 and an NMOS transistor n15, wherein the source of the PMOS transistor p15 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p15 receives the signal of the common node N7; the source of the NMOS transistor n15 is grounded, and the gate of the NMOS transistor n15 receives the signal of the common node N7; the drain of the NMOS transistor n15 is connected to the drain of the PMOS transistor p15 to form a common node N8, and the common node N8 serves as an output end to output the data signal D3;

[0038] The C unit C7 includes a PMOS transistor p17, a PMOS transistor p18, an NMOS transistor n17, and an NMOS transistor n18, wherein the source of the PMOS transistor p17 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p17 receives the signal of the common node N8; the source of the PMOS transistor p18 is connected to the drain of the PMOS transistor p17, and the gate of the PMOS transistor p18 receives the signal of the common node N5; the source of the NMOS transistor n17 is grounded, and the gate of the NMOS transistor n17 receives the signal of the common node N8; the source of the NMOS transistor n18 is connected to the drain of the NMOS transistor n17, and the gate of the NMOS transistor n18 receives the signal of the common node N5, and the drain of the NMOS transistor n18 is connected to the drain of the PMOS transistor p18, forming a common node N9;

[0039] The inverter INV4 includes: a PMOS transistor p16 and an NMOS transistor n16, wherein the source of the PMOS transistor p16 is connected to the power supply voltage VDD, the gate of the PMOS transistor p16 receives the signal of the common node N9, and the drain of the PMOS transistor p16 is connected to the common node N4 and the common node N2; the source of the NMOS transistor n16 is grounded, the gate of the NMOS transistor n16 receives the signal of the common node N9; and the drain of the NMOS transistor n16 is connected to the common node N4 and the common node N2.

[0040] In the redundant self-recovery latch resistant to multiple nodes and clock signal single event upset, the driving capability of the clock-controlled transmission unit C2 and the clock-controlled transmission unit C3 is greater than that of the inverter INV4, and the driving capability of the inverter INV4 is greater than that of the DICE structure.

[0041] In the above-mentioned redundant self-recovery latch resistant to multi-node and clock signal single-event upset, the output circuit includes a C unit C8; the C unit C8 includes a PMOS transistor p19, a PMOS transistor p20, an NMOS transistor n19 and an NMOS transistor n20, wherein the source of the PMOS transistor p19 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p19 receives the data signal D2 output by the common node N6; the source of the PMOS transistor p20 is connected to the drain of the PMOS transistor p19, and the gate of the PMOS transistor p20 is connected to the drain of the PMOS transistor p19. The data signal D3 output from the common node N8 is received; the source of the NMOS transistor n19 is grounded, and the gate of the NMOS transistor n19 receives the data signal D2 output from the common node N6; the source of the NMOS transistor n20 is connected to the drain of the NMOS transistor n19, and the gate of the NMOS transistor n20 receives the data signal D3 output from the common node N8. The drain of the NMOS transistor n20 is connected to the drain of the PMOS transistor p20 to form a common node N10. The common node N10 serves as the output end of the output circuit and outputs the data signal Q to the outside.

[0042] Compared with the prior art, the present invention has at least the following beneficial effects:

[0043] The redundant self-recovery latch resistant to multi-node and clock signal single-particle upsets provided by the present invention makes the clock signal circuit redundant and is divided into two identical clock signal circuits CLK1 and CLK2. The working states of the first latch circuit and the second latch circuit are controlled by the clock signals of the two clock signal circuits. The clock signal of any clock signal circuit is flipped due to a single particle, which at most causes the output signal of one of the first latch circuit and the second latch circuit to flip, and the latch will not output an erroneous result; and the redundant transmission circuit and the first latch circuit in the second latch circuit can recover the affected nodes. Only when the clock signals of the clock signal circuit CLK1 and the clock signal circuit CLK2 are flipped, causing the overall function of the latch circuit to malfunction, will the latch circuit output an erroneous result, significantly improving the latch's ability to resist clock signal single-particle upsets.

[0044] When multiple nodes of the DICE structure in the second latch circuit are flipped, causing the output signal of the second latch circuit to flip, the output signal of the first latch circuit does not flip, and the latch will not output an erroneous result. In addition, the redundant transmission circuit in the second latch circuit and the first latch circuit can recover the affected nodes, thereby preventing the latch circuit from latching erroneous data signals, significantly improving the latch's ability to resist multi-node single-particle flips. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Schematic diagram of the structure of a redundant self-recovery reinforced latch according to an embodiment of the present invention;

[0046] Figure 2 Schematic diagram of a DICE structure in a latch according to an embodiment of the present invention;

[0047] Figure 3 Schematic diagram of a clock circuit in a latch according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments:

[0049] like Figure 1 FIG2 is a schematic diagram of the structure of a redundant self-recovery reinforced latch according to an embodiment of the present invention. The reinforced latch includes: an input circuit, a first latch circuit, a second latch circuit, an output circuit, a first clock signal circuit CLK1, and a second clock signal circuit CLK2.

[0050] The input circuit receives an externally transmitted data signal D, inverts the data signal D, obtains a data signal D1 and transmits the data signal D1 to the first latch circuit and the second latch circuit.

[0051] The first clock signal circuit CLK1 receives an externally transmitted clock signal CLK, inverts the clock signal CLK to obtain clock signals CLKN1 and CLKNN1, and transmits the clock signals to the first latch circuit and the second latch circuit to control their working states.

[0052] The second clock signal circuit CLK2 receives the externally transmitted clock signal CLK, inverts the clock signal CLK to obtain clock signals CLKN2 and CLKNN2, and transmits the obtained clock signals to the first latch circuit to control the working state of the first latch circuit.

[0053] The first latch circuit is controlled by the clock signals CLKN1 and CLKNN1 of the first clock signal circuit CLK1, and the clock signals CLKN2 and CLKNN2 of the second clock signal circuit CLK2. When the clock signal CLK is at a high level, the first latch circuit receives the data signal D1 transmitted by the input circuit, and is in a transparent state. The data signal D1 input by the input circuit in real time is flipped to obtain the data signal D2 and transmit it to the output circuit. When the clock signal CLK is at a low level, the data signal D1 transmitted by the input circuit is not received, and the first latch circuit is in a latched state. The data signal D1 transmitted by the input circuit that was last received when the clock signal CLK was at a high level is latched, and is flipped to obtain the data signal D2 and transmit it to the output circuit.

[0054] The second latch circuit is controlled by the clock signal CLKN1 and the clock signal CLKNN1 of the first clock signal circuit CLK1. When the clock signal CLK is at a high level, the second latch circuit receives the data signal D1 transmitted by the input circuit, and is in a transparent state. The data signal D1 input by the input circuit in real time is flipped to obtain the data signal D3 and transmit it to the output circuit. When the clock signal CLK is at a low level, the data signal D1 transmitted by the input circuit is not received. The second latch circuit is in a latched state, latches the data signal D1 transmitted by the input circuit last received when the clock signal CLK is at a high level, flips it, obtains the data signal D3 and transmits it to the output circuit.

[0055] The output circuit receives the data signal D2 transmitted by the first latch circuit and the data signal D3 transmitted by the second latch circuit, inverts the data signals D2 and D3, obtains the data signal Q and outputs it.

[0056] The following is a detailed description of each component circuit:

[0057] like Figure 3 As shown, the clock signal circuit includes a first clock signal circuit CLK1 and a second clock signal circuit CLK2 , wherein the first clock signal circuit CLK1 includes an inverter INV5 and an inverter INV6 .

[0058] Inverter INV5 includes a PMOS transistor p27 and an NMOS transistor n27; the source of the PMOS transistor p27 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p27 receives the clock signal CLK; the source of the NMOS transistor n27 is grounded, the gate of the NMOS transistor n27 receives the clock signal CLK, and the drain of the NMOS transistor n27 is connected to the drain of the PMOS transistor p27 to form a common node N11. The common node N11 serves as an output end and outputs the clock signal CLKN1.

[0059] Inverter INV6 includes a PMOS transistor p28 and an NMOS transistor n28; the source of the PMOS transistor p28 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p28 receives the clock signal CLKN1 output from the common node N11; the source of the NMOS transistor n28 is grounded, and the gate of the NMOS transistor n28 receives the clock signal CLKN1 from the common node N11. The drain of the NMOS transistor n28 is connected to the drain of the PMOS transistor p28 to form a common node N12. The common node N12 serves as an output end and outputs the clock signal CLKNN1.

[0060] The second clock signal circuit CLK2 includes an inverter INV7 and an inverter INV8.

[0061] Inverter INV7 includes a PMOS transistor p29 and an NMOS transistor n29; the source of the PMOS transistor p29 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p29 receives the clock signal CLK; the source of the NMOS transistor n29 is grounded, the gate of the NMOS transistor n29 receives the clock signal CLK, and the drain of the NMOS transistor n29 is connected to the drain of the PMOS transistor p29 to form a common node N13. The common node N13 serves as an output end and outputs the clock signal CLKN2.

[0062] Inverter INV8 includes a PMOS transistor p30 and an NMOS transistor n30; the source of the PMOS transistor p30 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p30 receives the clock signal CLKN2 output from the common node N13; the source of the NMOS transistor n30 is grounded, and the gate of the NMOS transistor n30 receives the clock signal CLKN2 from the common node N13. The drain of the NMOS transistor n30 is connected to the drain of the PMOS transistor p30 to form a common node N14. The common node N14 serves as an output end and outputs the clock signal CLKNN2.

[0063] like Figure 1 As shown, the input circuit includes an inverter INV1.

[0064] Inverter INV1 includes a PMOS transistor p1 and an NMOS transistor n1; the source of the PMOS transistor p1 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p1 receives the data signal D from the outside; the source of the NMOS transistor n1 is grounded, the gate of the NMOS transistor n1 receives the data signal D from the outside, and the drain of the NMOS transistor n1 is connected to the drain of the PMOS transistor p1 to form a common node DN. The common node DN serves as an output end to output the data signal D1.

[0065] like Figure 1 As shown, the first latch circuit includes a clocked transmission unit C1, a clocked transmission unit C4, a clocked transmission unit C5 and an inverter INV2.

[0066] The clock-controlled transmission unit C1 includes a PMOS transistor p2, a PMOS transistor p3, an NMOS transistor n2, and an NMOS transistor n3; the source of the PMOS transistor p2 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p2 receives the data signal D1 output from the common node DN; the source of the PMOS transistor p3 is connected to the drain of the PMOS transistor p2, and the gate of the PMOS transistor p3 receives the clock signal CLKN1 output from the common node N11; the source of the NMOS transistor n2 is grounded, and the gate of the NMOS transistor n2 receives the data signal D1 output from the common node DN; the source of the NMOS transistor n3 is connected to the drain of the NMOS transistor n2, and the gate of the NMOS transistor n3 receives the clock signal CLKNN1 output from the common node N12; the drain of the NMOS transistor n3 is connected to the drain of the PMOS transistor p3, forming a common node N5.

[0067] The clock-controlled transmission unit C4 includes a PMOS transistor p8, a PMOS transistor p9, an NMOS transistor n8, and an NMOS transistor n9; the source of the PMOS transistor p8 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p8 receives the signal of the common node N5; the source of the PMOS transistor p9 is connected to the drain of the PMOS transistor p8, and the gate of the PMOS transistor p9 receives the clock signal CLKNN1 output from the common node N12; the source of the NMOS transistor n8 is grounded, and the gate of the NMOS transistor n8 receives the signal of the common node N5; the source of the NMOS transistor n9 is connected to the drain of the NMOS transistor n8, and the gate of the NMOS transistor n9 receives the clock signal CLKN1 output from the common node N11; the drain of the NMOS transistor n9 is connected to the drain of the PMOS transistor p9, forming a common node N6. The common node N6 serves as an output end and outputs the data signal D2.

[0068] The clock-controlled transmission unit C5 includes a PMOS transistor p10, a PMOS transistor p11, an NMOS transistor n10, and an NMOS transistor n11; the source of the PMOS transistor p10 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p10 receives the signal of the common node N5; the source of the PMOS transistor p11 is connected to the drain of the PMOS transistor p10, the gate of the PMOS transistor p11 receives the clock signal CLKN2 output from the common node N13, and the drain of the PMOS transistor p11 is connected to the common node N6; the source of the NMOS transistor n10 is grounded, and the gate of the NMOS transistor n10 receives the signal of the common node N5; the source of the NMOS transistor n11 is connected to the drain of the NMOS transistor n10, the gate of the NMOS transistor n11 receives the clock signal CLKNN2 output from the common node N14, and the drain of the NMOS transistor n11 is connected to the common node N6.

[0069] Inverter INV2 includes a PMOS transistor p12 and an NMOS transistor n12; the source of the PMOS transistor p12 is connected to the power supply voltage VDD, the gate of the PMOS transistor p12 receives the signal of the common node N6, and the drain of the PMOS transistor p12 is connected to the common node N5; the source of the NMOS transistor n12 is grounded, the gate of the NMOS transistor n12 receives the signal of the common node N6; and the drain of the NMOS transistor n12 is connected to the common node N5.

[0070] like Figure 1 As shown, the second latch circuit includes a clocked transmission unit C2, a clocked transmission unit C3, a DICE structure, a C unit C6, an inverter INV3, an inverter INV4 and a C unit C7.

[0071] The clock-controlled transmission unit C2 includes a PMOS transistor p4, a PMOS transistor p5, an NMOS transistor n4, and an NMOS transistor n5; the source of the PMOS transistor p4 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p4 receives the data signal D1 output from the common node DN; the source of the PMOS transistor p5 is connected to the drain of the PMOS transistor p4, and the gate of the PMOS transistor p5 receives the clock signal CLKN1 output from the common node N11; the source of the NMOS transistor n4 is grounded, and the gate of the NMOS transistor n4 receives the data signal D1 output from the common node DN; the source of the NMOS transistor n5 is connected to the drain of the NMOS transistor n4, and the gate of the NMOS transistor n5 receives the clock signal CLKNN1 output from the common node N12; the drain of the NMOS transistor n5 is connected to the drain of the PMOS transistor p5, forming a common node N4.

[0072] The clock-controlled transmission unit C3 includes a PMOS transistor p6, a PMOS transistor p7, an NMOS transistor n6, and an NMOS transistor n7; wherein the source of the PMOS transistor p6 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p6 receives the data signal D1 output from the common node DN; the source of the PMOS transistor p7 is connected to the drain of the PMOS transistor p6, and the gate of the PMOS transistor p7 receives the clock signal CLKN1 output from the common node N11; the source of the NMOS transistor n6 is grounded, and the gate of the NMOS transistor n6 receives the data signal D1 output from the common node DN; the source of the NMOS transistor n7 is connected to the drain of the NMOS transistor n6, and the gate of the NMOS transistor n7 receives the clock signal CLKNN1 output from the common node N12; the drain of the NMOS transistor n7 is connected to the drain of the PMOS transistor p7, forming a common node N2.

[0073] like Figure 2 As shown, the DICE structure includes a transmission unit C9, a clocked transmission unit C10, a transmission unit C11 and a clocked transmission unit C12.

[0074] The transmission unit C9 includes a PMOS transistor p21 and an NMOS transistor n21; the source of the PMOS transistor p21 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p21 receives the signal of the common node N4; the source of the NMOS transistor n21 is grounded, the gate of the NMOS transistor n21 receives the signal of the common node N2, and the drain of the NMOS transistor n21 is connected to the drain of the PMOS transistor p21, forming a common node N1.

[0075] The clock-controlled transmission unit C10 includes a PMOS transistor p22, a PMOS transistor p23, an NMOS transistor n22, and an NMOS transistor n23; the source of the PMOS transistor p22 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p22 receives the signal of the common node N1; the source of the PMOS transistor p23 is connected to the drain of the PMOS transistor p22, the gate of the PMOS transistor p23 receives the clock signal CLKNN1 output from the common node N12, and the drain of the PMOS transistor p23 is connected to the common node N2; the source of the NMOS transistor n22 is grounded, and the gate of the NMOS transistor n22 receives the signal of the common node N3; the source of the NMOS transistor n23 is connected to the drain of the NMOS transistor n22, the gate of the NMOS transistor n23 receives the clock signal CLKN1 output from the common node N11, and the drain of the NMOS transistor n23 is connected to the common node N2.

[0076] The transmission unit C11 includes a PMOS transistor p24 and an NMOS transistor n24; the source of the PMOS transistor p24 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p24 receives the signal of the common node N2; the source of the NMOS transistor n24 is grounded, the gate of the NMOS transistor n24 receives the signal of the common node N4, and the drain of the NMOS transistor n24 is connected to the drain of the PMOS transistor p24, forming a common node N3.

[0077] The clock-controlled transmission unit C12 includes a PMOS transistor p25, a PMOS transistor p26, an NMOS transistor n25, and an NMOS transistor n26; the source of the PMOS transistor p25 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p25 receives the signal of the common node N3; the source of the PMOS transistor p26 is connected to the drain of the PMOS transistor p25, the gate of the PMOS transistor p26 receives the clock signal CLKNN1 output from the common node N12, and the drain of the PMOS transistor p26 is connected to the common node N4; the source of the NMOS transistor n25 is grounded, and the gate of the NMOS transistor n25 receives the signal of the common node N1; the source of the NMOS transistor n26 is connected to the drain of the NMOS transistor n25, the gate of the NMOS transistor n26 receives the clock signal CLKN1 output from the common node N11, and the drain of the NMOS transistor n26 is connected to the common node N4.

[0078] The C unit C6 includes a PMOS transistor p13, a PMOS transistor p14, an NMOS transistor n13, and an NMOS transistor n14; the source of the PMOS transistor p13 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p13 receives the signal of the common node N3; the source of the PMOS transistor p14 is connected to the drain of the PMOS transistor p13, and the gate of the PMOS transistor p14 receives the signal of the common node N1; the source of the NMOS transistor n13 is grounded, and the gate of the NMOS transistor n13 receives the signal of the common node N3; the source of the NMOS transistor n14 is connected to the drain of the NMOS transistor n13, and the gate of the NMOS transistor n14 receives the signal of the common node N1; the drain of the NMOS transistor n14 is connected to the drain of the PMOS transistor p14, forming a common node N7.

[0079] Inverter INV3 includes a PMOS transistor p15 and an NMOS transistor n15; the source of the PMOS transistor p15 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p15 receives the signal of the common node N7; the source of the NMOS transistor n15 is grounded, and the gate of the NMOS transistor n15 receives the signal of the common node N7; the drain of the NMOS transistor n15 is connected to the drain of the PMOS transistor p15, forming a common node N8, which serves as an output end to output the data signal D3.

[0080] The C unit C7 includes a PMOS transistor p17, a PMOS transistor p18, an NMOS transistor n17, and an NMOS transistor n18; the source of the PMOS transistor p17 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p17 receives the signal of the common node N8; the source of the PMOS transistor p18 is connected to the drain of the PMOS transistor p17, and the gate of the PMOS transistor p18 receives the signal of the common node N5; the source of the NMOS transistor n17 is grounded, and the gate of the NMOS transistor n17 receives the signal of the common node N8; the source of the NMOS transistor n18 is connected to the drain of the NMOS transistor n17, and the gate of the NMOS transistor n18 receives the signal of the common node N5, and the drain of the NMOS transistor n18 is connected to the drain of the PMOS transistor p18, forming a common node N9.

[0081] Inverter INV4 includes a PMOS transistor p16 and an NMOS transistor n16; the source of the PMOS transistor p16 is connected to the power supply voltage VDD, the gate of the PMOS transistor p16 receives the signal of the common node N9, and the drain of the PMOS transistor p16 is connected to the common node N4 and the common node N2; the source of the NMOS transistor n16 is grounded, the gate of the NMOS transistor n16 receives the signal of the common node N9; and the drain of the NMOS transistor n16 is connected to the common node N4 and the common node N2.

[0082] In an optional embodiment of the present invention, the latch is further improved based on the DICE structure, the clock signal circuit is redundant, and a redundant transmission circuit composed of the C unit C7 and the inverter INV4 and the first latch circuit are added in the second latch circuit, so that the latch can restore the signal of the node affected by the single-particle upset, thereby enhancing the latch's ability to resist multi-node and clock signal single-particle upsets.

[0083] like Figure 1 As shown, the output circuit includes a C unit C8.

[0084] The C unit C8 includes a PMOS transistor p19, a PMOS transistor p20, an NMOS transistor n19, and an NMOS transistor n20; the source of the PMOS transistor p19 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p19 receives the data signal D2 output from the common node N6; the source of the PMOS transistor p20 is connected to the drain of the PMOS transistor p19, and the gate of the PMOS transistor p20 receives the data signal D3 output from the common node N8; the source of the NMOS transistor n19 is grounded, and the gate of the NMOS transistor n19 receives the data signal D2 output from the common node N6; the source of the NMOS transistor n20 is connected to the drain of the NMOS transistor n19, and the gate of the NMOS transistor n20 receives the data signal D3 output from the common node N8. The drain of the NMOS transistor n20 is connected to the drain of the PMOS transistor p20 to form a common node N10. The common node N10 serves as the output end of the output circuit and outputs the data signal Q to the outside.

[0085] Depend on Figure 1 、 Figure 2 、 Figure 3It can be seen that when the data signal D is at a high level, the NMOS tube n1 is turned on, the inverter INV1 is turned on, and the signal at the common node DN is at a low level. When the clock signal CLK is at a high level, the NMOS tubes n27 and n29 are turned on, the inverters INV5 and INV7 are turned on, and the clock signals CLKN1 and CLKN2 output by the common nodes N11 and N13 are at a low level. The PMOS tubes p28 and p30 are turned on, the inverters INV6 and INV8 are turned on, and the clock signals CLKNN1 and CLKNN2 of the common nodes N12 and N14 are at a high level, then the PMOS tubes p2, p3, p4, p5, p6, and p7 are turned on, and the clock-controlled transmission units C1, C2, and C3 are turned on. When the signals at the common nodes N5, N4, and N2 are high, the NMOS transistors n10, n11, n21, and n24 are turned on, the clock-controlled transmission unit C5 is turned on, the transmission unit C9, and the transmission unit C11 are turned on, and the DICE structure is in a transparent state. At this time, the signals at the common nodes N6, N3, and N1 are low, the PMOS transistors p12, p13, and p14 are turned on, the C unit C6 is turned on, and the inverter INV2 is turned on. At this time, the signal at the common node N7 is high, the NMOS transistor n15 is turned on, and the inverter INV3 is turned on. At this time, the signal at the common node N8 is low, the NMOS transistor n18 and PMOS transistor p17 are turned on, the C unit C7 is not turned on, the PMOS transistors p19 and p20 are turned on, and the C unit C8 is turned on. At this time, the output signal Q of the common node N10 is high. The first latch circuit and the second latch circuit are in a transparent state, and the latch is in a transparent state.

[0086] When the clock signal CLK becomes low, the PMOS tubes p27 and p29 are turned on, and the inverters INV5 and INV7 are turned on. At this time, the clock signals CLKN1 and CLKN2 of the common nodes N11 and N13 are high, the NMOS tubes n28 and n30 are turned on, and the inverters INV6 and INV8 are turned on. At this time, the clock signals CLKNN1 and CLKNN2 of the common nodes N12 and N14 are low, and the clock-controlled transmission units C1, C2, C3, and C5 are not turned on. At this time, the signals of the common nodes N5, N4, and N2 remain unchanged and are still high, then the NMOS tubes n8, n9, n21, n24, PMOS tubes p22, and p23 , PMOS transistors p25 and p26 are turned on, clocked transmission unit C4 is turned on, transmission unit C9, clocked transmission unit C10, transmission unit C11, and clocked transmission unit C12 are turned on, and the DICE structure is in a latched state. The signals at common nodes N6, N3, and N1 are low, then PMOS transistors p12, p13, and p14 are turned on, inverter INV2 is turned on, and C unit C6 is turned on. At this time, the signal at common node N7 is high, then NMOS transistor n15 is turned on, inverter INV3 is turned on, and the signal at common node N8 is low, then NMOS transistor n18 and PMOS transistor p17 are turned on, C unit C7 is not turned on, then PMOS transistors p19 and p20 are turned on, and C unit C8 is turned on. At this time, the output signal Q of common node N10 is high. The first latch circuit and the second latch circuit are in a latched state, and the latch is in a latched state.

[0087] When the data signal D is low, the PMOS tube p1 is turned on, and the inverter INV1 is turned on. At this time, the signal of the common node DN is high. When the clock signal CLK is high, the NMOS tubes n27 and n29 are turned on, and the inverters INV5 and INV7 are turned on. At this time, the clock signals CLKN1 and CLKN2 output by the common nodes N11 and N13 are low. The PMOS tubes p28 and p30 are turned on, and the inverters INV6 and INV8 are turned on. At this time, the clock signals CLKNN1 and CLKNN2 of the common nodes N12 and N14 are high. Then the NMOS tubes n2, n3, n4, n5, n6, and n7 are turned on, and the clock-controlled transmission units C1, C2, and C3 are turned on. At this time, the common When the signals at nodes N5, N4, and N2 are low, the PMOS transistors p10, p11, p21, and p24 are turned on, the clock-controlled transmission unit C5 is turned on, and the transmission unit C9 and C11 are turned on. The DICE structure is in a transparent state. At this time, the signals at common nodes N6, N3, and N1 are high, then the NMOS transistors n12, n13, and n14 are turned on, the C unit C6 is turned on, and the inverter INV2 is turned on. At this time, the signal at common node N7 is low, then the PMOS transistor p15 is turned on, and the inverter INV3 is turned on. At this time, the signal at common node N8 is high, then the PMOS transistor p18 and NMOS transistor n17 are turned on, and the C unit C7 is not turned on. Then the NMOS transistors n19 and n20 are turned on, and the C unit C8 is turned on. At this time, the output signal Q of the common node N10 is low. The first latch circuit and the second latch circuit are in a transparent state, and the latch is in a transparent state.

[0088] When the clock signal CLK becomes low, the PMOS tubes p27 and p29 are turned on, and the inverters INV5 and INV7 are turned on. At this time, the clock signals CLKN1 and CLKN2 of the common nodes N11 and N13 are high, the NMOS tubes n28 and n30 are turned on, and the inverters INV6 and INV8 are turned on. At this time, the clock signals CLKNN1 and CLKNN2 of the common nodes N12 and N14 are low, and the clock-controlled transmission units C1, C2, C3, and C5 are not turned on. At this time, the signals of the common nodes N5, N4, and N2 remain unchanged and are still low, then the PMOS tubes p8, p9, p21, p24, n22, and n23 , NMOS transistors n25 and n26 are turned on, clocked transmission unit C4 is turned on, transmission unit C9, clocked transmission unit C10, transmission unit C11, and clocked transmission unit C12 are turned on, and the DICE structure is in a latched state. The signals at common nodes N6, N3, and N1 are high, then NMOS transistors n12, n13, and n14 are turned on, inverter INV2 is turned on, and C unit C6 is turned on. At this time, the signal at common node N7 is low, then PMOS transistor p15 is turned on, inverter INV3 is turned on, and the signal at common node N8 is high, then PMOS transistor p18 and NMOS transistor n17 are turned on, C unit C7 is not turned on, then NMOS transistors n19 and n20 are turned on, and C unit C8 is turned on. At this time, the output signal Q of common node N10 is low. The first latch circuit and the second latch circuit are in a latched state, and the latch is in a latched state.

[0089] In summary, the logic function of the redundant self-recovery reinforced latch of the present invention is normal.

[0090] The DICE structure has excellent resistance to single-node single-event upsets. However, when all redundant nodes in a conventional DICE structure flip, the DICE output signal flips, resulting in an erroneous output. In one embodiment of the present invention, a redundant transmission circuit consisting of a C cell C7 and an inverter INV4, as well as a first latch circuit, is added. When the data signal D is high and the clock signal CLK transitions from high to low, the first and second latch circuits transition from a transparent state to a latched state, and the latches are in the latched state. At this point, the common nodes N5, N4, and N2 are all high, while the common nodes N6, N3, and N1 are all low. When the signals of at least two common nodes among the common nodes N1, N2, N3, and N4 are flipped, the other nodes will also be flipped. The output signal of the DICE structure, that is, the signals of the common nodes N3 and N1, will be flipped. The common nodes N3 and N1 will flip to a high level, and the common nodes N4 and N2 will flip to a low level. The signals of the common nodes N3 and N1 will remain consistent. The C unit C6 is turned on, which will cause the signals of the common nodes N7 and N8 to flip. The common node N7 flips to a low level, and the common node N8 flips to a high level. The output data signal D3 of the second latch circuit is flipped, the first latch circuit is not affected, the common nodes N5 and N6 are not affected, the common node N5 is a high level, and the common node N6 is a low level. The first latch circuit still outputs the correct data signal D2, and the signal level of the common node N8 is the same as that of the common node N6. Different, at this time, the C unit C8 enters a high-impedance state and will not output a single-particle upset signal. The output signal Q of the common node N10 remains unchanged, and the signal levels of the common node N5 and the common node N8 are the same at this time. The C unit C7 is turned on, and the redundant transmission circuit composed of the C unit C7 and the inverter INV4 is turned on, and the driving capability of the inverter INV4 is stronger than the DICE structure. The signal output by the redundant transmission circuit can pull up the signals of the common nodes N4 and N2, and then restore the signals of the common nodes N4 and N2. The signal of the common node N8 is restored to a low level. At this time, the signal levels of the common node N8 and the common node N5 are different. The C unit C7 enters a high-impedance state, the redundant transmission circuit is not turned on, the signal levels of the common node N8 and the common node N6 are the same, the C unit C8 is turned on, and the output signal Q of the common node N10 remains high and unchanged.

[0091] When the data signal D is low and the clock signal CLK changes from high to low, the first latch circuit and the second latch circuit change from transparent to latched, and the latch is in the latched state. At this time, the common nodes N5, N4, and N2 are all low, and the common nodes N6, N3, and N1 are all high. When the signals of at least two common nodes among the common nodes N1, N2, N3, and N4 are flipped, the other nodes will also be flipped. The output signal of the DICE structure, that is, the signals of the common nodes N3 and N1, will be flipped. The common nodes N3 and N1 will flip to a low level, and the common nodes N4 and N2 will flip to a high level. The signals of the common nodes N3 and N1 will remain consistent. The C unit C6 is turned on, which will cause the signals of the common nodes N7 and N8 to flip. The common node N7 flips to a high level, and the common node N8 flips to a low level. The output data signal D3 of the second latch circuit is flipped, the first latch circuit is not affected, the common nodes N5 and N6 are not affected, the common node N5 is a low level, and the common node N6 is a high level. The first latch circuit still outputs the correct data signal D2, and the signal level of the common node N8 is the same as that of the common node N6. Different, at this time, the C unit C8 enters a high-impedance state and will not output a single-particle upset signal. The output signal Q of the common node N10 remains unchanged, and the signal levels of the common node N5 and the common node N8 are the same at this time. The C unit C7 is turned on, and the redundant transmission circuit composed of the C unit C7 and the inverter INV4 is turned on, and the driving capability of the inverter INV4 is stronger than the DICE structure. The signal output by the redundant transmission circuit can pull down the signals of the common nodes N4 and N2, and then restore the signals of the common nodes N4 and N2. The signal of the common node N8 is restored to a high level. At this time, the signal levels of the common node N8 and the common node N5 are different. The C unit C7 enters a high-impedance state, the redundant transmission circuit is not turned on, the signal levels of the common node N8 and the common node N6 are the same, the C unit C8 is turned on, and the output signal Q of the common node N10 remains at a low level and remains unchanged.

[0092] It can be seen from this that an optional embodiment of the present invention has obvious resistance to multi-node single event upsets.

[0093] According to the traditional DICE structure, when the clock signal flips due to a single-particle effect, the latch circuit changes from a latched state to a transparent state, changing the working state of the latch circuit. If the input signal is different from the signal at the time of latching, the latch outputs an incorrect result. In one embodiment of the present invention, a clock signal circuit is redundantly divided into two identical clock signal circuits CLK1 and CLK2. When the clock signal CLK is at a low level, the first latch circuit and the second latch circuit are in a latched state. The clock-controlled transmission units C1, C2, and C3 are not conducting, the clock-controlled transmission unit C5 is not conducting, and the clock-controlled transmission unit C4 is conducting. The latch is in a latched state. A single event causes the clock signal CLKN2 at the common node N13 to transition to a low level, and the clock signal CLKNN2 at the common node N14 is high. Only the first latch circuit is affected, and the second latch circuit is not affected. At this time, the clock-controlled transmission units C1, C2, and C3 are not conducting, the clock-controlled transmission unit C4 is conducting, and the clock-controlled transmission unit C5 is conducting. The first latch circuit and the second latch circuit remain in a latched state. The signals at the common nodes N5 and N6 remain unchanged, and the signal at the common node N8 is unaffected, thereby causing the latch output signal Q to remain unchanged.

[0094] When the clock signal CLK is at a low level, the first latch circuit and the second latch circuit are in a latched state, the clock-controlled transmission unit C1, the clock-controlled transmission unit C2, and the clock-controlled transmission unit C3 are not conducting, the clock-controlled transmission unit C5 is not conducting, and the clock-controlled transmission unit C4 is conducting. The single particle causes the clock signal CLKN1 of the common node N11 to turn to a low level, and the clock signal CLKNN1 of the common node N12 is a high level. The first latch circuit and the second latch circuit are both affected. At this time, the clock-controlled transmission unit C1, the clock-controlled transmission unit C2, and the clock-controlled transmission unit C3 are conducting, the clock-controlled transmission unit C5 is not conducting, and the clock-controlled transmission unit C4 is not conducting. The second latch circuit changes from a latched state to a transparent state, and the first latch circuit changes from a latched state to a transparent state. A latch circuit is not conducting. If the signal at the common node DN is the same as the signal at the time of latching, the signals at the common nodes N5, N2, N4, N3, N1, N7, and N8 do not change, and the signal at the common node N6 is not affected. Therefore, the output signal Q of the common node N10 remains unchanged, and the latch output signal remains unchanged. If the signal at the common node DN is opposite to the signal at the time of latching, when the signals at the common nodes N5, N2, and N4 flip from a high level to a low level, the signals at the common nodes N3 and N1 flip to a high level, the signal at the common node N7 flip to a low level, the signal at the common node N8 flip to a high level, and the signal at the common node N6 remains unaffected and remains at a low level. The signal at the common node N8 is different from the signal at the common node N6, and the C unit C8 enters a high-impedance state. The output signal Q of the common node N10 remains unchanged. And when the single-particle flip of the clock signal of the clock signal circuit CLK1 ends, the latch is in the latched state again. Since the driving ability of the inverter INV2 is stronger than the clock-controlled transmission unit C4, the signal of the unaffected common node N6 is flipped by the inverter INV2 to pull up the signal of the common node N5, so that the signal of the common node N5 is restored to a high level. The first latch circuit is in the latched state, and the signal of the common node N6 is still at a low level. At this time, the levels of the signals of the common node N5 and the common node N8 are the same, and the C unit C7 is turned on. The C unit C7 and the inverter INV4 form a The redundant transmission circuit is turned on, and the driving capability of inverter INV4 is stronger than that of the DICE structure. The signal output by the redundant transmission circuit can pull up the signals of common nodes N4 and N2, thereby recovering the signals of common nodes N4 and N2. The signal of common node N8 is restored to a low level. At this time, the signal levels of common node N8 and common node N5 are different, C unit C7 enters a high-impedance state, the redundant transmission circuit is not turned on, the signal levels of common node N8 and common node N6 are the same, C unit C8 is turned on, and the output signal Q of common node N10 is a high level, and no incorrect data signal is output. Further analysis based on the same principle shows that when the signal of common node DN is opposite to the signal during latching, and the signals of common nodes N5, N2, and N4 flip from a low level to a high level, an embodiment of the present invention still outputs the correct data signal, having the ability to self-recover.Only when the clock signals of the clock signal circuit CLK1 and the clock signal circuit CLK2 are both flipped, and at this time the common node DN signal is opposite to the signal during latching, the clock-controlled transmission unit C1, the clock-controlled transmission unit C2, the clock-controlled transmission unit C3, and the clock-controlled transmission unit C5 are turned on, the first latch circuit and the second latch circuit are both changed from the latched state to the transparent state, the signals of the common nodes N5, N4, N2, N3, N1, N6, N7, and N8 are all flipped, the C unit C8 is turned on, the output signal Q of the common node N10 is flipped, and the latch output signal is erroneous.

[0095] It can be seen from this that an optional embodiment of the present invention has obvious resistance to single event upset of clock signals.

[0096] In summary, an optional embodiment of the present invention exhibits significant resistance to multi-node single-event upsets and clock signal single-event upsets. By adding a redundant latch circuit and a redundant transmission circuit, the DICE-based latch is both resistant to multi-node single-event upsets and self-recovery capable. The redundant clock signal circuit also enables the latch to resist clock signal single-event upsets.

[0097] In an optional embodiment of the present invention, the clock signal circuit is made redundant and divided into two identical clock signal circuits CLK1 and CLK2. The operating states of the first latch circuit and the second latch circuit are controlled by the clock signals of the two clock signal circuits. If the clock signal of any clock signal circuit is flipped by a single particle, at most one of the output signals of common nodes N6 and N8 will flip, C unit C8 will enter a high-impedance state, the output signal Q of common node N10 will remain unchanged, and the latch will not output an erroneous result. In addition, the redundant transmission circuit composed of C unit C7 and inverter INV4 of the second latch circuit and the first latch circuit can recover the affected node. Only when the clock signals of clock signal circuit CLK1 and clock signal circuit CLK2 are flipped, causing the overall function of the latch circuit to malfunction, will the latch circuit output an erroneous result, thereby improving the latch's ability to resist single-particle flips of clock signals.

[0098] When all redundant nodes in a conventional DICE structure flip, the data output by the DICE structure flips, resulting in erroneous data output. In an embodiment of the present invention, when multiple nodes in the DICE structure flip, flipping the output signals of common nodes N3 and N1, which in turn flips the output signals of common nodes N7 and N8, the output signal of common node N6 does not flip, and C cell C8 enters a high-impedance state. The output signal Q of common node N10 remains unchanged, and the latch does not output an erroneous result. At the same time, the voltage levels of common nodes N5 and N8 are the same, and the redundant transmission circuit composed of C cell C7 and inverter INV4 is conductive, which can restore the signals of common nodes N4 and N2. This prevents the latch circuit from latching erroneous data signals, thereby improving the latch's ability to withstand multi-node single-event upsets.

[0099] The above description is only the best specific implementation method of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

[0100] The contents not described in detail in the specification of the present invention belong to the common knowledge of professionals in this field.

Claims

1. A redundant self-recovery latch resistant to multiple nodes and clock signal single event upset, characterized in that: include: An input circuit receives an external data signal D, flips the data signal D, obtains a data signal D1 and transmits the data signal D1 to the first latch circuit and the second latch circuit; A first clock signal circuit CLK1 receives an external clock signal CLK, inverts the clock signal CLK to obtain a first clock signal CLKN1 and a clock signal CLKNN1, and transmits the obtained signals to a first latch circuit and a second latch circuit to control the working states of the first latch circuit and the second latch circuit; The second clock signal circuit CLK2 receives an external clock signal CLK, inverts the clock signal CLK to obtain a second clock signal CLKN2 and a clock signal CLKNN2, and transmits the obtained clock signals to the first latch circuit to control the working state of the first latch circuit; The first latch circuit is controlled by the first clock signal CLKN1 and the clock signal CLKNN1, as well as the second clock signal CLKN2 and the clock signal CLKNN2. When the clock signal CLK is at a high level, the first latch circuit receives the data signal D1 transmitted by the input circuit in real time. The first latch circuit is in a transparent state and performs inversion processing on the data signal D1 to obtain a data signal D2 and transmits it to the output circuit. When the clock signal CLK is at a low level, the first latch circuit does not receive the data signal D1 transmitted by the input circuit. The first latch circuit is in a latched state and latches the data signal D1 transmitted by the input circuit last received when the clock signal CLK is at a high level, performs inversion processing on the data signal D2 and transmits it to the output circuit. The second latch circuit is controlled by the first clock signal CLKN1 and the clock signal CLKNN1. When the clock signal CLK is at a high level, the second latch circuit receives the data signal D1 transmitted by the input circuit in real time. The second latch circuit is in a transparent state and inverts the data signal D1 to obtain a data signal D3 and transmits it to the output circuit. When the clock signal CLK is at a low level, the second latch circuit does not receive the data signal D1 transmitted by the input circuit. The second latch circuit is in a latched state and latches the data signal D1 transmitted by the input circuit last received when the clock signal CLK is at a high level, inverts the data signal D3 and transmits it to the output circuit. an output circuit, receiving a data signal D2 transmitted by the first latch circuit and a data signal D3 transmitted by the second latch circuit, flipping the data signals D2 and D3, obtaining a data signal Q and outputting it externally; The first latch circuit includes a clock-controlled transmission unit C1, a clock-controlled transmission unit C4, a clock-controlled transmission unit C5 and an inverter INV2; The second latch circuit includes a clocked transmission unit C2, a clocked transmission unit C3, a DICE structure, a C unit C6, an inverter INV3, an inverter INV4 and a C unit C7.

2. The redundant self-recovery latch resistant to multiple nodes and clock signal single event upset according to claim 1, characterized in that: Meet at least one of the following: The levels of the clock signals CLKN1 and CLKN2 are synchronized; The high and low levels of the clock signals CLKNN1 and CLKNN2 are synchronized.

3. The redundant self-recovery latch resistant to multiple nodes and clock signal single event upset according to claim 1, characterized in that: When the clock signal CLK is at a low level, the clock signals CLKN1 and CLKN2 are at a high level, and the clock signals CLKNN1 and CLKNN2 are at a low level.

4. The redundant self-recovery latch resistant to multiple nodes and clock signal single event upset according to claim 1, characterized in that: The first clock signal circuit CLK1 includes an inverter INV5 and an inverter INV6; The inverter INV5 includes a PMOS transistor p27 and an NMOS transistor n27, wherein the source of the PMOS transistor p27 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p27 receives the clock signal CLK; the source of the NMOS transistor n27 is grounded, the gate of the NMOS transistor n27 receives the clock signal CLK, and the drain of the NMOS transistor n27 is connected to the drain of the PMOS transistor p27 to form a common node N11. The common node N11 serves as an output end and outputs the clock signal CLKN1. The inverter INV6 includes a PMOS transistor p28 and an NMOS transistor n28, wherein the source of the PMOS transistor p28 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p28 receives the clock signal CLKN1 output from the common node N11; the source of the NMOS transistor n28 is grounded, and the gate of the NMOS transistor n28 receives the clock signal CLKN1 from the common node N11. The drain of the NMOS transistor n28 is connected to the drain of the PMOS transistor p28 to form a common node N12. The common node N12 serves as an output end to output the clock signal CLKNN1.

5. The redundant self-recovery latch resistant to multiple nodes and clock signal single event upset according to claim 1, characterized in that: The second clock signal circuit CLK2 includes an inverter INV7 and an inverter INV8; The inverter INV7 includes a PMOS transistor p29 and an NMOS transistor n29, wherein the source of the PMOS transistor p29 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p29 receives the clock signal CLK; the source of the NMOS transistor n29 is grounded, the gate of the NMOS transistor n29 receives the clock signal CLK, and the drain of the NMOS transistor n29 is connected to the drain of the PMOS transistor p29 to form a common node N13. The common node N13 serves as an output end and outputs the clock signal CLKN2. The inverter INV8 includes a PMOS transistor p30 and an NMOS transistor n30, wherein the source of the PMOS transistor p30 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p30 receives the clock signal CLKN2 output from the common node N13; the source of the NMOS transistor n30 is grounded, and the gate of the NMOS transistor n30 receives the clock signal CLKN2 from the common node N13; the drain of the NMOS transistor n30 is connected to the drain of the PMOS transistor p30 to form a common node N14, and the common node N14 serves as an output end to output the clock signal CLKNN2.

6. The redundant self-recovery latch resistant to multiple nodes and clock signal single event upset according to claim 1, characterized in that: The input circuit includes an inverter INV1; The inverter INV1 includes a PMOS transistor p1 and an NMOS transistor n1, wherein the source of the PMOS transistor p1 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p1 receives the data signal D transmitted from the outside; the source of the NMOS transistor n1 is grounded, the gate of the NMOS transistor n1 receives the data signal D transmitted from the outside, and the drain of the NMOS transistor n1 is connected to the drain of the PMOS transistor p1 to form a common node DN. The common node DN serves as an output end to output the data signal D1.

7. The redundant self-recovery latch resistant to multiple nodes and clock signal single event upset according to claim 1, characterized in that: The clock-controlled transmission unit C1 includes a PMOS transistor p2, a PMOS transistor p3, an NMOS transistor n2, and an NMOS transistor n3, wherein the source of the PMOS transistor p2 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p2 receives the data signal D1 output from the common node DN; the source of the PMOS transistor p3 is connected to the drain of the PMOS transistor p2, and the gate of the PMOS transistor p3 receives the clock signal CLKN1 output from the common node N11; the source of the NMOS transistor n2 is grounded, and the gate of the NMOS transistor n2 receives the data signal D1 output from the common node DN; the source of the NMOS transistor n3 is connected to the drain of the NMOS transistor n2, and the gate of the NMOS transistor n3 receives the clock signal CLKNN1 output from the common node N12; the drain of the NMOS transistor n3 is connected to the drain of the PMOS transistor p3, forming a common node N5; The clock-controlled transmission unit C4 includes a PMOS transistor p8, a PMOS transistor p9, an NMOS transistor n8, and an NMOS transistor n9, wherein the source of the PMOS transistor p8 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p8 receives the signal of the common node N5; the source of the PMOS transistor p9 is connected to the drain of the PMOS transistor p8, and the gate of the PMOS transistor p9 receives the clock signal CLKNN1 output from the common node N12; the source of the NMOS transistor n8 is grounded, and the gate of the NMOS transistor n8 receives the signal of the common node N5; the source of the NMOS transistor n9 is connected to the drain of the NMOS transistor n8, and the gate of the NMOS transistor n9 receives the clock signal CLKN1 output from the common node N11; the drain of the NMOS transistor n9 is connected to the drain of the PMOS transistor p9, forming a common node N6, and the common node N6 serves as an output end to output the data signal D2; The clock-controlled transmission unit C5 includes a PMOS transistor p10, a PMOS transistor p11, an NMOS transistor n10, and an NMOS transistor n11, wherein the source of the PMOS transistor p10 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p10 receives the signal of the common node N5; the source of the PMOS transistor p11 is connected to the drain of the PMOS transistor p10, the gate of the PMOS transistor p11 receives the clock signal CLKN2 output from the common node N13, and the drain of the PMOS transistor p11 is connected to the common node N6; the source of the NMOS transistor n10 is grounded, and the gate of the NMOS transistor n10 receives the signal of the common node N5; the source of the NMOS transistor n11 is connected to the drain of the NMOS transistor n10, the gate of the NMOS transistor n11 receives the clock signal CLKNN2 output from the common node N14, and the drain of the NMOS transistor n11 is connected to the common node N6; The inverter INV2 includes a PMOS transistor p12 and an NMOS transistor n12, wherein the source of the PMOS transistor p12 is connected to the power supply voltage VDD, the gate of the PMOS transistor p12 receives the signal of the common node N6, and the drain of the PMOS transistor p12 is connected to the common node N5; the source of the NMOS transistor n12 is grounded, the gate of the NMOS transistor n12 receives the signal of the common node N6; and the drain of the NMOS transistor n12 is connected to the common node N5.

8. The redundant self-recovery latch resistant to multiple nodes and clock signal single event upset according to claim 7, characterized in that: The driving capability of the clock-controlled transmission unit C1 is greater than that of the inverter INV2 , and the driving capability of the inverter INV2 is greater than that of the clock-controlled transmission unit C4 .

9. The redundant self-recovery latch resistant to multiple nodes and clock signal single event upset according to claim 1, characterized in that: The clock-controlled transmission unit C2 includes a PMOS transistor p4, a PMOS transistor p5, an NMOS transistor n4, and an NMOS transistor n5, wherein the source of the PMOS transistor p4 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p4 receives the data signal D1 output from the common node DN; the source of the PMOS transistor p5 is connected to the drain of the PMOS transistor p4, and the gate of the PMOS transistor p5 receives the clock signal CLKN1 output from the common node N11; the source of the NMOS transistor n4 is grounded, and the gate of the NMOS transistor n4 receives the data signal D1 output from the common node DN; the source of the NMOS transistor n5 is connected to the drain of the NMOS transistor n4, and the gate of the NMOS transistor n5 receives the clock signal CLKNN1 output from the common node N12; the drain of the NMOS transistor n5 is connected to the drain of the PMOS transistor p5, forming a common node N4; The clock-controlled transmission unit C3 includes a PMOS transistor p6, a PMOS transistor p7, an NMOS transistor n6, and an NMOS transistor n7, wherein the source of the PMOS transistor p6 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p6 receives the data signal D1 output from the common node DN; the source of the PMOS transistor p7 is connected to the drain of the PMOS transistor p6, and the gate of the PMOS transistor p7 receives the clock signal CLKN1 output from the common node N11; the source of the NMOS transistor n6 is grounded, and the gate of the NMOS transistor n6 receives the data signal D1 output from the common node DN; the source of the NMOS transistor n7 is connected to the drain of the NMOS transistor n6, and the gate of the NMOS transistor n7 receives the clock signal CLKNN1 output from the common node N12; the drain of the NMOS transistor n7 is connected to the drain of the PMOS transistor p7, forming a common node N2; The DICE structure includes a transmission unit C9, a clock-controlled transmission unit C10, a transmission unit C11, and a clock-controlled transmission unit C12. The transmission unit C9 includes a PMOS transistor p21 and an NMOS transistor n21, wherein the source of the PMOS transistor p21 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p21 receives a signal from the common node N4; the source of the NMOS transistor n21 is grounded, the gate of the NMOS transistor n21 receives a signal from the common node N2, and the drain of the NMOS transistor n21 is connected to the drain of the PMOS transistor p21 to form a common node N1; the clock-controlled transmission unit C10 includes a PMOS transistor p22, a PMOS transistor p23, an NMOS transistor n22, and an NMOS transistor n23, wherein the source of the PMOS transistor p22 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p22 receives a signal from the common node N1; The source of the PMOS transistor p23 is connected to the drain of the PMOS transistor p22, the gate of the PMOS transistor p23 receives the clock signal CLKNN1 output from the common node N12, and the drain of the PMOS transistor p23 is connected to the common node N2; the source of the NMOS transistor n22 is grounded, and the gate of the NMOS transistor n22 receives the signal of the common node N3; the source of the NMOS transistor n23 is connected to the drain of the NMOS transistor n22, the gate of the NMOS transistor n23 receives the clock signal CLKN1 output from the common node N11, and the drain of the NMOS transistor n23 is connected to the common node N2; the transmission unit C11 includes a PMOS transistor p24 and an NMOS transistor n24, wherein the source of the PMOS transistor p24 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p24 receives the signal of the common node N2; the source of the NMOS transistor n24 is grounded, the gate of the NMOS transistor n24 receives the signal of the common node N4, and the drain of the NMOS transistor n24 is connected to the common node N2. The gate of the PMOS transistor p24 is connected to the drain of the PMOS transistor p24 to form a common node N3; the clock-controlled transmission unit C12 includes a PMOS transistor p25, a PMOS transistor p26, an NMOS transistor n25, and an NMOS transistor n26, wherein the source of the PMOS transistor p25 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p25 receives the signal of the common node N3; the source of the PMOS transistor p26 is connected to the drain of the PMOS transistor p25, the gate of the PMOS transistor p26 receives the clock signal CLKNN1 output from the common node N12, and the drain of the PMOS transistor p26 is connected to the common node N4; the source of the NMOS transistor n25 is grounded, and the gate of the NMOS transistor n25 receives the signal of the common node N1; the source of the NMOS transistor n26 is connected to the drain of the NMOS transistor n25, the gate of the NMOS transistor n26 receives the clock signal CLKN1 output from the common node N11, and the drain of the NMOS transistor n26 is connected to the common node N4; The C unit C6 includes a PMOS transistor p13, a PMOS transistor p14, an NMOS transistor n13, and an NMOS transistor n14, wherein the source of the PMOS transistor p13 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p13 receives the signal of the common node N3; the source of the PMOS transistor p14 is connected to the drain of the PMOS transistor p13, and the gate of the PMOS transistor p14 receives the signal of the common node N1; the source of the NMOS transistor n13 is grounded, and the gate of the NMOS transistor n13 receives the signal of the common node N3; the source of the NMOS transistor n14 is connected to the drain of the NMOS transistor n13, and the gate of the NMOS transistor n14 receives the signal of the common node N1; the drain of the NMOS transistor n14 is connected to the drain of the PMOS transistor p14, forming a common node N7; The inverter INV3 includes a PMOS transistor p15 and an NMOS transistor n15, wherein the source of the PMOS transistor p15 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p15 receives a signal from the common node N7; The source of the NMOS transistor n15 is grounded, and the gate of the NMOS transistor n15 receives a signal from the common node N7; The drain of the NMOS transistor n15 is connected to the drain of the PMOS transistor p15 to form a common node N8. The common node N8 serves as an output terminal to output the data signal D3. The C unit C7 includes a PMOS transistor p17, a PMOS transistor p18, an NMOS transistor n17, and an NMOS transistor n18, wherein the source of the PMOS transistor p17 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p17 receives the signal of the common node N8; the source of the PMOS transistor p18 is connected to the drain of the PMOS transistor p17, and the gate of the PMOS transistor p18 receives the signal of the common node N5; the source of the NMOS transistor n17 is grounded, and the gate of the NMOS transistor n17 receives the signal of the common node N8; the source of the NMOS transistor n18 is connected to the drain of the NMOS transistor n17, and the gate of the NMOS transistor n18 receives the signal of the common node N5, and the drain of the NMOS transistor n18 is connected to the drain of the PMOS transistor p18, forming a common node N9; The inverter INV4 includes: a PMOS transistor p16 and an NMOS transistor n16, wherein the source of the PMOS transistor p16 is connected to the power supply voltage VDD, the gate of the PMOS transistor p16 receives the signal of the common node N9, and the drain of the PMOS transistor p16 is connected to the common node N4 and the common node N2; the source of the NMOS transistor n16 is grounded, the gate of the NMOS transistor n16 receives the signal of the common node N9; and the drain of the NMOS transistor n16 is connected to the common node N4 and the common node N2.

10. The redundant self-recovery latch resistant to multiple nodes and clock signal single event upset according to claim 9, characterized in that: The driving capabilities of the clock-controlled transmission unit C2 and the clock-controlled transmission unit C3 are greater than those of the inverter INV4 , and the driving capability of the inverter INV4 is greater than that of the DICE structure.

11. The redundant self-recovery latch resistant to multiple nodes and clock signal single event upset according to claim 1, characterized in that: The output circuit includes a C unit C8; The C unit C8 includes a PMOS transistor p19, a PMOS transistor p20, an NMOS transistor n19, and an NMOS transistor n20, wherein the source of the PMOS transistor p19 is connected to the power supply voltage VDD, and the gate of the PMOS transistor p19 receives the data signal D2 output by the common node N6; the source of the PMOS transistor p20 is connected to the drain of the PMOS transistor p19, and the gate of the PMOS transistor p20 receives the data signal D3 output by the common node N8; the source of the NMOS transistor n19 is grounded, and the gate of the NMOS transistor n19 receives the data signal D2 output by the common node N6; the source of the NMOS transistor n20 is connected to the drain of the NMOS transistor n19, and the gate of the NMOS transistor n20 receives the data signal D3 output by the common node N8; the drain of the NMOS transistor n20 is connected to the drain of the PMOS transistor p20 to form a common node N10. The common node N10 serves as the output end of the output circuit and outputs the data signal Q to the outside.

Images