A data transmission method and device, electronic equipment and storage medium

Abstract

The application provides a data transmission method and device, electronic equipment and storage medium. A programmable logic element is connected to a host through a first bus and connected to a plurality of slave devices with the same device address through a plurality of second buses. In response to a start signal triggered by the first bus, a read-write instruction and a to-be-transmitted address sent by the host are received. The to-be-transmitted address is transmitted to the plurality of slave devices through the plurality of second buses. Target transmission data is transmitted based on the read-write instruction until a termination signal triggered by the first bus, and the transmission of the target transmission data is terminated. Based on the above method, the data transmission between the host and the plurality of slave devices with the same device address can be directly realized by the programmable logic element without configuring access parameters, the design complexity required for bus communication is reduced, and the data transmission efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a data transmission method, apparatus, electronic device, and storage medium. Background Technology

[0002] An Inter-Integrated Circuit (I2C) bus is a bidirectional, two-wire synchronous serial bus that transmits data between a master and slave devices via communication ports. Each slave device connected to an I2C bus with the same communication port has a unique device address. Therefore, when a master needs to access multiple slave devices with the same device address simultaneously, multiple different I2C buses are typically connected to access these slave devices with the same device address. Figure 1 As shown, when the host needs to access multiple optical modules, the host needs to provide multiple communication ports to connect multiple different integrated circuit buses because the device address of each optical module is fixed. Since the host usually has a limited number of communication interfaces (4 or less), it is necessary to connect external logic devices to expand the host's communication interfaces.

[0003] External logic devices connected to the host often simulate control units facing multiple integrated circuit buses. These control units need to transmit data with slave devices connected to each of the multiple integrated circuit buses through access parameters (such as device address, registers, etc.) pre-configured in the external logic device by the host. This method requires the host to configure the corresponding access parameters during data transmission, resulting in a certain transmission delay. At the same time, the host needs to read the transmitted data obtained from the slave device from the external logic device again, further increasing the design complexity required for bus communication and reducing data transmission efficiency. Summary of the Invention

[0004] This application provides a data transmission method, apparatus, electronic device, and storage medium to reduce device complexity and improve data transmission efficiency.

[0005] In a first aspect, this application provides a data transmission method, in which a programmable logic element is connected to a host via a first bus and to multiple slave devices via multiple second buses, wherein the multiple slave devices are associated with the same first device address, and the method includes:

[0006] The programmable logic element responds to the start signal triggered by the first bus and receives a read / write instruction and a transmission address sent by the host, wherein the read / write instruction is used to instruct the host to perform data processing operations on the target data to be transmitted, and the transmission address is the first device address.

[0007] The address to be transmitted is transmitted to the multiple slave devices via the multiple second buses;

[0008] Based on the read / write instruction, the target data is transmitted until the first bus triggers a termination signal.

[0009] In one possible implementation, the programmable logic element is a field-programmable gate array (FPGA) or a complex programmable logic device (CPL), and the first bus and the second bus are integrated circuit buses.

[0010] The first bus includes at least: a first serial clock line and a first serial data line, wherein the first serial clock line is used to generate clock pulses for the target transmission data, and the first serial data line is used to transmit the target transmission data between the host and the programmable logic element.

[0011] The second bus includes at least a second serial clock line and a second serial data line, wherein the second serial clock line is used to synchronously generate the clock pulse, and the second serial data line is used to transmit the target transmission data between the programmable logic element and the plurality of slave devices.

[0012] In one possible implementation, the programmable logic element carries a state machine, which is used to indicate the transmission status of the target data. Then, the step of receiving a read / write instruction and the address to be transmitted from the host in response to the first bus trigger start signal includes:

[0013] In response to the start signal triggered by the first bus, the state machine is controlled to operate in the bus configuration state;

[0014] The start signal is transmitted to the multiple slave devices through the multiple second buses respectively, and the working state of the state machine is controlled based on the start response clock and the response results of the multiple slave devices to the start signal. The start response clock is generated through the first serial clock line and is used to indicate the response results of the multiple slave devices to the start signal.

[0015] In response to the state machine being in the device address transmission state, the device receives read / write instructions and the address to be transmitted from the host.

[0016] In one possible implementation, controlling the operating state of the state machine based on the start acknowledgment clock and the respective acknowledgment results of the plurality of slave devices in response to the start signal includes:

[0017] In response to the first serial clock line generating the start response clock, the operating state of the state machine is controlled to the configuration response state;

[0018] Based on the configured response status, it is determined whether the response results of each of the plurality of slave devices to the start signal carry the signal response of each of the plurality of slave devices to the start signal; wherein:

[0019] If so, then control the working state of the state machine to the device address transmission state;

[0020] Otherwise, the state machine is controlled to be in an idle state.

[0021] In one possible implementation, transmitting the address to be transmitted to the plurality of slave devices via the plurality of second buses includes:

[0022] The address to be transmitted is transmitted to the multiple slave devices through the multiple second buses, so that each of the multiple slave devices is matched with the address to be transmitted, and the address matching result of each of the multiple slave devices is obtained;

[0023] The operating state of the state machine is controlled based on the address acknowledgment clock and the address matching results of the plurality of slave devices. The address acknowledgment clock is generated through the first serial clock line and is used to indicate the receipt of the address matching results of the plurality of slave devices. Wherein:

[0024] If there is a mismatch between the multiple slave devices and the address to be transmitted, the state machine is controlled to be in an idle state.

[0025] If the multiple slave devices do not match the address to be transmitted, then the state machine is controlled to operate in the data transmission state.

[0026] In one possible implementation, transmitting the target data based on the read / write instruction includes:

[0027] In response to the state machine's operating state being a data transmission state, the data transmission direction for the target data is determined based on the read / write instruction; wherein:

[0028] If the data processing operation associated with the read / write indication is write, then the working state of the state machine is controlled to be the data write state, and based on the data write state, the data transmission direction for the target transmission data is determined to be the first direction, wherein the first direction is the transmission direction of the target transmission data from the host to the multiple slave devices;

[0029] If the data processing operation associated with the read / write indication is read, then the working state of the state machine is controlled to be the bus configuration state, and based on the bus configuration state, the first bus is controlled to trigger a restart signal, and based on the restart signal, the data transmission direction for the target data is determined;

[0030] The target data is transmitted in accordance with the data transmission direction.

[0031] In one possible implementation, determining the data transmission direction for the target data transmission based on the restart signal includes:

[0032] In response to the first serial clock line generating a restart response clock, the operating state of the state machine is controlled to the configured response state, wherein the restart response clock is generated through the first serial clock line and is used to indicate the response results received from the plurality of slave devices in response to the restart signal;

[0033] Based on the configured response status, it is determined whether the response results of each of the plurality of slave devices in response to the restart signal carry the signal response of each of the plurality of slave devices in response to the restart signal; wherein:

[0034] If so, the state machine is controlled to operate in a data reading state, and in response to the data reading state, the data transmission direction for the target data is determined to be a second direction, wherein the second direction is the transmission direction in which the target data is output from the plurality of slave devices and input to the host.

[0035] Otherwise, the working state of the state machine is controlled to be the idle state.

[0036] In one possible implementation, the data transmission direction is a first direction, and after transmitting the target data according to the data transmission direction, the method further includes:

[0037] The working state of the state machine is controlled based on the write acknowledgment clock, wherein the write acknowledgment clock is generated by the first serial clock line, and when the first serial clock line generates the write acknowledgment clock, it controls the working state of the state machine to the write acknowledgment state.

[0038] The data transmission direction is a second direction. After transmitting the target data according to the data transmission direction, the process further includes:

[0039] The state machine's operating state is controlled based on the read response clock, wherein the read response clock is generated by the first serial clock line, and the first serial clock line controls the state machine's operating state to the read response state when generating the read response clock.

[0040] In one possible implementation, the start signal is triggered when the first serial clock line is at a high level and the first serial data line transitions from a high level to a low level; the stop signal is triggered when the first serial clock line is at a high level and the first serial data line transitions from a low level to a high level; and the restart signal is triggered when the first serial clock line is at a high level and the first serial data line transitions from a high level to a low level.

[0041] Secondly, this application provides a data transmission apparatus in which a programmable logic element is connected to a host via a first bus and to multiple slave devices via multiple second buses, wherein the multiple slave devices are associated with the same device address, and the apparatus includes:

[0042] A start response module is used to respond to a start signal triggered by the first bus and receive a read / write instruction and a transmission address sent by the host, wherein the read / write instruction is used to instruct the host to perform data processing operations on the target data to be transmitted, and the transmission address is the address of the first device.

[0043] The address transmission module is used to transmit the address to be transmitted to the multiple slave devices via the multiple second buses;

[0044] The data transmission module is used to transmit the target data based on the read / write instruction until the first bus triggers a termination signal.

[0045] In one possible implementation, the programmable logic element is a field-programmable gate array (FPGA) or a complex programmable logic device (CPL), and the first bus and the second bus are integrated circuit buses.

[0046] The first bus includes at least: a first serial clock line and a first serial data line, wherein the first serial clock line is used to generate clock pulses for the target transmission data, and the first serial data line is used to transmit the target transmission data between the host and the programmable logic element.

[0047] The second bus includes at least a second serial clock line and a second serial data line, wherein the second serial clock line is used to synchronously generate the clock pulse, and the second serial data line is used to transmit the target transmission data between the programmable logic element and the plurality of slave devices.

[0048] In one possible implementation, the programmable logic element carries a state machine, which is used to indicate the transmission status of the target data. Then, in response to the first bus trigger start signal, the module receives a read / write instruction and the address to be transmitted from the host. The start response module is used to:

[0049] In response to the start signal triggered by the first bus, the state machine is controlled to operate in the bus configuration state;

[0050] The start signal is transmitted to the multiple slave devices through the multiple second buses respectively, and the working state of the state machine is controlled based on the start response clock and the response results of the multiple slave devices to the start signal. The start response clock is generated through the first serial clock line and is used to indicate the response results of the multiple slave devices to the start signal.

[0051] In response to the state machine being in the device address transmission state, the device receives read / write instructions and the address to be transmitted from the host.

[0052] In one possible implementation, the operating state of the state machine is controlled based on the start response clock and the response results of each of the plurality of slave devices in response to the start signal. The start response module is used for:

[0053] In response to the first serial clock line generating the start response clock, the operating state of the state machine is controlled to the configuration response state;

[0054] Based on the configured response status, it is determined whether the response results of each of the plurality of slave devices to the start signal carry the signal response of each of the plurality of slave devices to the start signal; wherein:

[0055] If so, then control the working state of the state machine to the device address transmission state;

[0056] Otherwise, the state machine is controlled to be in an idle state.

[0057] In one possible implementation, the address to be transmitted is transmitted to the plurality of slave devices respectively via the plurality of second buses, wherein the address transmission module is used for:

[0058] The address to be transmitted is transmitted to the multiple slave devices through the multiple second buses, so that each of the multiple slave devices is matched with the address to be transmitted, and the address matching result of each of the multiple slave devices is obtained;

[0059] The operating state of the state machine is controlled based on the address acknowledgment clock and the address matching results of the plurality of slave devices. The address acknowledgment clock is generated through the first serial clock line and is used to indicate the receipt of the address matching results of the plurality of slave devices. Wherein:

[0060] If there is a mismatch between the multiple slave devices and the address to be transmitted, the state machine is controlled to be in an idle state.

[0061] If the multiple slave devices do not match the address to be transmitted, then the state machine is controlled to operate in the data transmission state.

[0062] In one possible implementation, the target data is transmitted based on the read / write instruction, and the data transmission module is used to:

[0063] In response to the state machine's operating state being a data transmission state, the data transmission direction for the target data is determined based on the read / write instruction; wherein:

[0064] If the data processing operation associated with the read / write indication is write, then the working state of the state machine is controlled to be the data write state, and based on the data write state, the data transmission direction for the target transmission data is determined to be the first direction, wherein the first direction is the transmission direction of the target transmission data from the host to the multiple slave devices;

[0065] If the data processing operation associated with the read / write indication is read, then the working state of the state machine is controlled to be the bus configuration state, and based on the bus configuration state, the first bus is controlled to trigger a restart signal, and based on the restart signal, the data transmission direction for the target data is determined;

[0066] The target data is transmitted in accordance with the data transmission direction.

[0067] In one possible implementation, the data transmission module is used to determine the data transmission direction for the target transmission data based on the restart signal, wherein the data transmission module is configured to:

[0068] In response to the first serial clock line generating a restart response clock, the operating state of the state machine is controlled to the configured response state, wherein the restart response clock is generated through the first serial clock line and is used to indicate the response results received from the plurality of slave devices in response to the restart signal;

[0069] Based on the configured response status, it is determined whether the response results of each of the plurality of slave devices in response to the restart signal carry the signal response of each of the plurality of slave devices in response to the restart signal; wherein:

[0070] If so, the state machine is controlled to operate in a data reading state, and in response to the data reading state, the data transmission direction for the target data is determined to be a second direction, wherein the second direction is the transmission direction in which the target data is output from the plurality of slave devices and input to the host.

[0071] Otherwise, the working state of the state machine is controlled to be the idle state.

[0072] In one possible implementation, the data transmission direction is a first direction, and after transmitting the target data according to the data transmission direction, the data transmission module is further configured to:

[0073] The working state of the state machine is controlled based on the write acknowledgment clock, wherein the write acknowledgment clock is generated by the first serial clock line, and when the first serial clock line generates the write acknowledgment clock, it controls the working state of the state machine to the write acknowledgment state.

[0074] The data transmission direction is the second direction. After transmitting the target data according to the data transmission direction, the data transmission module is further used for:

[0075] The state machine's operating state is controlled based on the read response clock, wherein the read response clock is generated by the first serial clock line, and the first serial clock line controls the state machine's operating state to the read response state when generating the read response clock.

[0076] In one possible implementation, the start signal is triggered when the first serial clock line is at a high level and the first serial data line transitions from a high level to a low level; the stop signal is triggered when the first serial clock line is at a high level and the first serial data line transitions from a low level to a high level; and the restart signal is triggered when the first serial clock line is at a high level and the first serial data line transitions from a high level to a low level.

[0077] Thirdly, an electronic device is proposed, comprising a processor and a memory, wherein the memory stores program code that, when executed by the processor, causes the processor to perform the steps of the data transmission method described in the first aspect.

[0078] Fourthly, a computer-readable storage medium is provided, comprising program code that, when executed on an electronic device, causes the electronic device to perform the steps of the data transmission method described in the first aspect.

[0079] The technical effects that the technical solution provided in this application can bring are as follows:

[0080] This application provides a data transmission method, apparatus, electronic device, and storage medium. Based on programmable logic elements, a host is connected via a first bus, and multiple slave devices with the same device address are connected via multiple second buses. The method responds to a start signal triggered by the first bus by receiving read / write instructions and a target address from the host. The read / write instructions instruct the host to perform data processing operations on the target data to be transmitted. The target address is the same device address associated with the multiple slave devices. The target address is transmitted to the multiple slave devices via the multiple second buses, and the target data is transmitted based on the read / write instructions until a stop signal is triggered by the first bus. Based on this method, data transmission between the host and multiple slave devices with the same device address can be directly achieved using programmable logic elements without configuring access parameters, reducing the design complexity required for bus communication and thus improving data transmission efficiency. Attached Figure Description

[0081] Figure 1 A schematic diagram of a common data transmission device provided in an embodiment of this application;

[0082] Figure 2 This is a schematic diagram illustrating a possible application scenario provided by an embodiment of this application;

[0083] Figure 3 A flowchart illustrating a data transmission method provided in an embodiment of this application;

[0084] Figure 4 A schematic diagram illustrating a specific implementation scenario provided in this application.

[0085] Figure 5 A schematic diagram illustrating another specific implementation scenario provided by the embodiments of this application;

[0086] Figure 6 This is a schematic diagram of the structure of a data transmission device provided in an embodiment of this application;

[0087] Figure 7 This is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0088] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this invention.

[0089] It should be noted that in the description of this application, "multiple" is understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. A connected to B can represent: A and B directly connected, or A and B connected through C. Furthermore, in the description of this application, terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0090] Furthermore, in the embodiments of this application, the host refers to the device that obtains bus control during the transmission process, while the other devices connected to the bus are slave devices for the host. It is understood that in specific implementations, any device connected to the bus can be used as the aforementioned host, and this application does not impose any restrictions on this.

[0091] The data transmission method provided in this application will now be described and explained in detail with reference to the accompanying drawings.

[0092] See Figure 2 As shown, this is a schematic diagram of a possible application scenario provided by an embodiment of this application. The application scenario includes: a host 21, a programmable logic element 22, and multiple slave devices 23, wherein:

[0093] The host 21 can be a server or any electronic device with data processing capabilities. The host 21 can be connected to the programmable logic element 22 via a first bus. Specifically, it can be connected to the integrated circuit bus port carried on the programmable logic element 22 via the first bus. The first bus can include at least a first serial clock line and a first serial data line. The first serial clock line can be an integrated circuit serial clock line (SCL) used to generate clock pulses for the target data transmission. The first serial data line can be an integrated circuit serial data line (SDA) used to transmit the target data between the host 21 and the programmable logic element 22.

[0094] Furthermore, the programmable logic element 22 can be an external programming device with logic conversion and logic processing capabilities. Specifically, the programmable logic element 22 can be a field programmable gate array (FPGA) or a complex programmable logic device (CPLD). In this embodiment, the programmable logic element 22 can be connected to the host 21 via a first bus through an integrated circuit bus port, and connected to multiple slave devices 23 via second buses through the remaining bus ports.

[0095] Furthermore, the slave device 23 can be an external device corresponding to the server where the host 21 is located, or it can be any electronic device with data processing capabilities required by the host 21, such as an optical module. In this embodiment, the multiple slave devices 23 that are to transmit data have the same first device address and transmit target data with the host 21 through the multiple second buses.

[0096] See Figure 3 As shown, based on the above application scenario, this application provides a flowchart of a data transmission method. It is worth noting that the data transmission method provided in this application can be executed by the aforementioned programmable logic element, or jointly by the programmable logic element and its associated driving device. This application does not impose any restrictions on this. Specifically, the method includes:

[0097] S301: In response to the start signal triggered by the first bus, it receives the read / write instruction and the address to be transmitted sent by the host.

[0098] Specifically, the target data to be transmitted can be the data to be transmitted stored in the host or the data to be transmitted stored in any slave device. When the host determines to start transmitting the target data, it triggers a start signal to the programmable logic element through the first bus and sends read / write instructions and the addresses to be transmitted for multiple slave devices to the programmable logic element.

[0099] In one possible implementation, the programmable logic element is the aforementioned Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD), and the first bus and the second bus are the aforementioned Integrated Circuit Bus (I2C). The first bus includes at least a first serial clock line and a first serial data line. The first serial clock line is used to generate clock pulses for target data transmission, and the first serial data line is used to transmit target data between the host and the programmable logic element. The second bus includes at least a second serial clock line and a second serial data line. The second serial clock line is used to synchronously generate clock pulses, and the second serial data line is used to transmit target data between the programmable logic element and multiple slave devices.

[0100] In one possible implementation, the address to be transmitted can be a first device address of each slave device, for example, the first device address can be 7 bits or 10 bits; the read / write indication can be any bit of a logic signal that follows the address to be transmitted, for example, the read / write indication can be a 1-bit logic signal, wherein when the first serial data line is high, the corresponding read / write indication is "1", used to indicate that the host is to perform a "read" operation on the target transmitted data, and when the first serial data line is low, the corresponding read / write indication is "0", used to indicate that the host is to perform a "write" operation on the target transmitted data.

[0101] Based on the above implementation method, Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD) are used as programmable logic elements to alleviate the device resources occupied by the communication interface on the host side, ensuring normal data transmission between the host and multiple slave devices. At the same time, since FPGA and CPLD can carry multiple communication interfaces supporting integrated circuit buses, data transmission with a large number of slave devices can be guaranteed without further developing multiple logic devices, further saving the resource cost required for data transmission and reducing the development complexity required for hardware development.

[0102] In one possible implementation, the programmable logic element carries a state machine. Specifically, upon receiving a read / write instruction and the address to be transferred from the host in response to a first bus trigger start signal, the following steps are executed based on the carried state machine:

[0103] Step 1: In response to the start signal triggered by the first bus, the operating state of the control state machine is set to the bus configuration state.

[0104] Step 2: Transmit the start signal to multiple slave devices through multiple second buses, and control the working state of the state machine based on the start response clock and the response results of each slave device to the start signal.

[0105] Step 3: In response to the state machine's working state being device address transmission state, receive read / write instructions and the address to be transmitted sent by the host.

[0106] Specifically, before the first bus triggers the start signal, the state machine is in an idle state. Then, in response to the first bus triggering the start signal, the state machine is controlled to be in a bus configuration state.

[0107] Furthermore, the aforementioned start acknowledgment clock is generated through the first serial clock line, and the start acknowledgment clock is used to receive the acknowledgment results of multiple slave devices in response to the start signal.

[0108] For example, the first bus is an integrated circuit bus, and the start acknowledgment clock can be the 9th clock pulse generated by the first serial clock line after the start signal.

[0109] Optionally, the start signal can be a specified level signal triggered by the first bus. Specifically, in this embodiment, the first bus trigger start signal is determined when the first serial clock line is at a high level and the first serial data line jumps from a high level to a low level.

[0110] In the above implementation, the state machine has multiple working states set for each transmission state between the master and multiple slave devices. When the first bus triggers the start signal, the state machine first enters the bus configuration state and transmits the start signal to multiple slave devices through multiple second buses. Furthermore, based on the response results of the multiple slave devices to the start signal obtained by the start response clock, the state machine is controlled to enter the corresponding next working state. Thus, the transmission process is decomposed into multiple steps corresponding to the multiple working states of the state machine. By switching the working states through the state machine, the normal operation of each step is ensured, effectively resisting possible abnormal situations such as bus stretching (I2C_stretch) and bus non-response, and ensuring the robustness and robustness of the design.

[0111] In one possible implementation, step 2 above, based on the start response clock and the response results of the multiple slave devices to the start signal, controls the operating state of the state machine, including:

[0112] Step 21: In response to the first serial clock line generating a start acknowledgment clock, the operating state of the control state machine is set to the configuration acknowledgment state.

[0113] Step 22: Based on the configuration response status, determine whether the response results of each of the multiple slave devices to the start signal carry the signal response of each of the multiple slave devices to the start signal; if yes, proceed to step 23; otherwise, proceed to step 24.

[0114] Step 23: The operating state of the control state machine is set to device address transmission state.

[0115] Step 24: Set the state machine to idle state.

[0116] Specifically, at the start of the response clock, the state machine enters the configuration response state. At this time, it controls multiple second buses to transmit the corresponding response results from multiple slave devices to the master. The configuration response state is the working state set when the first serial clock line generates the start response clock normally. The device address transmission state is the working state set when multiple slave devices respond normally to the start signal trigger signal. The idle state is the working state set when the master does not need to transmit data.

[0117] It is worth noting that if step 21 or step 22 above is not executed normally (e.g., no start response clock is generated), the working state of the control state machine is idle, which will not be elaborated here.

[0118] Based on the above steps, the control flow for the working state of the state machine in S301 is as follows:

[0119] Idle state (IDLE) - Bus configuration state (I2C_DEVICE) - Configuration acknowledgment state (DEVICE_ACK) - Device address transfer state (I2C_ADDR).

[0120] Specifically, in this embodiment, the aforementioned idle state (IDLE) indicates a state where no data transmission is required between the host and multiple slave devices; in other words, there is no start signal or any other signal transmission on the first bus. The aforementioned bus configuration state (I2C_DEVICE) indicates a state where the host sends a start signal to multiple slave devices when data transmission is required. The aforementioned configuration acknowledgment state (DEVICE_ACK) indicates a state where the host receives the acknowledgment results from multiple slave devices for the start signal at the start acknowledgment clock. The aforementioned device address transmission state (I2C_ADDR) indicates a state where the host sends read / write instructions and the address to be transmitted to multiple slave devices.

[0121] Based on the above control flow, when the host needs to transmit data with multiple slave devices, the state machine switches from the idle state (IDLE) to the bus configuration state (I2C_DEVICE) to transmit the start signal from the host to the multiple slave devices. Further, in response to the start acknowledgment clock, the state machine switches from the bus configuration state (I2C_DEVICE) to the configuration acknowledgment state (DEVICE_ACK) to transmit each acknowledgment result from the multiple slave devices to the host. The acknowledgment result includes whether the host responded to or did not respond to the start signal. Then, upon determining that multiple slave devices have responded... When responding, the state machine automatically switches from the acknowledgment state (DEVICE_ACK) to the device address transmission state (I2C_ADDR). This state is used to receive read / write instructions and the address to be transmitted from the host, and to transmit these instructions and the address to be transmitted from the host to multiple slave devices. As can be seen, based on the above working states, the signals between the host and multiple slave devices can only be transmitted in one way at any given time (from the host to multiple slave devices or from multiple slave devices to the host). This further protects against abnormal situations and avoids signal loops in bidirectional transmission, ensuring the robustness and sturdiness of the state machine design.

[0122] S302: The address to be transmitted is transmitted to multiple slave devices through multiple second buses.

[0123] In one possible implementation, the programmable logic element transmits the address to be transmitted to multiple slave devices through multiple second buses for addressing the multiple slave devices. Specifically, the address to be transmitted is transmitted to multiple slave devices through multiple second buses to trigger each slave device to match its own device address with the address to be transmitted, and to determine whether its own device address matches the address to be transmitted, thereby obtaining the corresponding address matching result.

[0124] Furthermore, based on the address acknowledgment clock, the address matching results of multiple slave devices are received. The address acknowledgment clock is generated via a first serial clock line and is used to receive the acknowledgment clock pulses of the address matching results of the multiple slave devices. For example, in this embodiment, the address acknowledgment clock can be generated by the first serial clock line. The 9th clock pulse generated after the aforementioned initial acknowledgment clock is then used to control the operating state of the state machine again based on each address matching result. Specifically, this includes:

[0125] Case 1: If multiple slave devices do not match the address to be transmitted, the control state machine will be in an idle state.

[0126] Specifically, if one or more slave devices do not match the address to be transmitted in the received address matching results, the method is interrupted and the state machine is in an idle state.

[0127] Case 2: If multiple slave devices do not match the address to be transmitted, the control state machine will be in the data transmission state.

[0128] Specifically, if none of the received address matching results are inconsistent between the slave device and the address to be transmitted, that is, each slave device is consistent with the address to be transmitted, then the method continues and the working state of the control state machine is the data transmission state.

[0129] Based on the above steps, in S302, the control flow for the working state of the state machine is as follows: device address transmission state (I2C_ADDR) - device address acknowledgment state (ADDR_ACK) - data transmission state (I2C_START).

[0130] Specifically, in this embodiment, the aforementioned device address response state (ADDR_ACK) indicates the state in which the host receives the response results from multiple slave devices for the address to be transmitted during the address response clock; the aforementioned data transmission state (I2C_START) indicates the state in which data transmission can occur between the host and multiple slave devices. Based on the above method, when the state machine switches from the device address transmission state (I2C_ADDR) to the device address response state (ADDR_ACK), the address matching results are transmitted from the multiple slave devices to the host. Furthermore, the programmable logic element determines that the device addresses of the multiple slave devices match, and when the matching is consistent, the state machine switches from the device address response state (ADDR_ACK) to the data transmission state (I2C_START).

[0131] S303: Based on read / write instructions, transmit target data until the first bus triggers a termination signal.

[0132] In one possible implementation, the read / write instruction is used to instruct the host to perform a "read" operation on the target transmission data, that is, based on the read / write instruction, the target transmission data output by the slave device is read into the host; the read / write instruction is used to instruct the host to perform a "write" operation on the target transmission data, that is, based on the read / write instruction, the host outputs the target transmission data and writes it into the slave device.

[0133] Furthermore, based on read / write instructions, the target data is transmitted, including:

[0134] Step 1: In response to the state machine's working state being the data transmission state, determine the data transmission direction based on the read / write indication.

[0135] Step 2: Transmit the target data according to the data transmission direction.

[0136] Optionally, in step 1 above, based on the read / write instruction, any one of the following steps can be performed:

[0137] Step 1.1: If the data processing operation associated with the read / write indication is write, then the working state of the control state machine is the data write state, and based on the data write state, the data transmission direction for the target data is determined to be the first direction, wherein the first direction is the transmission direction of the target data from the host to multiple slave devices.

[0138] Specifically, when the data processing operation associated with the read / write instruction is write, the control state machine is in the data write state (I2C_WRITE), and in response to the data write state (I2C_WRITE), the target transmission data is transmitted in the first direction, that is, the target transmission data of the host is transmitted from the host to multiple slave devices through programmable logic elements.

[0139] Optionally, based on step 1.1 performed above, during the write operation transmission process, after transmitting data to the target in the first direction, the process further includes:

[0140] The operating state of the control state machine is based on the write acknowledgment clock, which is generated by the first serial clock line and is used to indicate that each of the multiple slave devices receives an acknowledgment clock pulse for the target transmitted data.

[0141] For example, if the write acknowledgment clock is generated via the first serial clock line, and is the 9th clock pulse after the target data is transmitted, then when the data processing operation associated with the read / write indication is write, the control flow of the state machine is as follows:

[0142] Data transfer status (I2C_START) - Data write status (I2C_WRITE) - Write acknowledgment clock (WRITE_ACK).

[0143] Step 1.2: If the data processing operation associated with the read / write instruction is read, the working state of the control state machine is the bus configuration state. Based on the bus configuration state, the first bus is controlled to trigger a restart signal, and based on the restart signal, the data transmission direction for the target data is determined.

[0144] Specifically, when the data processing operation associated with the read / write instruction is read, the operating state of the control state machine is the bus configuration state (I2C_DEVICE), and in response to the bus configuration state (I2C_DEVICE), the control of the first bus triggers a restart signal. The restart signal can be the same signal with the same characteristics as the start signal, or it can be another signal used to indicate that the state machine re-enters the bus configuration state. This application does not limit this.

[0145] For example, in this embodiment of the application, after the start signal is triggered, when the first serial clock line is at a high level and the first serial data line jumps from a high level to a low level, the first bus trigger restart signal is determined.

[0146] Optionally, the operating state of the state machine is controlled based on the triggered restart signal and the restart response clock, and the data transmission direction for the target data is determined based on the operating state of the state machine. The restart response clock is generated by the first serial clock line and is used to indicate the clock pulses received from the respective response results of multiple slave devices to the restart signal.

[0147] For example, the restart response clock is the 9th clock pulse after the restart signal is triggered.

[0148] Specifically, the above-mentioned determination of the data transmission direction for the target transmission data based on the restart signal includes:

[0149] Step 1.2.1: In response to the first serial clock line generating a restart response clock, the operating state of the control state machine is set to the configuration response state.

[0150] Step 1.2.2: Based on the configuration response status, determine whether the response results of each of the multiple slave devices in response to the restart signal carry the signal response of each of the multiple slave devices in response to the restart signal; if yes, proceed to step 1.2.3, otherwise proceed to step 1.2.4.

[0151] Step 1.2.3: Control the state machine to the data reading state, and in response to the data reading state, determine the data transmission direction for the target data transmission as the second direction.

[0152] Specifically, the second direction is the direction in which target data is transmitted from multiple slave devices to the host.

[0153] Step 1.2.4: Set the working state of the control state machine to the idle state.

[0154] Furthermore, based on the above method, if the data transmission direction is determined to be the second direction, then after transmitting the data to the target in the second direction, the process also includes:

[0155] The operating state of the control state machine is determined based on the read response clock, wherein the read response clock is generated by the first serial clock line. When the first serial clock line generates the read response clock, the operating state of the control state machine is the read response state.

[0156] Based on the above method, the state machine switches from the bus configuration state (I2C_DEVICE) to the configuration acknowledgment state (DEVICE_ACK) in response to the restart signal. During the restart acknowledgment clock, it receives the acknowledgment results from multiple slave devices in response to the restart signal. In response to the signal responses from multiple slave devices in the acknowledgment results, the state machine is controlled to operate in the data read state (I2C_READ). In response to the data read state (I2C_READ), the target transmission data is transmitted in the second direction, that is, the target transmission data from multiple slave devices is transmitted to the host through programmable logic elements. Further, based on the read acknowledgment clock, the state machine is controlled to operate in the read acknowledgment state (READ_ACK). The read acknowledgment clock is used to instruct the host to receive the acknowledgment clock pulse for the target transmission data. For example, it is generated by the first serial clock line and is the 9th clock pulse after the transmission of the target transmission data.

[0157] Based on the above approach, when the data processing operation associated with the read / write instruction is a read operation, the control flow of the state machine is as follows:

[0158] Data transfer status (I2C_START) - Bus configuration status (I2C_DEVICE) - Configuration acknowledgment status (DEVICE_ACK) - Data read status (I2C_READ) - Read acknowledgment status (READ_ACK).

[0159] The target data is then transmitted in the determined data transmission direction using the above method until the first bus triggers a termination signal.

[0160] Optionally, the termination signal can be a specified level signal triggered by the first bus. Specifically, in this embodiment, the termination signal is determined to be triggered by the first bus when the first serial clock line is at a high level and the first serial data line jumps from a low level to a high level.

[0161] Furthermore, in response to the termination signal, the transmission of the target data is terminated, and the control state machine enters the termination state (I2C_STOP).

[0162] For ease of understanding, please refer to Figure 4As shown, in one possible implementation scenario, the programmable logic element carries a state machine with each of the working states in S301-S303 described above. In this specific implementation scenario, the data processing operation associated with the read / write instruction sent by the host is write. When the first bus triggers the start signal, the state machine switches from the idle state (IDLE) to the bus configuration state (I2C_DEVICE), and switches to the configuration acknowledgment state (DEVICE_ACK) at the start acknowledgment clock. Further, in response to determining that multiple slave devices have received their respective signal responses to the start signal, it switches to the device address transmission state (I2C_ADDR), and switches to the device address acknowledgment state (ADDR_ACK) at the address acknowledgment clock. Further, in response to determining that multiple slave devices have received their respective address matching results, it switches to the data transmission state (I2C_START). Based on the above read / write instruction, the state machine then enters the data write state (I2C_WRITE), and enters the write acknowledgment state (WRITE_ACK) at the write acknowledgment clock, until it enters the transmission termination state (I2C_STOP) at the termination signal.

[0163] See Figure 5 As shown, in another possible implementation scenario, the programmable logic element carries a state machine with each of the working states in S301-S303 described above. In this specific implementation scenario, the data processing operation associated with the read / write instruction sent by the host is a read. Therefore, when the first bus triggers the start signal, the state machine switches from the idle state (IDLE) to the bus configuration state (I2C_DEVICE), and switches to the configuration acknowledgment state (DEVICE_ACK) at the start acknowledgment clock. Furthermore, in response to determining that multiple slave devices have received their respective signal responses to the start signal, it switches to the device address transfer state (I2C_ADDR), and switches to the device address transfer state at the address acknowledgment clock. In the address acknowledgment state (ADDR_ACK), in response to confirming that the address matching results of multiple slave devices have been received, the state machine switches to the data transmission state (I2C_START). Based on the above read / write indication, the state machine then responds to the restart signal to enter the bus configuration state (I2C_DEVICE), and enters the configuration acknowledgment state (DEVICE_ACK) on the restart acknowledgment clock. In response to the acknowledgment results of multiple slave devices in response to the restart signal, the state machine enters the data read state (I2C_READ), and further responds to the read acknowledgment clock to enter the read acknowledgment state (READ_ACK). Finally, upon the termination signal, the state machine enters the transmission termination state (I2C_STOP).

[0164] As can be seen, based on the above method, by configuring a state machine, data transmission between the host and multiple slave devices can only proceed in one data transmission direction at any given time, thereby ensuring normal data transmission and further ensuring the robustness and robustness of the design.

[0165] Based on the same technical concept, embodiments of this application also provide a data transmission apparatus. This apparatus is used to connect to a host via a first bus based on programmable logic elements, and to connect to multiple slave devices via multiple second buses respectively. The multiple slave devices are associated with the same device address, implementing the data transmission method flow described above. (See reference...) Figure 6 As shown, the device includes: a start response module 601, an address transmission module 602, and a data transmission module 603, wherein:

[0166] The start response module 601 is used to respond to the start signal triggered by the first bus and receive the read / write instruction and the address to be transmitted sent by the host, wherein the read / write instruction is used to instruct the host to perform data processing operations on the target data to be transmitted, and the address to be transmitted is the address of the first device.

[0167] Address transmission module 602 is used to transmit the address to be transmitted to the multiple slave devices through the multiple second buses respectively;

[0168] The data transmission module 603 is used to transmit the target data based on the read / write instruction until the first bus triggers a termination signal.

[0169] In one possible implementation, the programmable logic element is a field-programmable gate array (FPGA) or a complex programmable logic device (CPL), and the first bus and the second bus are integrated circuit buses.

[0170] The first bus includes at least: a first serial clock line and a first serial data line, wherein the first serial clock line is used to generate clock pulses for the target transmission data, and the first serial data line is used to transmit the target transmission data between the host and the programmable logic element.

[0171] The second bus includes at least a second serial clock line and a second serial data line, wherein the second serial clock line is used to synchronously generate the clock pulse, and the second serial data line is used to transmit the target transmission data between the programmable logic element and the plurality of slave devices.

[0172] In one possible implementation, the programmable logic element carries a state machine, which is used to indicate the transmission status of the target data. Then, in response to the first bus trigger start signal, the start response module 601, which receives a read / write instruction and the address to be transmitted from the host, is used to:

[0173] In response to the start signal triggered by the first bus, the state machine is controlled to operate in the bus configuration state;

[0174] The start signal is transmitted to the multiple slave devices through the multiple second buses respectively, and the working state of the state machine is controlled based on the start response clock and the response results of the multiple slave devices to the start signal. The start response clock is generated through the first serial clock line and is used to indicate the response results of the multiple slave devices to the start signal.

[0175] In response to the state machine being in the device address transmission state, the device receives read / write instructions and the address to be transmitted from the host.

[0176] In one possible implementation, the operating state of the state machine is controlled based on the start response clock and the response results of the plurality of slave devices in response to the start signal. The start response module 601 is used for:

[0177] In response to the first serial clock line generating the start response clock, the operating state of the state machine is controlled to the configuration response state;

[0178] Based on the configured response status, it is determined whether the response results of each of the plurality of slave devices to the start signal carry the signal response of each of the plurality of slave devices to the start signal; wherein:

[0179] If so, then control the working state of the state machine to the device address transmission state;

[0180] Otherwise, the state machine is controlled to be in an idle state.

[0181] In one possible implementation, the address to be transmitted is transmitted to the plurality of slave devices respectively via the plurality of second buses, wherein the address transmission module 602 is used for:

[0182] The address to be transmitted is transmitted to the multiple slave devices through the multiple second buses, so that each of the multiple slave devices is matched with the address to be transmitted, and the address matching result of each of the multiple slave devices is obtained;

[0183] The operating state of the state machine is controlled based on the address acknowledgment clock and the address matching results of the plurality of slave devices. The address acknowledgment clock is generated through the first serial clock line and is used to indicate the receipt of the address matching results of the plurality of slave devices. Wherein:

[0184] If there is a mismatch between the multiple slave devices and the address to be transmitted, the state machine is controlled to be in an idle state.

[0185] If the multiple slave devices do not match the address to be transmitted, then the state machine is controlled to operate in the data transmission state.

[0186] In one possible implementation, the data transmission module 603 is used to transmit the target data based on the read / write instruction, wherein the data transmission module 603 is configured to:

[0187] In response to the state machine's operating state being a data transmission state, the data transmission direction for the target data is determined based on the read / write instruction; wherein:

[0188] If the data processing operation associated with the read / write indication is write, then the working state of the state machine is controlled to be the data write state, and based on the data write state, the data transmission direction for the target transmission data is determined to be the first direction, wherein the first direction is the transmission direction of the target transmission data from the host to the multiple slave devices;

[0189] If the data processing operation associated with the read / write indication is read, then the working state of the state machine is controlled to be the bus configuration state, and based on the bus configuration state, the first bus is controlled to trigger a restart signal, and based on the restart signal, the data transmission direction for the target data is determined;

[0190] The target data is transmitted in accordance with the data transmission direction.

[0191] In one possible implementation, the data transmission module 603 is used to determine the data transmission direction for the target transmission data based on the restart signal, wherein the data transmission module 603 is configured to:

[0192] In response to the first serial clock line generating a restart response clock, the operating state of the state machine is controlled to the configured response state, wherein the restart response clock is generated through the first serial clock line and is used to indicate the response results received from the plurality of slave devices in response to the restart signal;

[0193] Based on the configured response status, it is determined whether the response results of each of the plurality of slave devices in response to the restart signal carry the signal response of each of the plurality of slave devices in response to the restart signal; wherein:

[0194] If so, the state machine is controlled to operate in a data reading state, and in response to the data reading state, the data transmission direction for the target data is determined to be a second direction, wherein the second direction is the transmission direction in which the target data is output from the plurality of slave devices and input to the host.

[0195] Otherwise, the working state of the state machine is controlled to be the idle state.

[0196] In one possible implementation, the data transmission direction is a first direction, and after transmitting the target data according to the data transmission direction, the data transmission module 603 is further configured to:

[0197] The working state of the state machine is controlled based on the write acknowledgment clock, wherein the write acknowledgment clock is generated by the first serial clock line, and when the first serial clock line generates the write acknowledgment clock, it controls the working state of the state machine to the write acknowledgment state.

[0198] The data transmission direction is the second direction. After transmitting the target data according to the data transmission direction, the data transmission module 603 is further configured to:

[0199] The state machine's operating state is controlled based on the read response clock, wherein the read response clock is generated by the first serial clock line, and the first serial clock line controls the state machine's operating state to the read response state when generating the read response clock.

[0200] In one possible implementation, the start signal is triggered when the first serial clock line is at a high level and the first serial data line transitions from a high level to a low level; the stop signal is triggered when the first serial clock line is at a high level and the first serial data line transitions from a low level to a high level; and the restart signal is triggered when the first serial clock line is at a high level and the first serial data line transitions from a high level to a low level.

[0201] Based on the same inventive concept as the embodiments described above, this application also provides an electronic device that can be used for data transmission. In one embodiment, the electronic device can be a server, a terminal device, or other electronic equipment. In this embodiment, the structure of the electronic device can be as follows: Figure 7As shown, it includes a memory 701, a communication interface 703, and one or more processors 702.

[0202] The memory 701 is used to store computer programs executed by the processor 702. The memory 701 may mainly include a program storage area and a data storage area. The program storage area may store the operating system and programs required to run instant messaging functions, etc.; the data storage area may store various instant messaging information and operation instruction sets, etc.

[0203] Memory 701 may be volatile memory, such as random-access memory (RAM); memory 701 may also be non-volatile memory, such as read-only memory, flash memory, hard disk drive (HDD), or solid-state drive (SSD); or memory 701 may be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto. Memory 701 may be a combination of the above-described memories.

[0204] The processor 702 may include one or more central processing units (CPUs) or digital processing units, etc. The processor 702 is used to implement the aforementioned data transfer method when calling a computer program stored in the memory 701.

[0205] Communication interface 703 is used to communicate with terminal devices and other servers.

[0206] This application embodiment does not limit the specific connection medium between the memory 701, the communication interface 703, and the processor 702 described above. This application embodiment... Figure 7 The memory 701 and the processor 702 are connected via a bus 704, and the bus 704 is in Figure 7 The connections between other components are shown in bold lines only and are not intended to be limiting. The 704 bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, Figure 7 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0207] Based on the same inventive concept, embodiments of this application also provide a storage medium storing computer instructions that, when executed on a computer, cause the computer to perform a data transmission method described above.

[0208] It should be noted that although several units or sub-units of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0209] Furthermore, although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0210] This application provides a data transmission method, apparatus, electronic device, and storage medium. Based on programmable logic elements, a host is connected via a first bus, and multiple slave devices with the same device address are connected via multiple second buses. The method responds to a start signal triggered by the first bus by receiving read / write instructions and a target address from the host. The read / write instructions instruct the host to perform data processing operations on the target data to be transmitted. The target address is the same device address associated with the multiple slave devices. The target address is transmitted to the multiple slave devices via the multiple second buses, and the target data is transmitted based on the read / write instructions until a stop signal is triggered by the first bus. Based on this method, data transmission between the host and multiple slave devices with the same device address can be directly achieved using programmable logic elements without configuring access parameters, reducing the design complexity required for bus communication and thus improving data transmission efficiency.

[0211] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0212] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a server, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0213] Program code for performing the operations of this application can be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0214] In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0215] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0216] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0217] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A data transmission method, characterized in that, A programmable logic element is connected to a host via a first bus and to multiple slave devices via multiple second buses, wherein the multiple slave devices are associated with the same first device address. The method includes: The programmable logic element responds to a start signal triggered by the first bus and receives a read / write instruction and a transmission address sent by the host, wherein the read / write instruction is associated with the host's data processing operation for the target data to be transmitted, and the transmission address is the first device address; The address to be transmitted is transmitted to the multiple slave devices via the multiple second buses. Based on the read / write instruction, the target data is transmitted until the first bus triggers a termination signal; Wherein, the programmable logic element is a field-programmable gate array device or a complex programmable logic device, and the first bus and the second bus are integrated circuit buses; The first bus includes at least: a first serial clock line and a first serial data line, wherein the first serial clock line is used to generate clock pulses for the target transmission data, and the first serial data line is used to transmit the target transmission data between the host and the programmable logic element. The second bus includes at least: a second serial clock line and a second serial data line, wherein the second serial clock line is used to synchronously generate the clock pulse, and the second serial data line is used to transmit the target transmission data between the programmable logic element and the plurality of slave devices; Wherein, the programmable logic element carries a state machine, which is used to indicate the transmission status of the target data. Then, the step of receiving the read / write instruction and the address to be transmitted sent by the host in response to the first bus trigger start signal includes: In response to the start signal triggered by the first bus, the state machine is controlled to operate in the bus configuration state; The start signal is transmitted to the multiple slave devices through the multiple second buses respectively, and the working state of the state machine is controlled based on the start response clock and the response results of the multiple slave devices to the start signal. The start response clock is generated through the first serial clock line and is used to indicate the response results of the multiple slave devices to the start signal. In response to the state machine being in the device address transmission state, the device receives read / write instructions and the address to be transmitted from the host.

2. The method as described in claim 1, characterized in that, The step of controlling the operating state of the state machine based on the start response clock and the response results of each of the multiple slave devices in response to the start signal includes: In response to the first serial clock line generating the start response clock, the state machine is controlled to operate in the configuration response state. Based on the configured response status, it is determined whether the response results of each of the plurality of slave devices to the start signal carry the signal response of each of the plurality of slave devices to the start signal; wherein: If so, then control the working state of the state machine to the device address transmission state; Otherwise, the state machine is controlled to be in an idle state.

3. The method as described in claim 1 or 2, characterized in that, The step of transmitting the address to be transmitted to the multiple slave devices via the multiple second buses includes: The address to be transmitted is transmitted to the multiple slave devices through the multiple second buses, so that each of the multiple slave devices is matched with the address to be transmitted, and the address matching result of each of the multiple slave devices is obtained; The operating state of the state machine is controlled based on the address acknowledgment clock and the address matching results of the plurality of slave devices. The address acknowledgment clock is generated through the first serial clock line and is used to indicate the receipt of the address matching results of the plurality of slave devices. Wherein: If there is a mismatch between the multiple slave devices and the address to be transmitted, the state machine is controlled to be in an idle state. If the multiple slave devices do not match the address to be transmitted, then the state machine is controlled to operate in the data transmission state.

4. The method as described in claim 3, characterized in that, The transmission of the target data based on the read / write instruction includes: In response to the state machine's operating state being a data transmission state, the data transmission direction for the target data is determined based on the read / write instruction; wherein: If the data processing operation associated with the read / write indication is write, then the working state of the state machine is controlled to be the data write state, and based on the data write state, the data transmission direction for the target transmission data is determined to be the first direction, wherein the first direction is the transmission direction of the target transmission data from the host to the multiple slave devices; If the data processing operation associated with the read / write indication is read, then the working state of the state machine is controlled to be the bus configuration state, and based on the bus configuration state, the first bus is controlled to trigger a restart signal, and based on the restart signal, the data transmission direction for the target data is determined; The target data is transmitted in accordance with the data transmission direction.

5. The method as described in claim 4, characterized in that, Determining the data transmission direction for the target data transmission based on the restart signal includes: In response to the first serial clock line generating a restart response clock, the operating state of the state machine is controlled to the configured response state, wherein the restart response clock is generated through the first serial clock line and is used to indicate the response results received from the plurality of slave devices in response to the restart signal; Based on the configured response status, it is determined whether the response results of each of the plurality of slave devices in response to the restart signal carry the signal response of each of the plurality of slave devices in response to the restart signal; wherein: If so, the state machine is controlled to operate in a data reading state, and in response to the data reading state, the data transmission direction for the target data is determined to be a second direction, wherein the second direction is the transmission direction in which the target data is output from the plurality of slave devices and input to the host. Otherwise, the working state of the state machine is controlled to be the idle state.

6. The method as described in claim 4 or 5, characterized in that, The data transmission direction is a first direction. After transmitting the target data according to the data transmission direction, the process further includes: The working state of the state machine is controlled based on the write acknowledgment clock, wherein the write acknowledgment clock is generated by the first serial clock line, and when the first serial clock line generates the write acknowledgment clock, it controls the working state of the state machine to the write acknowledgment state. The data transmission direction is a second direction. After transmitting the target data according to the data transmission direction, the process further includes: The state machine's operating state is controlled based on the read response clock, wherein the read response clock is generated by the first serial clock line, and the first serial clock line controls the state machine's operating state to the read response state when generating the read response clock.

7. The method as described in claim 4 or 5, characterized in that, The start signal is triggered when the first serial clock line is at a high level and the first serial data line transitions from a high level to a low level; the stop signal is triggered when the first serial clock line is at a high level and the first serial data line transitions from a low level to a high level; the restart signal is triggered when the first serial clock line is at a high level and the first serial data line transitions from a high level to a low level.

8. A data transmission device, characterized in that, A programmable logic element is connected to a host via a first bus and to multiple slave devices via multiple second buses, wherein the multiple slave devices are associated with the same device address. The device includes: A start response module is used to respond to a start signal triggered by the first bus and receive a read / write instruction and a transmission address sent by the host, wherein the read / write instruction is used to instruct the host to perform data processing operations on the target data to be transmitted, and the transmission address is the address of the first device. The address transmission module is used to transmit the address to be transmitted to the multiple slave devices via the multiple second buses; The data transmission module is used to transmit the target data based on the read / write instruction until the first bus triggers a termination signal. Wherein, the programmable logic element is a field-programmable gate array device or a complex programmable logic device, and the first bus and the second bus are integrated circuit buses; The first bus includes at least: a first serial clock line and a first serial data line, wherein the first serial clock line is used to generate clock pulses for the target transmission data, and the first serial data line is used to transmit the target transmission data between the host and the programmable logic element. The second bus includes at least: a second serial clock line and a second serial data line, wherein the second serial clock line is used to synchronously generate the clock pulse, and the second serial data line is used to transmit the target transmission data between the programmable logic element and the plurality of slave devices; The programmable logic element carries a state machine, which is used to indicate the transmission status of the target data. The process of receiving a read / write instruction and the address to be transmitted from the host in response to a start signal triggered by the first bus includes: In response to the start signal triggered by the first bus, the state machine is controlled to operate in the bus configuration state; The start signal is transmitted to the multiple slave devices through the multiple second buses respectively, and the working state of the state machine is controlled based on the start response clock and the response results of the multiple slave devices to the start signal. The start response clock is generated through the first serial clock line and is used to indicate the response results of the multiple slave devices to the start signal. In response to the state machine being in the device address transmission state, the device receives read / write instructions and the address to be transmitted from the host.

9. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1-7.

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