Display panel and display device

Abstract

The present application provides a display panel and a display device. The display panel includes a gate driving circuit, and the gate driving circuit includes a plurality of cascaded gate driving circuit units. The nth stage gate driving circuit unit includes an input control module, an input pull-up module, and an output pull-up module. The input control module controls whether the current stage gate driving circuit outputs the scanning signal of the current stage, and within one frame display time, the preset multi-stage gate driving circuit units can be continuously scanned multiple times, and only single scans are performed on the other stage gate driving circuit units, so that high-frequency refresh display is achieved in some areas of the display panel, and low-frequency refresh display is achieved in other areas, thereby reducing the power consumption of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Thin film transistor liquid crystal display (TFT-LCD) panels have advantages such as thin thickness, excellent picture quality, and the ability to achieve high-speed, high-brightness, and high-contrast display of information, and have been widely used in electronic display devices.

[0003] With the development of the display industry, users have higher and higher requirements for the refresh rate of display panels. The increase in the refresh rate directly leads to an increase in the power consumption of the display panel. Currently, the refresh rate of the entire display area of the display panel remains the same. When there is a display requirement for a high-frequency refresh rate in a partial display area, only the entire display area can be refreshed at a high frequency, resulting in an increase in the power consumption of the display panel.

[0004] Therefore, it is necessary to provide a display panel and a display device to improve this defect. Summary of the Invention

[0005] Embodiments of the present application provide a display panel and a display device, which can reduce the power consumption of the display panel while meeting the high-frequency refresh display requirements of a partial display area.

[0006] Embodiments of the present application provide a display panel. The display panel includes a gate driving circuit unit with multiple levels in cascade, an input control signal line, a clock signal line, and a first constant voltage signal line. The nth-level gate driving circuit unit in the multiple levels of the gate driving circuit unit includes an input control module, an input pull-up module, and an output pull-up module. The input control module is electrically connected to the input control signal line and the input pull-up module. The input pull-up module is electrically connected to the first constant voltage signal line and is electrically connected to the output pull-up module at a first node. The output pull-up module is electrically connected to the clock signal line and the scan signal output terminal of the current level.

[0007] Wherein, after the (k + a)th-level gate driving circuit outputs the (k + a)th-level scan signal to the corresponding pixel row, the input control module of the kth-level gate driving circuit unit is used to control the output of the input pull-up module in response to the input control signal provided by the input control signal line. The input pull-up module is used to control the conduction of the line between the first constant voltage signal line and the first node in response to the signal output by the input control module. The output pull-up module is used to control the conduction of the line between the clock signal line and the scan signal output terminal of the current level in response to the potential of the first node, and output the scan signal of the current level to the corresponding pixel row and the next-level cascaded gate driving circuit unit.

[0008] Alternatively, after the (k + a)-th level gate driving unit outputs the (k + a)-th level scanning signal to the corresponding pixel row and the next cascaded gate driving circuit unit, the input control module of the k-th level gate driving circuit unit is configured to control the input pull-up module not to output in response to the input control signal; where n, k, and a are all positive integers.

[0009] According to an embodiment of the present application, the display panel further includes a second constant voltage signal line, the input control signal line includes a first input control signal line and a second input control signal line, the input control module includes a first transistor, a second transistor, and a first capacitor. The gate of the first transistor is electrically connected to the (n - m)-th level scanning signal output terminal, the source of the first transistor is electrically connected to the first input control signal line, the drain of the first transistor is electrically connected to the first pole of the first capacitor and the source of the second transistor, the second pole of the first capacitor is electrically connected to the second constant voltage signal line, the gate of the second transistor is electrically connected to the second input control signal line, and the drain of the second transistor is electrically connected to the control terminal of the input pull-up module; where m is a positive integer.

[0010] According to an embodiment of the present application, after the (k - 1)-th level gate driving circuit unit outputs the (k - 1)-th level scanning signal, the input control module of the k-th level gate driving circuit unit is configured to control the input pull-up module not to output in response to the input control signal, and the first transistor is configured to control the line between the first input control signal line and the first pole of the first capacitor to be turned on in response to the (n - m)-th level scanning signal provided by the (n - m)-th level scanning signal output terminal.

[0011] After the first capacitor is charged, the second transistor is configured to control the line between the first pole of the first capacitor and the control terminal of the input pull-up module to be turned on in response to the second input control signal provided by the second input control signal line, and the input pull-up module controls the line between the first constant voltage signal line and the first node to be turned on.

[0012] According to an embodiment of the present application, the input control module further includes a third transistor, the input control signal line includes a third input control signal line, the gate of the third transistor is electrically connected to the third input control signal line, the source of the third transistor is electrically connected to the (n - m)-th level scanning signal output terminal, and the drain of the third transistor is electrically connected to the drain of the second transistor and the control terminal of the input pull-up module.

[0013] According to an embodiment of the present application, the input control signal line includes a fourth input control signal line, and the input control module further includes a fourth transistor. The gate of the fourth transistor is electrically connected to the fourth input control signal line, the source of the fourth transistor is electrically connected to the second constant voltage signal line, and the drain of the fourth transistor is electrically connected to the drain of the second transistor and the control end of the input pull-up module.

[0014] According to an embodiment of the present application, the display panel further includes a reset signal line, and the input control module further includes a fifth transistor. The gate of the fifth transistor is electrically connected to the reset signal line, and the source of the fifth transistor is electrically connected to the drain of the first transistor, the first pole of the first capacitor, and the source of the second transistor.

[0015] According to an embodiment of the present application, the input pull-up module includes a sixth transistor. The gate of the sixth transistor is electrically connected to the drain of the second transistor, the source of the sixth transistor is electrically connected to the first constant voltage signal line, and the drain of the sixth transistor is electrically connected to the first node.

[0016] According to an embodiment of the present application, the output pull-up module includes a seventh transistor, an eighth transistor, and a second capacitor. The gate of the seventh transistor is electrically connected to the first constant voltage signal line, the source of the seventh transistor is electrically connected to the first node, the drain of the seventh transistor is electrically connected to the gate of the eighth transistor, the source of the eighth transistor is electrically connected to the clock signal line, the drain of the eighth transistor is electrically connected to the output end of the current-stage scan signal, the first pole of the second capacitor is electrically connected to the first node, and the second pole of the second capacitor is electrically connected to the second constant voltage signal line.

[0017] According to an embodiment of the present application, the nth-stage gate driving circuit unit further includes a pull-down control module and an output pull-down module. The pull-down control module is electrically connected to the clock signal line, the output end of the (n + m)th-stage scan signal, the first node, and the output pull-down module. The pull-down control module is configured to pull down the potential of the first node in response to the (n + m)th-stage scan signal provided by the output end of the (n + m)th-stage scan signal, where m is a positive integer;

[0018] The output pull-down module is electrically connected to the first node and the output end of the current-stage scan signal, and the output pull-down module is configured to pull down the potential of the output end of the current-stage scan signal.

[0019] An embodiment of the present application further provides a display device, and the display device includes the display panel as described above.

[0020] Advantages of the embodiments of the present application: The embodiments of the present application provide a display panel and a display device. The display panel includes a gate driving circuit, which includes a plurality of cascaded gate driving circuit units. The nth-stage gate driving circuit unit includes an input control module, an input pull-up module, and an output pull-up module. The input control module is electrically connected to an input control signal line and the input pull-up module. The input pull-up module is electrically connected to a first constant voltage signal line and is electrically connected to the output pull-up module at a first node. The output pull-up module is electrically connected to a clock signal line and an output terminal of the current-stage scan signal. By controlling the input control module, it can be determined whether the current-stage gate driving circuit outputs the current-stage scan signal. And within one frame display time, the preset multi-stage gate driving circuit units can be scanned multiple times, while other-stage gate driving circuit units are only scanned once. In this way, the effect of high-frequency refresh display in some areas of the display panel and low-frequency refresh display in other areas is achieved, thereby reducing the power consumption of the display panel. Brief Description of the Drawings

[0021] Figure 1 It is a schematic structural diagram of the display panel provided by the embodiments of the present application;

[0022] Figure 2 It is an architecture diagram of the gate driving circuit provided by the embodiments of the present application;

[0023] Figure 3 It is a circuit architecture diagram of the gate driving circuit unit provided by the embodiments of the present application;

[0024] Figure 4 It is a circuit diagram of the gate driving circuit unit provided by the embodiments of the present application;

[0025] Figure 5 It is a timing diagram of the first working mode provided by the embodiments of the present application;

[0026] Figure 6 It is a timing diagram of the second working mode provided by the embodiments of the present application. Detailed Description of the Embodiments

[0027] The descriptions of the following embodiments refer to the attached drawings, which are used to illustrate specific embodiments in which the present application can be implemented. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only references to the directions in the attached drawings. Therefore, the directional terms used are for explaining and understanding the present application, rather than for limiting the present application. In the drawings, units with similar structures are denoted by the same reference numerals.

[0028] The present application will be further described below with reference to the accompanying drawings and specific embodiments.

[0029] Embodiments of the present application provide a display panel-level display device, which can reduce the power consumption of the display panel while meeting the high-frequency refresh display requirements of part of the display area.

[0030] As Figure 1 shown, Figure 1 FIG. is a schematic structural diagram of a display panel provided by an embodiment of the present application. The display panel 100 includes a display area AA and a non-display area NA disposed outside the display area AA. The display panel 100 further includes a gate driving circuit 1, and the gate driving circuit 1 is disposed in the non-display area NA on at least one side of the display area AA.

[0031] As Figure 2 shown, Figure 2 FIG. is an architecture diagram of a gate driving circuit provided by an embodiment of the present application. The gate driving circuit 1 includes a plurality of cascaded gate driving circuit units, and the gate driving circuit units are used to control whether the corresponding pixel rows emit light in response to a control signal.

[0032] Combined with Figure 3 and Figure 4 shown, Figure 3 FIG. is a circuit architecture diagram of a gate driving circuit unit provided by an embodiment of the present application. Figure 4 FIG. is a circuit diagram of a gate driving circuit unit provided by an embodiment of the present application. The display panel further includes a plurality of input control signal lines, a plurality of clock signal lines, and a first constant voltage signal line (not shown in the figure). The gate driving circuit unit includes an input control module 11, an input pull-up module 12, and an output pull-up module 13. The input control module 11 is electrically connected to the input control signal line and the input pull-up module 12. The input pull-up module 12 is electrically connected to the first constant voltage signal line VG1 and is electrically connected to the output pull-up module 13 at a first node Q. The output pull-up module 13 is electrically connected to the clock signal line and the output terminal of the current-stage scan signal. Among them, the input control module 11 is used to control the input pull-up module 12 to output or not output in response to the input control signal provided by the input control signal line. The input pull-up module 12 is used to control the conduction and cutoff of the line between the first constant voltage signal line VG1 and the first node Q in response to the signal output by the input control module 11. The output pull-up module 13 is used to control the conduction and cutoff of the line between the clock signal line and the output terminal of the current-stage scan signal in response to the potential of the first node Q.

[0033] Taking the n-th level gate drive circuit unit as an example, the input control module 11 of the n-th level gate drive circuit unit is electrically connected to the input control signal line and the input pull-up module 12 respectively, the input pull-up module 12 is electrically connected to the first constant voltage signal line VG1, and is electrically connected to the output pull-up module 13 at the first node Q, the output pull-up module 13 is electrically connected to the clock signal line CK(n) and the n-th level scan signal output terminal G(n), the n-th level clock signal line CK(n) is used to provide a first clock signal, and n is a positive integer.

[0034] In an embodiment of the present application, the display panel has two operating modes. In the first operating mode, within one frame display time, the signal is continuously transmitted from the first-level gate driving circuit unit to the last-level gate driving circuit unit without interruption, and each level of the gate driving circuit unit is scanned only once.

[0035] In the second working mode, one frame display time may include three refresh stages: in the first stage, the signal is transmitted from the first-stage gate driving circuit unit to the k-1-th-stage gate driving circuit unit in succession; in the second stage, the signal is transmitted from the k-th-stage gate driving circuit unit to the k+a-th-stage gate driving circuit unit in succession, and then to the k+a-th-stage gate driving circuit unit, and the k+a-th-stage scanning signal Gate(k+a) is output to the corresponding pixel row; the input control module 11 of the k-th-stage gate driving circuit unit is used to control the output of the input pull-up module 12 in response to the input control signal provided by the input control signal line; the input pull-up module 12 is used to control the line conduction between the first constant voltage signal line VG1 and the first node Q in response to the signal output by the input control module 11, and pull up the potential of the first node Q to a high potential; the output pull-up module 13 is used to control the line conduction between the clock signal line CK(n) and the output end of the scanning signal of this stage in response to the potential of the first node Q, and output the signal to the corresponding pixel row; The pixel row and the next cascaded gate driving circuit unit output the current level scanning signal (i.e., the kth level scanning signal (Gate(k))) and thus restart from the kth level to the k+ath level. The above process can be repeated multiple times in the second stage, that is, the kth level gate driving circuit to the k+ath level gate driving circuit are continuously scanned multiple times until the end of the second stage, that is, the last refresh of the kth level driving circuit unit to the k+ath level gate driving circuit unit is completed; in the third stage, after the current level scanning signal is transmitted to the k+ath level gate driving unit and outputs the current level scanning signal to the corresponding pixel row and the next cascaded gate driving circuit unit (i.e., the k+a+1th level gate driving circuit unit), the input control module of the kth level gate driving circuit unit is used to respond to the input control signal to control the input pull-up module not to output, and start to transmit from the k+a+1th level gate driving circuit unit to the last level gate driving circuit unit, wherein k and a are both positive integers.

[0036] In the second working mode, the input control module 11 controls whether the local gate driving circuit outputs the local scanning signal. And within one frame display time, the preset multi-stage gate driving circuit units can be scanned multiple times, while only a single scan is performed on the other-stage gate driving circuits, so that high-frequency refresh display is achieved in some areas of the display panel, and low-frequency refresh display is achieved in other areas, thereby reducing the power consumption of the display panel.

[0037] Further, as Figure 4 shown, the display panel further includes a second constant voltage signal line VG2. The input control signal lines include a first input control signal line TN1 and a second input control signal line TN2. The input control module 11 includes a first transistor T1, a second transistor T2, and a first capacitor C1. The gate of the first transistor T1 is electrically connected to the (n - m)-th stage scan signal output terminal G(n - m), where m is a positive integer. The source of the first transistor T1 is electrically connected to the first input control signal line TN1. The drain of the first transistor T1 is electrically connected to the first pole of the first capacitor C1 and the source of the second transistor T2. The second pole of the first capacitor C1 is electrically connected to the second constant voltage signal line VG2. The gate of the second transistor T2 is electrically connected to the second input control signal line TN2. The drain of the second transistor T2 is electrically connected to the control terminal of the input pull-up module 12.

[0038] In one embodiment, m = 2, that is, the gate of the first transistor T1 is electrically connected to the (n - 2)-th stage scan signal output terminal G(n - 2).

[0039] After the signal is transmitted to the (k - 1)-th stage gate driving circuit unit and the (k - 1)-th stage scan signal is output to the corresponding pixel row, the input control module 11 of the k-th stage gate driving circuit unit is used to control the input pull-up module 12 to cut off in response to the input control signal. The first transistor T1 is used to control the conduction of the line between the first input control signal line TN1 and the first pole of the first capacitor C1 in response to the (n - m)-th stage scan signal Gate(n - m) provided by the (n - m)-th stage scan signal output terminal G(n - m), so as to charge the first capacitor C1.

[0040] After the first capacitor C1 is charged, the second transistor T2 is used to control the conduction of the line between the first pole of the first capacitor C1 and the control terminal of the input pull-up module 12 in response to the second input control signal provided by the second input control signal line TN2. The input pull-up module 12 controls the conduction of the line between the first constant voltage signal line VG1 and the first node Q, so as to pull up the potential of the first node Q from a low potential to a high potential.

[0041] Further, as Figure 4As shown, the input control signal line further includes a third input control signal line TN3, and the input control module 11 further includes a third transistor T3. The gate of the third transistor T3 is electrically connected to the third input control signal line TN3. The source of the third transistor T3 is electrically connected to the (n - m)-th stage scan signal output terminal G(n - m). The drain of the third transistor T3 is electrically connected to the drain of the second transistor T2 and the control terminal of the input pull-up module 12.

[0042] The input control module 11 further includes a fourth transistor T4. The gate of the fourth transistor T4 is electrically connected to the fourth input control signal line TN4. The source of the fourth transistor T4 is electrically connected to the second constant voltage signal line VG2. The drain of the fourth transistor T4 is electrically connected to the drain of the second transistor T2 and the control terminal of the input pull-up module 12.

[0043] Further, as Figure 4 shown, the input control module 11 further includes a fifth transistor T5. The gate of the fifth transistor T5 is electrically connected to the reset signal line Reset. The source of the fifth transistor T5 is electrically connected to the drain of the first transistor T1, the first pole of the first capacitor C1, and the source of the second transistor T2.

[0044] Further, as Figure 4 shown, the input pull-up module 12 includes a sixth transistor T6. The gate of the sixth transistor T6 is electrically connected to the drain of the second transistor T2, the drain of the third transistor T3, and the drain of the fourth transistor T4. The source of the sixth transistor T6 is electrically connected to the first constant voltage signal line VG1. The drain of the sixth transistor T6 is electrically connected to the first node Q.

[0045] In one embodiment, as Figure 4 shown, the output pull-up module 13 includes a seventh transistor T7, an eighth transistor T8, and a second capacitor C2. The gate of the seventh transistor T7 is electrically connected to the first constant voltage signal line VG1. The source of the seventh transistor T7 is electrically connected to the first node Q. The drain of the seventh transistor T7 is electrically connected to the gate of the eighth transistor T8. The source of the eighth transistor T8 is electrically connected to the clock signal line CK(n). The drain of the eighth transistor T8 is electrically connected to the n-th stage scan signal output terminal G(n). The first pole of the second capacitor C2 is electrically connected to the first node Q. The second pole of the second capacitor C2 is electrically connected to the second constant voltage signal line VG2.

[0046] Further, as Figure 4As shown, the n-th level gate driving circuit unit also includes a pull-down control module 14 and an output pull-down module 15. The pull-down control module 14 is electrically connected to the clock signal line CK(n+m), the clock signal line CK(nm), the n+m-th level scan signal output terminal G(n+m), the first node Q and the output pull-down module 15, wherein m=2, the clock signal line CK(n+m) corresponding to the n+m-th level gate driving circuit unit is used to provide a second clock signal, and the clock signal line CK(nm) corresponding to the nm-th level gate driving circuit unit is used to provide a third clock signal. The pull-down control module 14 is used to pull down the potential of the first node Q in response to the n+m-th level scan signal provided by the n+m-th level scan signal output terminal G(n+m). The output pull-down module 15 is electrically connected to the first node Q and the current level scan signal output terminal G(n), and the output pull-down module 15 is used to pull down the potential of the current level scan signal output terminal G(n).

[0047] In one embodiment, if Figure 4 As shown, the pull-down control module 14 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a twelfth transistor T12, the gate of the ninth transistor T9 is electrically connected to the first constant voltage signal line VG1, the source of the ninth transistor T9 is electrically connected to the clock signal line CK(n+m), the drain of the ninth transistor T9 and the drain of the tenth transistor T10 are electrically connected to the gate of the eleventh transistor T11, the gate of the tenth transistor T10 is electrically connected to the second constant voltage signal line VG2, the source of the tenth transistor T10 is electrically connected to the clock signal line CK(nm), the source of the eleventh transistor is electrically connected to the first constant voltage signal line VG1, the drain of the eleventh transistor T11 is electrically connected to the output pull-down module 15, the gate of the twelfth transistor T12 is electrically connected to the n+mth level scan signal output terminal, the source of the twelfth transistor T12 is electrically connected to the second constant voltage signal line VG2, and the drain of the twelfth transistor T12 is electrically connected to the first node Q and the output pull-down module 15.

[0048] In one embodiment, the output pull-down module 15 includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15 and a third capacitor C3, the gate of the thirteenth transistor T13 is electrically connected to the drain of the twelfth transistor T12 and the first node Q, the source of the thirteenth transistor T13 is electrically connected to the drain of the eleventh transistor T11, the gate of the fourteenth transistor T14, the gate of the fifteenth transistor T15 and the first electrode of the third capacitor C3, the source of the fourteenth transistor T14 is electrically connected to the first node Q, the drain of the fourteenth transistor T14, the drain of the thirteenth transistor T13, the drain of the fifteenth transistor T15 and the second electrode of the third capacitor C3 are electrically connected to the second constant voltage signal line VG2, and the drain of the fifteenth transistor T15 is electrically connected to the current level scan signal output terminal G(n).

[0049] In one embodiment, each transistor in the gate driving circuit unit is an N-type transistor. The voltage of the first constant voltage signal line VG1 is a constant first voltage, and the voltage of the second constant voltage signal line VG2 is a constant second voltage. Both the first voltage and the second voltage are operating voltages, and the first voltage is higher than the second voltage.

[0050] Combined with Figure 5 as shown in Figure 5 FIG. is a timing diagram of the first working mode provided by the embodiment of the present application. The working principle of the gate driving circuit in the first working mode is as follows:

[0051] Taking the first-stage gate driving circuit unit as an example, one frame display time includes a pre-charge sub-stage, an output sub-stage, and a pull-down sub-stage. During one frame display time, the potentials of the first input control signal line TN1, the second input control signal line TN2, and the fourth control signal line TN4 are all low potentials, and the potential of the third input control signal line TN3 is a high potential. The first transistor T1, the second transistor T2, and the fourth transistor T4 always remain off, and the third transistor T3 remains on all the time. In the pre-charge sub-stage, the start signal STV jumps to a high potential, and the sixth transistor T6 turns on. The circuit between the first power signal line VG1 and the first node Q conducts, pulling up the potential of the first node Q from a low potential to a high potential and charging the first capacitor C1. The seventh transistor T7 remains on all the time, and the eighth transistor T8 turns on. At this time, the potential of the first clock signal provided by the clock signal line CK(1) is a low potential, and the first-stage scan signal terminal does not output. In the output sub-stage, the start signal STV jumps to a low potential, the sixth transistor T6 turns off, the first capacitor C1 discharges to maintain the potential of the first node Q, and the eighth transistor T8 remains on. The potential of the first clock signal provided by the clock signal line CK(1) jumps to a high potential and pulls up the potential of the first-stage scan signal output terminal G(1). The first-stage scan signal output terminal G outputs a high-potential first-stage scan signal Gate(1) to the corresponding pixel row of this stage and the cascaded gate driving circuit unit of the next stage. In the pull-down sub-stage, the potential of the second clock signal provided by the clock signal line CK(3) jumps to a high potential, and the eleventh transistor T11, the fourteenth transistor T14, and the fifteenth transistor T15 all turn on. The potentials of the first node Q and the first-stage scan signal output terminal are pulled down to low potentials, and this continues to be transmitted to the last-stage gate driving circuit unit in sequence. This working mode can replace the working mode of the existing gate driving circuit, that is, after starting the scan, it is continuously transmitted from the first-stage gate driving circuit unit to the last-stage gate driving circuit unit without interruption in the middle.

[0052] Combined with Figure 6 as shown in Figure 6The timing diagram of the second working mode provided by the embodiments of the present application. The working principle of the gate driving circuit in the second working mode is as follows:

[0053] In the first stage t1, the potentials of the first input control signal line TN1, the second input control signal line TN2, and the fourth input control signal line TN4 are all low, and the potential of the third input control signal line TN3 is high. The third transistor T3 is turned on, and the start signal STV is high and output to the sixth transistor T6 through the third transistor T3. The sixth transistor T6 is turned on, and the high potential of the first constant voltage signal line VG1 is output to the first node Q, pulling up the potential of the first node Q and charging the second capacitor C2. The first constant voltage signal line VG1 is high and turns on the seventh transistor T7. The potential of the first node Q is output to the gate of the eighth transistor T8 and turns on the eighth transistor T8. Subsequently, the start signal STV jumps from high to low. The sixth transistor T6 is turned off. The first capacitor C1 discharges and maintains the potential of the first node Q at a high level. The potential of the first clock signal provided by the clock signal line CK(1) jumps from low to high. The potential of the first clock signal provided by the clock signal line CK(1) is output to the first-stage scan signal output terminal G(1), pulling up the potential of the first-stage scan signal output terminal G(1) and outputting the first-stage scan signal Gate(1). This is continuously transmitted to the (k - 1)-th stage gate driving circuit unit, and the (k - 1)-th stage gate scan signal Gate(k - 1) is normally output in the above manner. At this time, the potential of the third input control signal line TN3 jumps to low, the third transistor T3 in the k-th stage gate driving circuit unit is turned off, the potentials of the first input control signal TN1 and the fourth control signal terminal TN4 jump to high, the first transistor T1 and the fourth transistor T4 are turned on, the first capacitor C1 starts to be charged, the sixth transistor T6 is turned off, the potential of the first node Q is pulled down to low, the eighth transistor T8 is turned off, and the k-th stage scan signal output terminal G(k) outputs the k-th stage scan signal Gate(k) with a low level.

[0054] In the second stage t2, the second input control signal TN2 jumps to a high potential, the second transistor T2 turns on, the first capacitor C1 discharges, the sixth transistor T6 turns on, the high potential of the first constant voltage signal line VG1 is output to the first node Q, raising the potential of the first node Q and charging the second capacitor C2. The first constant voltage signal line VG1 is at a high potential and turns on the seventh transistor T7. The potential of the first node Q is output to the gate of the eighth transistor T8, and the eighth transistor T8 is turned on. The potential of the first clock signal provided by the clock signal line CK(k) is output to the k-th stage scan signal output terminal G(k), pulling up the potential of the k-th stage scan signal output terminal G(k) and outputting the k-th stage scan signal Gate(k) at a high level. At this time, the potentials of the first input control signal line TN1, the second input control signal line, and the fourth input control signal line TN4 all jump to a low potential, the potential of the third input control signal line TN3 jumps to a high potential, and the gate driving circuit continuously cascades from the k-th stage gate driving circuit unit to the (k + a)-th stage gate driving circuit unit. After the (k + a)-th stage gate driving circuit unit outputs the (k + a)-th stage scan signal Gate(k + a) at a high level of this stage, the third input control signal TN3 jumps to a low potential, the second input control signal TN2 jumps to a high potential, the first capacitor C1 of the k-th stage gate driving circuit unit discharges, and the gate driving circuit continuously refreshes from the k-th stage gate driving circuit unit to the (k + a)-th stage gate driving circuit unit again. The area corresponding to the pixel rows of the k-th stage gate driving circuit unit to the (k + a)-th stage gate driving circuit unit is set as the visual fixation area, and other areas are non-fixation areas. The refresh times of the k-th stage gate driving circuit unit to the (k + a)-th stage gate driving circuit unit within one frame time in the visual fixation area can be adjusted according to the timing, and the refresh times can be 2 times or 3 times or more.

[0055] In the third stage t3, when the last refresh of the k-th stage gate driving circuit unit to the (k + a)-th stage gate driving circuit unit in the second stage ends, the potentials of the second input control signal TN2 and the third input control signal TN3 remain unchanged, and the (k + a)-th stage gate driving circuit unit continues to cascade to the (k + a + 1)-th stage gate driving circuit unit until it cascades to the last stage gate driving circuit unit, and one frame refresh ends.

[0056] In the second working mode, arbitrary row start and stop of the gate driving circuit can be achieved. And within one frame time, the pixels in the visual fixation area are refreshed multiple times, while the pixels in the non-fixation area are refreshed once, so as to achieve high-frequency display only in the visual fixation area and low-frequency display in the non-fixation area, thereby effectively reducing the power consumption of the display panel without affecting the visual experience.

[0057] According to the display panel provided by the above embodiments of the present application, the embodiments of the present application further provide a display device, which includes a display panel and a middle frame. The display panel is installed on the middle frame, and the display panel can be replaced with the display panel provided by any of the above embodiments to achieve the same technical effects.

[0058] Advantages of the embodiments of the present application: The embodiments of the present application provide a display panel and a display device. The display panel includes a gate driving circuit, and the gate driving circuit includes a plurality of cascaded gate driving circuit units. The nth-level gate driving circuit unit includes an input control module, an input pull-up module, and an output pull-up module. The input control module is electrically connected to an input control signal line and the input pull-up module. The input pull-up module is electrically connected to a first constant voltage signal line and is electrically connected to the output pull-up module at a first node. The output pull-up module is electrically connected to a clock signal line and the scanning signal output terminal of this level. By controlling, through the input control module, whether the gate driving circuit of this level outputs the scanning signal of this level, and within one frame display time, continuous multiple scans can be performed on a preset multi-level gate driving circuit unit, and only single scans are performed on the gate driving circuit units of other levels. In this way, the effect of high-frequency refresh display is achieved in some areas of the display panel, and low-frequency refresh display is achieved in other areas, thereby reducing the power consumption of the display panel.

[0059] In summary, although the present application is disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is based on the scope defined by the claims.

Claims

1. A display panel, characterized in that: The display panel comprises a plurality of cascaded gate drive circuit units, an input control signal line, a clock signal line and a first constant voltage signal line, wherein the nth gate drive circuit unit in the plurality of gate drive circuit units comprises an input control module, an input pull-up module and an output pull-up module, wherein the input control module is electrically connected to the input control signal line and the input pull-up module, the input pull-up module is electrically connected to the first constant voltage signal line and is electrically connected to the output pull-up module at a first node, and the output pull-up module is electrically connected to the clock signal line and a scanning signal output terminal of the current stage; Wherein, after the k+a-th gate driving circuit unit outputs the k+a-th scanning signal to the corresponding pixel row, the input control module of the k-th gate driving circuit unit is used to control the output of the input pull-up module in response to the input control signal provided by the input control signal line, the input pull-up module is used to control the line conduction between the first constant voltage signal line and the first node in response to the signal output by the input control module, the output pull-up module is used to control the line conduction between the clock signal line and the output end of the current-stage scanning signal in response to the potential of the first node, and output the current-stage scanning signal to the corresponding pixel row and the gate driving circuit unit of the next cascade; Alternatively, after the k+a-th level gate driving unit outputs the k+a-th level scanning signal to the corresponding pixel row and the next-level cascaded gate driving circuit unit, the input control module of the k-th level gate driving circuit unit is used to control the input pull-up module not to output in response to the input control signal; wherein n, k, and a are all positive integers; Wherein, the display panel also includes a second constant voltage signal line, the input control module includes a first transistor, a second transistor and a first capacitor, the gate of the first transistor is electrically connected to the nm-th level scanning signal output terminal, the source of the first transistor is electrically connected to the first input control signal line, the drain of the first transistor is electrically connected to the first electrode of the first capacitor and the source of the second transistor, the second electrode of the first capacitor is electrically connected to the second constant voltage signal line, the gate of the second transistor is electrically connected to the second input control signal line, and the drain of the second transistor is electrically connected to the control end of the input pull-up module; wherein m is a positive integer.

2. The display panel according to claim 1, wherein: After the k-1th level gate driving circuit unit outputs the k-1th level scanning signal, the input control module of the kth level gate driving circuit unit is used to respond to the input control signal to control the input pull-up module not to output, and the first transistor is used to respond to the nmth level scanning signal provided by the nmth level scanning signal output terminal to control the line between the first input control signal line and the first electrode of the first capacitor to be turned on; After the first capacitor is charged, the second transistor is used to control the conduction of the line between the first electrode of the first capacitor and the control end of the input pull-up module in response to the second input control signal provided by the second input control signal line, and the input pull-up module controls the conduction of the line between the first constant voltage signal line and the first node.

3. The display panel according to claim 1, wherein: The input control signal line includes a third input control signal line, and the input control module also includes a third transistor, the gate of the third transistor is electrically connected to the third input control signal line, the source of the third transistor is electrically connected to the nm-level scanning signal output end, and the drain of the third transistor is electrically connected to the drain of the second transistor and the control end of the input pull-up module.

4. The display panel according to claim 1, wherein: The input control signal line includes a fourth input control signal line, and the input control module also includes a fourth transistor, the gate of the fourth transistor is electrically connected to the fourth input control signal line, the source of the fourth transistor is electrically connected to the second constant voltage signal line, and the drain of the fourth transistor is electrically connected to the drain of the second transistor and the control end of the input pull-up module.

5. The display panel according to claim 1, wherein: The display panel also includes a reset signal line, and the input control module also includes a fifth transistor, the gate of the fifth transistor is electrically connected to the reset signal line, and the source of the fifth transistor is electrically connected to the drain of the first transistor, the first electrode of the first capacitor, and the source of the second transistor.

6. The display panel according to any one of claims 1 to 5, characterized in that: The input pull-up module includes a sixth transistor, a gate of the sixth transistor is electrically connected to a drain of the second transistor, a source of the sixth transistor is electrically connected to the first constant voltage signal line, and a drain of the sixth transistor is electrically connected to the first node.

7. The display panel according to claim 6, wherein: The output pull-up module includes a seventh transistor, an eighth transistor and a second capacitor, the gate of the seventh transistor is electrically connected to the first constant voltage signal line, the source of the seventh transistor is electrically connected to the first node, the drain of the seventh transistor is electrically connected to the gate of the eighth transistor, the source of the eighth transistor is electrically connected to the clock signal line, the drain of the eighth transistor is electrically connected to the current level scan signal output terminal, the first electrode of the second capacitor is electrically connected to the first node, and the second electrode of the second capacitor is electrically connected to the second constant voltage signal line.

8. The display panel according to claim 1, wherein: The n-th level gate driving circuit unit further comprises a pull-down control module and an output pull-down module, wherein the pull-down control module is electrically connected to the clock signal line, the n+m-th level scanning signal output terminal, the first node and the output pull-down module, and the pull-down control module is used to pull down the potential of the first node in response to the n+m-th level scanning signal provided by the n+m-th level scanning signal output terminal, where m is a positive integer; The output pull-down module is electrically connected to the first node and the current-stage scan signal output terminal, and the output pull-down module is used to pull down the potential of the current-stage scan signal output terminal.

9. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 8.

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