Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of making the same are disclosed. The semiconductor device includes a source, a drain, a gate, a channel structure, a gate dielectric layer, a barrier layer, and a top dielectric layer. The drain, the gate, and the source are stacked. The channel structure is disposed between and connects the drain and the source. The gate dielectric layer is disposed between the channel structure and the gate. The barrier layer is disposed between the gate and the gate dielectric layer. The top dielectric layer is disposed between the drain and the source and includes a protrusion projecting toward the channel structure and sandwiched between the gate and the drain. The protrusion covers at least a portion of an upper surface of the barrier layer. In this way, the barrier layer is self-aligned to insulate the gate dielectric layer from directly contacting a metal material to produce a high resistance, improving the operational performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Semiconductor integrated circuit technology continues to advance and grow over time, with each new generation of manufacturing processes featuring smaller and more complex circuit designs than the previous generation. The number and density of functional components on each chip area must continue to increase due to product innovation, which naturally requires the geometric dimensions of each component to become smaller and smaller. Because traditional planar metal-oxide-semiconductor (MOS) transistor manufacturing processes are difficult to continue to scale, the industry has proposed replacing traditional planar transistor components with three-dimensional or non-planar transistor components, thereby reducing the geometric dimensions of transistor components and / or improving the operating performance of transistor devices. Summary of the Invention

[0003] In view of the above problems, an embodiment of the present invention provides a semiconductor device and a manufacturing method thereof, wherein a barrier layer is set between the gate dielectric layer and the gate to prevent the gate dielectric layer from directly contacting the metal material and generating a high-resistance product, thereby improving the operating performance of the semiconductor device.

[0004] In order to achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0005] According to a first aspect of an embodiment of the present invention, a semiconductor device is provided, comprising a source, a drain, a gate, a channel structure, a gate dielectric layer, a barrier layer, and a top dielectric layer. The drain and the source are stacked. The gate is disposed between the drain and the source. The channel structure is disposed between the drain and the source and connects the drain and the source. The gate dielectric layer is disposed between the channel structure and the gate. The barrier layer is disposed between the gate and the gate dielectric layer. The top dielectric layer is disposed between the drain and the source, wherein the top dielectric layer includes a protrusion protruding toward the channel structure and sandwiched between the gate and the drain. The protrusion covers at least a portion of the upper surface of the barrier layer.

[0006] In order to achieve the above-mentioned purpose, the second aspect of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: forming a source and a drain stacked in sequence; forming a gate between the source and the drain; forming a channel structure between the drain and the source, and connecting the drain and the source; forming a gate dielectric layer between the channel structure and the gate. Forming a top dielectric layer between the drain and the source. The gate is arranged in the top dielectric layer, wherein a portion of the top dielectric layer protrudes toward the channel structure and is sandwiched between the gate and the drain. The portion of the top dielectric layer has a protrusion, and the gate is arranged below the protrusion.

[0007] The semiconductor device and its manufacturing method of the present invention form a protrusion protruding toward the channel structure on the top dielectric layer located between the drain and the gate, so that the setting position of the barrier layer can be self-aligned with the protrusion of the top dielectric layer, effectively isolating the gate dielectric layers located on both sides of the barrier layer from direct contact with the metal material, preventing the dielectric material of the gate dielectric layer from reacting with the metal material of the gate to produce a high-resistance product, thereby improving the component performance of the gate and the channel structure, and thus enhancing the operating performance of the semiconductor device.

[0008] In addition to the technical problems solved by the embodiments of the present invention described above, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions, other technical problems that can be solved by the semiconductor device and the manufacturing method thereof provided by the embodiments of the present invention, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings provide a deeper understanding of the embodiments of the present invention and are incorporated into and become a part of this specification. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all figures are schematic and relative sizes and proportions have been adjusted for illustrative and drawing convenience. The same symbols in different embodiments represent corresponding or similar features.

[0010] Figure 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention;

[0011] Figures 2 to 8 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0012] Figure 2 is a schematic cross-sectional view of a semiconductor device after gate formation;

[0013] Figure 3is a schematic cross-sectional view of a semiconductor device after a barrier material layer is formed;

[0014] Figure 4 is a schematic cross-sectional view of a semiconductor device after a barrier layer is formed;

[0015] Figure 5 is a schematic cross-sectional view of a semiconductor device after a dielectric material layer is formed;

[0016] Figure 6 is a schematic cross-sectional view of a semiconductor device after a semiconductor material layer is formed;

[0017] Figure 7 is a schematic cross-sectional view of a semiconductor device after a channel structure is formed;

[0018] Figure 8 is a schematic cross-sectional view of a semiconductor device after a drain electrode is formed;

[0019] Figure 9 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention;

[0020] Figure 10 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

[0021] Description of reference numerals:

[0022] 10, 48: dielectric layer;

[0023] 12, 22, 42: metal barrier layer;

[0024] 14, 24, 44: electrode layer;

[0025] 16: Metal barrier layer;

[0026] 18: bottom semiconductor layer;

[0027] 20: bottom dielectric layer;

[0028] 26: top dielectric layer;

[0029] 26a: protrusion;

[0030] 28, 50, 52: barrier layer;

[0031] 30, 54: first dielectric layer;

[0032] 32, 56: second dielectric layer;

[0033] 34: first semiconductor layer;

[0034] 36: insulation layer;

[0035] 38: second semiconductor layer;

[0036] 40: channel layer;

[0037] 52a, 54a: bottom surface;

[0038] 101, 102, 104: semiconductor devices;

[0039] 120: bottom dielectric material layer;

[0040] 126: top dielectric material layer;

[0041] 126a: curved sidewalls;

[0042] 126a: arc side wall;

[0043] 128, 228: barrier material layer;

[0044] 130: a first dielectric material layer;

[0045] 132: a second dielectric material layer;

[0046] 134: first semiconductor material layer;

[0047] 150: sacrificial layer;

[0048] D1: vertical direction;

[0049] D2: horizontal direction;

[0050] D3: opposite direction;

[0051] DE: drain;

[0052] GE: Gate;

[0053] GE: gate;

[0054] GD: gate dielectric layer;

[0055] GD: gate dielectric layer;

[0056] ΔH1, ΔH2: height difference;

[0057] OP1: Perforation;

[0058] OP2: Opening;

[0059] SE: source;

[0060] SS: Channel structure. DETAILED DESCRIPTION

[0061] To help those skilled in the art further understand the present invention, several preferred embodiments of the present invention are listed below, along with accompanying diagrams, to provide a detailed description of the technical solutions and intended effects of the present invention. Those skilled in the art can, without departing from the spirit of the present invention, refer to the following embodiments and replace, reorganize, or combine the features of the various embodiments to create other embodiments.

[0062] Please refer to Figure 1 As shown, Figure 1 FIG is a cross-sectional view of a semiconductor device 100 according to a first embodiment of the present invention. Figure 1 As shown, semiconductor device 100 includes a source electrode SE, a drain electrode DE, a gate electrode GE, a channel structure SS, a gate dielectric layer GD, a barrier layer 28, and a top dielectric layer 26. The drain electrode DE and the source electrode SE are stacked in a vertical direction D1, with the gate electrode GE located above and between the source electrode SE. The channel structure SS is partially disposed within the gate electrode GE and also disposed between the drain electrode DE and the source electrode SE in the vertical direction D1, electrically connecting the drain electrode DE and the source electrode SE. The top dielectric layer 26 is disposed between the drain electrode DE and the source electrode SE in the vertical direction D1, with the gate electrode GE disposed within the top dielectric layer 26. The gate dielectric layer GD and the barrier layer 28 are also arranged in the top dielectric layer 26 and are located between the channel structure SS and the gate GE in the horizontal direction D2 or the opposite direction D3. The barrier layer 28 is arranged between the gate GE and the gate dielectric layer GD to isolate the gate dielectric layer GD from directly contacting the metal material and generating a high-resistance product.

[0063] It should be noted that the top dielectric layer 26 includes a protrusion 26a that protrudes toward the channel structure SS and is sandwiched between the drain electrode DE and the gate electrode GE. The protrusion 26a covers at least a portion of the upper surface of the barrier layer 28, further isolating the gate dielectric layer GD from direct contact with the metal material. Thus, the provision of the top dielectric layer 26 allows the barrier layer 28 to be self-aligned with the protrusion 26a of the top dielectric layer 26, ensuring that the barrier layer 28 effectively isolates the gate dielectric layer GD from the contacting metal material, preventing the dielectric material of the gate dielectric layer GD from reacting with the metal material of the gate electrode GE to produce a high-resistance product. This improves the device performance of the gate electrode GE and the channel structure SS, thereby enhancing the operating performance of the semiconductor device 100. In one embodiment, the barrier layer 28 comprises, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or other suitable metal barrier materials, preferably titanium nitride, but not limited thereto.

[0064] In detail, Figure 1As shown, the protrusion 26a partially covers the upper surface of the barrier layer 28. Furthermore, because there is a recess at the junction of the protrusion 26a and the gate GE, the barrier layer 28 also partially fills the recess, while the gate dielectric layer GD covers and contacts the remaining portion of the upper surface of the barrier layer 28. The gate dielectric layer GD further includes a first dielectric layer 30 disposed between the barrier layer 28 and the channel structure SS in the horizontal direction D2, and a second dielectric layer 32 disposed on the first dielectric layer 30 in the vertical direction D1 and between the first dielectric layer 30 and the channel structure SS in the horizontal direction D2. The first dielectric layer 30 fills the remaining space in the recess, while the second dielectric layer 32 uniformly covers the sidewalls of the first dielectric layer 30. In one embodiment, both the first dielectric layer 30 and the second dielectric layer 32 comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, or a high-k dielectric material. For example, the first dielectric layer 30 and the second dielectric layer 32 comprise silicon nitride and silicon oxide, respectively, but are not limited thereto. In a preferred embodiment, the top surface of the gate dielectric layer GD is higher than the top surfaces of the gate GE and the barrier layer 28, such that the gate dielectric layer GD completely covers the curved sidewalls of the protrusion 26a. Furthermore, the top surface of the barrier layer 28 is preferably higher than the top surface of the gate GE, with a height difference of, for example, approximately ΔH1, to ensure that the gate dielectric layer GD and the gate GE, respectively, located on either side of the barrier layer 28, do not physically contact each other. Furthermore, the bottom surface of the gate dielectric layer GD is preferably coplanar with the bottom surfaces of the gate GE, the barrier layer 28, and the top dielectric layer 26, but is not limited thereto.

[0065] For example Figure 1As shown, semiconductor device 100 further includes a dielectric layer 10, a bottom semiconductor layer 18, a bottom dielectric layer 20, a dielectric layer 48, a through-hole OP1, and an opening OP2. The aforementioned components, such as the source SE, drain DE, gate GE, channel structure SS, gate dielectric layer GD, barrier layer 28, and top dielectric layer 26, are all disposed on dielectric layer 10. Dielectric layer 10 is disposed on a substrate (not shown), such as, but not limited to, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or other suitable materials. It should be readily understood by those skilled in the art that various desired active and / or passive components, not limited to the aforementioned components, may be further formed on or within the substrate based on actual device requirements. Specifically, the bottom semiconductor layer 18 is disposed between the bottom dielectric layer 20 and the source electrode SE in the vertical direction D1, the top dielectric layer 26 is disposed between the dielectric layer 48 and the top dielectric layer 26, and the drain electrode DE is disposed within the dielectric layer 48, but this is not limited to the above. It should be noted that a through-hole OP1 penetrates the top dielectric layer 26 and the gate electrode GE in the vertical direction D1, while an opening OP2 penetrates the bottom dielectric layer 20 in the vertical direction D1, directly connecting the through-hole OP1 and the opening OP2. The through-hole OP1 has a relatively large aperture to completely cover the opening OP2, but this is not limited to the above. Thus, the gate dielectric layer GD, the barrier layer 28, and a portion of the channel structure SS can be sequentially disposed within the through-hole OP1 in the horizontal direction D2 or its opposite direction D3, while another portion of the channel structure SS is disposed within the opening OP2, such that the channel structure SS further penetrates the bottom dielectric layer 20 in the vertical direction D1 and is in physical contact with the bottom semiconductor layer 18. Those skilled in the art will readily appreciate that the configuration of the through-hole OP1 and the opening OP2 in the present invention is not limited to the aforementioned configurations, and may have other configurations or shapes depending on actual device requirements.

[0066] In one embodiment, the source electrode SE, gate electrode GE, and drain electrode DE each comprise a composite layer structure. For example, the source electrode SE preferably comprises a metal barrier layer 12, an electrode layer 14, and a metal barrier layer 16 stacked in sequence in the vertical direction D1. The gate electrode GE comprises a metal barrier layer 22 and an electrode layer 24 stacked in sequence in the vertical direction D1, with the barrier layer 28 physically contacting both the metal barrier layer 22 and the electrode layer 24 of the gate electrode GE. The drain electrode DE comprises a metal barrier layer 42 and an electrode layer 44 stacked in sequence in the vertical direction D1. In other embodiments, the metal barrier layer 12, the metal barrier layer 16, the metal barrier layer 22, and / or the metal barrier layer 42 may be selectively omitted based on actual device requirements. Alternatively, the metal barrier layer 12, the metal barrier layer 16, the metal barrier layer 22, and / or the metal barrier layer 42 may be composite layers, but the present invention is not limited thereto. In one embodiment, the metal barrier layers 12, 16, 22, and 42 include, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, or other suitable metal barrier materials. The materials of the metal barrier layers 12, 16, 22, and 42 can be the same or different, and preferably, all include titanium nitride, but are not limited thereto. Furthermore, the electrode layers 14, 24, and 44 can all include copper (Cu), aluminum (Al), tungsten (W), or other suitable low-resistance metal materials. The materials of the electrode layers 14, 24, and 44 can be the same or different, and preferably, all include tungsten, but are not limited thereto.

[0067] On the other hand, the channel structure SS details include a channel layer 40 and an insulating layer 36 stacked in sequence in the horizontal direction D2 or the opposite direction D3, wherein the insulating layer 36 can be used to indirectly control the composition of the channel structure SS and / or support the channel structure SS. The channel layer 40 further includes a first semiconductor layer 34 and a second semiconductor layer 38 sequentially arranged in the horizontal direction D2 or the opposite direction D3. The first semiconductor layer 34 is partially arranged in the through-hole OP1 and partially arranged in the opening OP2, while the second semiconductor layer 38 is arranged in the through-hole OP1 and is located between the insulating layer 36 and the drain DE. In this embodiment, the first semiconductor layer 34 surrounds the second semiconductor layer 38 and the insulating layer 36 in the horizontal direction D2 and / or the opposite direction D3, so that the first semiconductor layer 34 is as shown in FIG. Figure 1The cross-section shown has a U-shaped cross-section and is located between the drain DE and the bottom semiconductor layer 18 in the vertical direction D1. Thus, the first semiconductor layer 34 of the channel layer 40 physically contacts both the second semiconductor layer 38 and the bottom semiconductor layer 18, thereby enabling the channel layer 40 to be electrically connected to the drain DE and the source SE when a threshold voltage is applied to the gate GE. In one embodiment, the bottom semiconductor layer 18 and the first semiconductor layer 34 and the second semiconductor layer 38 in the channel layer 40 all include a semiconductor material, such as, but not limited to, doped polysilicon, doped amorphous silicon, indium zinc oxide (IZO), aluminum zinc oxide (AZO), or indium gallium zinc oxide (IGZO). Furthermore, the materials of the first semiconductor layer 34, the second semiconductor layer 38, and the bottom semiconductor layer 18 may be the same or different. In another embodiment, the dielectric layer 10, the bottom dielectric layer 20, the top dielectric layer 26 and the dielectric layer 48 all include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride, or a high-k dielectric material, preferably including silicon oxide, but not limited thereto.

[0068] Under this configuration, the channel structure SS of the semiconductor device 100 in this embodiment exhibits a columnar structure extending along a vertical direction D1, while the gate dielectric layer GD exhibits a ring-shaped structure that surrounds a portion of the channel structure SS and is positioned between the gate GE and the channel structure SS in a horizontal direction D2. Thus, the drain DE, gate dielectric layer GD, gate GE, channel structure SS, and source SE collectively form a three-dimensional transistor device, with the channel structure SS serving as the vertical channel structure of the three-dimensional transistor device. The gate GE surrounding the channel structure SS achieves a gate-all-around (GAA) effect. According to the semiconductor device 100 of this embodiment, the top dielectric layer 26 is provided so that the barrier layer 28 is self-aligned with the protrusion 26a of the top dielectric layer 26, thereby effectively isolating the gate dielectric layer GD from direct contact with the metal material, preventing the dielectric material of the gate dielectric layer GD from reacting with the metal material of the gate GE to produce a high-resistance product, thereby improving the device performance of the gate GE and the channel structure SS. Furthermore, the semiconductor device 100 of this embodiment can be electrically connected downwardly and / or upwardly to other active and / or passive devices through other connecting components in subsequent fabrication processes. The provision of the top dielectric layer 26 and the barrier layer 28 effectively improves the device performance of the gate GE and the channel structure SS, thereby achieving more optimized operating performance.

[0069] In order to enable a person skilled in the art to easily understand and implement the semiconductor device of the present invention, a method for manufacturing the semiconductor device 100 of the present invention will be further described below.

[0070] See also Figures 2 to 8 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device 100 according to an embodiment of the present invention. Figure 2 As shown, a source electrode SE, a bottom semiconductor layer 18, a bottom dielectric material layer 120, a gate electrode GE, and a top dielectric material layer 126 are sequentially formed on the dielectric layer 10. Subsequently, a through-hole OP1 is formed sequentially through the top dielectric material layer 126 and the gate electrode GE, partially exposing the bottom dielectric material layer 120. The fabrication of the top dielectric material layer 126 and the gate electrode GE includes, but is not limited to, the following steps: First, an electrode barrier material layer (not shown) and an electrode material layer (not shown) are sequentially formed on the bottom dielectric material layer 120. These electrode material layers and the electrode barrier material layer are then patterned to form a metal barrier layer 22 and an electrode layer 24 stacked in a vertical direction D1 to form the gate electrode GE. Then, a dielectric material layer (not shown) is formed on the gate GE to fill the gap therebetween, and an etching process is performed through a mask layer (not shown), such as a wet etching process, a dry etching process, or a wet etching process and a dry etching process in sequence, to partially remove the dielectric material layer and the gate GE, thereby forming a through-hole OP1 that sequentially penetrates the dielectric material layer and the gate GE in the vertical direction D1, and simultaneously forming a top dielectric material layer 126, and then completely removing the mask layer.

[0071] It should be noted that, when performing the etching process, due to the etching selectivity difference between the dielectric material layer and the electrode material layer, as well as factors such as corner rounding, by adjusting the etching parameters, the top dielectric material layer 126 formed on the gate GE can form a circular sidewall 126a, and a recess is formed at the intersection of the circular sidewall 126a and the gate GE, as shown in FIG. Figure 2As shown. In one embodiment, the metal barrier layers 12, 16, and 22 comprise, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, or other suitable metal barrier materials, and may be the same or different, preferably all comprising titanium nitride. The electrode layers 14 and 24 comprise, for example, copper, aluminum, tungsten, or other suitable low-resistance metal materials, and may be the same or different, preferably all comprising tungsten, but not limited thereto. The dielectric layer 10, the bottom dielectric material layer 120, and the top dielectric material layer 126 comprise, for example, a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, or a high-k dielectric material, preferably all comprising silicon oxide, but not limited thereto. Furthermore, the bottom semiconductor layer 18 comprises, for example, but not limited to, a semiconductor material such as doped polysilicon, doped amorphous silicon, indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide.

[0072] like Figure 3 As shown, a film formation process such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable method is performed to form a barrier material layer 128, which is partially located within the through-hole OP1 and partially located outside the through-hole OP1, so that the barrier material layer 128 conformally covers the top surface of the top dielectric material layer 126, the curved sidewalls 126a, the sidewalls of the gate GE, and the exposed top surface of the bottom dielectric material layer 120. Then, a deposition and etch-back process is performed to form a sacrificial layer 150 that fills the through-hole OP1, so that the barrier material layer 128 covering the top dielectric material layer 126 is coplanar with the top surface of the sacrificial layer 150. In one embodiment, the barrier material layer 128 includes, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, or other suitable metal barrier materials, and its material is preferably the same as the material of the aforementioned metal barrier layer 12, metal barrier layer 16, and metal barrier layer 22, for example, all including titanium nitride, and the sacrificial layer 150 includes, for example, a dielectric material such as silicon oxide, silicon oxynitride, etc., but is not limited thereto.

[0073] like Figure 4 As shown, a wet etching process is performed under the cover of the sacrificial layer 150 to remove the barrier material layer 128 covering the top surface and curved sidewalls 126a of the top dielectric material layer 126, forming a barrier material layer 228 having a U-shaped cross-section. The barrier material layer 228 physically contacts both the metal barrier layer 22 and the electrode layer 24 of the gate GE. Furthermore, the top surface of the barrier material layer 228 is preferably higher than the top surface of the gate GE, partially filling the recess between the curved sidewalls 126a and the gate GE. In one embodiment, the height difference between the top surface of the barrier material layer 228 and the top surface of the gate GE is, for example, approximately ΔH1, but is not limited thereto.

[0074] like Figure 5As shown, a dry etching process is performed to shield the barrier material layer 228 on the lower vertical sidewall with the arc-shaped sidewall 126a of the top dielectric material layer 126, and completely remove the sacrificial layer 150 and the barrier material layer 228 directly below it, forming a Figure 1 The barrier layer 28 is shown. Then, another film formation process is performed, such as by chemical vapor deposition, physical vapor deposition, or other suitable methods, to sequentially form a first dielectric material layer 130 and a second dielectric material layer 132. Both are partially formed within the through-hole OP1 and partially formed outside the through-hole OP1. In other words, the first dielectric material layer 130 and the second dielectric material layer 132 conformally cover the top surface and curved sidewalls 126a of the top dielectric material layer 126, the sidewalls of the barrier layer 28, and the exposed top surface of the bottom dielectric material layer 120. The first dielectric material layer 130 further fills the remaining space in the recess. In one embodiment, the first dielectric material layer 130 and the second dielectric material layer 132 each comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, or a high-k dielectric material. For example, the first dielectric material layer 130 and the second dielectric material layer 132 include silicon nitride and silicon oxide, respectively, but the present invention is not limited thereto.

[0075] like Figure 6 As shown, an etching process is performed through masking the second dielectric material layer 132 and the first dielectric material layer 130 to remove the second dielectric material layer 132 and the first dielectric material layer 130 outside the through-hole OP1, as well as the second dielectric material layer 132 and the first dielectric material layer 130 located at the bottom of the through-hole OP1, thereby forming the second dielectric layer 32 and the first dielectric layer 30 to form the gate dielectric layer GD. The through-hole OP1 exposes a portion of the bottom dielectric material layer 120. Furthermore, the etching process also removes the portion of the bottom dielectric material layer 120 exposed by the through-hole OP1 downwardly, forming the bottom dielectric layer 20 and the opening OP2 penetrating the bottom dielectric layer 20, thereby exposing a portion of the bottom semiconductor layer 18.

[0076] It should be noted that the opening OP2 overlaps with the through hole OP1 in the vertical direction D1, and the projection area of ​​the opening OP2 in the vertical direction D1 is smaller than the projection area of ​​the through hole OP1 in the vertical direction D1, so that the opening OP2 and the through hole OP1 can be directly connected, but this is not limited to this. Figure 6As shown, another film formation process, such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable method, is performed to form a first semiconductor material layer 134, which is partially located within the opening OP2, partially located within the through-hole OP1, and partially located outside the through-hole OP1, so that the first semiconductor material layer 134 conformally covers the top surface of the top dielectric material layer 126, the sidewalls of the second dielectric layer 32 and the bottom dielectric layer 20, and the portion of the bottom semiconductor layer 18. In one embodiment, the first semiconductor material layer 134 includes a semiconductor material, such as doped polysilicon, doped amorphous silicon, indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide, and preferably includes the same semiconductor material as the bottom semiconductor layer 18, but is not limited thereto.

[0077] like Figure 7 As shown, after the opening OP2 is formed, a deposition and etch-back process is performed to first form an insulating material layer (not shown), fill the opening OP2 and the through-hole OP1, and further cover the first semiconductor material layer 134 outside the through-hole OP1. The insulating material layer is then partially removed, for example, the insulating material layer outside the through-hole OP1 and the opening OP2 is removed, while the insulating material layer inside the through-hole OP1 is partially removed to form an insulating layer 36. The top surface of the insulating layer 36 is, for example, lower than the top surface of the gate GE. In one embodiment, the insulating material layer includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, preferably silicon oxide, but not limited thereto.

[0078] Then, as Figure 7 As shown, a second semiconductor material layer (not shown) is formed to fill the through-hole OP1 and further cover the first semiconductor material layer 134 outside the through-hole OP1. A planarization process, such as a chemical mechanical polishing process or other suitable method, is then performed to simultaneously remove the second semiconductor material layer and the first semiconductor material layer 134 covering the through-hole OP1, thereby forming a second semiconductor layer 38 and a first semiconductor layer 34. This allows the first semiconductor layer 34 and the second semiconductor layer 38, stacked sequentially in the horizontal direction D2 or the opposite direction D3 within the through-hole OP1, to form a channel layer 40. Furthermore, the channel layer 40 and the insulating layer 36 together form the channel structure SS of the semiconductor device 100. In one embodiment, the second semiconductor material layer also comprises a semiconductor material, such as doped polysilicon, doped amorphous silicon, indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide. Preferably, the second semiconductor material layer comprises the same semiconductor material as the first semiconductor material layer 134 and the bottom semiconductor layer 18, but is not limited thereto. On the other hand, the planarization process also removes part of the second dielectric layer 32, the first dielectric layer 30 and the top dielectric material layer 126, forming Figure 1The second dielectric layer 32, the first dielectric layer 30, and the top dielectric layer 26 are shown. A portion of the top dielectric layer 26 protrudes toward the channel structure SS and is sandwiched between the drain electrode DE and the gate electrode GE, forming a protrusion 26a. The first dielectric layer 30 and the second dielectric layer 32 together form the gate dielectric layer GD of the semiconductor device 100. As such, the gate dielectric layer GD and the top dielectric layer 26 have top surfaces that are flush with each other and coplanar with the top surface of the channel structure SS.

[0079] like Figure 8 As shown, after forming the channel structure SS, the drain electrode DE is formed so that the drain electrode DE is formed on the channel structure SS, the gate dielectric layer GD and the protrusion 26a of the dielectric layer 26. Then, the dielectric layer 48 is formed to form the following structure: Figure 1 In the semiconductor device 100 shown, the first semiconductor layer 34 of the channel layer 40 physically contacts the second semiconductor layer 38 and the bottom semiconductor layer 18, thereby electrically connecting the drain DE and the source SE. Thus, the semiconductor device 100 of this embodiment is completed.

[0080] According to the fabrication method of this embodiment, a source electrode SE is first formed on the dielectric layer 10, followed by a gate electrode GE formed above the source electrode SE. Next, a through-hole OP1 is formed vertically along the top dielectric material layer 126 and the gate electrode GE. The arcuate sidewalls 126a formed on the top dielectric material layer 126 define the location for forming the barrier layer 28. This ensures that the barrier layer 28 physically contacts both the metal barrier layer 22 and the electrode layer 24 of the gate electrode GE and has a top surface higher than the gate electrode GE. A gate dielectric layer GD and a channel structure SS are then sequentially formed within the through-hole OP1, followed by a drain electrode DE formed on the gate dielectric layer GD and the channel structure SS. During this operation, at least a portion of the channel structure SS is located within the gate GE, between the drain DE and the source SE, and electrically connects the drain DE and the source SE. Furthermore, the barrier layer 28 effectively isolates the gate dielectric layer GD from direct contact with the metal material, preventing the dielectric material of the gate dielectric layer GD from reacting with the metal material of the gate GE and producing a high-resistance product. Consequently, the semiconductor device 100 fabricated by the fabrication method of this embodiment has a gate GE and channel structure SS with optimized device performance, thereby improving the operating performance of the semiconductor device 100.

[0081] A person skilled in the art of the present invention should readily understand that, in order to meet actual product requirements, the semiconductor device and its manufacturing method of the present invention may also have other aspects or be achieved by other means, and are not limited to the aforementioned. The following will further describe other embodiments or variations of the semiconductor device and its manufacturing method of the present invention. To simplify the description, the following description will primarily detail the differences between the various embodiments, without reiterating the similarities. Furthermore, identical components in the various embodiments of the present invention are designated with identical reference numerals to facilitate comparison between the various embodiments.

[0082] Please refer to Figure 9 As shown, Figure 9 FIG2 is a schematic cross-sectional view of a semiconductor device 102 according to a second embodiment of the present invention. The structure of the semiconductor device 102 according to this embodiment is substantially the same as that of the semiconductor device 100 according to the first embodiment, including a source electrode SE, a drain electrode DE, a gate electrode GE, a channel structure SS, a gate dielectric layer GD, and a top dielectric layer 26. The similarities are not further described here. The main difference between the semiconductor device 102 according to this embodiment and the first embodiment is that the protrusion 26a of the top dielectric layer 26 completely covers the top surface of the barrier layer 50.

[0083] Specifically, this embodiment adjusts the etching conditions of the aforementioned wet etching process, and partially retains the Figure 4 The barrier material layer 128 on the arc-shaped sidewall 126a of the top dielectric material layer 126 is shown, so that the barrier layer 50 formed subsequently completely fills the recess between the protrusion 26a of the top dielectric layer 26 and the top surface of the gate GE, as shown in FIG. Figure 9 As shown. The top surface of the barrier layer 50 is also preferably higher than the top surface of the gate GE, with the height difference between the two being, for example, approximately ΔH2. Thus, the provision of the barrier layer 50 ensures that the gate dielectric layer GD and the gate GE do not physically contact each other, preventing the dielectric material of the gate dielectric layer GD from reacting with the metal material of the gate GE and producing a high-resistance product. Under this configuration, the semiconductor device 102 of this embodiment can also utilize the provision of the top dielectric layer 26 to ensure that the formation position of the barrier layer 50 is self-aligned with the protrusion 26a of the top dielectric layer 26. This ensures that the barrier layer 50 effectively isolates the gate dielectric layer GD from direct contact with the metal material, improves the device performance of the gate GE and the channel structure SS, and thus enhances the operating performance of the semiconductor device 100.

[0084] Please refer to Figure 10 As shown, Figure 10FIG3 is a schematic cross-sectional view of a semiconductor device 104 according to a third embodiment of the present invention. The structure of the semiconductor device 104 according to this embodiment is substantially the same as that of the semiconductor device 100 according to the first embodiment, including a source electrode SE, a drain electrode DE, a gate electrode GE, a channel structure SS, and a top dielectric layer 26. The similarities are not further described here. The main difference between the semiconductor device 102 according to this embodiment and the first embodiment is that the bottom surface 52a of the barrier layer 52 is lower than the bottom surface of the gate electrode GE and higher than the bottom surface of the gate dielectric layer GD.

[0085] In detail, this embodiment is based on the aforementioned Figure 3 forming a barrier material layer 128, and Figure 5 Before forming the first dielectric material layer 130 and the second dielectric material layer 132, an etching process is performed in advance to slightly etch the bottom dielectric layer 20 along the through hole OP1, so that the barrier layer 52 and the first dielectric layer 54 formed subsequently are partially extended into the bottom dielectric layer 20. The bottom surface 52a of the barrier layer 52 is lower than the bottom surface of the gate GE and higher than the bottom surface 54a of the first dielectric layer 54. Figure 10 shown.

[0086] The barrier layer 52 of this embodiment also has a top surface higher than the gate GE, ensuring that the gate dielectric layer GD and the gate GE do not physically contact each other, thereby preventing the dielectric material of the gate dielectric layer GD from reacting with the metal material of the gate GE and producing a high-resistance product. With this configuration, the semiconductor device 104 of this embodiment can also utilize the top dielectric layer 26 to ensure that the formation position of the barrier layer 52 is self-aligned with the protrusion 26a of the top dielectric layer 26. This ensures that the barrier layer 52 effectively isolates the gate dielectric layer GD from direct contact with the metal material, thereby improving the device performance of the gate GE and the channel structure SS, thereby enhancing the operating performance of the semiconductor device 100.

[0087] In summary, the semiconductor device and its fabrication method of the present invention form a protrusion protruding toward the channel structure on the top dielectric layer located between the drain and the gate, so that the barrier layer is positioned in a self-aligned manner with the protrusion of the top dielectric layer, effectively isolating the gate dielectric layers located on either side of the barrier layer from direct contact with the metal material, thereby preventing the dielectric material of the gate dielectric layer from reacting with the metal material of the gate to produce a high-resistance product, thereby improving the component performance of the gate and the channel structure, and thus enhancing the operating performance of the semiconductor device.

[0088] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: source; a drain electrode, the drain electrode and the source electrode being stacked; a gate, disposed between the drain and the source; a channel structure, disposed between the drain and the source and connecting the drain and the source; a gate dielectric layer, disposed between the channel structure and the gate; a barrier layer disposed between the gate and the gate dielectric layer; as well as A top dielectric layer is disposed between the drain and the source, wherein the top dielectric layer includes a protrusion protruding toward the channel structure and sandwiched between the gate and the drain, and the protrusion at least covers a portion of the upper surface of the barrier layer.

2. The semiconductor device according to claim 1, wherein The protrusion completely covers the upper surface of the barrier layer.

3. The semiconductor device according to claim 1, wherein The gate dielectric layer contacts the upper surface of the barrier layer.

4. The semiconductor device according to claim 1, wherein The top surface of the barrier layer is higher than the top surface of the gate.

5. The semiconductor device according to claim 1, wherein The bottom surface of the barrier layer is lower than the bottom surface of the gate and higher than the bottom surface of the gate dielectric layer.

6. The semiconductor device according to claim 2, wherein A recess is formed at the junction of the protrusion and the gate, and the barrier layer fills the recess.

7. The semiconductor device according to claim 1, wherein The top surfaces of the gate and the barrier layer are lower than the top surface of the gate dielectric layer.

8. The semiconductor device according to claim 1, wherein The gate dielectric layer further comprises: a first dielectric layer disposed between the barrier layer and the channel structure and physically contacting the protrusion; and The second dielectric layer is disposed between the first dielectric layer and the channel structure.

9. The semiconductor device according to claim 1, wherein The channel structure includes a channel layer and an insulating layer stacked in sequence, and the channel layer entirely covers the insulating layer.

10. The semiconductor device according to claim 1, wherein The gate, the drain, and the source further include: an electrode layer, wherein the drain, the source, and the gate electrode layers comprise the same metal material; and The metal barrier layer is disposed below the electrode layer, and the metal barrier layer of the drain, the source, and the gate comprises the same metal barrier material.

11. The semiconductor device according to claim 10, wherein: The barrier layer physically contacts the metal barrier layer and the electrode layer of the gate.

12. The semiconductor device according to claim 1, wherein Also includes: A bottom dielectric layer is disposed between the source and the gate and physically contacts a bottom surface of the top dielectric layer, wherein a portion of the channel structure is disposed in the bottom dielectric layer.

13. A method for manufacturing a semiconductor device, characterized in that: include: forming a source electrode and a drain electrode stacked in sequence; forming a gate between the source and the drain; forming a channel structure between the drain and the source, and connecting the drain and the source; forming a gate dielectric layer between the channel structure and the gate; as well as A top dielectric layer is formed between the drain and the source, and the gate is arranged in the top dielectric layer, wherein a portion of the top dielectric layer protrudes toward the channel structure and is sandwiched between the gate and the drain, the portion of the top dielectric layer has a protrusion, and the gate is arranged below the protrusion.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: Also includes: Before forming the gate, forming a bottom dielectric layer on the source; forming a top dielectric material layer on the gate and the bottom dielectric layer to cover the top surface of the gate; as well as A through hole is formed in a vertical direction penetrating the top dielectric material layer and the gate. The top dielectric material layer has an arc sidewall, wherein a concave is formed at the intersection of the arc sidewall and the gate.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: Also includes: Before forming the channel structure, a barrier layer is formed in the through hole, located below the arc sidewall; as well as The gate dielectric layer and the channel structure are formed in the through hole, wherein the barrier layer is located between the gate dielectric layer and the gate in a horizontal direction.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The barrier layer fills the recess.

17. The method for manufacturing a semiconductor device according to claim 15, wherein: The barrier layer and a portion of the gate dielectric layer fill the recess.

18. The method for manufacturing a semiconductor device according to claim 15, wherein: Forming the barrier layer further includes: forming a barrier material layer partially located within the through-hole and partially located outside the through-hole; forming a sacrificial layer to fill the through-hole; removing the barrier material layer covering the top dielectric layer to form the barrier layer; and The sacrificial layer is completely removed.

19. The method for manufacturing a semiconductor device according to claim 14, wherein: Forming the channel structure further includes: forming a first semiconductor material layer and an insulating material layer in sequence in the through hole; Partially removing the insulating material layer and the first semiconductor material layer to form an insulating layer and a first semiconductor layer; forming a second semiconductor material layer in the through hole; and The second semiconductor material layer is partially removed to form a second semiconductor layer, wherein the channel structure includes a channel layer and the insulating layer stacked in sequence in a horizontal direction, and the channel layer includes the first semiconductor layer and the second semiconductor layer.

20. The method for manufacturing a semiconductor device according to claim 14, wherein: Forming the gate dielectric layer further includes: forming a first dielectric material layer and a second dielectric material layer, partially located within the through-hole and partially located outside the through-hole; and The second dielectric material layer and the first dielectric material layer are partially removed to form a second dielectric layer and a first dielectric layer, wherein the gate dielectric layer includes the first dielectric layer and the second dielectric layer.

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