In-memory computing units, in-memory computing methods, in-memory computing blocks, and neural network circuit components

Abstract

This invention discloses a memory computing unit, a memory computing method, an in-memory computing block, and a neural network circuit component, relating to the field of electronic circuits. The memory computing unit includes a static random access circuit unit with a first voltage terminal and a second voltage terminal, the first voltage terminal and the second voltage terminal respectively having a first voltage and a second voltage, and weight information determined according to the values ​​of the first voltage and the second voltage; at least one non-volatile memory cell connected to the first voltage terminal or the second voltage terminal; and a logic gate circuit unit, the two input terminals of which are respectively connected to the second voltage terminal and an input line. The memory computing unit provided by this invention can perform multiplication calculations in the digital domain, improving the accuracy of the calculation results and possessing high energy efficiency advantages. Furthermore, the in-memory computing circuit uses a non-volatile memory cell, ensuring that data is not lost when power is off, significantly reducing power consumption.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a memory computing unit, a memory computing method, an in-memory computing block, and a neural network circuit component. Background Technology

[0002] With the rise and development of a large number of data-intensive applications such as artificial intelligence, machine learning, and autonomous driving, there are higher requirements for the storage and processing of massive amounts of data. However, the bottleneck of the von Neumann architecture used in modern computer systems is beginning to emerge. The physical separation of its storage and processing units necessitates data transfer between them. In modern CMOS technology, the power consumption and latency generated by data transfer between processing and storage units far exceed the power consumption and latency of data processing itself—a phenomenon known as the memory wall problem. Therefore, designing solutions to overcome the bottlenecks of the von Neumann architecture is becoming increasingly important. In-Memory Computing (IMC), as an emerging architecture, has been proposed to address the memory wall problem faced by traditional computing architectures. On the one hand, this new architecture makes it possible to complete data-intensive applications with high energy efficiency; on the other hand, high-energy-efficiency processing of such tasks allows for wider deployment at resource-constrained edge computing, promoting the development of the intelligent ecosystem. Static Random Access Memory (SRAM), due to its high speed, logical compatibility, and mature technology, has received widespread attention from research institutions both domestically and internationally as a medium for in-memory computing. SRAM-based in-memory computing can be mainly divided into two categories: analog computing and digital computing.

[0003] Existing analog-domain in-memory computing schemes implement array-level parallel multiply-accumulate operations based on physical laws such as Kirchhoff's current law or the law of conservation of charge. In this computing mode, because the calculation results are represented in the form of analog voltages, they are highly sensitive to circuit noise, temperature, and process disturbances, resulting in uncertain output data and low accuracy. Furthermore, analog-domain in-memory computing schemes require analog-to-digital conversion (ADC) circuits, which occupy a large area and consume extremely high power, thus significantly reducing computational efficiency. While existing digital-domain in-memory computing schemes do not require ADC units and are more disturbance-resistant, the SRAM-based in-memory circuits must be continuously powered to compensate for leakage current and prevent information storage errors, such as when the chip enters standby mode. This power consumption overhead is a major problem with SRAM-based in-memory computing. Summary of the Invention

[0004] In view of the problems existing in the prior art, the present invention is proposed. The present invention provides a memory computing unit, a memory computing method, an in-memory computing block and a neural network circuit component, which can perform multiplication calculations in the digital domain and will not lose important information such as weights even when no power is provided, so that the computing circuit has the advantages of high performance, low power consumption and high energy efficiency.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a storage and computing unit, comprising: a static random access circuit unit having a first voltage terminal and a second voltage terminal, wherein the first voltage terminal and the second voltage terminal have a first voltage and a second voltage, and weight information is determined according to the values ​​of the first voltage and the second voltage; at least one non-volatile memory unit connected to the first voltage terminal or the second voltage terminal; and a logic gate circuit unit, wherein the two input terminals of the logic gate circuit unit are respectively connected to the second voltage terminal and an input line.

[0006] As a preferred embodiment of the storage unit of the present invention, the non-volatile storage unit has a first connection terminal and a second connection terminal, the first connection terminal is connected to the first voltage terminal or the second voltage terminal, and the second connection terminal is connected to the board wire.

[0007] As a preferred embodiment of the storage unit described in this invention, the non-volatile storage unit includes at least one non-volatile storage element.

[0008] As a preferred embodiment of the storage unit described in this invention, the non-volatile storage unit is a ferroelectric storage unit.

[0009] As a preferred embodiment of the storage unit described in this invention, the non-volatile storage unit includes a plurality of self-polarizing capacitors connected in parallel.

[0010] In a preferred embodiment of the storage unit described in this invention, the non-volatile storage element is a three-dimensional spontaneously polarized capacitor, which is located above the static random access circuit unit.

[0011] As a preferred embodiment of the storage unit of the present invention, the non-volatile storage unit further includes a third transistor, the first terminal of the third transistor is connected to the first voltage terminal or the second voltage terminal, the second terminal of the third transistor is connected to the non-volatile storage element, and the gate terminal of the third transistor is connected to the non-volatile storage word line.

[0012] As a preferred embodiment of the storage and computing unit of the present invention, the static random access circuit unit includes a latch circuit unit, and the latch circuit unit includes two inverter circuits.

[0013] As a preferred embodiment of the storage and computing unit of the present invention, the static random access circuit unit further includes: a first transistor, the first terminal of the first transistor being connected to a bit line, the second terminal of the first transistor being connected to the latch circuit unit, and the gate terminal of the first transistor being connected to a word line; and a second transistor, the first terminal of the second transistor being connected to a complementary bit line, the second terminal of the second transistor being connected to the latch circuit unit, and the gate terminal of the second transistor being connected to the word line.

[0014] As a preferred embodiment of the memory computing unit described in this invention, the logic gate circuit unit is a NOR gate circuit.

[0015] Secondly, the present invention provides a storage-based computing method, the method comprising: adjusting a storage-based computing circuit to either a storage mode or a computing mode according to a pre-configured mode control signal; when the storage-based computing circuit is in computing mode, acquiring an input signal and weight information and inputting them together to a logic gate device unit for computation; wherein the weight information is stored in a non-volatile memory device, the non-volatile memory device being composed of a static random access memory and a storage unit; the storage unit can store the weight information when the storage-based computing circuit is powered off.

[0016] As a preferred embodiment of the storage computing method of the present invention, obtaining the weight information in the storage cell includes activating the word line in the non-volatile storage device and adjusting the voltage of the bit line and complementary bit line to 0 and floating, and adjusting the voltage of the board line connected to the storage cell to read the weight information stored in the storage cell.

[0017] In a preferred embodiment of the storage computing method of the present invention, when the storage computing circuit is in storage mode, it operates as a static random access memory (SRAM) when powered on; before power is cut off, the board line voltage is adjusted to polarize the storage cell so that the weight information on the SRAM is written into the storage cell.

[0018] As a preferred embodiment of the storage computing method of the present invention, when the storage computing circuit is in standby mode, the polarization-related leakage current of the storage cell will perform current compensation on the voltage terminal in the static random access memory that stores weight information, so that the static random access memory can maintain data in the standby state.

[0019] Thirdly, the present invention provides an in-memory computing block, including an in-memory computing unit array, which is composed of a plurality of the above-mentioned in-memory computing units; and an addition tree circuit unit, which is connected to the in-memory computing unit array.

[0020] As a preferred embodiment of the in-memory computing block of the present invention, the in-memory computing unit array is composed of M rows and N columns of in-memory computing units; the M rows and N columns of in-memory computing units are connected one-to-one with M word lines, M input lines, N bit lines, N complementary bit lines and board lines.

[0021] As a preferred embodiment of the in-memory computing block of the present invention, the in-memory computing unit array stores N bits of weight information, sends M single-bit signals in each cycle, generates M N-bit multiplication results and provides them to the addition tree circuit unit, which then accumulates and sums them.

[0022] Fourthly, the present invention provides a neural network circuit component, including multiple in-memory computing blocks as described above, and further including a row address decoder, an input module, a word line driver, a board line driver, a column address decoder, a bit line driver, an inductive amplifier group, and an output module. The output terminal of the row address decoder is connected to the input terminal of the word line driver, the output terminal of the column address decoder is connected to the input terminal of the bit line driver, the word line driver is connected to multiple in-memory computing blocks via word lines, the bit line driver is connected to multiple in-memory computing blocks via bit lines, the board line driver is connected to multiple in-memory computing blocks via board lines, and the inductive amplifier group includes multiple inductive amplifiers, which are connected to multiple in-memory computing blocks via the bit lines.

[0023] The beneficial effects of this invention are as follows: The in-memory computing unit provided by this invention can perform multiplication calculations in the digital domain, improving the accuracy of the calculation results and possessing high energy efficiency. Furthermore, the in-memory computing circuit uses non-volatile memory cells, ensuring data is not lost during power outages and significantly reducing power consumption. In standby mode, this invention does not require power to the in-memory computing unit, thus achieving extremely low power consumption. Compared to SRAM-based in-memory computing circuits that require power supply in standby mode, this invention reduces power consumption by more than 30 times. In normal neural network calculation operations, compared to SRAM-based in-memory computing circuits, this invention does not require external non-volatile memory for read / write operations, thus significantly saving operation time and eliminating the power consumption consumed by data transfer. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the memory computing unit circuit structure described in Example 1.

[0026] Figure 2 This is a schematic diagram of the memory computing unit circuit structure described in Example 2.

[0027] Figure 3 This is a schematic diagram of the memory computing unit circuit structure described in Example 3.

[0028] Figure 4 This is a schematic diagram of the memory computing unit circuit structure described in Example 4.

[0029] Figure 5 This is a schematic diagram of another structure of the memory computing unit circuit described in Example 4.

[0030] Figure 6 This is a schematic diagram of the memory computing unit circuit structure described in Example 5.

[0031] Figure 7 This is a schematic diagram of the memory computing unit circuit structure described in Example 6.

[0032] Figure 8 This is a schematic diagram of the in-memory computing block described in Example 8.

[0033] Figure 9 This is a schematic diagram of the neural network circuit component described in Example 9.

[0034] In the diagram: 10, In-memory unit; 100, Static Random Access (SRAM) circuit unit; 101, Inverter circuit; 102, Latch circuit unit; 120, First transistor; 130, Second transistor; 20, Adder tree circuit unit; 200, Non-volatile memory unit; 210, Third transistor; 220, Non-volatile memory element; 30, In-memory unit array; 300, Logic gate circuit unit; 410, Word line; 420, Board line; 430, Bit line; 440, Complementary bit line; 450, Input line; 460, Non-volatile memory word line; 50, In-memory computation block; 510, Row address decoder; 520, Input module; 530, Word line driver; 540, Board line driver; 550, Column address decoder; 560, Bit line driver; 570, Sensing amplifier group; 580, Output module; Q, First voltage terminal; QB, Second voltage terminal. Detailed Implementation

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0037] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it an embodiment that is mutually exclusive, either alone or selectively, with other embodiments. Example 1

[0038] Reference Figure 1 This is the first embodiment of the present invention. This embodiment provides a storage and computing unit 10, which includes a static random access circuit unit 100, a non-volatile memory unit 200, and a logic gate circuit unit 300.

[0039] Specifically, the static random access circuit unit 100 includes a latch circuit unit 102, which includes two inverter circuits 101. The output terminals of the two inverters 101 are respectively the first voltage terminal Q and the second voltage terminal QB of the static random access circuit unit 100. The voltage values ​​of the first voltage terminal Q and the second voltage terminal QB determine the weighting information. In this embodiment, the static random access circuit unit 100 is based on a 4T SRAM circuit.

[0040] In this embodiment, the non-volatile memory cell 200 is a ferroelectric memory cell and there are two of them. Each non-volatile memory cell 200 has a non-volatile memory element 220. Each non-volatile memory element 220 has a first connection terminal and a second connection terminal. The first connection terminals of the two non-volatile memory elements 220 are respectively connected to the first voltage terminal Q and the second voltage terminal QB of the static random access circuit unit 100, and the second connection terminals are both connected to the board line 420.

[0041] The logic gate unit 300 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the second voltage terminal QB of the static random access circuit unit 100 and is used to receive weighting information. The second input terminal is connected to the input line 450 and is used to receive the input signal. The output terminal is used to output the calculation result for further calculation.

[0042] Furthermore, this storage and computing unit 10 has two operating modes: storage mode and computing mode.

[0043] In normal storage mode, the memory unit 10 operates solely as SRAM. The memory unit 10 can read and write data through the same interface as SRAM. In this design, board line 420 needs to be set at a relatively high initial voltage (V). start The non-volatile memory cell 200, i.e., the ferroelectric memory cell, is initialized with a voltage of 1.5V to achieve its polarization state. The polarization-dependent leakage current (PDLC) will increase. The ferroelectric memory cell is now in a positive polarization state. The PDLC then flows to the first voltage terminal Q and the second voltage terminal QB.

[0044] When the memory storage unit 10 enters standby mode, the polarization-dependent leakage current (PDLC) can compensate for the leakage current at the first voltage terminal Q (assuming Q = "1"). Compared to the prior art using resistive loads, i.e., placing two load resistors across the first voltage Q and the second power supply QB, the DC current through the load resistor path to ensure data retention in the SRAM during standby is in the microampere range, resulting in significant power consumption. The polarization-dependent leakage current (PDLC), however, is only in the nanoampere range, thus compensating for leakage current while significantly reducing power consumption.

[0045] When the system is powered on in storage mode, the weighted data in the first voltage terminal Q and the second voltage terminal QB must be stored in the non-volatile memory cell 200, i.e., the ferroelectric memory cell. The first voltage terminal Q and the second voltage terminal QB are VDD = 0.9V and GND = 0V, respectively. To complete this storage operation, the board line 420 is pulled up to voltage VDD = 0.9V. store = 2.0V, pulled down to voltage VDD-V store =-1.1V. A bias voltage of 2.0V or -2.0V on one ferroelectric memory cell is sufficient to write to one of the ferroelectric memory cells and generate spontaneous polarization. At the same time, if the bias voltage on the other ferroelectric memory cell is a safe voltage of 1.1V and -1.1V, polarization reversal cannot occur.

[0046] When the storage unit 10 is woken up, it needs to read the stored weight data into the first voltage terminal Q and the second voltage terminal QB to resume operation. To start this process, the word line 410 should be turned on first, then the bit line 430 and the complementary bit line 440 should be discharged to 0 and floated, and then the board line 420 should be pulled to voltage V. store =2.0V for recovery operation. Internal nodes have different capacitance values, which helps restore the voltage at the first voltage terminal Q and the second voltage terminal QB to their previous values ​​before power failure. Afterwards, board line 420 is pulled to V. start =1.5V, and the storage unit 10 enters normal SRAM mode.

[0047] The memory-in-memory unit 10 of this embodiment is used for low-power applications. Two ferroelectric memory cells are embedded in a 4T SRAM. Due to the compatibility of ferroelectric memory cells with CMOS processes, the ferroelectric memory cells can be directly integrated into the back-end process. The area of ​​the 4T SRAM is 1 / 3 smaller than that of a standard 6T SRAM. Therefore, the memory-in-memory unit 10 of this embodiment has a significant advantage in terms of area saving.

[0048] Furthermore, ferroelectric memory cells possess excellent memory characteristics. By utilizing the polarization-dependent leakage current (PDLC) of ferroelectric memory cells to compensate for the dynamic node leakage current of traditional 4T no-load SRAM, power consumption is significantly reduced, making the ferroelectric memory cell-based in-memory computing unit 10 a promising solution for future low-power applications. This in-memory computing unit 10 features low power consumption, small area, simple structure, and high CMOS compatibility. Example 2

[0049] Reference Figure 2 This is the second embodiment of the present invention. This embodiment also provides a storage unit 10, but unlike the first embodiment, the static random access circuit unit 100 in the storage unit 10 of this embodiment uses 6T SRAM.

[0050] Specifically, the static random access circuit unit 100 also includes a first transistor 120, which has a first terminal, a second terminal and a gate terminal. The first terminal of the first transistor 120 is connected to the bit line 430, the second terminal of the first transistor 120 is connected to the latch circuit unit 102, and the gate terminal is connected to the word line 410.

[0051] The second transistor 130 has a first terminal, a second terminal, and a gate terminal. The first terminal of the second transistor 130 is connected to the complementary bit line 440, the second terminal of the second transistor 130 is connected to the latch circuit unit 102, and the gate terminal is connected to the word line 410.

[0052] Preferably, the non-volatile memory cell 200 is a ferroelectric memory cell.

[0053] It is worth noting that in normal mode, board line 420 is set to V. start =VDD / 2 (VDD=0.9V), storage unit 10 operates as SRAM, allowing read and write operations. If VDD / 2 < V c (Coercive voltage) without polarization reversal and without loss.

[0054] During storage, board line 420 is pulled up to V. store Scroll down to VDD-V storeA bias voltage of 2.0V or -2.0V on one ferroelectric memory cell is sufficient to write to it and generate spontaneous polarization. Simultaneously, a bias voltage of 1.1V and -1.1V on the other ferroelectric memory cell prevents polarization reversal. To perform a recovery operation during startup, word line 410 (WL) should be opened first. Then, bit line 430 (BL) and complementary bit line 440 (BLB) should be discharged to 0 and floated. Finally, board line 420 should be pulled to the recovery voltage Vstore to complete the recovery operation. Example 3

[0055] Reference Figure 3 This is the third embodiment of the present invention. This embodiment is based on the previous embodiment, but unlike embodiment 2, there is only one non-volatile memory unit 200 in this embodiment. The first connection terminal of this non-volatile memory unit 200 is connected to the first voltage terminal Q of the static random access circuit unit 100, and the second connection terminal is connected to the board line 420. Example 4

[0056] Reference Figure 4 This is the fourth embodiment of the present invention. This embodiment is based on the previous embodiment, but unlike embodiment 3, the non-volatile memory cell 200 in this embodiment includes a third transistor 210 in addition to a non-volatile memory element 220.

[0057] Specifically, the third transistor 210 has a first terminal, a second terminal, and a gate terminal. The first terminal of the third transistor 210 is connected to the first voltage terminal Q, the second terminal is connected to the non-volatile memory element 220, and the gate terminal is connected to the non-volatile memory word line 460.

[0058] In normal mode, the memory unit 10 operates like SRAM, and can read and write data through the same interface as SRAM. The drain of the third transistor 210 adds a quasi-capacitance at the first voltage terminal Q, but this does not significantly affect the read and write access time.

[0059] During storage operations, word line 410 is turned on, and data from bit line 430 is written to the first voltage terminal Q. Simultaneously, the third transistor 210 is turned on, and board line 420 is at VDD - Vstore = -1.1V. The ferroelectric memory cell is programmed based on the voltage at the first voltage terminal Q. Therefore, if the first voltage terminal Q is VDD = 0.9V, the voltage of the ferroelectric memory cell is -2.0V, and the ferroelectric memory cell will be fully polarized. If the first voltage terminal Q is GND = 0V, the bias voltage of the ferroelectric memory cell is -1.1V, the ferroelectric memory cell will be partially polarized, and then the power is turned off.

[0060] In recovery mode, the third transistor 210 is turned on, and then the board line 420 is pulled up to V. store A recovery operation is performed at 2.0V. If the ferroelectric memory cell stores a high level, it releases enough charge to bring the first voltage terminal Q high, while the second voltage terminal QB is low. If the ferroelectric memory cell stores a low level, the first voltage terminal Q will return to low, and the second voltage terminal QB will reach high.

[0061] Reference Figure 5 The non-volatile memory cell 200, which includes a non-volatile memory element 220 and a third transistor 210, can also be configured as two cells, and connected to the first voltage terminal Q and the second voltage terminal QB respectively. The two non-volatile memory cells 200 store opposite information, and their operation is the same as above. Example 5

[0062] Reference Figure 6 This is the fifth embodiment of the present invention. This embodiment is based on embodiment 2, but unlike embodiment 2, the non-volatile memory cell 200 has a plurality of non-volatile memory elements 220 connected in parallel.

[0063] Preferably, the non-volatile storage element 220 is a self-polarized capacitor. During the recovery operation, the self-polarized capacitor can discharge to the first voltage terminal Q and the second voltage terminal QB. The discharge causes different voltages to be generated at the two voltage terminals. The inductive amplifier amplifies this voltage value to obtain the weight. At the same time, the more self-polarized capacitors are connected in parallel, the more discharge occurs, the more obvious the voltage difference becomes, and the more accurate the result of the recovery operation.

[0064] Preferably, the non-volatile memory element 220 is a three-dimensional spontaneously polarized capacitor, which is located above the static random access circuit unit 100. Using a three-dimensional spontaneously polarized capacitor significantly reduces the footprint and allows for placement above the static random access circuit unit 100. It also reduces cost and allows information to be retained for over 10 years even when power is off. It requires a lower operating voltage, generates less current, and operates at extremely high speed, resulting in very low power consumption. Furthermore, spontaneously polarized capacitors have excellent resistance to radiation and electromagnetic interference and are heat-resistant. If a magnetic tunnel junction, for example, is used instead of a spontaneously polarized capacitor, the manufacturing process is more difficult and costly, the current is higher leading to higher power consumption, and it is more susceptible to magnetic field interference and not heat-resistant. If a resistive switching memory cell is used, its durability is very poor. Example 6

[0065] Reference Figure 7 This is the sixth embodiment of the present invention. This embodiment is based on embodiment 2. The difference between this embodiment and embodiment 2 is that the logic gate unit 300 in this embodiment is a NOR gate circuit, which includes two PMOS transistors and two NMOS transistors.

[0066] The NOR gate unit 300, composed of two PMOS transistors and two NMOS transistors, has a small area overhead and is well-suited for large-scale in-memory computing circuits. One operand W is input from the inverted terminal of the static random access circuit unit 100, and the other operand A is input from the outside in one's complement form. Then, the output result M of the NOR gate unit 300 is the result of the operation W·A. Example 7

[0067] This embodiment provides a storage method for a storage circuit, the storage method including:

[0068] First, the storage circuit is controlled to operate in either storage mode or computing mode based on the mode control signals pre-configured in the peripheral circuits.

[0069] When the memory-based computing circuit is in computing mode, it acquires the input signal and weight information and inputs them together to the logic gate device unit for calculation.

[0070] The input signal is obtained by loading the input signal onto the logic gate device unit through an external input line. The logic gate device unit can be a NOR gate device unit.

[0071] Weight information is stored in a non-volatile memory device, which consists of static random access memory (SRAM) and memory cells. When powered on, the weight information can be directly loaded from the SRAM into the logic gate device and combined with the input signal for computation. The memory cells can store the weight information when the computation circuit is powered off. The memory cells can be ferroelectric memory cells.

[0072] If the in-memory computing circuit has experienced a power outage, the weight information stored in the memory cells must be loaded into the static random access memory (SRAM) upon power-up. To accomplish this, the word lines in the in-memory computing circuit must first be activated, and then the bit lines and complementary bit lines must be discharged to 0 and allowed to float. Next, the board line voltages in the non-volatile memory devices must be adjusted to the specified voltages so that the weight information stored in the memory cells is loaded into the SRAM.

[0073] It is worth noting that when the memory-based computing circuit is in storage mode, it operates as a conventional static random access memory when powered on, for example, performing storage operations.

[0074] Before a power outage, the board line voltage is adjusted to polarize the memory cells, allowing the weight information from the static random access memory to be written into the memory cells. This ensures that the information in the memory circuitry is not lost due to power failure. If ferroelectric memory cells are selected, a large amount of information can be written in parallel through multiple memory circuits within a microsecond-level timeframe before a power outage, thus eliminating the need for a backup battery, significantly simplifying the system and saving costs.

[0075] When the memory circuit is in standby mode, the polarization-related leakage current of the memory cell will compensate the voltage terminal in the static random access memory that stores weight information, so that the static random access memory can retain data in standby mode. Example 8

[0076] Reference Figure 8 The eighth embodiment of the present invention provides an in-memory computing block 50 structure, including an in-memory computing unit array 30 and an addition tree circuit unit 20.

[0077] Specifically, the memory cell array 30 is composed of multiple memory cells 10;

[0078] The addition tree circuit unit 20 is connected to the memory computing unit array 30.

[0079] Furthermore, the memory cell array 30 is composed of M rows and N columns of memory cells 10 and is connected to M word lines 410, M input lines 450, N bit lines 430, N complementary bit lines 440 and board lines 420.

[0080] Furthermore, the storage unit array 30 stores N bits of weight information, and sends M single-bit signals in each cycle to generate M N-bit multiplication results, which are provided to the adder tree circuit unit 20, which then accumulates and sums them.

[0081] It should be noted that multiple in-memory computing units 10 can be arranged in an M*N rectangular array to form an in-memory computing block 50. Specifically, there are M word lines 410 and input lines 450 in total, with each word line 410 corresponding to one input line 450; each group of word lines 410 and input lines 450 connects to a row of in-memory computing units 10.

[0082] A bit line 430 and a complementary bit line 440 form a group, and there are N groups in total. Each group is connected to a column of memory units 10. The input line 450 is the inverse signal of the neural network input signal. A single bit signal enters each cycle, and the p-bit IN_B signal is serially sent to the memory unit through p cycles. The output of p cycles will be summed in the adder tree circuit unit 20 through shift accumulation. Example 9

[0083] Reference Figure 9 The ninth embodiment of the present invention provides a neural network circuit component, including multiple in-memory computing blocks 50, and further including a row address decoder 510, an input module 520, a word line driver 530, a board line driver 540, a column address decoder 550, a bit line driver 560, an inductive amplifier group 570, and an output module 580.

[0084] Furthermore, the output of the row address decoder 510 is connected to the input of the word line driver 530; the output of the column address decoder 550 is connected to the input of the bit line driver 560; the word line driver 530 is connected to multiple in-memory computing blocks 50 via word lines 410; the bit line driver 560 is connected to multiple in-memory computing blocks 50 via bit lines 430; and the board line driver 540 is connected to multiple in-memory computing blocks 50 via board lines 420. The sense amplifier group 570 includes multiple sense amplifiers and is connected to multiple in-memory computing blocks 50 via bit lines 430.

[0085] It should be noted that the multiple in-memory computing blocks 50 in the neural network circuit form an in-memory computing array. Specifically, the output of the in-memory computing array input module 520 is connected to the input of the row address decoder 510 and the column address decoder 550. The encoder of the input module 520 is used to receive neural network input data and encode the input data to match the input requirements of the row address decoder 510; the row address decoder 510 decodes the input data and provides word line signals to the 10 columns of the in-memory computing units through the word line driver to perform convolution operations; the column address decoder 550 selects the required 10 columns of the in-memory computing units according to the obtained column address, while the inductive amplifier group 570 can amplify the voltage signal.

[0086] The proposed circuit architecture supports two operating modes: normal SRAM mode and in-memory computation mode. In normal SRAM mode, the SRAM cells in the neural network circuit can perform regular data access, consistent with basic SRAM memory. The timing module generates corresponding read / write control signals to perform read / write operations on the rows where word line 410 is activated. In in-memory computation mode, its advantage lies in the parallelism of operations; multiple rows can be processed simultaneously. Before performing multiplication, weight data must be written to the in-memory computation block 50 in SRAM mode, and then the circuit is switched to in-memory computation mode via the mode control signal. Multiplication in memory is performed by the neural network circuit in conjunction with a well-defined pulse sequence. Upon receiving the mode control signal, corresponding timing signals are generated, which control the neural network circuit to perform operations. During this process, external input is driven sequentially from least significant bit to most significant bit into the in-memory computation block 50, with the entire in-memory computation array operating in parallel.

[0087] Additionally, it should be noted that the non-volatile memory cell 200 in this invention can also employ an ultra-stable random access memory (HsRAM) cell. This type of memory is a novel type of memory chip that uses High-K spontaneously polarized materials as capacitor dielectrics to achieve storage functionality, based on a logic chip. The High-K spontaneously polarized material and the top and bottom electrodes are deposited within the 3D computing module using atomic layer deposition (ALD). ALD is a method of thin film deposition using atomic layer-by-layer growth, achieving atomic-level thickness in its thinnest layer, and is widely used in chip wafer manufacturing. Existing memories using spontaneously polarized materials to construct memory cells include ultra-stable memories and ferroelectric memories.

[0088] In summary, the in-memory computing circuit provided by this invention performs calculations in a fully digital domain, is resistant to process and noise disturbances, and has deterministic output.

[0089] In the event of a power outage, a non-volatile memory cell 200 is used to store weight information. The preferred non-volatile memory element 220 is a self-polarized capacitor. Because self-polarized capacitors are non-volatile and have ultra-low standby power consumption, they effectively avoid the problem of SRAM memory cells needing constant power to compensate for leakage current, significantly reducing power consumption. This invention can be widely applied to applications based on multiply-accumulate operations, such as neural networks and image filtering.

[0090] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A storage unit (10) applied to a neural network, characterized in that: include, A static random access circuit unit (100) has a first voltage terminal (Q) and a second voltage terminal (QB), wherein the first voltage terminal (Q) and the second voltage terminal (QB) have a first voltage and a second voltage, respectively, and weight information is determined according to the values ​​of the first voltage and the second voltage; At least one non-volatile memory cell (200) is connected to either the first voltage terminal (Q) or the second voltage terminal (QB); and, A logic gate circuit unit (300) is provided, wherein the two input terminals of the logic gate circuit unit (300) are respectively connected to the second voltage terminal (QB) and the input line (450); The non-volatile memory cell (200) is a FeRAM ferroelectric memory cell.

2. The in-memory computing unit (10) applied to a neural network as described in claim 1, characterized in that: The non-volatile memory cell (200) has a first connection terminal and a second connection terminal. The first connection terminal is connected to the first voltage terminal (Q) or the second voltage terminal (QB), and the second connection terminal is connected to the board line (420).

3. The in-memory computing unit (10) applied to a neural network as described in claim 1 or 2, characterized in that: The non-volatile memory cell (200) includes at least one non-volatile memory element (220), which is a spontaneously polarized capacitor.

4. The in-memory computing unit (10) applied to a neural network as described in claim 1, characterized in that: The non-volatile memory cell (200) includes a plurality of self-polarized capacitors connected in parallel.

5. The in-memory computing unit (10) applied to a neural network as described in claim 3, characterized in that: The non-volatile storage element (220) is a three-dimensional spontaneously polarized capacitor located above the static random access circuit unit (100).

6. The in-memory computing unit (10) applied to a neural network as described in claim 3, characterized in that: The non-volatile memory cell (200) further includes a third transistor (210), the first terminal of the third transistor (210) is connected to the first voltage terminal (Q) or the second voltage terminal (QB), the second terminal of the third transistor (210) is connected to the non-volatile memory element (220), and the gate terminal of the third transistor (210) is connected to the non-volatile memory word line (460).

7. The in-memory computing unit (10) applied to a neural network as described in claim 1, characterized in that: The static random access circuit unit (100) includes a latch circuit unit (102), which includes two inverter circuits (101).

8. The in-memory computing unit (10) applied to a neural network as described in claim 7, characterized in that: The static random access circuit unit (100) also includes, A first transistor (120) is connected to a bit line (430) at its first terminal, and to the latch circuit unit (102) at its second terminal. The gate of the first transistor (120) is connected to a word line (410). The second transistor (130) has its first terminal connected to the complementary bit line (440), its second terminal connected to the latch circuit unit (102), and its gate terminal connected to the word line (410).

9. The in-memory computing unit (10) applied to a neural network as described in claim 1, characterized in that: The logic gate circuit unit (300) is an NOR gate circuit.

10. A storage and calculation method, characterized in that: Based on the pre-configured mode control signal, the in-memory circuit is put into either storage mode or computing mode; When the memory computing circuit is in computing mode, it acquires input signals and weight information and inputs them together to the logic gate device unit for calculation. The weight information is stored in a non-volatile storage device, which consists of a static random access memory and a storage unit; the storage unit can store the weight information when the computing circuit is powered off.

11. The storage and computation method as described in claim 10, characterized in that: Obtaining the weight information in the storage unit includes, Activate the word lines in the non-volatile memory device and adjust the voltages of the bit lines and complementary bit lines to 0 and allow them to float. Adjust the voltage of the board line connected to the memory cell to read the weight information stored in the memory cell.

12. The storage and computation method as described in claim 11, characterized in that: When the memory computing circuit is in memory mode When powered on, the memory circuit operates as a static random access memory; Before power is cut off, the plate line voltage is adjusted to polarize the storage cell so that the weight information on the static random access memory is written into the storage cell.

13. The storage and computation method as described in claim 12, characterized in that: When the memory circuit is in standby mode, the polarization-related leakage current of the memory cell will compensate the voltage terminal in the static random access memory that stores weight information, so that the static random access memory can retain data in standby mode.

14. An in-memory computing block (50), characterized in that: include, The in-memory computing unit array (30) is composed of a plurality of in-memory computing units (10) as described in any one of claims 1 to 9; An adder tree circuit unit (20) is connected to the memory unit array (30).

15. The in-memory computing block (50) as described in claim 14, characterized in that: The storage unit array (30) consists of M rows and N columns of storage units (10); The storage unit (10) in rows M and columns N is connected one-to-one with M word lines (410), M input lines (450), N bit lines (430), N complementary bit lines (440) and board lines (420).

16. The in-memory computing block (50) as described in claim 15, characterized in that: The storage unit array (30) stores N bits of weight information. M single-bit signals are sent in each cycle to generate M N-bit multiplication results, which are provided to the addition tree circuit unit (20). The addition tree circuit unit (20) then sums them up.

17. A neural network circuit component, characterized in that: Including multiple in-memory computing blocks (50) as described in any one of claims 14-16, and further including a row address decoder (510), an input module (520), a word line driver (530), a board line driver (540), a column address decoder (550), a bit line driver (560), an inductive amplifier group (570), and an output module (580), wherein the output terminal of the row address decoder (510) is connected to the input terminal of the word line driver (530), and the output terminal of the column address decoder (550) is connected to the bit line driver (560). The input terminal of the driver (560) is connected to multiple in-memory computing blocks (50) via word lines (410), the bit line driver (560) via bit lines (430) and the board line driver (540) via board lines (420). The sensing amplifier group (570) includes multiple sensing amplifiers and is connected to multiple in-memory computing blocks (50) via the bit lines (430).

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