Array substrate, display panel, and method for repairing broken scanning line of display panel

Abstract

The present application provides an array substrate, a display panel, and a method for repairing a broken scanning line of a display panel. The array substrate includes n rows of sub-pixel units, n scanning lines electrically connected to the n rows of sub-pixel units one by one, and m coupling lines. The n scanning lines are used to receive corresponding first scanning signals to perform progressive scanning on the n rows of sub-pixel units. The voltage value of the first scanning signal received by each scanning line starts to decrease from the turn-on voltage to the blanking voltage at the end of the scanning. The m coupling lines correspond to the m scanning lines one by one. Each coupling line is arranged in parallel with the corresponding scanning line to form a coupling capacitor. Each coupling line is used to receive a corresponding second scanning signal to shorten the time for the voltage value of the corresponding scanning line to decrease from the turn-on voltage to the blanking voltage after the scanning ends through the coupling effect of the corresponding coupling capacitor. The array substrate provided by the present application can solve the problem of upper ghosting when the display screen is displaying.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to an array substrate, a display panel, and a method for repairing broken scanning lines of a display panel. Background Art

[0002] With the continuous development of the display industry, various technologies for improving display effects emerge in an endless stream. Among them, MiniLED (Mini light-emitting diode, sub-millimeter light-emitting diode) technology has quickly become popular with its powerful advantages. With characteristics such as higher resolution, contrast ratio, and color gamut range, it has a wide range of applications in both the direct display and backlight markets. Due to the increasingly dense integration of MiniLED lamp beads, the distance between MiniLED lamp beads is getting smaller, the wiring is getting denser, and the parasitic capacitance is increasing, which has a greater impact on the display effect. Most existing MiniLED display products adopt a dynamic scanning driving method. Due to the existence of coupling capacitance, when the scanning circuit is turned off, the charge stored in the coupling capacitance cannot be released in time, which will cause the MiniLED lamp in the required dark area to be slightly bright, resulting in upper ghosting.

[0003] Therefore, how to eliminate the upper ghosting that appears when a MiniLED display screen is displaying is an urgent problem to be solved. Summary of the Invention

[0004] In view of this, the main purpose of the present application is to propose an array substrate, a display panel, and a method for repairing broken scanning lines of a display panel, aiming to solve the problem of upper ghosting that appears when an existing MiniLED display screen is displaying.

[0005] To achieve the above object, a first aspect of the present application provides an array substrate. The array substrate includes n rows of sub-pixel units and n scanning lines electrically connected to the n rows of sub-pixel units one by one. The n scanning lines are used to receive corresponding first scanning signals to perform progressive scanning on the n rows of sub-pixel units. Among them, the voltage value of the first scanning signal received by each scanning line drops from the turn-on voltage to the blanking voltage at the end of the scanning. n > 1. The array substrate further includes m coupling lines. The m coupling lines correspond to m scanning lines among the n scanning lines one by one. Each coupling line is arranged in parallel with the corresponding scanning line to form a coupling capacitance. Each coupling line is used to receive a corresponding second scanning signal to shorten the time for the voltage value of the corresponding scanning line to drop from the turn-on voltage to the blanking voltage after the scanning ends through the coupling action of the corresponding coupling capacitance. Among them, n ≥ m ≥ 1, and the voltage value of the second scanning signal received by each coupling line drops from a second voltage to a first voltage at the end of the scanning of the scanning line corresponding to the coupling line.

[0006] The array substrate provided by the present application forms a coupling capacitance between a corresponding scanning line and a coupling line by setting a coupling line parallel to the scanning line, and outputs a corresponding second scanning signal to the coupling line, so that at the end of the scanning of the scanning line, the voltage of the coupling line synchronously drops from the second voltage to the first voltage, thereby quickly releasing the stored charge of the parasitic capacitance of the corresponding scanning line through the coupling action of the corresponding coupling capacitance, and then shortening the time for the voltage value of the scanning line to drop from the turn-on voltage to the blanking voltage after the scanning ends. It can avoid the mis-lighting of the sub-pixel units in this row due to the too high voltage of the scanning line in this row when the next row of scanning lines is scanned, and can solve the problem of upper ghosting in the MiniLED display screen.

[0007] In some embodiments, the number of the coupling lines is equal to the number of the scanning lines.

[0008] In some embodiments, the difference between the turn-on voltage and the blanking voltage is greater than or equal to the difference between the first voltage and the second voltage.

[0009] In some embodiments, the second voltage is less than or equal to the turn-on voltage.

[0010] In some embodiments, the second scanning signal received by each coupling line starts to rise from the first voltage to the second voltage at the start of the scanning of the scanning line corresponding to the coupling line.

[0011] In some embodiments, the waveform of the second scanning signal received by each coupling line during the process of rising from the first voltage to the second voltage is in a stepped increasing shape, or a linear increasing shape, or a non-linear increasing shape.

[0012] In some embodiments, the array substrate includes a substrate, a first conductor layer, an insulating layer, and a second conductor layer formed on the substrate in sequence. Among them, the n scanning lines are located in the first conductor layer, the m coupling lines are located in the second conductor layer, or the m coupling lines are located in the first conductor layer, and the n scanning lines are located in the second conductor layer.

[0013] In some embodiments, the projection of each coupling line on the substrate at least partially coincides with the projection of the scanning line corresponding to the coupling line on the substrate.

[0014] The second aspect of the present application further provides a display panel, which includes a row driver and the array substrate described in the first aspect above. Among them, the row driver is used to output n first scan signals and m second scan signals. The n scan lines and m coupling lines of the array substrate each include opposite first ends and second ends. The first ends of the n scan lines and the first ends of the m coupling lines are all electrically connected to the row driver. The n scan lines are used to receive the corresponding first scan signals from the row driver through the first ends, and the m coupling lines are used to receive the corresponding second scan signals from the row driver through the first ends.

[0015] The third aspect of the present application further provides a method for repairing a broken scan line of a display panel. The repair method is applied to the display panel described in the second aspect above. The repair method includes: when a break point appears in the scan line corresponding to any coupling line in the display panel, finding the position of the break point; and electrically connecting the part between the break point and the second end of the broken scan line to the coupling line corresponding to the broken scan line.

[0016] The additional aspects and advantages of the present application will be partly given in the following description, partly become obvious from the following description, or be understood through the practice of the present application. Description of the Drawings

[0017] Figure 1 It is a schematic circuit structure diagram of the display panel provided by the embodiment of the present application;

[0018] Figure 2 It is the first waveform diagram of the driving signal of the display panel provided by the embodiment of the present application;

[0019] Figures 3 to 4 It is a schematic diagram of the layered structure of the array substrate provided by the embodiment of the present application;

[0020] Figure 5 It is a sectional view of the array substrate provided by the embodiment of the present application;

[0021] Figure 6 It is the second waveform diagram of the driving signal of the display panel provided by the embodiment of the present application;

[0022] Figure 7 It is the third waveform diagram of the driving signal of the display panel provided by the embodiment of the present application;

[0023] Figure 8 It is a flowchart of the method for repairing a broken scan line of the display panel provided by the embodiment of the present application;

[0024] Figure 9 It is a schematic diagram of the repair process of the method for repairing a broken scan line of the display panel provided by the embodiment of the present application.

[0025] The descriptions of the reference numerals are as follows:

[0026] Display panel 100

[0027] Array substrate 1

[0028] TCON 201

[0029] Row driver 202

[0030] Column driver 203

[0031] Scan line 101

[0032] First scan signal G1

[0033] Data line 102

[0034] Data signal S1

[0035] Sub-pixel unit P

[0036] Parasitic capacitance C1

[0037] Coupling line 101s

[0038] Second scan signal G1s

[0039] Coupling capacitance Cs

[0040] Substrate 11

[0041] First conductor layer 12

[0042] Second conductor layer 13

[0043] LED layer 14

[0044] Anti-glare protection layer 15

[0045] Turn-on voltage Vk

[0046] Blanking voltage Vs

[0047] First voltage V1

[0048] Second voltage V2

[0049] Operating voltage Vd

[0050] Turn-off voltage Vg

[0051] Scan start time t1

[0052] Scan end time t2

[0053] The following specific embodiments will further illustrate the present application in conjunction with the above-mentioned drawings. Detailed implementation manners

[0054] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0055] In addition, terms such as "first" and "second" in the specification of the present invention are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0056] It should be noted that, without conflict, the features in the embodiments of the present application can be combined with each other.

[0057] Please refer to Figure 1 , Figure 1 which is a schematic circuit structure diagram of a display panel provided by an embodiment of the present application. As Figure 1 shown, the display panel 100 includes an array substrate 1, a timing controller (TCON) 201, a gate driver 202, and a source driver 203.

[0058] Among them, the array substrate 1 includes n scan lines 101 extending in the row direction, x data lines 102 extending in the column direction, and a plurality of sub-pixel units P arranged in a multi-row and multi-column array defined by the n scan lines 101 and the x data lines 102, where n>1 and x>1.

[0059] The timing controller 201 is electrically connected to the gate driver 202 and the source driver 203 respectively. The gate driver 202 is electrically connected to each row of the sub-pixel units P through n scan lines 101, and the source driver 203 is electrically connected to each column of the sub-pixel units P through x data lines 102.

[0060] The timing controller 201 is used to store the picture data of the frame to be displayed. For example, during the process of the display panel 100 displaying the current frame picture, the next frame of picture data is stored in the timing controller 201. When driving the display panel 100 to display the frame picture to be displayed, based on the picture data of the frame to be displayed, the timing controller 201 controls the row driver 202 to output corresponding first scan signals to multiple sub-pixel unit rows through the n scan lines 101 according to a preset timing, and controls the column driver 203 to output corresponding data signals to multiple sub-pixel unit columns through the x data lines 102, so as to drive the display panel 100 to display the frame picture to be displayed.

[0061] Further, the display panel 100 is an LED display panel, such as a MiniLED display panel or a MicroLED display panel. Specifically, each sub-pixel unit P includes a light-emitting diode (LED). The anode of the light-emitting diode is electrically connected to the corresponding scan line 101 to receive the first scan signal, and the cathode of the light-emitting diode is electrically connected to the corresponding data line 102 to receive the data signal. The light-emitting diode emits light based on the received first scan signal and data signal.

[0062] The following combines Figures 1 to 2 to introduce the working process of the LED display panel. Among them, Figure 2 is the first waveform diagram of the driving signal of the display panel provided by the embodiment of the present application.

[0063] The driving method of the display panel 100 is progressive scanning. When scanning to the first row, at Figure 1Taking the sub-pixel unit P located in the first row and the first column as an example, when the anode of the light-emitting diode in the sub-pixel unit P receives the turn-on voltage Vk in the first scan signal G1 through the first scan line, and the cathode of the light-emitting diode in the sub-pixel unit P receives the operating voltage Vg in the data signal S1 through the first data line, a voltage difference is formed between the anode and the cathode of the light-emitting diode in the sub-pixel unit P at this time, and the current flows from the anode of the light-emitting diode to the cathode, so that the light-emitting diode emits light. Among them, the turn-on voltages Vk of all the first scan signals are equal (for example, all equal to the first turn-on voltage Vk1), and the operating voltages Vg of all the data signals are also equal (for example, all equal to the first operating voltage Vd1). The display gray level of the sub-pixel unit P is determined by the duty ratio of the duration of the operating voltage Vg in the data signal S1, that is, the timing controller 201 adjusts the display gray level by adjusting the duty ratio of the duration of the operating voltage Vg in each data signal. Exemplarily, taking the operating voltage Vg = 0V and the turn-off voltage Vd = 5V of the data signal, and the turn-on voltage Vk = 5V and the blanking voltage Vs = 3V of the first scan signal as an example, in an ideal situation, when the light-emitting diode emits light, the anode receives the turn-on voltage Vk, and the cathode receives the operating voltage Vg and is pulled to 1V, and the light-emitting diode emits light based on the voltage difference between the anode and the cathode (that is, 5V - 1V = 4V).

[0064] However, due to the existence of the parasitic capacitance C1 on the scan line 101, during the scanning process, the voltage waveform on the scan line 101 is not an ideal square wave, as Figure 2 shown Figure 2 respectively shows the voltage waveform of the first scan line 101 in an ideal state (represented by A in the figure) and the actual voltage waveform of the first scan line 101 in the existing display panel (represented by B in the figure). Specifically, at the scanning start time t1 of the first scan line 101, the first scan signal G1 changes from the blanking voltage Vs to the turn-on voltage Vk. At this time, it is necessary to charge the parasitic capacitance C1 of the first scan line 101. Therefore, the first scan line 101 needs to pass through the first delay time Δt1 to reach the turn-on voltage Vk. At the scanning end time t2 of the first scan line 101, the first scan signal G1 changes from the turn-on voltage Vk to the blanking voltage Vs. At this time, it is necessary to discharge the parasitic capacitance C1 of the first scan line 101. Therefore, the first scan line 101 needs to pass through the second delay time Δt2 to reach the blanking voltage Vs. Thus, when the second scan line 101 starts to scan, since the charge stored in the parasitic capacitance C1 of the first scan line 101 is not released in time, this will cause the voltage of the first scan line 101 to be higher than the blanking voltage Vs, resulting in the light-emitting diodes in the sub-pixel units P in the first row being slightly lit, thus generating upper ghosting.

[0065] In view of this, the present application provides an array substrate 1. Please refer to Figures 3 to 5 , Figures 3 to 4 which is a schematic diagram of the layered structure of the array substrate provided by the embodiment of the present application, Figure 5 and which is a cross-sectional view of the array substrate provided by the embodiment of the present application.

[0066] Among them, the array substrate 1 includes n rows of sub-pixel units P, n scan lines 101 electrically connected to the n rows of sub-pixel units P one by one, and m coupling lines 101s. The n scan lines 101 are used to receive corresponding first scan signals to perform row-by-row scanning on the n rows of sub-pixel units P. Among them, the voltage value of the first scan signal received by each scan line 101 starts to drop from the turn-on voltage Vk to the blanking voltage Vs at the end of the scan. n > 1, n ≥ m ≥ 1.

[0067] The m coupling lines 101s correspond to m scan lines 101 among the n scan lines 101 one by one. Each coupling line 101s is arranged in parallel with the corresponding scan line 101 to form a coupling capacitor Cs. Each coupling line 101s is used to receive a corresponding second scan signal to shorten the time for the voltage value of the corresponding scan line 101 to drop from the turn-on voltage Vk to the blanking voltage Vs after the scan ends through the coupling action of the corresponding coupling capacitor Cs. Among them, the voltage value of the second scan signal received by each coupling line 101s drops from the second voltage V2 to the first voltage V1 at the end of the scan of the scan line 101 corresponding to the coupling line 101s.

[0068] For the array substrate 1 provided by the present application, by arranging the coupling lines 101s parallel to the scan lines 101 to form a coupling capacitor Cs between the corresponding scan lines 101 and coupling lines 101s, and outputting the corresponding second scan signal to the coupling lines 101s, at the end of the scan of the scan line 101, the voltage of the coupling line 101s synchronously drops from the second voltage V2 to the first voltage V1, so that the stored charge of the parasitic capacitor C1 of the corresponding scan line 101 is quickly released through the coupling action of the corresponding coupling capacitor Cs, thereby shortening the time for the voltage value of the scan line 101 to drop from the turn-on voltage Vk to the blanking voltage Vs after the scan ends, and it is possible to avoid the sub-pixel units P of this row from emitting light erroneously due to the too high voltage of the scan line 101 of this row during the scanning of the next row scan line 101, and the problem of upper ghosting during the display of the MiniLED display screen can be solved.

[0069] In some embodiments, the second scan signal received by each coupling line 101s rises from the first voltage V1 to the second voltage V2 at the start of the scan of the scan line 101 corresponding to the coupling line 101s.

[0070] Exemplarily, please refer to Figure 6 , Figure 6 which is the second waveform diagram of the driving signal of the display panel provided by the embodiment of the present application, Figure 6 respectively showing the voltage waveform of the first scan line 101 in an ideal state (denoted by A in the figure), the actual voltage waveform of the first scan line 101 in the existing display panel (denoted by B in the figure), and the actual voltage waveform of the first scan line 101 in the array substrate 1 provided by the present application (denoted by C in the figure). As Figure 6 shown, at the scanning start moment t1 of the first scan line 101, the first scan signal G1 changes from the blanking voltage Vs to the turn-on voltage Vk, and the second scan signal G1s changes from the first voltage V1 to the second voltage V2, so that the voltage waveforms of the first scan line 101 and the first coupling line 101s rise simultaneously. Furthermore, through the coupling effect of the corresponding coupling capacitor Cs of the first coupling line 101s, the charging speed of the parasitic capacitor C1 of the first scan line 101 can be accelerated, and the time for the first scan line 101 to rise from the first voltage V1 to the second voltage V2 can be shortened (as Figure 6 shown, from the first delay time Δt1 to the third delay time Δt3). At the scanning end moment t2 of the first scan line 101, the first scan signal G1 changes from the turn-on voltage Vk to the blanking voltage Vs, and the second scan signal G1s changes from the second voltage V2 to the first voltage V1, so that the voltage waveforms of the first scan line 101 and the first coupling line 101s fall simultaneously. Furthermore, through the coupling effect of the corresponding coupling capacitor Cs of the first coupling line 101s, the discharging speed of the parasitic capacitor C1 of the first scan line 101 can be accelerated, and the time for the first scan line 101 to fall from the second voltage V2 to the first voltage V1 can be shortened (as Figure 6 shown, from the second delay time Δt2 to the fourth delay time Δt4). In this way, it is possible to avoid the first row of sub-pixel units P from emitting light erroneously due to the too high voltage of the first scan line 101 when the second scan line 101 is scanned, and the problem of upper ghosting of the first row of sub-pixel units P can be solved.

[0071] In some embodiments, the number of the coupling lines 101s is equal to the number of the scanning lines 101, that is, m = n, and one coupling line 101s is correspondingly arranged for each scanning line 101. In this way, the problem of upper ghosting can be avoided for any row of sub-pixel units P in the array substrate 1, and the display effect is optimal. In some other embodiments, the number of the coupling lines 101s can also be less than the number of the scanning lines 101, that is, the coupling lines 101s are arranged only for some of the n scanning lines 101, and no limitation is made here.

[0072] In some embodiments, the difference between the turn-on voltage Vk and the blanking voltage Vs is greater than or equal to the difference between the first voltage V1 and the second voltage V2, that is, Vk~Vs≥V2~V1.

[0073] Further, the second voltage V2 is less than or equal to the turn-on voltage Vk.

[0074] Exemplarily, when Vk = 5V, Vs = 3V, V2 = 2V, V1 = 1V, or V2 = 3V, V1 = 2V, or V2 = 4V, V1 = 3V, etc.

[0075] In this way, when each scanning line 101 is scanned, each coupling line 101s will not couple the voltage of the corresponding scanning line 101 to be higher than the turn-on voltage Vk, so that the light-emitting diode in the sub-pixel unit P can be prevented from having too high a light-emitting brightness due to too high a voltage between the anode and the cathode, and further the service life of the light-emitting diode can be prolonged.

[0076] In some embodiments, when the difference between the turn-on voltage Vk and the blanking voltage Vs is less than the difference between the first voltage V1 and the second voltage V2, that is, Vk~Vs<V2~V1, in order to reduce the coupling effect of the coupling lines 101s on the corresponding scanning lines 101, it can be set that the waveform of the second scanning signal received by each coupling line 101s is in a stepped increasing shape, or a linearly increasing shape, or a non-linearly increasing shape (such as Figure 7 shown).

[0077] Such as Figure 3 shown, in some embodiments, the array substrate 1 includes a substrate 11, a first conductor layer 12, an insulating layer (not shown in the figure), and a second conductor layer 13 formed in sequence on the substrate 11. Among them, the m coupling lines 101s are located in the first conductor layer 12, and the n scanning lines 101 are located in the second conductor layer 13.

[0078] Further, the projection of each of the coupling lines 101s on the substrate 11 coincides at least partially with the projection of the corresponding scanning line 101 of the coupling line 101s on the substrate 11. Preferably, the projection of each of the coupling lines 101s on the substrate 11 coincides completely with the projection of the corresponding scanning line 101 of the coupling line 101s on the substrate 11. In this way, the capacitance value of the coupling capacitance Cs between each of the coupling lines 101s and the corresponding scanning line 101 is larger, and the coupling effect is stronger.

[0079] The m coupling lines 101s and the n scanning lines 101 can be selected from one or more of metals such as molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), etc., or one or more of alloys formed by any combination of the above metals, or formed of other suitable materials.

[0080] Among them, the second conductor layer 13 may include a first metal layer M1 (not shown in the figure), a gate insulating layer Gi / A_SI (not shown in the figure), an active layer (not shown in the figure), and a second metal layer M2 (not shown in the figure) stacked in sequence. Among them, the n scanning lines 101 are located in the first metal layer M1, and the x data lines 102 are located in the second metal layer M2.

[0081] In some embodiments, the array substrate 1 further includes an LED layer, and the LED layer is provided with the n rows of sub-pixel units P. Among them, each sub-pixel unit P may include a cathode (not shown in the figure), a light-emitting layer (not shown in the figure), and an anode (not shown in the figure) stacked in sequence along the thickness direction of the array substrate 1. Among them, the anodes of the sub-pixel units P in the same row are all electrically connected to the corresponding scanning line 101, and the cathodes of the sub-pixel units P in the same column are all electrically connected to the corresponding data line 102.

[0082] Among them, the n rows of sub-pixel units P may include R sub-pixel units, G sub-pixel units, and B sub-pixel units. The light-emitting layer in the R sub-pixel unit is used to emit red light, the light-emitting layer in the G sub-pixel unit is used to emit green light, and the light-emitting layer in the B sub-pixel unit is used to emit blue light. The light-emitting layer may be an organic light-emitting layer or an inorganic light-emitting layer such as a nano-sized material layer, a quantum dot light-emitting layer, a micro LED layer, or a mini LED layer, but is not limited thereto. The light-emitting layer may not only include a light-emitting material layer, but may also include an electron injection layer and a hole injection layer for respectively injecting electrons and holes into the light-emitting material layer, an electron transport layer and a hole blocking layer for transporting the injected electrons to the light-emitting material layer, and an electron blocking layer and a hole transport layer for transporting the injected holes to the light-emitting material layer, but is not limited thereto.

[0083] In some embodiments, the array substrate 1 further includes an anti-glare protection layer 15 disposed on the light-emitting side of the LED layer.

[0084] In other embodiments, it may also be that the n scanning lines 101 are located in the first conductor layer 12, and the m coupling lines 101s are located in the second conductor layer 13, that is, the m coupling lines 101s are located on the side away from the substrate 11 of the layer where the n scanning lines 101 are located.

[0085] In other embodiments, the m coupling lines 101s and the n scanning lines 101 may also be located in the same layer. Among them, the distance between each coupling line 101s and the corresponding scanning line 101 is much smaller than the distance between the coupling line 101s and another adjacent scanning line 101. In this way, the capacitance value of the parasitic capacitance between the coupling line 101s and another adjacent scanning line 101 can be ignored.

[0086] Please refer to again Figures 3 to 4 , based on the same inventive concept, the present application further provides a display panel 100, and the display panel 100 includes a row driver 202 and the array substrate 1 described above.

[0087] Among them, it is used to output n first scanning signals and m second scanning signals.

[0088] The n scanning lines 101 and the m coupling lines 101s of the array substrate 1 both include opposite first ends and second ends. The first ends of the n scanning lines 101 and the first ends of the m coupling lines 101s are both electrically connected to the row driver 202. The n scanning lines 101 are used to receive the corresponding first scanning signals from the row driver 202 through the first ends, and the m coupling lines 101s are used to receive the corresponding second scanning signals from the row driver 202 through the first ends.

[0089] In some embodiments, the display panel 100 further includes the timing controller 201 and the column driver 203 described above, which will not be elaborated here.

[0090] The display panel includes an Organic Light Emitting Display (OLED) panel, a Light-Emitting Diode (LED) display panel, a Micro Light-Emitting Diode (Micro-LED) display panel, or a Mini Light-Emitting Diode (Mini-LED), etc. The display panel can be applied to electronic devices with display functions such as mobile phones, tablet computers, notebooks, game consoles, digital cameras, vehicle navigation devices, electronic billboards, and automated teller machines.

[0091] For the display panel 100 provided in this application, by setting a coupling line 101s parallel to the corresponding scanning line 101 on the array substrate 1 to form a coupling capacitance Cs between the corresponding scanning line 101 and the coupling line 101s, and outputting a corresponding second scanning signal to the coupling line 101s, such that at the end of the scan of the scanning line 101, the voltage of the coupling line 101s synchronously drops from the second voltage V2 to the first voltage V1, thereby quickly discharging the stored charge of the parasitic capacitance C1 of the corresponding scanning line 101 through the coupling action of the corresponding coupling capacitance Cs, and further shortening the time for the voltage value of the scanning line 101 to drop from the turn-on voltage Vk to the blanking voltage Vs after the scan ends. This can avoid the problem that the sub-pixel unit P of this row emits light erroneously due to the too-high voltage of the scanning line 101 of this row when the next row of scanning line 101 is scanned, and can solve the problem of upper ghosting in the MiniLED display screen during display.

[0092] Please refer to Figures 8 to 9 , this application also provides a method for repairing a broken scanning line of a display panel. Figure 8 is a flowchart of the method for repairing a broken scanning line of the display panel provided in the embodiments of this application; Figure 9 is a schematic diagram of the repair process of the method for repairing a broken scanning line of the display panel provided in the embodiments of this application. The repair method is applied to the display panel 100 described above.

[0093] The repair method includes the following steps:

[0094] Step 610, when a break occurs in the scanning line 101 corresponding to any coupling line 101s in the display panel 100, find the position of the break.

[0095] Step 620, electrically connect the part between the break point and the second end of the broken scanning line 101 to the coupling line 101s corresponding to the broken scanning line 101.

[0096] Exemplarily, as Figure 9As shown, when there is a break in the first scan line 101 in the display panel 100, the portion between the break point of the first scan line 101 and the second end is electrically connected to the first coupling line 101s by means of silver paste dots. In this way, during the display process of the display panel 100, the line driver 202 can continue to output the corresponding first scan signal to the first row of sub-pixel units P through the first coupling line 101s, thereby fixing the problem that the first row of sub-pixel units P cannot be displayed due to the break in the first scan line 101. It should be noted that after repairing using the above repair method, the problem of upper ghosting of the first row of sub-pixel units P cannot be solved. However, for the overall display effect and product cost, the ghosting of a single row is difficult to observe by the human eye, and it can be avoided that the product is scrapped due to the dark line caused by a non-lit row, which can improve the yield rate during the product production process and reduce the production cost.

[0097] In some embodiments, the repair method may further include: completely cutting off the broken scan line 101 from the break point. In this way, short circuits caused by virtual breaks can be avoided.

[0098] In some embodiments, the repair method may further include: cutting off the portion of the connection point of the target coupling line 101s that is far from the first end. Wherein, the target coupling line 101s is the coupling line 101s corresponding to the broken scan line 101, and the connection point is the position point where the target coupling line 101s is connected to the portion between the break point of the broken scan line 101 and the second end. In this way, when the corresponding first scan signal is output to the first row of sub-pixel units P through the first coupling line 101s, the line impedance can be reduced, and thus the loss of the first scan signal during transmission can be reduced.

[0099] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. An array substrate, comprising n rows of sub-pixel units, and n scanning lines electrically connected to the n rows of sub-pixel units in a one-to-one correspondence, wherein the n scanning lines are used to receive corresponding first scanning signals to scan the n rows of sub-pixel units row by row; wherein: The voltage value of the first scanning signal received by each of the scanning lines starts to drop from the start voltage to the blanking voltage at the scanning termination time, and n>1; characterized in that the array substrate further includes x data lines, and the n rows of sub-pixel units are defined by the intersection of the n scanning lines and the x data lines; each sub-pixel unit includes a light-emitting diode, an anode of the light-emitting diode is electrically connected to the corresponding scanning line to receive the first scanning signal, and a cathode of the light-emitting diode is electrically connected to the corresponding data line to receive the data signal, and the light-emitting diode emits light based on the received first scanning signal and the data signal; The array substrate further includes m coupling lines, the m coupling lines correspond to m scanning lines among the n scanning lines one by one, each of the coupling lines is arranged in parallel with the corresponding scanning line to form a coupling capacitor, and each of the coupling lines is used to receive a corresponding second scanning signal, so as to shorten the time for the voltage value of the corresponding scanning line to drop from the start voltage to the blanking voltage after the scanning is completed through the coupling effect of the corresponding coupling capacitor; wherein n≥m≥1, the voltage value of the second scanning signal received by each of the coupling lines drops from the second voltage to the first voltage at the scanning termination moment of the scanning line corresponding to the coupling line; A difference between the turn-on voltage and the blanking voltage is greater than or equal to a difference between the first voltage and the second voltage.

2. The array substrate according to claim 1, characterized in that: The number of the coupling lines is equal to the number of the scanning lines.

3. The array substrate according to claim 2, characterized in that: The second voltage is less than or equal to the turn-on voltage.

4. The array substrate according to claim 1, wherein: The second scanning signal received by each of the coupling lines starts to rise from the first voltage to the second voltage at a scanning start time of the scanning line corresponding to the coupling line.

5. The array substrate according to claim 4, characterized in that: The waveform of the second scanning signal received by each of the coupling lines in the process of rising from the first voltage to the second voltage is in a step-increasing shape, a linear increasing shape, or a nonlinear increasing shape.

6. The array substrate according to claim 1, characterized in that: The array substrate includes a substrate, a first conductor layer, an insulating layer and a second conductor layer formed in sequence on the substrate; wherein the n scanning lines are located in the first conductor layer, and the m coupling lines are located in the second conductor layer, or the m coupling lines are located in the first conductor layer, and the n scanning lines are located in the second conductor layer.

7. The array substrate according to claim 6, characterized in that: A projection of each of the coupling lines on the substrate at least partially overlaps with a projection of a scanning line corresponding to the coupling line on the substrate.

8. A display panel, characterized in that: The display panel comprises: a row driver, configured to output n first scanning signals and m second scanning signals; and According to the array substrate as described in any one of claims 1 to 7, the n scan lines and m coupling lines of the array substrate each include a first end and a second end opposite to each other, the first ends of the n scan lines and the first ends of the m coupling lines are both electrically connected to the row driver, the n scan lines are used to receive the corresponding first scan signals from the row driver through the first ends, and the m coupling lines are used to receive the corresponding second scan signals from the row driver through the first ends.

9. A method for repairing a broken scan line of a display panel, characterized in that: Applied to the display panel according to claim 8, the repair method comprises: When a breakpoint appears in a scan line corresponding to any coupling line in the display panel, finding the position of the breakpoint; and A portion between a breakpoint and the second end of the broken scan line is electrically connected to a coupling line corresponding to the broken scan line.

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