Charging line data decoding circuit, method, on-chip charging line system and electronic device

Abstract

The present invention provides a charging line data decoding circuit, a charging line data decoding method and an electronic device. The circuit compares the voltage value of an original protocol data signal with the voltage value of each reference voltage in real time through a first comparison module, outputs a first comparison signal when the original protocol data signal is at a high level, and a digital control module determines a down-flip threshold of the original protocol data signal according to the first comparison signal; outputs a second comparison signal when the original protocol data signal is at a low level; the digital control module determines an up-flip threshold of the original protocol data signal according to the second comparison signal, and the digital control module outputs a flip threshold adjustment signal according to the determined down-flip threshold and up-flip threshold, and a decoding module performs data decoding on the original protocol data signal according to the flip threshold adjustment signal. Thus, the present invention can adaptively adjust the detection threshold of the decoding circuit to avoid errors in decoding the data signal.

Description

Technical Field

[0001] The present invention relates to the field of USB charging technology, and in particular to a charging line data decoding circuit, a charging line data decoding method, an on-chip charging line system and an electronic device. Background Art

[0002] The device motherboard usually communicates with external devices via USB. The coding methods used in the communication process may include BMC (Biphase Mark Coding) and the like, or other coding methods of the charging line PD fast charging protocol may be used.

[0003] In the process of current device mainboard communicating with external devices, when the charging current is large, the line resistance of the USB cable will cause the power ground to be raised, thereby causing the low level of the received data signal to be raised. When the detection threshold of the subsequent decoding circuit is fixed, it will cause errors in decoding the data signal.

[0004] Therefore, how to adaptively adjust the detection threshold of the decoding circuit to avoid errors in decoding the data signal has become a technical problem that urgently needs to be solved in the industry. Summary of the invention

[0005] The present invention provides a charging line data decoding circuit, a charging line data decoding method, an on-chip charging line system and an electronic device to solve the problem of how to adaptively adjust the detection threshold of the decoding circuit to avoid errors in decoding of data signals.

[0006] According to a first aspect of the present invention, there is provided a charging line data decoding circuit, comprising: a first comparison module, a digital control module, a decoding module and a latch;

[0007] The first comparison module includes N comparators, the inverting receiving end of each comparator receives a corresponding reference voltage, the inverting receiving end of each comparator receives the original protocol data signal, the output end of each comparator is coupled to the input end of the digital control module, the output end of the digital control module is coupled to the first input end of the decoding module, the second input end of the decoding module receives the original protocol data signal, and the output end of the decoding module outputs a decoded data signal through the latch; wherein N is an integer greater than or equal to 6;

[0008] The first comparison module is used to compare the voltage value of the original protocol data signal with the voltage value of the reference voltage corresponding to each comparator in real time, and output a first comparison signal to the digital control module when the original protocol data signal jumps from a low level to a high level, and output a second comparison signal to the digital control module when the original protocol data signal jumps from a high level to a low level, wherein the first comparison signal and the second comparison signal both include the comparison result between the voltage value of the original protocol data signal and the voltage value of the reference voltage corresponding to each comparator;

[0009] The digital control module is used to determine the down-flip threshold and the up-flip threshold of the original protocol data signal according to the first comparison signal and the second comparison signal, and output a flip threshold adjustment signal to the decoding module;

[0010] The decoding module is used to perform data decoding on the original protocol data signal according to the flip threshold adjustment signal.

[0011] Optionally, the number of comparators is determined according to the original high level, original low level, maximum low level and detection accuracy of the original protocol data signal, and the calculation formula of the number of comparators N is:

[0012]

[0013] Wherein, V1 is the original high level voltage value of the original protocol data signal, V2 is the original low level voltage value of the original protocol data signal, V3 is the maximum low level voltage value of the original protocol data signal, and V4 is the voltage value of the detection accuracy;

[0014] in, The result is an integer rounded up.

[0015] Optionally, the reference voltage received by the jth comparator is:

[0016] VREF j-1 =V2+j×V4

[0017] Wherein, j is an integer, and 1≤j≤N.

[0018] The reference voltage received by the i-th comparator is less than or equal to the original high level voltage value of the original protocol data signal, and the reference voltage received by the i+1-th comparator is greater than the original high level voltage value of the original protocol data signal; wherein i is an integer, and 1 <i<N。

[0019] Optionally, determining an up-flip threshold and a down-flip threshold of the original protocol data signal according to the first comparison signal and the second comparison signal includes:

[0020] Determine a down-turn threshold of the original protocol data signal according to the signals output by the i-th comparator to the N-th comparator in the first comparison signal;

[0021] If there is a signal outputted from the kth comparator to the mth comparator that jumps from a low level signal to a high level signal, the down-flip threshold of the original protocol data signal increases by a first voltage, where the first voltage is the difference between a reference voltage corresponding to the mth comparator and a reference voltage corresponding to the ith comparator, k and m are both integers, and i≤k, k≤m, m≤N;

[0022] Determine the up-turn threshold of the original protocol data signal according to the signals output by the 1st comparator to the (i+1)th comparator in the second comparison signal;

[0023] If the signal output by the pth comparator to the qth comparator jumps from a high-level signal to a low-level signal, the up-flip threshold of the original protocol data signal is increased by a second voltage, and the second voltage is the difference between the reference voltage corresponding to the qth comparator and the reference voltage corresponding to the first comparator, p and q are both integers, and 1≤q, q≤p, p≤i+1.

[0024] Optionally, the flip threshold adjustment signal includes an up flip threshold adjustment signal and a down flip threshold adjustment signal;

[0025] The decoding module includes an up-flip threshold adjustment unit, a down-flip threshold adjustment unit, a first decoding comparator and a second decoding comparator;

[0026] The input end of the down-turn threshold adjustment unit receives the down-turn threshold adjustment signal, and the output end thereof is coupled to the inverting input end of the first decoding comparator, and outputs the down-turn threshold voltage corresponding to the original protocol data signal; the non-inverting input end of the first decoding comparator receives the original protocol data signal, and the output end thereof is coupled to the first input end of the latch;

[0027] The input end of the up-flip threshold adjustment unit receives the up-flip threshold adjustment signal, and the output end thereof is coupled to the inverting input end of the second decoding comparator, and outputs the up-flip threshold voltage corresponding to the original protocol data signal; the non-inverting input end of the second decoding comparator receives the original protocol data signal, and the output end thereof is coupled to the second input end of the latch.

[0028] Optionally, the latch is an RS latch.

[0029] According to a second aspect of the present invention, there is provided an on-chip charging line system, comprising the charging line data decoding circuit according to the first aspect of the present invention.

[0030] Optionally, the original protocol data signal is a charging line signal.

[0031] According to a third aspect of the present invention, there is provided an electronic device, comprising the charging line data decoding circuit according to the first aspect of the present invention.

[0032] According to a fourth aspect of the present invention, a charging line data decoding method is provided, wherein the charging line data decoding circuit according to the first aspect of the present invention is used to decode the original protocol data signal, and the method comprises:

[0033] Compare the voltage value of the original protocol data signal with the voltage value of the reference voltage corresponding to each comparator in real time, and output a first comparison signal to the digital control module when the original protocol data signal jumps from a low level to a high level, and output a second comparison signal to the digital control module when the original protocol data signal jumps from a high level to a low level, wherein the first comparison signal and the second comparison signal both include comparison results between the voltage value of the original protocol data signal and the voltage value of the reference voltage corresponding to each comparator;

[0034] Determine a down-turn threshold and an up-turn threshold of the original protocol data signal according to the first comparison signal and the second comparison signal, and output a turn-over threshold adjustment signal to the decoding module;

[0035] The original protocol data signal is decoded according to the flip threshold adjustment signal.

[0036] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0037] In the charging line data decoding circuit, charging line data decoding method and electronic device provided by the technical solution of the present invention, the circuit compares the voltage value of the original protocol data signal with the voltage value of each reference voltage in real time through a first comparison module, outputs a first comparison signal when the original protocol data signal is at a high level, and the digital control module determines the down-flip threshold of the original protocol data signal according to the first comparison signal; outputs a second comparison signal when the original protocol data signal is at a low level; the digital control module determines the up-flip threshold of the original protocol data signal according to the second comparison signal, the digital control module outputs a flip threshold adjustment signal based on the determined down-flip threshold and up-flip threshold, and the decoding module decodes the original protocol data signal according to the flip threshold adjustment signal, so that the present invention can adaptively adjust the detection threshold of the decoding circuit to avoid errors in decoding the data signal.

[0038] In the on-chip charging line system provided by the technical solution of the present invention, the system utilizes the charging line data decoding circuit provided by the technical solution of the present invention to parse the charging line signal, so that when the charging line current is large, the detection threshold of the decoding circuit is adaptively adjusted to avoid errors in decoding the charging line signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0040] Figure 1 is a schematic diagram of the structure of a charging line data decoding circuit in one embodiment of the present invention;

[0041] Figure 2 is a schematic diagram of the structure of a charging line data decoding circuit in another embodiment of the present invention

[0042] Figure 3 yes Figure 2 Schematic diagram of the waveform of the original protocol data signal and the corresponding output waveform of each comparator Figure 1 ;

[0043] Figure 4 yes Figure 2 Schematic diagram of the waveform of the original protocol data signal and the corresponding output waveform of each comparator Figure 2 ;

[0044] Figure 5 is a schematic structural diagram of a charging line data decoding circuit in yet another embodiment of the present invention;

[0045] Figure 6 It is a flowchart of a charging line data decoding method in one embodiment of the present invention.

[0046] Description of reference numerals:

[0047] 10- a first comparison module;

[0048] 20- Digital control module;

[0049] 30-decoding module;

[0050] 301-upward flip threshold adjustment unit;

[0051] 302-downward flip threshold adjustment unit;

[0052] 303-first decoding comparator;

[0053] 304-second decoding comparator;

[0054] 40- latch;

[0055] CMP - Comparator;

[0056] data_in-original protocol data signal;

[0057] data_out-decoded data signal;

[0058] verfl-down flip threshold voltage;

[0059] verfh - flip-up threshold voltage. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0062] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0063] In view of the fact that it is difficult to adaptively adjust the detection threshold of the decoding circuit in the prior art to avoid errors in decoding the data signal, the present invention provides a charging line data decoding circuit, which compares the voltage value of the original protocol data signal with the voltage value of each reference voltage in real time through a first comparison module, outputs a first comparison signal when the original protocol data signal is at a high level, and the digital control module determines the down-flip threshold of the original protocol data signal according to the first comparison signal; outputs a second comparison signal when the original protocol data signal is at a low level; the digital control module determines the up-flip threshold of the original protocol data signal according to the second comparison signal, and the digital control module outputs a flip threshold adjustment signal according to the determined down-flip threshold and up-flip threshold, and the decoding module decodes the original protocol data signal according to the flip threshold adjustment signal, so that the present invention can adaptively adjust the detection threshold of the decoding circuit to avoid errors in decoding the data signal.

[0064] Regarding the solution of the present invention, the specific description is as follows:

[0065] Please refer to Figure 1 , the present invention provides a charging line data decoding circuit, comprising: a first comparison module 10, a digital control module 20, a decoding module 30 and a latch 40;

[0066] The first comparison module 10 includes N comparators CMP, the inverting receiving end of each comparator CMP receives the corresponding reference voltage VREF, the inverting receiving end of each comparator CMP receives the original protocol data signal data_in, the output end of each comparator CMP is coupled to the input end of the digital control module 20, the output end of the digital control module 20 is coupled to the first input end of the decoding module 30, the second input end of the decoding module 30 receives the original protocol data signal data_in, and the output end of the decoding module 30 outputs the decoded data signal data_out through the latch 40; wherein N is an integer greater than or equal to 6;

[0067] The first comparison module 10 is used to compare the voltage value of the original protocol data signal data_in with the voltage value of the reference voltage VREF corresponding to each comparator CMP in real time, and output a first comparison signal to the digital control module 20 when the original protocol data signal data_in jumps from a low level to a high level, and output a second comparison signal to the digital control module 20 when the original protocol data signal data_in jumps from a high level to a low level, and the first comparison signal and the second comparison signal both include a comparison result cmp of the voltage value of the original protocol data signal data_in and the voltage value of the reference voltage VREF corresponding to each comparator CMP <n-1:0>;

[0068] The digital control module 20 is used to determine the down-turn threshold and the up-turn threshold of the original protocol data signal data_in according to the first comparison signal and the second comparison signal, and output a turn-over threshold adjustment signal to the decoding module 30;

[0069] The decoding module 30 is used to perform data decoding on the original protocol data signal data_in according to the flip threshold adjustment signal.

[0070] The down-turn threshold can be understood as the minimum voltage value that the original protocol data signal data_in must exceed when changing from a low level to a high level;

[0071] The up-turn threshold is the maximum voltage value below which the original protocol data signal data_in must drop when changing from a high level to a low level.

[0072] As an example, the latch 40 is an RS latch. Of course, the present invention is not limited to this, and other latches, such as a JK latch, etc., may also be used according to circuit requirements.

[0073] In one implementation, the number of the comparators CMP is determined based on the original high level, original low level, maximum low level and detection accuracy of the original protocol data signal data_in. The calculation formula for the number of comparators N is:

[0074]

[0075] Wherein, V1 is the original high level voltage value of the original protocol data signal, V2 is the original low level voltage value of the original protocol data signal, V3 is the maximum low level voltage value of the original protocol data signal, and V4 is the voltage value of the detection accuracy;

[0076] in, The result is an integer rounded up.

[0077] The maximum low-level voltage value may be understood as the maximum voltage value to which the ground level of the original protocol data signal data_in can be raised.

[0078] For example, if the original high level of the original protocol data signal data_in is 1.1V, the original low level is 0V, the maximum value that the power ground can be raised is 1V, and the detection accuracy is 0.3V, then according to the calculation formula, the number of comparators CMP is set to 6 to achieve detection; and the number of comparators CMP is set to 6 or more to effectively ensure the detection quality and decoding quality;

[0079] If the original high level of the original protocol data signal data_in is 1.2V, the original low level is 0V, the maximum value that the power ground can be raised is 1V, and the detection accuracy is 0.3V, then according to the calculation formula, The result is approximately equal to 7.3, which is rounded up to 8. The corresponding number of comparators CMP is set to 7 to achieve detection.

[0080] In one implementation, the reference voltage received by the jth comparator is:

[0081] VREF j-1 =V2+j×V4

[0082] Wherein, j is an integer, and 1≤j≤N.

[0083] The reference voltage VREF received by the i-th comparator CMP(i-1) is less than or equal to the maximum low level voltage value of the original protocol data signal data_in, and the reference voltage VREF received by the i+1-th comparator CMP(i) is greater than the maximum low level voltage value of the original protocol data signal data_in; wherein i is an integer, and 1 <i<N。

[0084] In this case, determining the up-turn threshold and the down-turn threshold of the original protocol data signal data_in according to the first comparison signal and the second comparison signal includes:

[0085] Determine a down-turn threshold of the original protocol data signal according to the signals output by the i-th comparator CMP(i-1) to the N-th comparator CMP(N-1) in the first comparison signal;

[0086] If the first comparison signal represents that among the signals output by the i-th comparator CMP(i-1) to the N-th comparator CMP(N-1), there is a signal output by the k-th comparator CMP(k-1) to the m-th comparator CMP(m-1) that jumps from a low-level signal to a high-level signal, then the downward flip threshold of the original protocol data signal data_in increases by a first voltage, and the first voltage is the difference between the reference voltage VREF(m-1) corresponding to the m-th comparator CMP(m-1) and the reference voltage VREF(i-1) corresponding to the i-th comparator CMP(i-1), k and m are both integers, and i≤k, k≤m, m≤N;

[0087] Determine the up-turn threshold of the original protocol data signal according to the signals output by the 1st comparator to the (i+1)th comparator in the second comparison signal;

[0088] If the signal output by the pth comparator CMP(p-1) to the qth comparator CMP(q-1) jumps from a high-level signal to a low-level signal, the up-flip threshold of the original protocol data signal data_in increases by a second voltage, and the second voltage is the difference between the reference voltage VREF(q-1) corresponding to the qth comparator CMP(q-1) and the reference voltage VREF0 corresponding to the first comparator CMP0, p and q are both integers, and 1≤q, q≤p, p≤i+1.

[0089] Therefore, the embodiment of the present invention can prevent the power supply from changing when the signal is at a high level and affecting the decoding result by detecting the corresponding flip threshold value at the rising edge and the falling edge of the signal respectively.

[0090] Of course, adjusting the number of comparators CMP and the flip threshold can achieve higher accuracy and wider range of detection of the raised voltage, so that the signal error after the charging line data is decoded is smaller. As an example, the charging line data can include BMC protocol data and the like.

[0091] The first comparison signal and the second comparison signal are now described in conjunction with specific implementations:

[0092] In a specific implementation, the original high level of the original protocol data signal data_in is 1.1V, and the original low level is 0V. When the power ground is raised, the high level and low level of the original protocol data signal data_in will be raised at the same time. It is now stipulated that the maximum value of the power ground that can be raised is 1V, and the detection accuracy is 0.3V. Please refer to Figure 2 The charging line data decoding circuit shown in the figure now takes the first comparison module 10 including 6 comparators CMP as an example to illustrate the working process of the charging line data decoding circuit provided by the embodiment of the present invention:

[0093] exist Figure 2 In the example shown, the reference voltage VREF0 received by the first comparator CMP0 is 0.3V;

[0094] The reference voltage VREF1 received by the second comparator CMP1 is 0.6V;

[0095] The reference voltage VREF2 received by the third comparator CMP2 is 0.9V;

[0096] The reference voltage VREF3 received by the fourth comparator CMP3 is 1.2V;

[0097] The reference voltage VREF4 received by the fifth comparator CMP4 is 1.5V;

[0098] The reference voltage VREF5 received by the sixth comparator CMP5 is 1.8V.

[0099] In this case, please continue to refer to Figure 3 as well as Figure 4 The waveform shown is Figure 2 The working process of the charging line data decoding circuit shown is further explained:

[0100] Figure 3 When the power ground of the original protocol data signal data_in is not raised, the original protocol data signal data_in ( Figure 3 1) and the waveform diagram of the output results of each comparator CMP in the first comparison module 10. Figure 3 In the example shown, the high level of the original protocol data signal data_in is 1.1V, and the low level is 0V;

[0101] Figure 4 When the power ground of the original protocol data signal data_in is raised by 1V, the original protocol data signal data_in ( Figure 4 The waveform diagram of data2) corresponds to the waveform diagram of the output result of each comparator CMP in the first comparison module 10. Figure 4 In the example shown, the high level of the original protocol data signal data_in is 2.1V, and the low level is 1V; where:

[0102] Data1 can be understood as the waveform of the original protocol data signal data_in when the power ground of the original protocol data signal data_in is not raised;

[0103] Data2 can be understood as the waveform of the original protocol data signal data_in when the power ground of the original protocol data signal data_in is raised by 1V;

[0104] cmp <0> , which can be understood as the output waveform of the first comparator CMP0;

[0105] cmp <1> , which can be understood as the output waveform of the second comparator CMP1;

[0106] cmp <2> , which can be understood as the output waveform of the third comparator CMP2;

[0107] cmp <3> , which can be understood as the output waveform of the fourth comparator CMP3;

[0108] cmp <4> , which can be understood as the output waveform of the fifth comparator CMP4;

[0109] cmp <5> , which can be understood as the output waveform of the sixth comparator CMP5.

[0110] Please refer to Figure 3 When Data1 is at a rising edge, the digital control module 20 can latch the down flip threshold vrefl0, where vrefl0 represents the value of the original down flip threshold. Figure 3 In the example of FIG. 1 , the value of the original down-turn threshold is the same as the reference voltage VREF2 received by the third comparator CMP2 ;

[0111] Figure 3 In the waveform diagram shown, the first comparison signal is characterized by the comparator cmp<5:3> being always at a low level and not triggered, and the signal output by the first comparator CMP0 to the signal output by the third comparator CMP2 are successively changed from a low level signal to a high level signal, which indicates that the down-turn threshold of the original protocol data signal data_in is the same as its original down-turn threshold;

[0112] Specifically, it can be considered that the digital control module 20 updates the down-flip threshold value to vrefl0 when the output of the third comparator CMP2 outputs a rising edge, determines the down-flip threshold value to be vrefl0 when the output of the fourth comparator CMP3 remains at a low level, and maintains the down-flip threshold value control signal at vrefl0 before the next rising edge of the original protocol data signal data_in arrives.

[0113] When Data1 is at a falling edge, the digital control module 20 has latched the up-flip threshold vrefh0, where vrefh0 represents the value of the original up-flip threshold. Figure 3 In the example, the value of the original down-turn threshold is the same as the reference voltage VREF0 received by the first comparator CMP0;

[0114] Figure 3 In the waveform diagram shown, the signal output by the third comparator CMP2 to the signal output by the first comparator CMP0 sequentially jumps from a high-level signal to a low-level signal, indicating that the down-turn threshold of the original protocol data signal data_in is the same as its original down-turn threshold;

[0115] In a specific implementation manner, the digital control module 20 updates the value of the up-flip threshold rise correspondingly when the third comparator CMP2 to the first comparator CMP0 output falling edges in sequence, until the first comparator CMP0 outputs a falling edge, the digital control module 20 latches the up-flip threshold control signal vrefh0;

[0116] Specifically, the digital control module 20 updates the up-flip threshold value to vrefh0+0.6V when the third comparator CMP2 outputs a falling edge;

[0117] When the second comparator CMP1 outputs a falling edge, the up-flip threshold is updated to vrefh0+0.3V;

[0118] When the first comparator CMP0 outputs a falling edge, the up-flip threshold is updated to vrefh0, and the up-flip threshold is kept at vrefh0 before the next falling edge of the original protocol data signal data_in arrives.

[0119] Please refer to Figure 4 When Data1 is at a rising edge, the digital control module 20 latches the down-flip threshold vrefl0, where vrefl0 represents the value of the original down-flip threshold. Figure 4 In the example of FIG. 1 , the value of the original down-turn threshold is the same as the reference voltage VREF2 received by the third comparator CMP2 ;

[0120] Figure 4 In the waveform diagram shown, the first comparison signal is characterized by the signal output by the third comparator CMP2 being kept at a high level, and the signal output by the fourth comparator CMP3 to the signal output by the sixth comparator CMP5 are successively changed from a low level signal to a high level signal, which indicates that the down-turn threshold of the original protocol data signal data_in is increased by 0.9V;

[0121] In a specific implementation manner, the digital control module 20 updates the increased value of the down-turn threshold value when the fourth comparator CMP3 to the sixth comparator CMP5 output rising edges in sequence, until the sixth comparator CMP5 outputs a falling edge, the digital control module 20 latches the down-turn threshold value vrefl0+0.9V;

[0122] Specifically, the digital control module 20 updates the down-turn threshold value to vrefl0+0.3V when the fourth comparator CMP3 outputs a rising edge;

[0123] When the output of the fifth comparator CMP4 rises, the down-flip threshold is updated to vrefl0+0.6V;

[0124] When the sixth comparator CMP5 outputs a rising edge, the down-turn threshold is updated to vrefl0+0.9V, and the down-turn threshold control signal is kept at vrefl0+0.9V before the next rising or falling edge of the original protocol data signal data_in arrives.

[0125] Figure 4 In the waveform diagram shown, the signal output by the sixth comparator CMP5 to the signal output by the fourth comparator CMP3 successively jumps from a high level signal to a low level signal, indicating that the up-turn threshold of the original protocol data signal data_in is vrefh0+0.9V;

[0126] In a specific implementation, the digital control module 20 directly determines the up-flip threshold value as vrefh0+0.9V based on the output of the third comparator CMP2 maintaining a high level, and the output of the fourth comparator CMP3 at a falling edge, and the up-flip threshold value is maintained at vrefh0+0.9V before the next falling edge of the original protocol data signal data_in arrives.

[0127] In a preferred embodiment, the number of comparators may be increased to obtain more accurate voltage raising values ​​of the up-flip threshold and the down-flip threshold.

[0128] In other embodiments, if the first comparison signal indicates that the i-th comparator CMP(i-1) to the N-th comparator CMP(N-1) all maintain output as a low level signal, it indicates that the lower flip threshold is raised to exceed the difference between the N-th comparator CMP(N-1) and the reference voltage VREF corresponding to the i-th comparator CMP(i-1). At this time, the circuit cannot be decoded. In this case, it is necessary to set the comparator CMP threshold according to the actual situation of the ground being raised. For example, the inverting receiving end of the i+1-th comparator CMP(i) to the N-th comparator CMP(N-1) can be controlled to receive the corresponding reference voltage VREF increased by a first set value to re-find a new lower flip threshold;

[0129] Similarly, if the second comparison signal represents that the signals output by the first comparator CMP0 to the i+1th comparator CMP(i) all remain high-level signals, it indicates that the circuit cannot decode the current up-flip threshold. In this case, it is necessary to set the comparator CMP threshold according to the actual situation that the ground is raised. For example, the inverting receiving end of the second comparator CMP1 to the i+1th comparator CMP(i) can be controlled to receive the corresponding reference voltage VREF increased by the second set value to re-search for a new up-flip threshold.

[0130] After determining the new up-flip threshold and down-flip threshold, the digital control module 20 can output a flip threshold adjustment signal to the decoding module 30. In one implementation, please refer to Figure 5 , the flip threshold adjustment signal includes an upper flip threshold adjustment signal verfh_ctrl and a lower flip threshold adjustment signal verfl_ctrl;

[0131] The decoding module 30 includes an up-turn threshold adjustment unit 301, a down-turn threshold adjustment unit 302, a first decoding comparator 303 and a second decoding comparator 304;

[0132] The input end of the down-turn threshold adjustment unit 302 receives the down-turn threshold adjustment signal verfl_ctrl, and the output end thereof is coupled to the inverting input end of the first decoding comparator 303, and outputs the down-turn threshold voltage verfl corresponding to the original protocol data signal data_in; the non-inverting input end of the first decoding comparator 303 receives the original protocol data signal data_in, and the output end thereof is coupled to the first input end of the latch 40;

[0133] The input end of the up-flip threshold adjustment unit 301 receives the up-flip threshold adjustment signal verfh_ctrl, and its output end is coupled to the inverting input end of the second decoding comparator 304, and outputs the up-flip threshold voltage verfh corresponding to the original protocol data signal data_in; the non-inverting input end of the second decoding comparator 304 receives the original protocol data signal data_in, and its output end is coupled to the second input end of the latch 40.

[0134] The down-turn threshold adjustment signal verfl_ctrl includes voltage difference information between the original down-turn threshold and the new down-turn threshold, and the up-turn threshold adjustment signal verfh_ctrl includes voltage difference information between the original up-turn threshold and the new up-turn threshold.

[0135] In addition, an embodiment of the present invention further provides an on-chip charging line system, comprising the above-mentioned charging line data decoding circuit. As an example, the original protocol data signal data_in is a charging line signal.

[0136] Therefore, the on-chip charging line system utilizes the charging line data decoding circuit provided by the technical solution of the present invention to analyze the charging line signal, so as to adaptively adjust the detection threshold of the decoding circuit when the charging line current is large, thereby avoiding errors in decoding the charging line signal.

[0137] In addition, an embodiment of the present invention further provides an electronic device, comprising the above-mentioned charging line data decoding circuit. As an example, the electronic device can be a USB data connection cable and the like.

[0138] In addition, the embodiment of the present invention also provides a charging line data decoding method for Figures 1 to 5 The charging line data decoding circuit of any embodiment shown in the figure is controlled to decode the original protocol data signal data_in, and the method comprises the following steps:

[0139] Compare the voltage value of the original protocol data signal data_in with the voltage value of the reference voltage VREF corresponding to each comparator CMP in real time, and output a first comparison signal to the digital control module 20 when the original protocol data signal data_in jumps from a low level to a high level, and output a second comparison signal to the digital control module 20 when the original protocol data signal data_in jumps from a high level to a low level, wherein the first comparison signal and the second comparison signal both include the comparison result between the voltage value of the original protocol data signal data_in and the voltage value of the reference voltage VREF corresponding to each comparator CMP;

[0140] Determine a down-turn threshold and an up-turn threshold of the original protocol data signal data_in according to the first comparison signal and the second comparison signal, and output a turn threshold adjustment signal to the decoding module 30;

[0141] The original protocol data signal data_in is decoded according to the flip threshold adjustment signal.

[0142] As a specific implementation, please refer to Figure 6 In actual use, Figure 1 The charging line data decoding circuit shown is controlled to decode the original protocol data signal, and the method comprises the following steps:

[0143] S51: Power on;

[0144] After power-on, the charging line data decoding circuit works normally;

[0145] S52: Compare the voltage value of the original protocol data signal with the voltage value of the reference voltage corresponding to each comparator in real time, and output a first comparison signal to the digital control module when the original protocol data signal jumps from a low level to a high level, wherein the first comparison signal includes a comparison result of the voltage value when the original protocol data signal jumps from a low level to a high level in real time with the voltage value of the reference voltage corresponding to each comparator;

[0146] S53: determining a down-flip threshold of the original protocol data signal according to the first comparison signal, and outputting a flip threshold adjustment signal to the decoding module;

[0147] S54: Compare the voltage value of the original protocol data signal with the voltage value of the reference voltage corresponding to each comparator in real time, and output a second comparison signal to the digital control module when the original protocol data signal jumps from a high level to a low level, wherein the second comparison signal includes a comparison result between the voltage value when the original protocol data signal jumps from a high level to a low level and the voltage value of the reference voltage corresponding to each comparator;

[0148] S55: determining an up-flip threshold of the original protocol data signal according to the second comparison signal, and outputting a flip threshold adjustment signal to the decoding module;

[0149] S56: Decoding the original protocol data signal according to the flip threshold adjustment signal;

[0150] S57: Output the decoded data signal.

[0151] In summary, the embodiment of the present invention compares the voltage value of the original protocol data signal with the voltage value of each reference voltage in real time through the first comparison module, outputs the first comparison signal when the original protocol data signal is at a high level, and the digital control module determines the down-flip threshold of the original protocol data signal according to the first comparison signal; outputs the second comparison signal when the original protocol data signal is at a low level; the digital control module determines the up-flip threshold of the original protocol data signal according to the second comparison signal, the digital control module outputs the flip threshold adjustment signal as well as the determined down-flip threshold and up-flip threshold, and the decoding module decodes the original protocol data signal according to the flip threshold adjustment signal, so that the present invention can adaptively adjust the detection threshold of the decoding circuit to avoid errors in decoding the data signal.

[0152] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A charging line data decoding circuit, characterized in that: include: A first comparison module, a digital control module, a decoding module and a latch; The first comparison module includes N comparators, the inverting receiving end of each comparator receives a corresponding reference voltage, the inverting receiving end of each comparator receives the original protocol data signal, the output end of each comparator is coupled to the input end of the digital control module, the output end of the digital control module is coupled to the first input end of the decoding module, the second input end of the decoding module receives the original protocol data signal, and the output end of the decoding module outputs a decoded data signal through the latch; wherein N is an integer greater than or equal to 6; The first comparison module is used to compare the voltage value of the original protocol data signal with the voltage value of the reference voltage corresponding to each comparator in real time, and output a first comparison signal to the digital control module when the original protocol data signal jumps from a low level to a high level, and output a second comparison signal to the digital control module when the original protocol data signal jumps from a high level to a low level, and the first comparison signal and the second comparison signal both include the comparison result between the voltage value of the original protocol data signal and the voltage value of the reference voltage corresponding to each comparator; The digital control module is used to determine the down-flip threshold and the up-flip threshold of the original protocol data signal according to the first comparison signal and the second comparison signal, and output a flip threshold adjustment signal to the decoding module; Wherein, determining the up-flip threshold and the down-flip threshold of the original protocol data signal according to the first comparison signal and the second comparison signal includes: Determine a down-turn threshold of the original protocol data signal according to the signals output by the i-th comparator to the N-th comparator in the first comparison signal; If there is a signal outputted from the kth comparator to the mth comparator that jumps from a low level signal to a high level signal, the down-flip threshold of the original protocol data signal increases by a first voltage, where the first voltage is the difference between a reference voltage corresponding to the mth comparator and a reference voltage corresponding to the ith comparator, k and m are both integers, and i≤k, k≤m, m≤N; Determine the up-turn threshold of the original protocol data signal according to the signals output by the 1st comparator to the (i+1)th comparator in the second comparison signal; If there is a signal outputted by the pth comparator to the qth comparator that jumps from a high level signal to a low level signal, the up-flip threshold of the original protocol data signal increases by a second voltage, and the second voltage is the difference between the reference voltage corresponding to the qth comparator and the reference voltage corresponding to the first comparator, p and q are both integers, and 1≤q, q≤p, p≤i+1; The decoding module is used to perform data decoding on the original protocol data signal according to the flip threshold adjustment signal.

2. The charging line data decoding circuit according to claim 1, characterized in that: The number of comparators is determined according to the original high level, original low level, maximum low level and detection accuracy of the original protocol data signal. The calculation formula of the number of comparators N is: Wherein, V1 is the original high level voltage value of the original protocol data signal, V2 is the original low level voltage value of the original protocol data signal, V3 is the maximum low level voltage value of the original protocol data signal, and V4 is the voltage value of the detection accuracy; in, The result is an integer rounded up.

3. The charging line data decoding circuit according to claim 2, characterized in that: The reference voltage received by the jth comparator is: VREF j-1 =V2+j×V4 Wherein, j is an integer, and 1≤j≤N; The reference voltage received by the i-th comparator is less than or equal to the original high level voltage value of the original protocol data signal, and the reference voltage received by the i+1-th comparator is greater than the original high level voltage value of the original protocol data signal; wherein i is an integer, and 1 <i<N。 4. The charging line data decoding circuit according to claim 1, characterized in that: The flip threshold adjustment signal includes an upper flip threshold adjustment signal and a lower flip threshold adjustment signal; The decoding module includes an up-flip threshold adjustment unit, a down-flip threshold adjustment unit, a first decoding comparator and a second decoding comparator; The input end of the down-turn threshold adjustment unit receives the down-turn threshold adjustment signal, and the output end thereof is coupled to the inverting input end of the first decoding comparator, and outputs the down-turn threshold voltage corresponding to the original protocol data signal; the non-inverting input end of the first decoding comparator receives the original protocol data signal, and the output end thereof is coupled to the first input end of the latch; The input end of the up-flip threshold adjustment unit receives the up-flip threshold adjustment signal, and the output end thereof is coupled to the inverting input end of the second decoding comparator, and outputs the up-flip threshold voltage corresponding to the original protocol data signal; the non-inverting input end of the second decoding comparator receives the original protocol data signal, and the output end thereof is coupled to the second input end of the latch.

5. The charging line data decoding circuit according to claim 1, characterized in that: The latch is an RS latch.

6. An on-chip charging cable system, characterized in that: The charging line data decoding circuit comprises the charging line data decoding circuit according to any one of claims 1 to 5.

7. The on-chip charging cable system according to claim 6, characterized in that: The original protocol data signal is a charging line signal.

8. An electronic device, characterized in that: The charging line data decoding circuit comprises the charging line data decoding circuit according to any one of claims 1 to 5.

9. A charging line data decoding method, characterized in that: The charging line data decoding circuit according to any one of claims 1 to 5 is used to decode the original protocol data signal, and the method comprises: Compare the voltage value of the original protocol data signal with the voltage value of the reference voltage corresponding to each comparator in real time, and output a first comparison signal to the digital control module when the original protocol data signal jumps from a low level to a high level, and output a second comparison signal to the digital control module when the original protocol data signal jumps from a high level to a low level, wherein the first comparison signal and the second comparison signal both include comparison results between the voltage value of the original protocol data signal and the voltage value of the reference voltage corresponding to each comparator; Determine a down-turn threshold and an up-turn threshold of the original protocol data signal according to the first comparison signal and the second comparison signal, and output a turn-over threshold adjustment signal to the decoding module; According to the flip threshold adjustment signal, data decoding is performed on the original protocol data signal; Wherein, determining the up-flip threshold and the down-flip threshold of the original protocol data signal according to the first comparison signal and the second comparison signal includes: Determine a down-turn threshold of the original protocol data signal according to the signals output by the i-th comparator to the N-th comparator in the first comparison signal; If there is a signal outputted from the kth comparator to the mth comparator that jumps from a low level signal to a high level signal, the down-flip threshold of the original protocol data signal increases by a first voltage, where the first voltage is the difference between a reference voltage corresponding to the mth comparator and a reference voltage corresponding to the ith comparator, k and m are both integers, and i≤k, k≤m, m≤N; Determine the up-turn threshold of the original protocol data signal according to the signals output by the 1st comparator to the (i+1)th comparator in the second comparison signal; If the signal output by the pth comparator to the qth comparator jumps from a high-level signal to a low-level signal, the up-flip threshold of the original protocol data signal is increased by a second voltage, and the second voltage is the difference between the reference voltage corresponding to the qth comparator and the reference voltage corresponding to the first comparator, p and q are both integers, and 1≤q, q≤p, p≤i+1.

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