A semiconductor structure, a manufacturing method thereof and a memory

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof and a memory, wherein the semiconductor structure comprises: a substrate; a bit line structure located on the surface of the substrate, the bit line structure comprising: a bit line body; a first side wall isolation layer located on the sidewall of the bit line body, the first side wall isolation layer comprising a first part close to the substrate and a second part away from the substrate; a second side wall isolation layer located on the second part of the first side wall isolation layer; a capacitor contact structure located between adjacent bit line structures, and the capacitor contact structure comprising: a contact plug located on the surface of the substrate, the contact plug covering the first part of the first side wall isolation layer, and the top surface of the contact plug being in contact with the bottom surface of the second side wall isolation layer; a landing pad located on the top surface of the contact plug, and the landing pad also covering the surface of the second side wall isolation layer, part of the top surface of the first side wall isolation layer and part of the top surface of the bit line body, so that the reliability of the semiconductor structure can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a semiconductor structure, a method for fabricating the semiconductor structure, and a memory. BACKGROUND

[0002] Memory is a memory component used to store programs and various data information. The random access memory (RAM) used by a general computer system can be divided into dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor memory device in computers, which is composed of many repeated memory cells.

[0003] A memory cell generally includes a capacitor and a transistor. The drain of the transistor is connected to a bit line structure, and the source is connected to the capacitor. The capacitor includes a capacitor contact structure and a capacitor. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, and then read the data information stored in the capacitor through the bit line structure, or write the data information into the capacitor through the bit line structure for storage.

[0004] At present, the reliability of the semiconductor structure needs to be improved. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor structure, a method for fabricating the semiconductor structure, and a memory, which can at least improve the reliability of the semiconductor structure.

[0006] According to some embodiments of the present disclosure, in one aspect, a semiconductor structure is provided, comprising: a substrate; a bit line structure located on a surface of the substrate, the bit line structure comprising: a bit line body; a first side wall isolation layer located on a sidewall of the bit line body, the first side wall isolation layer comprising a first portion close to the substrate and a second portion away from the substrate; a second side wall isolation layer located on the second portion of the first side wall isolation layer; and a capacitor contact structure located on one side of the bit line structure, the capacitor contact structure comprising: a contact plug located on a surface of the substrate, the contact plug covering the first portion of the first side wall isolation layer, and a top surface of the contact plug being in contact with a bottom surface of the second side wall isolation layer; and a landing pad located on the top surface of the contact plug, the landing pad also covering a surface of the second side wall isolation layer, a portion of a top surface of the first side wall isolation layer, and a portion of a top surface of the bit line body.

[0007] In some embodiments, the contact plug comprises: a flat portion in contact with the substrate; a protruding portion on a top surface of the flat portion, and a top surface of the protruding portion in contact with a bottom surface of the second side wall spacer.

[0008] In some embodiments, the flat portion and the protruding portion enclose a receiving space, and the landing pad fills the receiving space.

[0009] In some embodiments, the landing pad comprises: a diffusion barrier layer covering a sidewall of the protruding portion and a surface of the second side wall spacer, and further covering a top surface of the bit line structure; and a metal layer covering a surface of the diffusion barrier layer.

[0010] In some embodiments, the bit line body extends along a first direction, and in a second direction perpendicular to the first direction, a width of the protruding portion is 0.05-0.15 of a width of the flat portion.

[0011] In some embodiments, the bit line body extends along a first direction, and in a second direction perpendicular to the first direction, a width of the second side wall spacer is 0.15-0.25 of a width of the first side wall spacer.

[0012] In some embodiments, the semiconductor structure further comprises: a dielectric layer between adjacent bit line structures, and a sidewall of the dielectric layer in contact with a sidewall of the capacitor contact structure.

[0013] In some embodiments, the second side wall spacer is further on a sidewall of the dielectric layer.

[0014] In some embodiments, the first side wall spacer comprises: a first spacer sublayer on a sidewall of the bit line body; a second spacer sublayer on a sidewall of the first spacer sublayer; and a third spacer sublayer on a sidewall of the second spacer sublayer.

[0015] In some embodiments, the substrate comprises: an active region and an isolation structure defining the active region; and the bit line body comprises: a conductive layer and a cap layer stacked in sequence; wherein the contact plug and the conductive layer are both in contact with the active region.

[0016] According to some embodiments of the present disclosure, another aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming an initial bit line structure on a surface of the substrate, the initial bit line structure comprising: a bit line body; a first sidewall spacer layer on sidewalls of the bit line body, the first sidewall spacer layer comprising a first portion proximate to the substrate and a second portion distal to the substrate; forming an initial contact plug on the surface of the substrate between adjacent initial bit line structures, the initial contact plug covering the first portion of the first sidewall spacer layer; forming a second sidewall spacer layer on the second portion of the first sidewall spacer layer, a bottom surface of the second sidewall spacer layer in contact with a top surface of the initial contact plug, the second sidewall spacer layer and the initial bit line structure collectively forming a bit line structure; etching a portion of the initial contact plug using the second sidewall spacer layer as a mask, a remaining portion of the initial contact plug as a contact plug; forming a landing pad on a top surface of the contact plug, the landing pad also covering a surface of the second sidewall spacer layer, a portion of a top surface of the first sidewall spacer layer, and a portion of a top surface of the bit line body, the contact plug and the landing pad collectively forming a capacitor contact structure.

[0017] In some embodiments, the method of forming the initial contact plug comprises: forming a dielectric layer between the adjacent bit line bodies and spaced apart from the first sidewall spacer layer, the dielectric layer, the first sidewall spacer layer, and the substrate collectively forming a recess; and forming the initial contact plug in the recess.

[0018] In some embodiments, the method of forming the dielectric layer comprises: forming a sacrificial layer between the adjacent bit line bodies and in contact with a surface of the first sidewall spacer layer; patterning the sacrificial layer to form a first recess; and forming the dielectric layer to fill the first recess.

[0019] In some embodiments, the method of forming the second sidewall spacer layer comprises: forming a second initial sidewall spacer layer covering a top surface of the initial bit line structure, a portion of sidewalls of the initial bit line structure, a top surface of the dielectric layer, a portion of sidewalls of the dielectric layer, and a top surface of the initial contact plug; and etching back the second initial sidewall spacer layer to form the second sidewall spacer layer.

[0020] In some embodiments, forming the first side wall isolation layer includes: forming a first isolation sub-layer, the first isolation sub-layer is located on a sidewall of the bit line body; forming a second isolation sub-layer, the second isolation sub-layer is located on a sidewall of the first isolation sub-layer; forming a third isolation sub-layer, the third isolation sub-layer is located on a sidewall of the second isolation sub-layer.

[0021] In some embodiments, the method of forming the landing pad includes: forming an initial diffusion barrier layer, the initial diffusion barrier layer covers a top surface of the contact plug and a surface of a partial bit line structure; forming an initial metal layer, the initial metal layer covers a surface of the initial diffusion barrier layer; patterning the initial metal layer and the initial diffusion barrier layer, the initial metal layer and the initial diffusion barrier layer remaining as a diffusion barrier layer and a metal layer, the diffusion barrier layer and the metal layer jointly forming the landing pad.

[0022] According to some embodiments of the present disclosure, in yet another aspect, the present disclosure provides a semiconductor structure, including: the semiconductor structure as described above.

[0023] The technical scheme provided by the semiconductor structure provided by the present disclosure has at least the following advantages: by arranging the second side wall isolation layer on the second part of the first side wall isolation layer, the width of the top surface of the bit line structure can be increased, thereby increasing the process window of the top surface of the bit line structure, reducing the process difficulty of forming the capacitor contact structure, improving the insulation between adjacent capacitor structures, and further improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0024] One or more embodiments are illustrated by way of example in the drawings, which are for illustrative purposes only and are not meant to limit the embodiments unless otherwise specifically stated herein. The drawings in the accompanying drawings are not to scale and are provided for purposes of explanation only. As will be readily understood by those skilled in the art, the embodiments described herein can be carried out by specifically designed software, hardware, firmware, or software, hardware, firmware that contains no software, or combinations of the above, some of which will be described in greater detail below.

[0025] Figure 1 A top view of a semiconductor structure according to an embodiment of the present disclosure is provided.

[0026] Figure 2 A sectional view of a semiconductor structure according to an embodiment of the present disclosure is provided.

[0027] Figure 3 A partial enlarged view of a semiconductor structure according to an embodiment of the present disclosure is provided.

[0028] Figure 4A sectional view of a second semiconductor structure according to an embodiment of the present disclosure;

[0029] Figure 5 A partial enlarged view of a semiconductor structure according to an embodiment of the present disclosure;

[0030] Figures 6 to 24 A sectional view of a semiconductor structure according to an embodiment of the present disclosure; DETAILED DESCRIPTION

[0031] With the continuous miniaturization of integration, the spacing between the landing pads of the capacitive contact structure is also closer and closer, thus leading to difficulty in etching completely in the process of forming the landing pad, leading to easy shorting between adjacent landing pads, and the spacing between the landing pad and the bit line structure is also closer and closer, leading to easy shorting between the landing pad and the bit line structure.

[0032] The present disclosure provides a semiconductor structure, by setting the second part of the first side wall isolation layer located on the sidewall of the bit line main body, the top surface width of the bit line structure can be increased, so that the etching window for forming the landing pad can be increased, so that the formed landing pad morphology is better, avoiding shorting between adjacent landing pads, and by forming the second side wall isolation layer, the insulation between the landing pad and the bit line structure can be increased, avoiding shorting between the landing pad and the bit line structure.

[0033] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to make the reader better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be realized even without these technical details and various changes and modifications based on the following embodiments.

[0034] Reference Figures 1 to 5 , Figure 1 A top view of a semiconductor structure according to an embodiment of the present disclosure; Figure 2 A first sectional view of a semiconductor structure according to an embodiment of the present disclosure along the direction of AA' in FIG. 2, Figure 1 A first sectional view of a semiconductor structure according to an embodiment of the present disclosure along the direction of AA' in FIG. 2, Figure 3 A first sectional view of a semiconductor structure according to an embodiment of the present disclosure along the direction of AA' in FIG. 2, Figure 2 A first sectional view of a semiconductor structure according to an embodiment of the present disclosure along the direction of AA' in FIG. 2, Figure 4 A first sectional view of a semiconductor structure according to an embodiment of the present disclosure along the direction of AA' in FIG. 2, Figure 1 A first sectional view of a semiconductor structure according to an embodiment of the present disclosure along the direction of AA' in FIG. 2. Figure 5 Figure 4 A first sectional view of a semiconductor structure according to an embodiment of the present disclosure along the direction of AA' in FIG. 2.

[0035] ​In some embodiments, the semiconductor structure comprises: a substrate 100; a bit line structure 110, the bit line structure 110 is located on the surface of the substrate 100, the bit line structure 110 comprises: a bit line body 120; a first side wall isolation layer 130, the first side wall isolation layer 130 is located on the sidewall of the bit line body 120, the first side wall isolation layer 130 comprises a first part 131 close to the substrate 100 and a second part 132 away from the substrate 100; a second side wall isolation layer 140, the second side wall isolation layer 140 is located on the second part 132 of the first side wall isolation layer 130; a capacitor contact structure 150, the capacitor contact structure 150 is located between adjacent bit line structures 110, and the capacitor contact structure 150 comprises: a contact plug 160, the contact plug 160 is located on the surface of the substrate 100, the contact plug 160 covers the first part 131 of the first side wall isolation layer 130, and the top surface of the contact plug 160 is in contact with the bottom surface of the second side wall isolation layer 140; a landing pad 170, the landing pad 170 is located on the top surface of the contact plug 160, and the landing pad 170 also covers the surface of the second side wall isolation layer 140, part of the top surface of the first side wall isolation layer 130 and part of the top surface of the bit line body 120.

[0036] By setting the first side wall isolation layer 130, the insulation performance between adjacent bit line structures 110 can be increased, and the parasitic capacitance between adjacent bit line structures 110 can be reduced. By forming the first side wall isolation layer 130, the bit line body 120 can be protected. By forming the second side wall isolation layer 140 on the second part 132 of the first side wall isolation layer 130, the landing pads 170 formed during the formation of the capacitor contact structure can be spaced apart from each other, thereby avoiding shorting between adjacent landing pads 170, and also increasing the insulation between the landing pads 170 and adjacent bit line structures 110, thereby improving the reliability of the semiconductor structure.

[0037] In some embodiments, the material of the substrate 100 can be silicon, germanium or silicon germanium, etc. The material of the substrate 100 can also be doped. For example, when the material of the substrate 100 is silicon, a small amount of trivalent elements such as boron, indium, gallium or aluminum, etc. can be doped in the substrate 100, so as to form a P-type substrate. Similarly, a small amount of pentavalent elements such as phosphorus, antimony or arsenic, etc. can be doped in the substrate 100, so as to form an N-type substrate. The selection of the doped elements of the substrate 100 can be considered according to actual needs and product performance, etc. The present disclosure does not limit the material of the substrate 100 and the doped elements.

[0038] In some embodiments, the substrate 100 comprises the active regions 101 and the isolation structures 102 between the active regions 101, the bit line body 120 can comprise the conductive layer 121 and the cap layer 122 which are stacked in sequence, the conductive layer 121 is in contact with the active region 101, by arranging the conductive layer 121 as part of the bit line structure 110 for transmitting data information, by arranging the cap layer 122 to protect the top surface of the conductive layer 121, so as to improve the reliability of the bit line body 120.

[0039] In some embodiments, the isolation structure 102 can be a shallow trench isolation (STI) structure to isolate adjacent active regions 101.

[0040] In some embodiments, the material of the isolation structure 102 can only comprise silicon oxide; in some embodiments, the material of the isolation structure 102 can comprise a stack of multiple film layers, for example, a stack of silicon oxide film layer and silicon oxynitride film layer.

[0041] In some embodiments, the conductive layer 121 can comprise the first bit line conductive layer 123, the bit line barrier layer 124 and the second bit line conductive layer 125 which are stacked, by arranging the conductive layer 121 to comprise the first bit line conductive layer 123, the bit line barrier layer 124 and the second bit line conductive layer 125 which are stacked, the reliability of the bit line body 120 for transmitting data information can be improved.

[0042] In some embodiments, the material of the first bit line conductive layer 123 can be a semiconductor material such as polysilicon, the material of the bit line barrier layer 124 can be titanium nitride, and the material of the second bit line conductive layer 125 can be a metal such as tungsten, by arranging the material of the first bit line conductive layer 123 to be a semiconductor material such as polysilicon, the interface state of the contact surface between the bit line body 120 and the substrate 100 can be reduced, the possibility of abnormality when transmitting data information between the substrate and the bit line body 120 can be reduced, by arranging the bit line barrier layer 124, the metal ions in the second bit line conductive layer 125 can be prevented from diffusing into the first bit line conductive layer 123, so as to avoid affecting the performance of the first bit line conductive layer 123, by arranging the material of the second bit line conductive layer 125 to be a metal material, the transmission rate of the bit line body 120 for transmitting data information can be improved.

[0043] In some embodiments, the conductive layer 121 can only comprise a single film layer, for example, only composed of polysilicon or only composed of tungsten.

[0044] In some embodiments, the material of the cap layer 122 can be silicon nitride.

[0045] In some embodiments, the first side wall isolation layer 130 can include a first isolation sub-layer 133 located on the sidewall of the bit line body 120, a second isolation sub-layer 134 located on the sidewall of the first isolation sub-layer 133, and a third isolation sub-layer 135 located on the sidewall of the second isolation sub-layer 134. By configuring the first side wall isolation layer 130 to include the first isolation sub-layer 133, the second isolation sub-layer 134, and the third isolation sub-layer 135, the insulation performance of the first side wall isolation layer 130 can be improved, thereby avoiding short circuit between adjacent bit line structures 110.

[0046] In some embodiments, the material of the first isolation sub-layer 133 can be silicon nitride, the material of the second isolation sub-layer 134 can be silicon oxide, and the material of the third isolation sub-layer 135 can be silicon nitride, that is, the first side wall isolation layer 130 can have an N-O-N (nitride layer-oxide layer-nitride layer) structure. By configuring an oxide layer between two nitride layers, the insulation performance of the first side wall isolation layer 130 can be improved, and the parasitic capacitance between adjacent bit line structures 110 can be reduced. In addition, the material of the nitride layer is relatively hard, and by configuring two nitride layers, the morphology of the first side wall isolation layer 130 can be improved.

[0047] In some embodiments, the material of the first isolation sub-layer 133, the material of the second isolation sub-layer 134, and the material of the third isolation sub-layer 135 can also be other insulating materials, and the material of the first isolation sub-layer 133, the material of the second isolation sub-layer 134, and the material of the third isolation sub-layer 135 can be the same or different.

[0048] In some embodiments, referring to Figure 2 and Figure 3 , the top surface of the second side wall isolation layer 140 located on one side of the bit line body 120 is lower than the top surface of the second side wall isolation layer located on the other side of the bit line body 120. It can be understood that, in some embodiments, during the process of forming the landing pad 170, the etching agent will etch away part of the second side wall isolation layer 140 and part of the diffusion barrier layer 171, so that the second side wall isolation layer 140 located on one side of the bit line body 120 is lower than the second side wall isolation layer located on the other side of the bit line body 120.

[0049] In some embodiments, referring to Figure 4 , the top surfaces of the second side wall isolation layers 140 located on both sides of the bit line body 120 are flush, that is, the etching process is controlled to protect the second side wall isolation layer 140. By configuring the second side wall isolation layer 140 to be located on both sides of the bit line body 120, the process window for etching the diffusion barrier layer 171 in the landing pad 170 can be increased, thereby improving the morphology of the formed landing pad 170 when forming the spaced landing pads 170, and thereby improving the reliability of the formed semiconductor structure.

[0050] With reference to the above Figures 1 to 5 , the second side wall isolation layer 140 is also located on the sidewall of the dielectric layer 180, by setting the sidewall of the second side wall isolation layer 140, the process window of etching the diffusion barrier layer 171 in the landing pad 170 can also be increased, so that the morphology of the formed landing pad 170 can be improved when the spaced landing pad 170 is formed, thereby improving the reliability of the formed semiconductor structure.

[0051] In some embodiments, the second side wall isolation layer 140 is located on both sidewalls of the dielectric layer 180; in some embodiments, the second side wall isolation layer 140 is located on one sidewall of the dielectric layer 180.

[0052] In some embodiments, the bit line body 120 extends along a first direction X, and in a second direction Y perpendicular to the first direction X, the width of the second side wall isolation layer 140 is 0.15-0.25 of the width of the first side wall isolation layer 130. By setting the width of the second side wall isolation layer 140 to be 0.15-0.25 of the width of the first side wall isolation layer 130, the process window of the diffusion barrier layer 171 can be improved while avoiding affecting the size of the subsequently formed landing pad 170.

[0053] It can be understood that the greater the width of the second side wall isolation layer 140, the greater the size of the process window of etching the diffusion barrier layer 171, and the smaller the width of the second side wall isolation layer 140, the greater the space that can be used to form the landing pad 170 subsequently, which is more convenient for forming the landing pad 170. Therefore, when the width of the second side wall isolation layer 140 is less than 0.15 of the width of the first side wall isolation layer 130, the performance of improving the process window of the diffusion barrier layer 171 is poor, and when the width of the second side wall isolation layer 140 is greater than 0.25 of the width of the first side wall isolation layer 130, the size of the formed landing pad 170 is small, which increases the contact resistance of the landing pad 170.

[0054] In some embodiments, the width of the second side wall isolation layer 140 can be 10-20 nm, for example, 13 nm, 15 nm, or 17 nm, etc.

[0055] In some embodiments, the width of the first side wall isolation layer 130 can be 1-5 nm, for example, 2 nm, 3 nm, or 4 nm, etc.

[0056] In some embodiments, the contact plug 160 is also located on the sidewall of the dielectric layer 180, and the top surface of the contact plug 160 is in contact with the bottom surface of the second sidewall isolation layer 140 located on the sidewall of the dielectric layer 180. That is, the dielectric layer 180 and the bit line structure 110 enclose a space in which the contact plug 160 is located, and the profile of the contact plug 160 is defined by the dielectric layer 180 and the bit line structure 110.

[0057] In some embodiments, the active region includes a first doped region, a second doped region, and a third doped region, wherein the second doped region and the third doped region are located on two sides of the first doped region, the conductive layer 121 is in contact with the first doped region, and the two contact plugs 160 located on two sides of the same bit line structure 110 are in contact with the second doped region and the third doped region, respectively.

[0058] In some embodiments, the contact plug 160 includes a flat portion 161 in contact with the substrate 100, and a protruding portion 162 located on the top surface of the flat portion 161, and the top surface of the protruding portion 162 is in contact with the bottom surface of the second sidewall isolation layer 140. It can be understood that by providing the protruding portion 162 and the flat portion 161, the damage to the bit line structure 110 during the process of forming the landing pad 170 can be reduced, thereby improving the reliability of the semiconductor structure.

[0059] In some embodiments, the flat portion 161 and the protruding portion 162 enclose an accommodation space, and the landing pad 170 fills the accommodation space. It can be understood that for one contact plug 160, the accommodation space is enclosed by the sidewalls of the two protruding portions 162 and the top surface of the flat portion 161, and by providing the landing pad 170 in the accommodation space, the first sidewall isolation layer 130 of the bit line structure 110 can be avoided during the process of forming the spaced landing pads 170, and the etching loading effect control process can be stopped, thereby improving the reliability of the semiconductor structure.

[0060] In some embodiments, the contact plug 160 is in contact with the active region 101, and by providing the contact plug 160 in contact with the active region 101, the transmission of data information between the contact plug 160 and the active region 101 is achieved.

[0061] In some embodiments, the flat portion 161 is in contact with the active region 101.

[0062] Reference Figure 4 , Figure 4 The embodiments of the present disclosure are along Figure 2The enlarged schematic diagram within the dashed circle illustrates that, during the etching process to form the spaced landing pads 170, a portion of the first sidewall isolation layer 130 of the bitline structure 110 will inevitably be etched away. As the etching process continues, some material from the landing pads 170 may seep into the bitline structure 110 through the gaps created by etching the first sidewall isolation layer 130, causing a short circuit between the bitline structure 110 and the landing pads 170. However, by positioning the landing pads 170 within the receiving space, and due to the relatively large etching tolerance between the landing pads 170 and the contact plugs 160, excessive etching of the contact plugs 160 will not occur during the etching process. Therefore, as the etching process proceeds, at the beginning of etching, the width of the etching process window of the landing pad 170 is the first width D1. When etching reaches the top surface of the exposed protrusion 162, the width of the etching process window of the landing pad 170 is the second width D2. It can be seen that the etching process window decreases. According to the etching load effect, the smaller the etching process window, the more difficult the etching is. Therefore, it is equivalent to controlling the etching of the landing pad 170 to stop. By setting the protrusion 162, the first sidewall isolation layer 130 of the bit line structure 110 can be protected, and short circuit between the bit line structure 110 and the landing pad 170 can be avoided.

[0063] refer to Figure 1 and Figure 2 In some embodiments, the bit line body 120 extends along the first direction X. In the second direction Y perpendicular to the first direction X, the width of the protrusion 162 is 0.05 to 0.15 times the width of the flat portion 161. For example, the width of the protrusion 162 is 0.07 or 0.10 times the width of the flat portion 161, etc. It can be understood that the second direction Y here is the direction in which the bit line bodies 120 are spaced apart, and the width here is the size of the protrusion 162 along the second direction Y. By setting the width of the protrusion 162 to be 0.05 to 0.15 times the width of the flat portion 161, the volume of the landing pad located in the accommodating space can be avoided from being too small while having a certain ability to protect the first sidewall isolation layer 130, thereby improving the reliability of the semiconductor structure.

[0064] Understandably, when the width of the protrusion 162 is less than 0.05 times the width of the flat portion 161, although the etching options for the contact plug 160 and the landing pad 170 are relatively large, there is still a risk of etching through the contact plug 160 because it is too thin. When the width of the protrusion 162 is greater than 0.15 times the width of the flat portion 161, the space within the accommodating space for accommodating the landing pad 170 is reduced, which is not conducive to the formation of the landing pad 170, and the contact resistance between the formed landing pad 170 and the contact plug 160 will also increase.

[0065] In some embodiments, the width of the protrusion 162 is equal to the width of the second side wall spacer 140. By setting the width of the protrusion 162 equal to the width of the second side wall spacer 140, the protrusion 162 can be formed by directly etching the second side wall spacer 140 as a mask.

[0066] In some embodiments, the width of the protrusion 162 can also be less than the width of the second side wall spacer 140 or greater than the width of the second side wall spacer 140.

[0067] In some embodiments, the width of the contact plug 160 is 20 nm to 40 nm, such as 25 nm, 30 nm, or 35 nm, etc.

[0068] It should be noted that the width described above is the dimension along the second direction Y, and is not the width shown in FIGS. 1A and 1B. Figure 1 Figure 2 Figure 3

[0069] In some embodiments, the landing pad 170 includes a diffusion barrier layer 171 and a metal layer 172. The diffusion barrier layer 171 covers the sidewall of the protrusion 162 and the surface of the second side wall spacer 140, and also covers the top surface of the bit line structure 110. The metal layer 172 covers the surface of the diffusion barrier layer 171. The diffusion barrier layer 171 is used to prevent metal ions in the metal layer 172 from diffusing into the second side wall spacer 140 and the contact plug 160, so as to avoid affecting the performance of the second side wall spacer 140 and the contact plug 160.

[0070] In some embodiments, the semiconductor structure further includes a dielectric layer 180 located between adjacent bit line structures 110, and the sidewall of the dielectric layer 180 is in contact with the sidewall of the capacitor contact structure 150. By providing the dielectric layer 180, a groove for forming the capacitor contact structure 150 can be formed together with the bit line structure 110. That is, by forming the dielectric layer 180, the profile of the capacitor contact structure 150 can be defined, so as to improve the profile of the formed capacitor contact structure 150 and reduce the process difficulty of forming the capacitor contact structure 150.

[0071] In some embodiments, the material of the dielectric layer 180 can be an insulating material such as silicon nitride.

[0072] In some embodiments, the semiconductor structure can further include a word line structure 190. The word line structure 190 can be located in the substrate 100, i.e., a buried word line. By providing the word line structure 190, the on and off of the transistor formed in the semiconductor structure can be controlled. By forming a buried word line, the integration of the semiconductor structure can be increased, and the size of the semiconductor structure can be reduced. ​​​

[0073] In some embodiments, the word line structure 190 can include a gate dielectric layer 191, a word line barrier layer 192, a word line conductive layer 193, and a word line protection layer 194, the gate dielectric layer 191 is between the word line barrier layer 192 and the substrate 100, the word line barrier layer 192 is on the surface of the word line conductive layer 193, and the word line protection layer 194 is on the top surface of the word line conductive layer 193. The gate dielectric layer 191 can avoid contact between the word line conductive layer 193 and the substrate 100, and avoid the flow of carriers in the substrate 100 to the word line conductive layer 193. The word line barrier layer 192 can prevent the diffusion of conductive ions in the word line conductive layer 193 into the gate dielectric layer 191, and avoid affecting the performance of the gate dielectric layer 191. The word line protection layer 194 can protect the word line conductive layer 193, thereby reducing damage to the word line conductive layer 193.

[0074] In some embodiments, the semiconductor structure further includes a first isolation layer 210 and a second isolation layer 220 stacked, and the first isolation layer 210 and the second isolation layer 220 can be formed simultaneously when forming the isolation structure.

[0075] In some embodiments, the material of the first isolation layer 210 can be silicon oxide or the like, and the material of the second isolation layer 220 can be silicon nitride or the like.

[0076] In some embodiments, the semiconductor structure further includes a first filling layer 200. It can be understood that when forming the bit line structure 110 in contact with the substrate 100, part of the substrate 100 will be etched, so that the formed bit line structure 110 is partially located in the substrate 100. However, during the etching process of the substrate, as the etching reagent is consumed, a structure similar to an inverted trapezoid will be formed, that is, the upper opening is large and the lower opening is small. Therefore, after the formation of the conductive layer 121, the sidewall of the conductive layer 121 will be spaced apart from the substrate 100, which is not conducive to the subsequent formation of other structures, and the first isolation layer 133 formed is not easy to fill the gap between the sidewall of the conductive layer 121 and the substrate 100. Therefore, by forming the first filling layer 200, the gap between the conductive layer 121 and the substrate 100 is filled, thereby facilitating subsequent process steps and improving the reliability of the semiconductor structure.

[0077] In some embodiments, the material of the first filling layer 200 can be an insulating material such as silicon oxide.

[0078] The first side wall isolation layer 130 can be used to increase the insulation performance between the adjacent bit line structures 110, and can reduce the parasitic capacitance between the adjacent bit line structures 110. The first side wall isolation layer 130 can be used to protect the bit line body 120. The second side wall isolation layer 140 formed on the second part 132 of the first side wall isolation layer 130 can be used to separate the landing pads 170 from each other during the formation of the capacitor contact structure, so as to avoid the short circuit between the adjacent landing pads 170, and can increase the insulation performance between the landing pads 170 and the adjacent bit line structures 110, thereby improving the reliability of the semiconductor structure.

[0079] Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which can be used to manufacture the semiconductor structure. The method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or similar parts of the foregoing embodiments can refer to the corresponding description of the foregoing embodiments, which will not be described herein.

[0080] Reference Figures 6 to 24 And Figures 1 to 5 , Figures 6 to 24 The structure schematic diagram corresponding to each step of the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

[0081] The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure includes: providing a substrate 100; forming an initial bit line structure 111, the initial bit line structure 111 is located on the surface of the substrate 100, and the initial bit line structure 111 includes: a bit line body 120; a first side wall isolation layer 130, the first side wall isolation layer 130 is located on the side wall of the bit line body 120, and the first side wall isolation layer 130 includes a first part 131 close to the substrate 100 and a second part 132 away from the substrate 100; forming an initial contact plug 163, the initial contact plug 163 is located on the surface of the substrate 100 and between adjacent initial bit line structures 111, and the initial contact plug 163 covers the first part 131 of the first side wall isolation layer 130; forming a second side wall isolation layer 140, the second side wall isolation layer 140 is located on the second part 132 of the first side wall isolation layer 130, the bottom surface of the second side wall isolation layer 140 is in contact with the top surface of the initial contact plug 163, and the second side wall isolation layer 140 and the initial bit line structure 111 jointly form a bit line structure 110; etching part of the initial contact plug 163 with the second side wall isolation layer 140 as a mask, and the remaining initial contact plug 163 serves as a contact plug 160; forming a landing pad 170, the landing pad 170 is located on the top surface of the contact plug 160, and the landing pad 170 also covers the surface of the second side wall isolation layer 140, part of the top surface of the first side wall isolation layer 130 and part of the top surface of the bit line body 120, and the contact plug 160 and the landing pad 170 jointly form a capacitor contact structure 150.

[0082] The initial bit line structure 111 can provide a limiting space for forming the initial contact plug 163, which can facilitate the formation of the initial contact plug 163. The initial contact plug 163 can provide a process basis for forming the contact plug 160. The second side wall isolation layer 140 and the initial bit line structure 111 jointly form the bit line structure 110, and the second side wall isolation layer 140 formed on the side wall of the initial bit line structure 111 can increase the size of the top surface of the bit line structure 110, thereby facilitating the subsequent formation of the landing pad 170. Increasing the size of the top surface of the bit line structure 110, that is, increasing the process window for forming the landing pad 170, can facilitate the formation of mutually spaced landing pads and avoid shorting between adjacent landing pads 170, thereby improving the reliability of the capacitor contact structure 150 formed. Figures 6 to 11 The initial bit line structure 111 is formed.

[0083] The initial bit line structure 111 is formed. Figure 6 The substrate 100 is provided, and in some embodiments, before the initial bit line structure 111 is formed, a first isolation layer 210, a second isolation layer 220 and a second sacrificial layer 230 can be formed on the substrate 100 in a stacked manner.

[0084] In some embodiments, after the first isolation layer 210, the second isolation layer 220 and the second sacrificial layer 230 are formed, an initial conductive layer 126 can be formed. The initial conductive layer 126 includes a first bit line conductive layer 123, a bit line barrier layer 124 and a second bit line conductive layer 125, wherein the first bit line conductive layer 123 is in electrical contact with the substrate 100 through the first isolation layer 210, the second isolation layer 220 and the second sacrificial layer 230, the bit line barrier layer 124 covers the top surface of the second sacrificial layer 230 and the first bit line conductive layer 123, and the second bit line conductive layer 125 is on the top surface of the bit line barrier layer 124.

[0085] In some embodiments, after the initial conductive layer 126 is formed, an initial cap layer 127 can be formed on the top surface of the second bit line conductive layer 125.

[0086] In some embodiments, after the initial cap layer 127 is formed, a third sacrificial layer 240, a fourth sacrificial layer 250 and a first mask layer 260 can be formed in a stacked manner, wherein the third sacrificial layer 240 is on the top surface of the initial cap layer 127, the fourth sacrificial layer 250 is on the top surface of the third sacrificial layer 240, the first mask layer 260 is on the top surface of the fourth sacrificial layer 250, and the orthographic projection of the first mask layer 260 on the surface of the substrate 100 is within the orthographic projection of the first bit line conductive layer 123 on the surface of the substrate 100. The third sacrificial layer 240 and the fourth sacrificial layer 250 can improve the accuracy of subsequent mask etching to form a pattern, and the first mask layer 260 can provide a basis for subsequent formation of conductive layers and cap layers.

[0087] Referring to Figures 7 to 11 , a first side wall isolation layer 130 is formed.

[0088] Referring to Figure 7 , the initial conductive layer 126 and the initial cap layer 127 are etched with the first mask layer 260 as a mask to form a bit line body 120, the remaining initial conductive layer 126 serves as a conductive layer 121, and the remaining initial cap layer 127 serves as a cap layer 122.

[0089] In some embodiments, after the bit line body 120 is formed, the third sacrificial layer 240, the fourth sacrificial layer 250 and the first mask layer 260 can be removed.

[0090] In some embodiments, after the third sacrificial layer 240, the fourth sacrificial layer 250 and the first mask layer 260 are removed, a first isolation sub-layer 133 can be formed on the side wall of the bit line body 120.

[0091] In some embodiments, after forming the first isolation sublayer 133, a first filler layer 200 and a second filler layer 270 may be formed. The first filler layer 200 covers the surface of the first isolation sublayer 133, and the second filler layer 270 covers the surface of the first filler layer 200. It is understood that during the formation of the bit line body 120, there is a gap between the sidewall of the bit line body 120 and the substrate 100, and there are also gaps between the sidewall of the bit line body 120 and the first isolation layer 210 and the second isolation layer 220. These gaps can affect subsequent process steps. Therefore, by forming the first filler layer 200 and the second filler layer 270, the gaps between the sidewall of the bit line body 120 and the substrate 100, and the gaps between the sidewall of the bit line body 120 and the first isolation layer 210 and the second isolation layer 220, are filled, thereby facilitating subsequent process steps.

[0092] In some embodiments, the first isolation sublayer 133 may be a nitride layer, the first filling layer 200 may be an oxide layer, and the second filling layer 270 may be a nitride layer. That is, a NON (nitride-oxide-nitride) structure is formed on the sidewall of the bit line body 120. This can not only improve the insulation between adjacent bit line structures formed subsequently and reduce the parasitic capacitance of adjacent bit line structures, but also improve the insulation between the bit line structure and the word line structure 190 formed subsequently, and reduce the parasitic capacitance between the bit line structure and the word line structure 190.

[0093] refer to Figures 8 to 10 This forms a second isolation sublayer 134, which is located on the sidewall of the first isolation sublayer 133.

[0094] refer to Figure 8 The first filling layer 200 and the second filling layer 270 are etched to expose the sidewalls of the second isolation layer 220.

[0095] refer to Figure 9 This forms a second isolation sublayer 134, which covers the top surface of the second isolation layer 220 and the sidewalls of the first isolation sublayer 133.

[0096] refer to Figure 10 The second isolation sublayer 134 is etched to expose the surface of the second isolation layer 220.

[0097] refer to Figure 11 This forms a third isolation sublayer 135, which is located on the sidewall of the second isolation sublayer 134. Thus, the first isolation sublayer 133, the second isolation sublayer 134, and the third isolation sublayer 135 can be used as the first sidewall isolation layer of the bitline structure.

[0098] In some embodiments, the first isolation sub-layer 133, the first filling layer 200 and the second filling layer 270 can also be used as the first side wall isolation layer of the bit line structure, however, the way of etching the first filling layer 200 and the second filling layer 270 and then forming the second isolation sub-layer 134 and the third isolation sub-layer 135 can improve the reliability of the first side wall isolation layer, and the way of using the first isolation sub-layer 133, the first filling layer 200 and the second filling layer 270 as the first side wall isolation layer of the bit line structure can reduce the process steps.

[0099] Referring to Figures 12 to 20 , the initial contact plug 163 is formed. Figure 15 Figure 14 Referring to

[0100] In some embodiments, the method of forming the initial contact plug 163 can include: forming a dielectric layer 180, the dielectric layer 180 being located between adjacent bit line bodies 120 and being spaced apart from the first side wall isolation layer 130, and the dielectric layer 180, the first side wall isolation layer 130 and the substrate 100 enclosing a recess 280; forming the initial contact plug 163, the initial contact plug 163 being located in the recess 280. By forming the dielectric layer 180, a process basis can be provided for forming the initial contact plug 163, that is, the topography of the initial contact plug 163 is defined by the dielectric layer 180 and the bit line bodies 120, and by directly filling the material of the initial contact plug 163 into the recess 280 enclosed by the dielectric layer 180, the first side wall isolation layer 130 and the substrate 100, the process difficulty of forming the initial contact plug 163 can be reduced.

[0101] Referring to Figures 12 to 17 , the method of forming the dielectric layer 180 includes: forming a sacrificial layer 290, the sacrificial layer 290 being located between adjacent bit line bodies 120 and being in surface contact with the first side wall isolation layer 130; patterning the sacrificial layer 290 to form a first recess, and forming the dielectric layer 180, the dielectric layer 180 filling the first recess. By forming the sacrificial layer 290 and etching the sacrificial layer 290 to form the first recess, the topography of forming the dielectric layer 180 can be improved, so that the reliability of the semiconductor structure formed can be improved.

[0102] Referring to Figure 12 , the sacrificial layer 290 is formed.

[0103] Referring to Figure 13 , the sacrificial layer 290 is polished until the top surface of the sacrificial layer 290 is flush with the top surface of the bit line body 120.

[0104] Referring to Figure 14 and Figure 15 ​The protective layer 300 is formed on the top surface of the sacrificial layer 290 and the bit line body 120. The initial bit line structure 111 is protected by the protective layer 300, so that the initial bit line structure 111 is not affected by subsequent process steps.

[0105] In some embodiments, after the protective layer 300 is formed, a fifth sacrificial layer 310, a sixth sacrificial layer 320 and a second mask layer 330 are formed. The fifth sacrificial layer 310 is formed on the top surface of the protective layer 300. The sixth sacrificial layer 320 is formed on the top surface of the fifth sacrificial layer 310. The second mask layer 330 is formed on the top surface of the sixth sacrificial layer 320. The second mask layer 330 provides a process basis for forming the first recess.

[0106] Referring to Figure 16 and Figure 17 The sacrificial layer 290 is etched using the second mask layer 330 as a mask, and a dielectric layer 180 is formed to fill the first recess.

[0107] Referring to Figure 16 After the first recess is formed, the second mask layer 330, the sixth sacrificial layer 320 and the fifth sacrificial layer 310 are removed. After the second mask layer 330, the sixth sacrificial layer 320 and the fifth sacrificial layer 310 are removed, the dielectric layer 180 is formed. The dielectric layer 180 is also formed on the top surface of the protective layer 300.

[0108] Referring to Figure 17 The chemical mechanical polishing method is used to remove part of the dielectric layer 180 to expose the top surface of the protective layer 300.

[0109] Referring to Figures 18 to 20 The initial contact plug 163 is formed.

[0110] Referring to Figure 18 The protective layer 300 and the sacrificial layer 290 are removed. The first isolation layer 210 and the second isolation layer 220 are etched by the recess formed by removing the protective layer 300 and the sacrificial layer 290, until the active region in the substrate 100 is exposed. It can be understood that at this time, the dielectric layer 180, the first sidewall isolation layer 130 and the substrate 100 form the recess 280.

[0111] Referring to Figure 19 The contact plug material layer 164 is formed. The contact plug material layer 164 fills the recess 280 (see Figure 18 ), and the contact plug material layer 164 is also formed on the top surface of the dielectric layer 180 and the initial bit line structure 111.

[0112] Referring to Figure 20The partial contact plug material layer 164 is removed by combining chemical mechanical polishing and etch-back to form an initial contact plug 163. A top surface of the initial contact plug 163 is lower than a top surface of the initial bit line structure 111.

[0113] In some embodiments, a portion of the dielectric layer 180 can also be removed to make the top surface of the dielectric layer 180 flush with the top surface of the initial bit line structure 111. For example, a portion of the dielectric layer 180 is removed at the same time as a portion of the contact plug material layer 164 is removed by chemical mechanical polishing.

[0114] It should be noted that the flush here means that the top surface of the dielectric layer 180 is completely flush with the top surface of the initial bit line structure 111, or the height difference between the top surface of the dielectric layer 180 and the top surface of the initial bit line structure 111 is within the error allowable range (i.e. substantially flush), and the height difference between the top surface of the dielectric layer 180 and the top surface of the initial bit line structure 111 within the error allowable range can also be considered flush.

[0115] Reference is made to Figure 20 The second side wall isolation layer 140 is formed. It can be understood that after the second side wall isolation layer 140 is formed, the area of the initial landing pad on the top surface of the bit line structure 110 is increased in the subsequent process of forming the landing pad, that is, the process window for etching the initial landing pad is increased, and the short circuit between the subsequently formed landing pads 170 due to incomplete etching can be avoided, and the reliability of the formed landing pad is improved.

[0116] In some embodiments, the method of forming the second side wall isolation layer 140 can include: forming a second initial side wall isolation layer covering the top surface of the dielectric layer 180, a portion of the sidewall of the dielectric layer 180, and the top surface of the initial contact plug. Forming the second side wall isolation layer 140 by first forming the second initial side wall isolation layer and then etching can improve the morphology of the formed second side wall isolation layer 140.

[0117] In some embodiments, forming the second initial side wall isolation layer can be by atomic vapor deposition to form the second initial side wall isolation layer on the top surface of the dielectric layer 180, the sidewall of the dielectric layer 180, the top surface of the initial contact plug, and the sidewall and top surface of the bit line structure 110, and then removing the second initial side wall isolation layer on the top surface of the dielectric layer 180, the second initial side wall isolation layer on a portion of the top surface of the initial contact plug, and the second initial side wall isolation layer on the top surface of the bit line structure 110 by etching, and retaining the second initial side wall isolation layer on the sidewall of the dielectric layer 180 and the second initial side wall isolation layer on the sidewall of the bit line structure 110 as the second side wall isolation layer 140.

[0118] Reference is made to Figure 21The initial contact plug 163 is etched to form the contact plug 160 with the second sidewall isolation layer 140 as a mask. It can be understood that by etching part of the initial contact plug 163, part of the landing pad is located in the recess formed by etching the initial contact plug 163 in the subsequent process of forming the landing pad, so as to terminate the etching process in the subsequent process of etching the initial landing pad, and improve the reliability of the formed semiconductor structure.

[0119] With reference to Figures 22 to 24 And Figures 1 to 5 Wherein Figure 24 is Figure 23 The enlarged schematic diagram in the dashed box.

[0120] In some embodiments, the method of forming the landing pad 170 can include: forming an initial diffusion barrier layer 174 covering the top surface of the contact plug 160 and part of the surface of the bit line structure 110; forming an initial metal layer 175 covering the surface of the initial diffusion barrier layer 174; patterning the initial metal layer 175 and the initial diffusion barrier layer 174, and the remaining initial metal layer 175 and the initial diffusion barrier layer 174 as a diffusion barrier layer 171 and a metal layer 172, which together form the landing pad 170. The method of forming the initial diffusion barrier layer 174 and the initial metal layer 175 first and then etching can improve the topography of the formed landing pad 170.

[0121] In some embodiments, the method of patterning the initial metal layer 175 and the initial diffusion barrier layer 174 includes: forming a third mask layer 340 on the top surface of the initial metal layer 175, and etching the initial metal layer 175 and the initial diffusion barrier layer 174 with the third mask layer 340 as a mask to form the landing pad 170.

[0122] It can be understood that in the process of etching the initial metal layer 175 and the initial diffusion barrier layer 174, the second side wall isolation layer 140 will also be etched inevitably. In the related art, there is no second side wall isolation layer 140, so the first side wall isolation layer 130 will be etched in the process of etching the initial metal layer 175 and the initial diffusion barrier layer 174. As the etching continues, part of the impurities generated by etching may short the capacitor contact structure 150 and the bit line body 120 through the gap generated by etching the first side wall isolation layer 130, thereby shorting the capacitor contact structure 150 and the bit line structure 110. By setting the second side wall isolation layer 140, the thickness of the first part 131 of the first side wall isolation layer 130 can be increased, thereby reducing the probability of shorting the capacitor contact structure 150 and the bit line body 120 caused by impurities generated by etching. By forming the second side wall isolation layer 140, the length of the initial diffusion barrier layer 174 on the top surface of the bit line structure 110 can also be increased, thereby increasing the process window of etching the initial diffusion barrier layer 174, thereby reducing the difficulty of etching the initial diffusion barrier layer 174 and avoiding shorting of the adjacent landing pad 170 due to incomplete etching of the diffusion barrier layer 171.

[0123] In some embodiments, part of the initial metal layer 175 is located in the recess on the top surface of the contact plug 160. It can be understood that in the related art, the etching process of the initial metal layer 175 is usually difficult to control, and the initial metal layer 175 will be etched through in the etching process. However, etching the initial metal layer 175 through will inevitably etch part of the first side wall isolation layer 130 in the etching process, and the etching process of etching the first side wall isolation layer 130 is also difficult to control, so it may cause the metal layer 172 formed to be shorted with the bit line structure 110. By setting part of the initial metal layer 175 in the recess on the top surface of the contact plug 160, since the etching selectivity of the landing pad 170 and the contact plug 160 is large, too much contact plug 160 will not be etched in the etching process. Therefore, as the etching process proceeds, the etching process window width of etching the landing pad 170 is the first width D1 when etching starts, and the etching process window width of etching the landing pad 170 is the second width D2 when etching to expose the top surface of the protruding part 162. It can be seen that the etching process window is reduced. According to the etching load effect, the smaller the etching process window, the more difficult the etching is to proceed. Therefore, it is equivalent to controlling the etching of the landing pad 170 to stop. By setting the protruding part 162, the first side wall isolation layer 130 of the bit line structure 110 can be protected, and shorting between the bit line structure 110 and the landing pad 170 can be avoided.

[0124] The embodiments of the present disclosure can provide a limiting space for forming the initial contact plug 163 by forming the initial bit line structure 111, facilitate the formation of the initial contact plug 163, provide a process basis for forming the contact plug 160 by forming the initial contact plug 163, form the bit line structure 110 by forming the second side wall isolation layer 140 together with the initial bit line structure 111, and increase the top surface size of the bit line structure 110 by forming the second side wall isolation layer 140 on the sidewall of the initial bit line structure 111, thereby facilitating the subsequent formation of the landing pad, increasing the process window for forming the landing pad 170 by increasing the top surface size of the bit line structure 110, thereby facilitating the formation of the mutually spaced landing pads, avoiding the short circuit between adjacent landing pads 170, and thereby improving the reliability of the formed capacitor contact structure 150.

[0125] The embodiments of the present disclosure also provide a memory including the semiconductor structure as described above. It should be noted that the same or corresponding parts of the foregoing embodiments can refer to the corresponding description of the foregoing embodiments, which will not be described hereinafter.

[0126] It should be noted that the memory can be a storage unit or device based on a semiconductor device or component. For example, the memory device can be a volatile memory such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), a graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), a double data rate type two synchronous dynamic random access memory (DDR2 SDRAM), a double data rate type three synchronous dynamic random access memory (DDR3 SDRAM), a double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), a thyristor random access memory (TRAM), etc., or can be a non-volatile memory such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), etc.

[0127] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the embodiments of the present disclosure, and therefore the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a bit line structure on a surface of the substrate, the bit line structure comprising: a bit line body; a first sidewall isolation layer on a sidewall of the bit line body, the first sidewall isolation layer comprising a first portion close to the substrate and a second portion away from the substrate; a second sidewall isolation layer on the second portion of the first sidewall isolation layer; a capacitor contact structure on a side of the bit line structure, the capacitor contact structure comprising: a contact plug on a surface of the substrate, the contact plug covering the first portion of the first sidewall isolation layer, and a top surface of the contact plug being in contact with a bottom surface of the second sidewall isolation layer; a landing pad on the top surface of the contact plug, the landing pad also covering a surface of the second sidewall isolation layer, a portion of a top surface of the first sidewall isolation layer, and a portion of a top surface of the bit line body.

2. The semiconductor structure of claim 1, wherein, The contact plug comprises: a flat portion in contact with the substrate; a protruding portion on a top surface of the flat portion, and a top surface of the protruding portion being in contact with the bottom surface of the second sidewall isolation layer.

3. The semiconductor structure of claim 2, wherein, The flat portion and the protruding portion enclose a containing space, and the landing pad fills the containing space.

4. The semiconductor structure of claim 3, wherein, The landing pad comprises: a diffusion barrier layer covering a sidewall of the protruding portion and a surface of the second sidewall isolation layer, and the diffusion barrier layer also covering a top surface of the bit line structure; and a metal layer covering a surface of the diffusion barrier layer.

5. The semiconductor structure of claim 2, wherein, The bit line body extends along a first direction, and in a second direction perpendicular to the first direction, a width of the protruding portion is 0.05-0.15 of a width of the flat portion.

6. The semiconductor structure of claim 1, wherein, The bit line body extends along a first direction, and in a second direction perpendicular to the first direction, a width of the second sidewall isolation layer is 0.15-0.25 of a width of the first sidewall isolation layer.

7. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a dielectric layer between adjacent bit line structures, a sidewall of the dielectric layer being in contact with a sidewall of the capacitor contact structure.

8. The semiconductor structure of claim 7, wherein, The second sidewall isolation layer is also on a sidewall of the dielectric layer.

9. The semiconductor structure of claim 1, wherein, The first sidewall isolation layer comprises: a first sub-isolation layer on a sidewall of the bit line body; a second sub-isolation layer on a sidewall of the first sub-isolation layer; a third sub-isolation layer on a sidewall of the second sub-isolation layer.

10. The semiconductor structure of claim 1, wherein, The substrate comprises: an active region and an isolation structure defining the active region; the bit line body comprises: a conductive layer and a cap layer stacked in sequence; and the contact plug and the conductive layer are both in contact with the active region.

11. A method of fabricating a semiconductor structure, the method comprising: The semiconductor structure comprises: providing a substrate; forming an initial bit line structure on a surface of the substrate, the initial bit line structure comprising: a bit line body; a first sidewall isolation layer on a sidewall of the bit line body, the first sidewall isolation layer comprising a first portion close to the substrate and a second portion away from the substrate; forming an initial contact plug on a surface of the substrate and between adjacent initial bit line structures, the initial contact plug covering the first portion of the first sidewall spacer; forming a second sidewall spacer on the second portion of the first sidewall spacer, a bottom surface of the second sidewall spacer contacting a top surface of the initial contact plug, the second sidewall spacer and the initial bit line structure together forming a bit line structure; etching part of the initial contact plug with the second sidewall spacer as a mask, the remaining initial contact plug as a contact plug; forming a landing pad on a top surface of the contact plug, the landing pad also covering a surface of the second sidewall spacer, part of a top surface of the first sidewall spacer, and part of a top surface of the bit line body, the contact plug and the landing pad together forming a capacitor contact structure.

12. The method of fabricating a semiconductor structure of claim 11, wherein, The method of forming the initial contact plug comprises: forming a dielectric layer between the adjacent bit line bodies and spaced apart from the first sidewall spacer, the dielectric layer, the first sidewall spacer, and the substrate enclosing a recess; forming the initial contact plug in the recess.

13. The method of fabricating a semiconductor structure of claim 12, wherein, The method of forming the dielectric layer comprises: forming a sacrificial layer between the adjacent bit line bodies and in contact with a surface of the first sidewall spacer; patterning the sacrificial layer to form a first recess; forming a dielectric layer to fill the first recess.

14. The method of fabricating a semiconductor structure of claim 13, wherein, The method of forming the second sidewall spacer comprises: forming a second initial sidewall spacer covering a top surface of the initial bit line structure, part of a sidewall of the initial bit line structure, a top surface of the dielectric layer, part of a sidewall of the dielectric layer, and a top surface of the initial contact plug; etching back the second initial sidewall spacer, the remaining second initial sidewall spacer as the second sidewall spacer.

15. The method of fabricating a semiconductor structure of claim 11, wherein, The forming of the first sidewall spacer comprises: forming a first spacer sub-layer on a sidewall of the bit line body; forming a second spacer sub-layer on a sidewall of the first spacer sub-layer; forming a third spacer sub-layer on a sidewall of the second spacer sub-layer.

16. The method of fabricating a semiconductor structure of claim 11, wherein, The method of forming the landing pad comprises: forming an initial diffusion barrier layer covering a top surface of the contact plug and a surface of part of the bit line structure; forming an initial metal layer covering a surface of the initial diffusion barrier layer; patterning the initial metal layer and the initial diffusion barrier layer, the remaining initial metal layer and the initial diffusion barrier layer as a diffusion barrier layer and a metal layer, the diffusion barrier layer and the metal layer together forming the landing pad.

17. A memory, comprising: The semiconductor structure comprises any one of claims 1-10.

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