Synchronous reset de-assertion circuit

Abstract

The distribution of the reset signal across the system-on-chip (SoC) can be the highest latency signal in the circuit. Therefore, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. The reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronized reset signal as an output. The synchronized reset signal has a fixed timing relationship with the clock signal. When the reset signal is received, the clock signal can be paused. Therefore, the distribution of the synchronized reset signal can be performed without considering the latency of the signal. After all IP blocks have received the synchronized reset signal, the reset is de-asserted and the clock signal is restored.

Description

[0001] Cross - Reference to Related Applications

[0002] This application is a continuation of U.S. Patent Application Serial No. 17 / 491,745, filed on October 1, 2021, the content of which is incorporated herein by reference in its entirety. Background Art

[0003] A field - programmable gate array (FPGA) is an integrated circuit that is customized after manufacturing. The FPGA includes an array of logic blocks and more complex intellectual property (IP) blocks, and the logic blocks include elements such as lookup tables (LUTs), adders, and flip - flops.

[0004] A reset signal can be distributed to all the logic blocks on the FPGA. The reset signal resets each logic block to a known state. Brief Description of the Drawings

[0005] In the figures of the drawings, some embodiments of the disclosed technology are shown by way of example and not limitation.

[0006] Figure 1 is a schematic diagram of an example circuit chip fabric.

[0007] Figure 2 is a block diagram showing components of an example system for programming an FPGA.

[0008] Figure 3 is a schematic diagram of a synchronous reset de - assertion circuit according to various example embodiments.

[0009] Figure 4 is according to various example embodiments of Figure 3 a timing diagram of the synchronous reset de - assertion circuit.

[0010] Figure 5 is a schematic diagram of a synchronous reset de - assertion circuit according to various example embodiments.

[0011] Figure 6 is according to various example embodiments of Figure 5 a timing diagram of the synchronous reset de - assertion circuit.

[0012] Figures 7 to 9 is a schematic diagram of a synchronous reset de - assertion circuit according to various example embodiments.

[0013] Figure 10 is according to various example embodiments of Figures 7 to 9 a timing diagram of the synchronous reset de - assertion circuit.

[0014] Figure 11is a block diagram showing components of an FPGA including a synchronous reset de-assertion circuit according to various example embodiments. Detailed Description

[0015] Example methods, systems, and circuits for synchronously de-asserting a reset signal to multiple IP blocks of a system-on-chip (SoC), such as an FPGA or an application specific integrated circuit (ASIC), will now be described. In the following description, numerous examples with example specific details are set forth to provide an understanding of the examples. However, it will be apparent to those of ordinary skill in the art that the examples may be practiced without these example specific details and / or with a combination of details different from those given herein. Thus, specific examples are given for purposes of illustration rather than limitation.

[0016] IP blocks on an SoC typically provide functionality by receiving inputs and generating outputs. Additionally, these IP blocks typically receive a clock signal and a reset signal. When the reset signal is asserted (e.g., set to a low voltage value), the IP block stops performing its normal operation and resets its internal and output states to a known initialization state. For example, an accumulator may receive an input indicating whether to increment or not increment an accumulated value by 1 at each clock cycle. The output of the accumulator may be a representation of the accumulated value. When the reset is asserted, the accumulated value is reset to 0.

[0017] In many circuit designs, the reset signal distributed across an SoC is the signal with the highest latency in the circuit. Thus, the operating frequency of the device is reduced to ensure that the reset signal reaches all IP blocks during a single clock cycle. By using the circuits and methods described herein, when the reset signal is received, the clock signal is paused. Thus, the distribution of the reset signal can be performed without considering signal latency. After all IP blocks have received the reset signal, the reset is de-asserted (e.g., set to a high voltage value), and the clock signal is resumed. De-assertion of the reset signal refers to changing the state of the reset signal to the value that the receiving IP block expects for normal (non-reset) operation.

[0018] The input reset signal is asynchronous. Thus, the relative timing of the rising or falling clock edge with respect to the change in the input reset value is not restricted. For example, this may be caused by pressing a physical reset button that is independent of the internal clock generation circuit. Depending on the relative timing of the change in the input signal value with respect to the next clock edge, a different amount of time will be retained in the clock cycle to propagate the input reset signal to the IP blocks. Thus, various IP blocks will receive the reset signal before the next clock edge, while other IP blocks will receive the reset signal after the next clock edge, where the exact partitioning of the IP blocks depends on the precise time at which the input reset is received. This may lead to unpredictable behavior during transitions where some IP blocks are reset while others are not.

[0019] The reset synchronizer receives a clock signal and a reset signal as inputs and generates a synchronized reset signal as an output. The synchronized reset signal has a fixed timing relationship with the clock signal. Thus, the duration before the next clock edge can be selected as the entire clock cycle, maximizing the time for the synchronized reset signal to propagate to the synchronous elements in the IP block before the next clock edge.

[0020] The clock gating circuit receives a clock signal and a control signal as inputs. If the control signal activates the clock gating circuit, the clock gating circuit passes the clock signal. If the control signal deactivates the clock gating circuit, the clock gating circuit provides a constant output instead of the clock signal.

[0021] The saturation counter receives a clock signal and a reset signal as inputs, maintains an internal counter value and a fixed maximum value, and generates a signal indicating whether the internal counter value is equal to the fixed maximum value. When the reset signal is not asserted, the internal counter value increments at each clock cycle until it reaches the fixed maximum value. When the reset signal is asserted, the internal counter value is reset to 0.

[0022] In some example embodiments, a single saturation counter is used. The synchronized reset signal and the clock signal are provided as inputs to the saturation counter. The output of the saturation counter is used as the control signal for the clock gating circuit. Thus, the clock signal is disabled when the synchronized reset signal is asserted and is not re-enabled until a predetermined period after the synchronized reset signal is de-asserted. Thus, reset de-assertion is allowed to propagate to all IP blocks before the clock signal resumes.

[0023] In some example embodiments, two saturation counters are used. The second saturation counter allows the clock gating circuit to ungate the clock for a first predetermined number of clock cycles when the reset is asserted and also disables the clock signal for a second predetermined number of clock cycles after the reset is de-asserted. This provides support for IP blocks that utilize clock edges when the reset is asserted.

[0024] Additional saturation counters can be used to provide additional states during reset. For example, reset can be asserted and the clock disabled during a first state, reset can be asserted and the clock enabled during a second state, reset can be asserted and (again) the clock disabled during a third state, reset can be de-asserted and the clock disabled during a fourth state, and reset can be de-asserted and the clock enabled during a fifth state. Depending on the IP blocks controlled by the synchronized reset de-assertion circuit, the duration of each state and the specific states being used can be selected.

[0025] Figure 1FIG. 0 is a schematic diagram of an exemplary circuit chip configuration 100 according to various examples of the present invention. Configuration 100 includes a programmable array of logic blocks 101 that support various programmable logic functions. Routing tracks 102 in configuration 100, which are shown as a plurality of orthogonally oriented tracks, are used to carry electrical signals and implement reconfigurable interconnects between logic blocks 101. The main elements of the flexible routing architecture for interconnecting the routing tracks and configuring the logic blocks include connection boxes 110 and switch boxes 111.

[0026] In an implementation, switch box 111 can be a switch that connects wire to wire (e.g., wires in horizontal routing tracks and vertical routing tracks: wires in horizontal tracks are connected to wires in horizontal tracks, wires in vertical tracks are connected to wires in vertical tracks, and wires in horizontal tracks are connected to wires in vertical tracks). Connection box 110 can be a switch that connects wires in horizontal and / or vertical tracks to elements of logic block 101. For illustrative purposes, only exemplary elements are labeled in the drawings. However, one of ordinary skill in the art will understand that routing tracks 102, connection boxes 110, and switch boxes 111 can actually be replicated on the surface of the semiconductor chip to provide the desired interconnect functionality.

[0027] The structure of connection box 110 and switch box 111 determines the connection of routing tracks 102 to logic block 101, and thus determines the functionality of semiconductor chip 120 that includes them. For example, semiconductor chip 120 that includes configuration 100 can be configured as an FPGA, such as the type available from Achronix TM , Xilinx TM , Altera TM and other vendors.

[0028] In some examples, the reset signal and clock signal to logic block 101 are mediated by synchronous reset de-assertion circuit 120. Thus, the operating frequency of configuration 100 can be determined based on the propagation delays of input and output signals among logic blocks 101, regardless of the propagation delay of the reset signal. The increase in the operating frequency improves the functionality of configuration 100.

[0029] Figure 2 FIG. 19 is a block diagram showing components of a computer 200 for programming an FPGA according to some examples. Not all components need to be used in various embodiments. For example, clients, servers, autonomous systems, and cloud-based network resources can each use different sets of components, or in the case of a server, for example, a larger storage device can be used.

[0030] An example computing device (also referred to as computing device 200 and computer system 200) in the form of computer 200 can include a processor 205, a memory storage 210, a removable storage 215, and a non-removable storage 220, all connected by a bus 240. Although the example computing device is shown and described as a computer 200, in different embodiments, the computing device can take different forms. For example, the computing device can alternatively be a smart phone, a tablet computer, a smart watch, or another computing device including elements the same as or similar to the elements shown and described with respect to Figure 2 devices such as smart phones, tablet computers, and smart watches are collectively referred to as "mobile devices". In addition, although various data storage elements are shown as part of computer 200, the storage can also or alternatively include cloud-based storage accessible via a network such as the Internet, or server-based storage.

[0031] Memory storage 210 can include volatile memory 245 and non-volatile memory 250, and can store a program 255. Computer 200 can include or be able to access a computing environment including various computer-readable media such as volatile memory 245, non-volatile memory 250, removable storage 215, and non-removable storage 220. Computer storage includes random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM), flash memory, or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), or other optical disc storage, magnetic cassettes, magnetic tape, magnetic disk storage, or other magnetic storage devices, or any other medium capable of storing computer-readable instructions.

[0032] The computer 200 may include or be able to access a computing environment including an input interface 225, an output interface 230, and a communication interface 235. The output interface 230 may interface to or include a display device that can also be used as an input device, such as a touch screen. The input interface 225 may interface to or include one or more of the following: a touch screen, a touchpad, a mouse, a keyboard, a camera device, one or more device-specific buttons, one or more sensors integrated within the computer 200 or coupled to the computer 200 via a wired or wireless data connection, and other input devices. The computer 200 may operate in a networked environment using the communication interface 235 to connect to one or more remote computers, such as a database server. The remote computers may include personal computers (PCs), servers, routers, network PCs, peer devices, or other common network nodes, etc. The communication interface 235 may connect to a local area network (LAN), a wide area network (WAN), a cellular network, a WiFi network, a Bluetooth network, or other networks.

[0033] Computer instructions stored on a computer-readable medium (e.g., the program 255 stored in the memory storage device 210) may be executed by the processor 205 of the computer 200. Hard disk drives, CD-ROMs, and RAM are some examples of articles of manufacture including non-transitory computer-readable media such as storage devices. To the extent that a carrier wave is considered too transitory, the terms "computer-readable medium" and "storage device" do not include carrier waves. "Computer-readable non-transitory media" includes all types of computer-readable media, including magnetic storage media, optical storage media, flash media, and solid-state storage media. It should be understood that software may be installed in a computer and sold with the computer. Alternatively, the software may be obtained and loaded into the computer, including obtaining the software through a physical medium or a distribution system, including, for example, obtaining the software from a server owned by the software creator or from a server not owned by but used by the software creator. The software may be stored on a server for distribution, for example, via the Internet.

[0034] The program 255 is shown as including a configuration module 260 and a placement and routing module 265. Any one or more of the modules described herein may be implemented using hardware (e.g., a processor of a machine, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or any suitable combination thereof). Additionally, any two or more of these modules may be combined into a single module, and the functions described herein for a single module may be subdivided among multiple modules. Further, according to various examples, modules described herein as being implemented within a single machine, database, or device may be distributed across multiple machines, databases, or devices.

[0035] The configuration module 260 provides a user interface to allow a user to configure the FPGA. For example, the user interface may allow the user to identify a hardware design language (HDL) file specifying the configuration.

[0036] The place and route module 265 programs the FPGA based on the configuration. For example, the connection boxes 110, the switch boxes 111, and the routing tracks 102 may be configured. As another example, the connections to and from the LUTs, and their contents (i.e., the specific outputs generated for each input combination) may be configured.

[0037] Figure 3 FIG. 7 is a schematic diagram of a synchronous reset (RSTN) de-assertion circuit 300 according to various embodiments of the present invention. The synchronous reset de-assertion circuit 300 includes a saturation counter 310, a reset synchronizer 360, and a clock (CLK) gating circuit 380. The reset synchronizer 360 includes flip-flops 370A, 370B, and 370C. The saturation counter 310 includes an incrementer 320, a multiplexer 330, a counter 340, and a comparator 350. The synchronous reset de-assertion circuit 300 receives a clock input (I_CLKIN) and a reset input (I_RSTN), and provides a clock output (O_CLKOUT) and a reset output (O_RSTN). For ease of connection visibility, the I_RSTN and O_RSTN connections are shown as dashed lines.

[0038] I_CLKIN is provided to each of the saturation counter 310, the reset synchronizer 360, and the clock gating circuit 380. I_RSTN is provided only to the reset synchronizer 360. In Figure 3 the example, the reset signal is active low. It will be apparent to those of ordinary skill in the art that active high signals are supported with minor modifications.

[0039] When I_RSTN is asserted, each of the flip-flops 370A to 370C is reset, setting the stored value of the flip-flop to 0. The output (SYNC_RSTN) of the flip-flop 370C is provided as the reset output of the synchronous reset de-assertion circuit 300. Thus, once I_RSTN is asserted, O_RSTN is also asserted.

[0040] When I_RSTN is deasserted, the values of flip-flops 370A to 370C are initially 0. The value of flip-flop 370A is set to 1 in the next clock cycle. In the following two clock cycles, the 1 value propagates to flip-flop 370B and then to flip-flop 370C. Thus, after three clock cycles, the output of flip-flop 370C changes to 1 and the output reset signal is deasserted. By using flip-flops 370A to 370C, the deassertion of the output reset signal is synchronized with the clock edge. In various example embodiments, more or fewer flip-flops are used in the reset synchronizer 360 to vary the number of cycles before the deassertion of O_RSTN.

[0041] When the reset signal (RSTN) of the saturation counter 310 is asserted, the counter 340 is set to 0. When RSTN is deasserted, as long as the value of the counter 340 is not equal to the predefined value P, the output of the comparator 350 causes the multiplexer 330 to select the output of the incrementer 320 as the next value of the counter 340.

[0042] The comparator 350 of the saturation counter 310 compares the value of the counter 340 with P and generates a P_COUNTER_DONE signal indicating whether the comparison values are equal. When P_COUNTER_DONE is true, the multiplexer 330 bypasses the incrementer 320, thereby holding the value of the counter 340 at P. Thus, in each clock cycle, the value of the counter 340 is incremented by 1 until the value of the counter 340 reaches the predefined value P. If the counter is equal to the predefined value P, the comparator 350 causes the clock gating circuit (ICG) 380 to pass I_CLKIN as O_CLKOUT. Otherwise, the comparator 350 causes the clock gating circuit 380 to output a constant value (e.g., a logic 0 value), thereby disabling O_CLKOUT.

[0043] By using the saturation counter 310, after the output reset signal is deasserted, the output clock signal remains disabled for a predetermined period of time. This predetermined delay allows components of the circuit receiving the output reset signal and the output clock signal to detect the reset deassertion signal before the clock cycle resumes. Thus, the circuit can operate correctly even if the reset signal cannot be distributed across the circuit in a single clock cycle.

[0044] Figure 3 An example embodiment showing the use of the saturation counter 310 to control the predetermined delay between the time when the I_RSTN signal is deasserted and the time when the O_RSTN signal is deasserted is shown. In an alternative embodiment, a finite state machine is used instead of the saturation counter. The pseudo-Verilog for such an implementation is shown below.

[0045]

[0046]

[0047] Electronic design automation (EDA) tools can generate Figure 3 a saturating counter or another physical implementation in response to the above HDL description of the finite state machine.

[0048] Figure 4 is according to various embodiments of the present invention Figure 3 a timing diagram of the synchronous reset de-assertion circuit. Figure 4 The timing diagram shows the I_CLKIN timing 410, I_RSTN timing 420, SYNC_RSTN timing 430, P_COUNTER timing 440, P_COUNTER_DONE timing 450, CG_EN timing 460, O_CLKOUT timing 470, and O_RSTN timing 480.

[0049] The I_CLKIN timing 410 shows a stable clock signal input to the synchronous reset de-assertion circuit 300. The rising clock edges are numbered 0 to 27.

[0050] The I_RSTN timing 420 shows that for a first period, the input reset signal is inactive, then the reset is asserted near clock cycle 3, and the reset is de-asserted near clock cycle 13. The duration of the assertion of the input reset signal is controlled outside the synchronous reset de-assertion circuit 300 and can be longer or shorter than Figure 4 the duration shown.

[0051] The SYNC_RSTN timing 430 shows that the SYNC_RSTN signal output from the reset synchronizer 360 is initially inactive but becomes active once the I_RSTN signal becomes active. There is a delay after the input reset signal is de-asserted and before the SYNC_RSTN signal is de-asserted. As discussed above with respect to Figure 3 when using three flip-flops 370A to 370C, the delay is three clock cycles.

[0052] The P_COUNTER timing 440 shows the value of the counter 340. When the SYNC_RSTN signal received by the saturating counter 310 as a reset signal is asserted, the value of the counter is reset to 0. The counter 340 does not start incrementing the value until the next clock edge after the SYNC_RSTN signal is de-asserted. Therefore, the duration of the period during which the counter is 0 is controlled by the duration of the assertion of the input reset signal and the delay of the reset synchronizer 360. Thereafter, the value is incremented by 1 each clock cycle until a predefined value of P is reached. The duration of the period during which the counter has a value between 0 and P is determined by the value of P and the clock frequency.

[0053] The P_COUNTER_DONE timing 450 shows that when P_COUNTER is equal to P, this signal is set to 1, otherwise it is set to 0. The CG_EN timing 460 is the same as the P_COUNTER_DONE timing 450 because in Figure 3 the example circuit of, the control signal to the clock gating circuit 380 is coupled to the P_COUNTER_DONE signal from the saturation counter 310.

[0054] The O_CLKOUT timing 470 shows that when the CG_EN signal is asserted, the output clock signal is equal to the clock input, otherwise it is logic 0. Therefore, during the entire period when the reset is asserted and for a predetermined period after that, the output clock signal is disabled.

[0055] The O_RSTN timing 480 is the same as the SYNC_RSTN timing 430 because in Figure 3 the example circuit of, the output reset signal is coupled to the SYNC_RSTN signal from the reset synchronizer 360.

[0056] Figure 5 is a schematic diagram of a synchronous reset de-assertion circuit 500 according to various example embodiments. The synchronous reset de-assertion circuit 500 includes a saturation counter 310, a reset synchronizer 360, a clock gating circuit 380, a saturation counter 510, an XNOR gate 580, and a multiplexer 570. As Figure 3 shown, the reset synchronizer 360 includes flip-flops 370A, 370B, and 370C. The saturation counter 310, the reset synchronizer 360, and the clock gating circuit are described above with reference to Figure 3 although the connections between the components are different in Figure 5 . For ease of viewing the connections, the reset input (I_RSTN) and reset output (O_RSTN) connections are shown as dashed lines.

[0057] The clock input (I_CLKIN) is provided to each of the saturation counter 310, the reset synchronizer 360, the clock gating circuit 380, and the saturation counter 510. The I_RSTN is only provided to the reset synchronizer 360. In Figure 5 the example of, the reset signal is active low. It will be apparent to those of ordinary skill in the art that high active signals are supported with minor modifications.

[0058] When the I_RSTN is asserted, the SYNC_RSTN signal is asserted. When the input reset signal is de-asserted, the SYNC_RSTN signal is de-asserted after a delay synchronized with the clock edge.

[0059] The comparator 550 of the saturation counter 510 compares the value of the counter 540 with a predefined value (N) and generates an N_COUNTER_DONE signal indicating whether the comparison values are equal. If the counter 540 is equal to the predefined value N, the comparator 550 sets the reset signals RSTN and O_RSTN input to the saturation counter 310 to logic 1, thereby de-asserting the reset signals. Otherwise, the comparator 350 causes the clock gating circuit 380 to output a logic 0 value, thereby asserting the reset.

[0060] When the reset signal RSTN of the saturation counter 510 is asserted, the counter 540 is set to 0. When the reset signal RSTN of the saturation counter 510 is de-asserted, as long as the value of the counter 540 is not equal to the predefined value N, the comparator 550 causes the multiplexer 530 to select the output of the incrementer 520 as the next value of the counter 540. Therefore, in each clock cycle, the value of the counter 540 is incremented by 1 until the value of the counter 540 reaches the predefined value N. When the value of the counter 540 is equal to the predefined value N of the comparator 550, O_RSTN is de-asserted. During the period when the value of the counter 540 is not equal to the predefined value N, O_RSTN is asserted.

[0061] Therefore, when I_RSTN is asserted, SYNC_RSTN is asserted without delay, and N_COUNTER_DONE becomes logic 0, thereby asserting O_RSTN. When I_RSTN is de-asserted, SYNC_RSTN is de-asserted with a delay, and N_COUNTER_DONE becomes logic 1 after an additional predefined delay of N clock cycles, thereby de-asserting O_RSTN.

[0062] The N_COUNTER_DONE signal is also an input to the XNOR gate 580 and is used as a reset input to the saturation counter 310. When N_COUNTER_DONE is low, the saturation counter 310 is reset, and the P_COUNTER_DONE output is low. Therefore, both the N_COUNTER_DONE and P_COUNTER_DONE inputs to the XNOR gate 580 are low, and the output of the XNOR gate 580 is high. The multiplexer 570 selects between a constant logic 0 value and the output of the XNOR gate 580.

[0063] Thus, when SYNC_RSTN is de-asserted and N_COUNTER_DONE and P_COUNTER_DONE are equal, the output of multiplexer 570 is only logic 1. The output of multiplexer 570 is coupled to the CG_EN input of clock gating circuit 380. Thus, although N_COUNTER_DONE is logic 0 (resetting saturation counter 310 and forcing P_COUNTER_DONE to also be logic 0), O_CLKOUT is enabled. Thus, O_CLKOUT is enabled for N cycles while O_RSTN is asserted.

[0064] After saturation counter 510 has finished counting N clock cycles, N_COUNTER_DONE becomes a logic 1 value and O_RSTN is de-asserted. Saturation counter 310 begins counting P clock cycles. Until P clock cycles are complete, the P_COUNTER_DONE value is logic 0. When the N_COUNTER_DONE signal is logic 1 and the P_COUNTER_DONE value is logic 0, the output of XNOR gate 580 is 0. When SYNC_RSTN is logic 1, the output of XNOR gate 580 is selected as the output of multiplexer 570. Thus, when SYNC_RSTN is de-asserted, saturation counter 510 has counted N clock cycles, and saturation counter 310 has not counted P clock cycles, the CG_EN signal to clock gating circuit 380 disables O_CLKOUT.

[0065] O_CLKOUT remains disabled for a predetermined period of P clock cycles until the value of P_COUNT_DONE changes. Once both P_COUNTER_DONE and N_COUNTER_DONE are logic 1 values, the output of XNOR gate 580 becomes logic 1, thus changing the CG_EN signal to clock gating circuit 380 and enabling O_CLKOUT.

[0066] Thus, like synchronous reset de-assertion circuit 300, synchronous reset de-assertion circuit 500 delays the recovery of the clock signal after de-asserting the reset signal to allow the reset signal to propagate to all parts of the circuit. Additionally, synchronous reset de-assertion circuit 500 allows a predetermined number of clock cycles to be provided to the circuit while the reset signal is asserted. Some circuit components can use these clock cycles to perform more complex reset operations. As a simple example, a component can store the sum of its inputs. When reset is asserted, the input values are reset to 0, but the stored sum is not reset until a clock cycle is received and an updated addition operation is performed.

[0067] Figure 5An example implementation of controlling predetermined delays N and P using two saturation counters is shown. In an alternative implementation, a finite state machine is used instead of the saturation counters. The pseudo-Verilog for such an implementation is shown below.

[0068]

[0069]

[0070] The EDA tool can generate Figure 5 a saturation counter or another physical implementation in response to the above HDL description of the finite state machine.

[0071] Figure 6 is the Figure 5 timing diagram of the synchronous reset de-assertion circuit according to various embodiments of the present invention. Figure 6 The timing diagram shows the I_CLKIN timing 610, I_RSTN timing 620, SYNC_RSTN timing 630, N_COUNTER timing 640, P_COUNTER timing 650, N_COUNTER_DONE timing 660, P_COUNTER_DONE timing 670, CG_EN timing 680, O_CLKOUT timing 690, and O_RSTN timing 695.

[0072] The I_CLKIN timing 610 shows a stable clock signal input to the synchronous reset de-assertion circuit 500. The rising clock edges are numbered from 0 to 27.

[0073] The I_RSTN timing 620 shows that for a first period, the input reset signal is inactive, and then the reset is asserted near clock cycle 3 and de-asserted near clock cycle 8. The duration of the assertion of the input reset signal is controlled outside the synchronous reset de-assertion circuit 500 and can be longer or shorter than Figure 6 the duration shown.

[0074] The SYNC_RSTN timing 630 shows that the SYNC_RSTN signal output from the reset synchronizer 360 is initially inactive but becomes active once the I_RSTN signal becomes active. There is a delay after the input reset signal is de-asserted and before the SYNC_RSTN signal is de-asserted. As discussed above with respect to Figure 3 when using three flip-flops 370A to 370C, the delay is three clock cycles.

[0075] The N_COUNTER timing 640 shows the value of counter 540. When the SYNC_RSTN signal received by the saturation counter 510 as a reset signal is asserted, the value of the counter is reset to 0. The counter 540 does not start incrementing the value until the next clock edge after the SYNC_RSTN signal is de-asserted. Thus, the duration of the period during which the counter is 0 is controlled by the duration of the assertion of the input reset signal and the delay of the reset synchronizer 360. Thereafter, the value is incremented by 1 each clock cycle until a predefined value of N is reached. The duration of the period during which the counter has a value between 0 and N is determined by the value of N and the clock frequency. The N_COUNTER_DONE timing 660 shows that this signal is set to 1 when N_COUNTER is equal to N, and 0 otherwise.

[0076] The P_COUNTER timing 650 shows the value of counter 340. When the N_COUNTER_DONE signal received by the saturation counter 310 as a reset signal is asserted, the value of the counter is reset to 0. The counter 340 does not start incrementing the value until the next clock edge after the N_COUNTER_DONE signal is de-asserted. Thus, the duration of the period during which the counter is 0 is controlled by the duration of the assertion of the input reset signal, the delay of the reset synchronizer 360, and the delay of the saturation counter 510. Thereafter, the value is incremented by 1 each clock cycle until a predefined value of P is reached. The duration of the period during which the counter has a value between 0 and P is determined by the value of P and the clock frequency. The P_COUNTER_DONE timing 670 shows that this signal is set to 1 when P_COUNTER is equal to P, and 0 otherwise.

[0077] The CG_EN timing 680 shows that the clock is disabled when the I_RSTN signal is received, and re-enabled within N clock cycles when SYNC_RSTN is not asserted and N_COUNTER_DONE is logic 0. The CG_EN signal is enabled after the P_COUNTER_DONE signal goes high, until the next time I_RSTN is asserted.

[0078] The O_CLKOUT timing 690 shows that the output clock signal is equal to the clock input when the CG_EN signal is asserted, and logic 0 otherwise. Thus, the output clock signal is disabled when SYNC_RSTN is asserted, enabled within N clock cycles thereafter, disabled within P clock cycles, and then enabled again thereafter. Thus, by selecting the values of P and N, the total delay after SYNC_RSTN assertion is selected, as well as the portion of that delay that includes the active clock output.

[0079] The O_RSTN timing 695 is the same as the N_COUNTER_DONE timing 660 because in the example circuit of Figure 5 the output reset signal is coupled to the N_COUNTER_DONE signal from the saturation counter 510.

[0080] Figures 7 to 9 is a schematic diagram of a synchronous reset de-assertion circuit 700 according to various example embodiments. The synchronous reset de-assertion circuit 700 includes a state decoder 705, which includes an incrementer 710, a multiplexer 715, a counter 720, AND gates 725, 740, 745, 750, 755, 760, 765, 770, and 775, and an OR gate 730. The synchronous de-assertion circuit 700 also includes a reset synchronizer 910 ( Figure 9 shown) and a clock gating circuit 380 ( Figure 3 shown), the reset synchronizer is used to generate the SYNC_RSTN signal received by the state decoder 705, and the clock gating circuit generates an output clock signal based on a clock input and a CG_EN signal. The reset synchronizer 910 also generates a MY_RSTN signal. The CG_EN signal is generated by the OR gate 785. Another output of the synchronous de-assertion circuit 700 is an output reset signal O_RSTN generated by the OR gate 780. The N counter 800, the Q counter 830, and the P counter 860, all shown in Figure 8 are also part of the synchronous de-assertion circuit 700, thus generating NDONE, QDONE, and PDONE signals received by the state decoder 705 as inputs. For better visibility, some internal connections are labeled instead of being indicated by lines.

[0081] In response to an input reset signal, the MY_RSTN signal is placed in an active state by the reset synchronizer 910 within a single clock cycle and then de-asserted. In response to the MY_RSTN signal, the state decoder 705, the N counter 800, the Q counter 830, and the P counter 860 are all reset. Once the MY_RSTN signal is de-asserted, these circuits return to operation even if the input reset signal remains asserted.

[0082] The N counter 800 includes an incrementer 805, a multiplexer 810, an AND gate 815, a counter 820, and a comparator 825. When the value of the counter 820 is not equal to N - as determined by the comparator 825 - and the SN signal is valid, the multiplexer 810 selects the output of the incrementer 805 as the input to the counter 820, such that the counter 820 increments its value with each clock cycle. When the value of the counter 820 is equal to N, the NDONE output signal goes high. In response to the MY_RSTN signal, the value of the counter 820 is reset to 1.

[0083] The Q counter 830 includes an incrementer 835, a multiplexer 840, an AND gate 845, a counter 850, and a comparator 855. The operation of the Q counter 860 is similar to that of the N counter 800. Similarly, the P counter 860 includes an incrementer 865, a multiplexer 870, an AND gate 875, a counter 880, and a comparator 885, and operates in a manner similar to the N counter 800 and the Q counter 830.

[0084] The state decoder 705 activates one of the output signals SN, SP, SW, SQ, and SU at any given time. The active output signal indicates whether the current state is the N state, the P state, the wait state, the Q state, or the user state. The AND gates 725 and 740 to 755, in combination with the OR gate 730, control the multiplexer 715. When the output of the AND gate 725 is 1, the multiplexer 715 selects the output of the incrementer 710 as the next value of the counter 720, thereby incrementing the state of the state decoder 705. Otherwise, the value of the counter 720 remains unchanged.

[0085] Whenever any of the following conditions is satisfied, the AND gates 740 to 755 will cause the output of the OR gate 730 to be 1: the current state of the state decoder 705 is the N state and NDONE is asserted by the N counter 800; the current state of the state decoder 705 is the P state and PDONE is asserted by the P counter 860; the current state of the state decoder 705 is the wait state and the SYNC_RSTN signal is de-asserted; or the current state of the state decoder 705 is the Q state and QDONE is asserted by the Q counter 830. When the state decoder 705 is in the user state, the AND gate 725 prevents the state of the state decoder 705 from being changed.

[0086] The AND gates 760 to 775 determine which of the five states the state decoder 705 is in based on the 3-bit value from the counter 720. As can be seen by examining the inverters on the inputs of the AND gates 760 to 775, the SN signal is asserted when S[1:0] is 0, the SP signal is asserted when S[1:0] is 1, the SW signal is asserted when S[1:0] is 2, and the SQ signal is asserted when S[1:0] is 3. The SU signal is asserted when S[2] is 1.

[0087] Accordingly, when the MY_RSTN signal is received, the counter 720 is reset and then moves through the N counter, P counter, wait, Q counter, and user state. When the state decoder 705 is in the Q state or user state, the O_RSTN signal is generated by the OR gate 780. When the state decoder 705 is in the P state or user state, the CG_EN signal is generated by the OR gate 785. Accordingly, in the N state, the synchronous reset de-assertion circuit 700 asserts the active-low reset signal and disables the clock signal. In the P state, the synchronous reset de-assertion circuit 700 continues to assert the active-low reset signal but enables the clock signal. During the wait state, the synchronous reset de-assertion circuit 700 continues to assert the active-low reset signal and disables the clock signal. When the SYNC_RSTN signal is de-asserted, the wait state is retained, at which point it enters the Q state and the O_RSTN signal is de-asserted. After Q clock cycles, QDONE is asserted, it enters the user state, O_RSTN is raised (reset signal de-asserted), and CG_EN is enabled, thereby restoring the circuit controlled by the synchronous reset de-assertion circuit 700 to its normal operating function.

[0088] The following pseudo-Verilog can be used to generate the state decoder 705.

[0089]

[0090]

[0091]

[0092] The above state machine can be easily extended to add additional states and counters. For example, if there is a requirement for a state between WAIT and Q_COUNTING such that the clock is turned on again when "i_async_rstn" is de-asserted but before "o_rstn" is de-asserted, the following "R_COUNTING" state can be added and the WAIT_FOR_I_RST_DEASSERT and Q_COOUNTING states can be modified appropriately.

[0093]

[0094]

[0095] It should also be noted that due to the richness of the synthesizable subset of the language features of Verilog available to the designer, there are many widely accepted ways to describe state machines in HDLs such as Verilog. Additionally, other HDLs such as VHDL bring their own styles of specifying state machines to the fore. However, for those of ordinary skill in the art, translating the above state machines into different HDLs or HDL styles would be straightforward, and the above pseudo-HDLs should be regarded as exemplary implementations of only the key features of the state machines. It should further be noted that the counters in the state machines can be implicitly (via a hardware synthesis tool) or explicitly reduced to a single counter with appropriate control signals and a maximum counting ability max(N, P, Q,...).

[0096] The reset synchronizer 910 includes flip-flops 920A, 920B, and 920C and an OR gate 930. For inputs, the reset synchronizer 910 receives an input clock signal (I_CLK) and an asynchronous reset signal (I_RSTN). The reset synchronizer 910 generates SYNC_RSTN signal and MY_RSTN signal as outputs. As discussed above with respect to Figures 7 to 8 what was discussed, in response to the I_RSTN signal being asserted, the MY_RSTN signal is asserted within a single clock cycle. The flip-flops 920A to 920C introduce a three-clock-cycle delay between receiving the I_RSTN signal and asserting the SYNC_RSTN signal. The OR gate 930 causes the MY_RSTN signal to be asserted only during the clock cycle in which the output of the flip-flop 920B has been changed by the propagation of the I_RSTN signal while the output of the flip-flop 920C has not changed. As soon as the I_RSTN signal has completed its propagation through the flip-flops 920A to 920C, the OR gate 930 disables the MY_RSTN signal.

[0097] Figure 10 is according to various embodiments of the present invention Figures 7 to 9 of the synchronization reset de-assertion circuit 700. Figure 10 The timing diagram shows the I_CLKIN timing 1005, I_RSTN timing 1010, SYNC_RSTN timing 1015, MY_RSTN timing 1020, N_COUNTER timing 1025, P_COUNTER timing 1030, Q_COUNTER timing 1035, state timing 1040, O_RSTN timing 1045, CG_EN timing 1050, and O_CLKOUT timing 1055.

[0098] The I_CLKIN timing 1005 shows the stable clock signal input to the synchronization reset de-assertion circuit 700. The rising clock edges are numbered from 0 to 27.

[0099] The I_RSTN timing 1010 shows that for the first time period, the input reset signal is invalid, then the reset is asserted around clock cycle 3, and the reset is de-asserted around clock cycle 15. The duration of the assertion of the input reset signal is controlled outside the synchronous reset de-assertion circuit 700 and can be longer or shorter than Figure 10 the duration shown.

[0100] The SYNC_RSTN timing 1010 shows that the SYNC_RSTN signal output from the reset synchronizer 360 is initially invalid but becomes valid once the I_RSTN signal becomes valid. There is a delay after the input reset signal is de-asserted and before the SYNC_RSTN signal is de-asserted. As discussed above regarding Figure 3 when using three flip-flops 370A to 370C, the delay is three clock cycles.

[0101] The MY_RSTN timing 1020 shows that in response to I_RSTN being asserted, the MY_RSTN signal is asserted within a single clock cycle. The MY_RSTN signal allows internal reset of the synchronous reset de-assertion circuit 700 and subsequently provides synchronous reset de-assertion capability.

[0102] The state timing 1040 shows which of the five states the state decoder 705 is in at each time point. Before the I_RSTN signal is asserted, the state decoder 705 is in the user state. When the MY_RSTN signal is asserted, the N counter state is reset to 1. For N clock cycles, the N_COUNTER timing 1025 shows the N counter incrementing with each clock cycle until the value N is reached. In response to the N counter reaching the N value, the state timing 1040 shows entering the P_COUNTING state. This triggers the P counter to start incrementing until the P counter reaches the P value, as shown by the P_COUNTER timing 1030. Thereafter, the state decoder 705 enters the wait state and remains in the wait state until the SYNC_RSTN signal is de-asserted. At this point, the state decoder 705 enters the Q_COUNTING state, and as shown by the Q_COUNTER timing 1035, the Q counter starts counting to Q. When the Q counter reaches Q, the state timing 1040 shows that the state decoder 705 enters the user state.

[0103] The O_RSTN timing 1045 shows that when the input reset signal is asserted, the output reset signal is asserted, but the output reset signal is not de-asserted until the wait state is completed. Thus, even if the I_RSTN signal is de-asserted during the N_COUNTING state or the P_COUNTING state, the synchronous de-assertion circuit 700 will ensure that these states are complete before leaving the wait state and de-asserting the reset signal. By appropriately choosing the values of N and P, this ensures that the components connected to the synchronous reset de-assertion circuit 700 have sufficient time to complete their reset processing.

[0104] The CG_EN timing 1050 shows that the clock output is initially disabled in response to the reset signal, but is enabled during the P_COUNTING state, allowing the connected components to receive the clock signal during reset. After the clock is enabled for P cycles, it is disabled again until the user state is re-entered and normal operation is resumed. The O_CLKOUT timing 1055 shows that the output clock is controlled by the CG_EN signal.

[0105] Figure 11 is a block diagram showing the components of an FPGA 1100 including a synchronous reset de-assertion circuit 1110 according to various embodiments of the present invention. In addition to the reset de-assertion circuit 1110, the FPGA 1100 also includes IP blocks 1120, 1130, 1140, 1150, and 1160. For clarity, in Figure 11 the clock signals are shown as solid lines and the reset signals are shown as dashed lines.

[0106] The FPGA 1100 receives a clock input I_CLKIN and an input reset signal I_RSTN. The I_CLKIN and I_RSTN are provided as inputs to the synchronous reset de-assertion circuit 1110, which can be implemented as described above with respect to Figures 3 to 10 The synchronous reset de-assertion circuit 1110 generates an output clock signal O_CLKOUT and an output reset signal O_RSTN. Each of the IP blocks 1120 to 1160 receives O_CLKOUT and O_RSTN instead of I_CLKIN and I_RSTN. Thus, the synchronous reset de-assertion circuit 1110 can control the timing of the assertion of the reset signal, the de-assertion of the reset signal, the provision of the clock signal, or any suitable combination thereof.

[0107] Thus, by configuring the synchronous reset de-assertion circuit 1110 to meet the requirements of IP blocks 1120 to 1160, the correct operation of IP blocks 1120 to 1160 is ensured. For example, if IP block 1120 takes three clock cycles to complete a reset, applying a reset signal in less than three clock cycles places IP block 1120 in an indeterminate state. If the I_RSTN signal is coupled to a physical button controlled by the user, FPGA 1100 can receive a reset signal of any duration. By configuring the synchronous reset de-assertion circuit 1110 to ensure that the O_RSTN signal is asserted for at least three clock cycles regardless of the assertion duration of the I_RSTN signal, the indeterminate state of IP block 1120 is avoided.

[0108] As another example, IP block 1120 can be a double data rate (DDR) memory controller, whose design specifies that 16 cycles are required during reset to ensure that the DDR memory controller is placed in a known state. To support this, N (refer to the timing diagram of Figure 6 ) or P (refer to the timing diagram of Figure 10 ) can be set to at least 16, thus ensuring that IP block 1120 receives at least 16 clock cycles when the reset is asserted.

[0109] The worst-case reset latency of a particular FPGA 1100 can be measured and divided by the clock frequency to determine the number of clock cycles for which the reset signal should be held at a constant value, thus ensuring that all IP blocks 1120 to 1160 receive the signal. The determined number of clock cycles can be used as the value of P (refer to the timing diagram of Figure 4 ) or N (refer to the timing diagrams of Figure 6 and Figure 10 ).

[0110] Although circuits are generally described herein as active high, such that a high voltage indicates logic 1 or a Boolean true value, alternative implementations are envisioned that are active low, such that a low voltage indicates logic 1 or a Boolean true value. Thus, an "active" signal can be either a high voltage or a low voltage, depending on the circuit design.

[0111] In the foregoing specification, some example implementations of the present disclosure have been described. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. The following is a non-exhaustive list of examples of implementations of the present disclosure.

[0112] Example 1 is a circuit that includes: a reset input; a clock input; a reset output; a clock output; a synchronizer block that receives the clock input and the reset input as inputs and generates a synchronized reset output as an output; a gating block that receives the clock input and a gating signal as inputs and generates the clock output as an output, where when a first value of the gating signal is received, the clock output is set to the clock input, and when a second value of the gating signal is received, the clock output has a constant value; and a counter block that receives the clock input and a counter reset input as inputs and generates a counter block signal as an output; and the counter block is configured to: in response to the counter reset input being asserted, set the counter block signal to a second value; and in response to the synchronized reset output being de-asserted, set the counter block signal to a first value after a predetermined delay.

[0113] In Example 2, the subject matter of Example 1 includes, wherein: the synchronized reset output of the synchronizer block is coupled to the reset output of the circuit; the synchronized reset output of the synchronizer block is coupled to the counter reset input of the counter block; and the counter block signal of the counter block is coupled to the gating signal of the gating block.

[0114] In Example 3, the subject matter of Examples 1 to 2 includes, wherein the counter block includes: a counter that is reset by the reset output and, when not reset, modifies the counter value by 1 each clock cycle; and a comparator that sets the counter block signal based on the counter value and a predetermined value corresponding to the predetermined delay.

[0115] In Example 4, the subject matter of Examples 1 to 3 includes a plurality of logic blocks, and each logic block in the plurality of logic blocks receives the reset output and the clock output as inputs.

[0116] In Example 5, the subject matter of Examples 1 to 4 includes, wherein the synchronizer block ensures that the synchronized reset output does not change value within a predetermined amount of time from a change in the value of the clock input.

[0117] In Example 6, the subject matter of Examples 1 to 5 includes a second counter block that receives the clock input and the synchronized reset output as inputs and generates a second counter block signal as an output; and the second counter block is configured to: in response to the synchronized reset output being asserted, set the second counter block signal to a second value; and in response to the synchronized reset output being de-asserted, set the second counter block signal to a first value after a second predetermined delay.

[0118] In Example 7, the subject matter of Example 6 includes, wherein: the counter block is a first counter block, and the counter block signal is a first counter block signal; the second counter block signal is coupled to the reset output; and the second counter block signal is coupled to the counter reset input of the first counter block.

[0119] In Example 8, the subject matter of Example 7 includes: an XNOR gate that receives a first counter block signal and a second counter block signal as inputs and generates an XNOR output; a multiplexer that selects between the XNOR output and a first value based on a synchronous reset output to generate a multiplexer output that is coupled to a gating block as a gating signal.

[0120] In Example 9, the subject matter of Examples 6 to 8 includes, wherein the second counter block includes: a counter that is reset by the synchronous reset output and, when not reset, modifies the counter value by 1 each clock cycle; and a comparator that sets the second counter block signal based on the counter value and a predetermined value corresponding to a second predetermined delay.

[0121] In Example 10, the subject matter of Examples 1 to 9 includes, wherein: the counter block is the first counter block and the counter block signal is the first counter block signal; and the subject matter further includes: a second counter block that receives a clock input and the first counter block signal as inputs and generates a second counter block signal as an output; and the second counter block is configured to: in response to the first counter block signal being asserted, set the second counter block signal to a second value; and in response to the first counter block signal being de-asserted, set the second counter block signal to a first value after a second predetermined delay.

[0122] In Example 11, the subject matter of Examples 1 to 10 includes a state machine that: controls the gating signals of the synchronous reset output and the clock output such that: in a first state, the gating signal has a second value and the synchronous reset output is asserted; in a second state, the gating signal has a first value and the synchronous reset output is asserted; in a third state, the gating signal has a first value and the synchronous reset output is de-asserted; and in a fourth state, the gating signal has a second value and the synchronous reset output is de-asserted.

[0123] Example 12 is a method that includes: receiving a reset input; receiving a clock input; generating, by a synchronizer block, a synchronous reset output based on the clock input and the reset input; generating, by a gating block, a clock output that is set to the clock input during a first time period based on the gating signal being equal to a first value during the first time period; generating, by the gating block, a clock output that is set to a constant value during a second time period based on the gating signal being equal to a second value during the second time period; generating, by a counter block, a counter block signal that is set to a second value during a third time period based on a counter reset signal being asserted during the third time period; and generating, by the counter block, a counter block signal that is set to a first value during a fourth time period based on the counter reset signal being de-asserted during a fifth time period, the fourth time period having a predetermined delay after the fifth time period.

[0124] In Example 13, the subject matter of Example 12 includes: providing the synchronous reset output of the synchronizer block as the reset output; providing the synchronous reset output of the synchronizer block as the counter reset input of the counter block; and providing the counter block signal of the counter block as the gating signal of the gating block.

[0125] In Example 14, the subject matter of Example 13 includes: providing the reset output and the clock output as inputs to a plurality of logic blocks.

[0126] In Example 15, the subject matter of Examples 12 to 14 includes: resetting the counter of the counter block based on the synchronous reset output; modifying the counter value by 1 each clock cycle during a predetermined delay period; and starting to generate a counter block signal set to a first value during a fourth time period based on the counter value and a predetermined value corresponding to the predetermined delay.

[0127] In Example 16, the subject matter of Examples 12 to 15 includes: ensuring by the synchronizer block that the synchronous reset output does not change value within a predetermined amount of time from a change in the value of the clock input.

[0128] In Example 17, the subject matter of Examples 12 to 16 includes: generating, by a second counter block during a sixth time period, a second counter block signal set to a second value based on the synchronous reset output being asserted during the sixth time period; and generating, by the second counter block during a seventh time period, a second counter block signal set to a first value based on the synchronous reset output being de-asserted during an eighth time period, the seventh time period having a second predetermined delay after the eighth time period.

[0129] In Example 18, the subject matter of Example 17 includes, wherein: the counter block is a first counter block and the counter block signal is a first counter block signal; and the subject matter further includes: providing the second counter block signal as the reset output; and providing the second counter block signal as the counter reset input of the first counter block.

[0130] In Example 19, the subject matter of Example 18 includes: selecting, based on the synchronous reset output, a first value or the exclusive NOR (XNOR) of the first counter block signal and the second counter block signal; and providing the selected value as the gating signal of the gating block.

[0131] In Example 20, the subject matter of Examples 17 to 19 includes: using the synchronous reset output to reset a counter that, when not reset, modifies the counter value by 1 each clock cycle; and setting the second counter block signal based on the counter value and a predetermined value corresponding to a third predetermined delay.

[0132] Example 21 is at least one machine-readable medium including instructions that, when executed by a processing circuitry, cause the processing circuitry to perform operations for implementing any one of Examples 1 to 20.

[0133] Example 22 is an apparatus including means for implementing any one of Examples 1 to 20.

[0134] Example 23 is a system for implementing any one of Examples 1 to 20.

[0135] Example 24 is a method for implementing any one of Examples 1 to 20.

[0136] The abstract of the disclosure is provided to comply with 37 C.F.R. § 1.72(b), requiring the abstract to enable the reader to quickly ascertain the nature of the technical disclosure. The abstract is submitted with the understanding that it will not be used to interpret or limit the claims. Additionally, in the foregoing detailed description, it can be seen that for the purpose of streamlining the disclosure, various features are combined in a single embodiment. The methods of the disclosure should not be construed as limiting the claims. Accordingly, the appended claims are hereby incorporated into the detailed description, where each claim stands on its own as a separate embodiment.

Claims

1. A circuit, comprising: A reset input; A clock input; A reset output; A clock output; A synchronizer block that receives the clock input and the reset input as inputs and generates a synchronized reset output as an output; A gating block that receives the clock input and a gating signal as inputs and generates the clock output as an output, wherein when a first value of the gating signal is received, the clock output is set to the clock input, and when a second value of the gating signal is received, the clock output has a constant value; And A counter block that: Receives the clock input and a counter reset input as inputs and generates a counter block signal as an output; and The counter block is configured to: Set the counter block signal to the second value in response to the counter reset input being asserted; and Set the counter block signal to the first value after a predetermined delay in response to the synchronized reset output being de-asserted.

2. The circuit according to claim 1, wherein: The synchronized reset output of the synchronizer block is coupled to the reset output of the circuit; The synchronized reset output of the synchronizer block is coupled to the counter reset input of the counter block; and The counter block signal of the counter block is coupled to the gating signal of the gating block.

3. The circuit according to claim 1, wherein, The counter block includes: A counter that is reset by the reset output and, when not reset, modifies the counter value by 1 each clock cycle; and A comparator that sets the counter block signal based on the counter value and a predetermined value corresponding to the predetermined delay.

4. The circuit according to claim 1, further comprising: A plurality of logic blocks, each of the plurality of logic blocks receiving the reset output and the clock output as inputs.

5. The circuit according to claim 1, wherein, The synchronizer block ensures that the synchronized reset output does not change value within a predetermined amount of time from a change in the value of the clock input.

6. The circuit according to claim 1, further comprising: A second counter block that: Receives the clock input and the synchronized reset output as inputs and generates a second counter block signal as an output; and The second counter block is configured to: Set the second counter block signal to the second value in response to the synchronized reset output being asserted; and Set the second counter block signal to the first value after a second predetermined delay in response to the synchronized reset output being de-asserted.

7. The circuit according to claim 6, wherein: The counter block is a first counter block and the counter block signal is a first counter block signal; The second counter block signal is coupled to the reset output; and The second counter block signal is coupled to the counter reset input of the first counter block.

8. The circuit according to claim 7, further comprising: An exclusive NOR (XNOR) gate that receives the first counter block signal and the second counter block signal as inputs and generates an XNOR output; A multiplexer that selects between the XNOR output and the first value based on the synchronous reset output to generate a multiplexer output that is coupled to the gating signal of the gating block.

9. The circuit according to claim 6, wherein The second counter block includes: A counter that is reset by the synchronous reset output and, when not reset, modifies the counter value by 1 each clock cycle; and A comparator that sets the second counter block signal based on the counter value and a predetermined value corresponding to the second predetermined delay.

10. The circuit according to claim 1, wherein: The counter block is a first counter block, and the counter block signal is a first counter block signal; and The circuit further includes: A second counter block that: Receives the clock input and the first counter block signal as inputs, and Generates a second counter block signal as an output; and The second counter block is configured to: In response to the first counter block signal being asserted, set the second counter block signal to the second value; and In response to the first counter block signal being de-asserted, set the second counter block signal to the first value after a second predetermined delay.

11. The circuit according to claim 1, further includes: A state machine that: Controls the gating signal of the synchronous reset output and the clock output such that: In a first state, the gating signal has the second value and the synchronous reset output is asserted; In a second state, the gating signal has the first value and the synchronous reset output is asserted; In a third state, the gating signal has the first value and the synchronous reset output is de-asserted; And In a fourth state, the gating signal has the second value and the synchronous reset output is de-asserted.

12. A method includes: Receiving a reset input; Receiving a clock input; Generating a synchronous reset output by a synchronizer block based on the clock input and the reset input; Generating a clock output that is set to the clock input by the gating block during a first time period based on the gating signal being equal to the first value during the first time period; Generating the clock output that is set to a constant value by the gating block during a second time period based on the gating signal being equal to the second value during the second time period; Generating a counter block signal that is set to the second value by the counter block during a third time period based on the counter reset signal being asserted during the third time period; And Generating the counter block signal that is set to the first value by the counter block during a fourth time period based on the counter reset signal being de-asserted during a fifth time period, the fourth time period having a predetermined delay after the fifth time period.

13. The method according to claim 12, further includes: Providing the synchronous reset output of the synchronizer block as a reset output; Providing the synchronous reset output of the synchronizer block as the counter reset input of the counter block; And Providing the counter block signal of the counter block as the gating signal of the gating block.

14. The method according to claim 13, further comprising: Providing the reset output and the clock output as inputs to a plurality of logic blocks.

15. The method according to claim 12, further comprising: Resetting a counter of the counter block based on the synchronous reset output; During the predetermined delay period, modifying the counter value by 1 for each clock cycle; And Based on the counter value and a predetermined value corresponding to the predetermined delay, starting to generate the counter block signal set to the first value during the fourth time period.

16. The method according to claim 12, further comprising: Ensuring by the synchronizer block that the synchronous reset output does not change value within a predetermined amount of time from a change in the value of the clock input.

17. The method according to claim 12, further comprising: Generating, by a second counter block during a sixth time period, a second counter block signal set to the second value based on the synchronous reset output being asserted during the sixth time period; And Generating, by the second counter block during a seventh time period, the second counter block signal set to the first value based on the synchronous reset output being de-asserted during an eighth time period, the seventh time period having a second predetermined delay after the eighth time period.

18. The method according to claim 17, wherein: The counter block is a first counter block, and the counter block signal is a first counter block signal; and The method further comprises: Providing the second counter block signal as a reset output; and Providing the second counter block signal as a counter reset input to the first counter block.

19. The method according to claim 18, further comprising: Selecting, based on the synchronous reset output, the first value or the exclusive NOR (XNOR) of the first counter block signal and the second counter block signal; And Providing the selected value as a gating signal to the gating block.

20. The method according to claim 17, further comprising: Using the synchronous reset output to reset a counter that modifies the counter value by 1 for each clock cycle when not reset; And Setting the second counter block signal based on the counter value and a predetermined value corresponding to a third predetermined delay.

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