Chip physical information acquisition method, device, storage medium and computer equipment

Abstract

The present application provides a chip physical information acquisition method, device, storage medium and computer equipment, the method comprising: obtaining a chip to be detected with the package removed; the chip to be detected comprises multiple groups of transistors; performing a layer removal process on the chip to be detected to expose the through-hole layer of the chip to be detected; connecting the electrode nodes of each group of transistors located in the through-hole layer by nanoprobes to detect the electrical parameters of each group of transistors; obtaining character data corresponding to each group of transistors according to the electrical parameters of the transistors; obtaining the physical information data of the chip to be detected according to the character data corresponding to each group of transistors. The present application can avoid short circuits or open circuits and accurately obtain chip physical information.

Description

Technical Field

[0001] The present application relates to the technical field of obtaining physical information of a chip, and in particular to a method, device, storage medium and computer equipment for obtaining physical information of a chip. Background Art

[0002] Security is of utmost importance in an increasingly connected world that relies heavily on electronics. Modern electronics almost uniformly rely on cryptography as the primary method of protecting electronic data. Physically Unclonable Function (PUF), a hardware information security technology, utilizes inherent chip physical information to generate an unclonable unique device response to a given input, serving as an identifier for each chip. See Figure 1 In the traditional chip physical information acquisition method, it is necessary to make the electrodes of the chip's transistors into pads with larger areas through circuit repair, so as to detect the electrical parameters of the transistors on the pads to obtain the chip physical information. However, during the circuit repair process, the deposited metal wires can easily cause the metal wires on the chip to short-circuit or break. Therefore, the traditional chip physical information acquisition method has the technical defect of being unable to accurately obtain the chip physical information. Summary of the invention

[0003] The purpose of this application is to overcome the shortcomings and deficiencies in the prior art and to provide a chip physical information acquisition method, device, storage medium and computer equipment, which can avoid short circuits or open circuits and accurately acquire chip physical information.

[0004] A first aspect of an embodiment of the present application provides a method for acquiring physical information of a chip, comprising:

[0005] Obtaining a chip to be tested that has been removed from its packaging; the chip to be tested includes a plurality of groups of transistors;

[0006] De-layering the chip to be detected to expose the through-hole layer of the chip to be detected;

[0007] Connecting electrode nodes of each group of transistors located in the through-hole layer by nanoprobes to detect electrical parameters of each group of transistors;

[0008] According to the electrical parameters of the transistors, character data corresponding to each group of the transistors are obtained;

[0009] The physical information data of the chip to be detected is obtained according to the character data corresponding to each group of transistors.

[0010] A second aspect of an embodiment of the present application provides a chip physical information acquisition device, including:

[0011] A chip acquisition module, used for acquiring a chip to be detected that has been removed from its package; the chip to be detected includes a plurality of groups of transistors;

[0012] A through-hole layer exposing module is used to perform a layer removal process on the chip to be detected to expose the through-hole layer of the chip to be detected;

[0013] An electrical parameter detection module, used for connecting the electrode nodes of each group of transistors located in the through-hole layer through a nanoprobe to detect the electrical parameters of each group of transistors;

[0014] A transistor data acquisition module, used for obtaining character data corresponding to each group of transistors according to electrical parameters of the transistors;

[0015] The physical information data acquisition module is used to obtain the physical information data of the chip to be detected according to the character data corresponding to each group of transistors.

[0016] A third aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip physical information acquisition method as described above are implemented.

[0017] The fourth aspect of an embodiment of the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the steps of the chip physical information acquisition method as described above when executing the computer program.

[0018] Compared with the related art, the present application performs a de-layering process on the chip from which the package is removed to expose the through-hole layer of the chip, thereby exposing the electrode nodes of multiple groups of transistors of the chip to the through-hole layer, and then detects the electrical parameters of each group of transistors through a nanoprobe to obtain the character data corresponding to each group of transistors, and then obtains the physical information data of the chip based on the character data corresponding to each group of transistors. Compared with the prior art chip physical information acquisition method based on circuit repair, the present application adopts a technical means of obtaining the physical information data of the chip by performing electrical detection on multiple groups of transistors exposed in the through-hole layer through a nanoprobe, so there will be no short circuit or short circuit on the chip caused by the metal wires deposited by the circuit repair, and the physical information data of the chip can be accurately obtained.

[0019] In order to provide a clearer understanding of the present application, the specific implementation of the present application will be described below in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a metal line for circuit repair according to an embodiment of the present application.

[0021] Figure 2 This is a flowchart of a method for acquiring chip physical information according to an embodiment of the present application.

[0022] Figure 3 This is a schematic diagram of the module connections of a device for acquiring chip physical information according to an embodiment of the present application.

[0023] 100. Chip physical information acquisition device; 101. Chip acquisition module; 102. Through-hole layer exposure module; 103. Electrical parameter detection module; 104. Transistor data acquisition module; 105. Physical information data acquisition module. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0025] It should be clear that the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present application.

[0026] When the following description relates to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. The singular forms of "a", "said" and "the" used in the present application and the appended claims are also intended to include the majority form, unless the context clearly indicates other meanings. The words "if" / "if" used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0027] In addition, in the description of this application, unless otherwise specified, "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0028] See also Figure 2 , which is a schematic diagram of a chip physical information acquisition method of the first embodiment of the present application, comprising:

[0029] Step S1: obtaining a chip to be tested without packaging; the chip to be tested includes a plurality of groups of transistors.

[0030] The chip to be tested refers to an integrated circuit that includes multiple groups of transistors. Integrated circuits can integrate analog and digital circuits on a single chip to make devices such as analog-to-digital converters and digital-to-analog converters. This circuit provides smaller size and lower cost, but care must be taken with signal conflicts.

[0031] After the chip is made, it needs to be packaged to prevent dust, moisture and radiation in the air from damaging the chip circuit. In addition, in order to ensure the normal use of the chip, the metal pins of the chip need to be pulled out during the packaging process. Since the chip is a tiny integrated short circuit, the distance between the metal pins needs to be maintained, and the chip needs to have good heat dissipation. After removing the package, the accuracy of the chip de-layering can be maintained.

[0032] Step S2: performing a layer removal process on the chip to be tested to expose the through-hole layer of the chip to be tested.

[0033] The through-hole layer is a common structural layer of the chip. The through-hole layer refers to the contact layer of the circuit board (PCB) of the chip, and refers to the location of the through-holes on the circuit board of the chip. Among them, a through-hole layer can include multiple through-holes. Through-holes are the most common type of structure in circuit boards. Through-holes are usually used to connect components to other layers of the circuit board and provide structural support. Through-holes are structures drilled from the top layer of the circuit board to the bottom layer. De-layering can be an operation of physically and / or methodically de-layering the chip to expose the through-holes corresponding to multiple groups of transistors.

[0034] Step S3: connecting the electrode nodes of each group of transistors located in the through-hole layer by nanoprobes to detect the electrical parameters of each group of transistors.

[0035] Among them, Nanoprobe is a new type of ultra-microbial sensor that can detect single living cells. The probe size is only at the nanometer level and can be used to measure the electrical parameters of connected transistors, such as the Vt of the transistor.

[0036] Step S4: obtaining character data corresponding to each group of transistors according to the electrical parameters of the transistors.

[0037] For example, a group of transistors includes 4 transistors, which are represented as PMOS1, NMOS1, PMOS2 and NMOS2. The electrical parameters of PMOS1, NMOS1, PMOS2 and NMOS2, such as the Vt of each transistor, can be measured in sequence by a nanoprobe, and then the character data corresponding to each group of transistors can be determined according to the value of the Vt of each pair of transistors. Among them, the character data corresponding to each group of transistors can adopt a binary counting method, that is, "1" and "0" are used as the character data corresponding to each group of transistors. If the sum of the absolute values ​​of Vt of PMOS1 and NMOS1 is smaller than the sum of the absolute values ​​of Vt of PMOS2 and NMOS2, the character number corresponding to the group of transistors is determined to be "1"; if the sum of the absolute values ​​of Vt of PMOS1 and NMOS1 is larger than the sum of the absolute values ​​of Vt of PMOS2 and NMOS2, the character number corresponding to the group of transistors is determined to be "0". The character data of the group of transistors can be obtained.

[0038] Step S5: obtaining the physical information data of the chip to be detected according to the character data corresponding to each group of transistors.

[0039] The physical information data of the chip can be obtained by sorting the character data corresponding to each group of transistors according to a preset order.

[0040] Compared with the related art, the present application performs a de-layering process on the chip from which the package is removed to expose the through-hole layer of the chip, thereby exposing multiple groups of transistors of the chip to the through-hole layer, and then detects the electrical parameters of each group of transistors through a nanoprobe to obtain the character data corresponding to each group of transistors, and then obtains the physical information data of the chip based on the character data corresponding to each group of transistors. Compared with the prior art chip physical information acquisition method based on circuit repair, the present application adopts a technical means of obtaining the physical information data of the chip by performing electrical detection on multiple groups of transistors exposed in the through-hole layer through a nanoprobe, so there will be no short circuit or short circuit on the chip caused by the metal wires deposited by the circuit repair, and the physical information data of the chip can be accurately obtained.

[0041] In a feasible embodiment, the step S2: performing a layer removal process on the chip to be detected to expose the through-hole layer of the chip to be detected includes:

[0042] The chip to be tested is subjected to mechanical grinding to expose the through-hole layer of the chip to be tested, thereby exposing the electrode nodes of multiple pairs of transistors of the chip to be tested.

[0043] Among them, mechanical grinding can achieve a large area of ​​observation range, and the steps of mechanical masking can include four steps: mechanical cutting, cold burying, grinding, and polishing.

[0044] In this embodiment, through mechanical grinding, multiple groups of transistors of the chip can be exposed on the through-hole layer, so that it is convenient for users to detect the electrical parameters of each group of transistors.

[0045] In a feasible embodiment, the step S2: performing a layer removal process on the chip to be detected to expose the through-hole layer of the chip to be detected includes:

[0046] The chip to be tested is subjected to plasma focused ion beam microscope analysis to expose the through-hole layer of the chip to be tested, thereby exposing electrode nodes of multiple pairs of transistors of the chip to be tested.

[0047] Among them, for 3D-IC semiconductor process technology, if you do not want to destroy the entire chip by grinding, you can consider using plasma focused ion beam microscopy (Plasma FIB, abbreviated as PFIB) analysis techniques, which combines plasma ion etching processing and SEM observation functions. It is suitable for analysis within a distance of 50-500um, and can perform cross-sectional analysis, de-layering observation, and electrical testing. Even for specific areas, it can also be cut and observed and electrical testing can be performed simultaneously. There is no need to worry about accidentally damaging the target area due to blind cutting, ensuring the integrity of abnormal or specific observation structures.

[0048] In this embodiment, plasma focused ion beam microscopy analysis can be used to reduce damage to the integrity of the chip, thereby facilitating users to more accurately detect the electrical parameters of each group of transistors dug out and exposed in the through-hole layer.

[0049] In a feasible embodiment, the step S5: obtaining the physical information data of the chip to be detected according to the character data corresponding to each group of transistors, comprises:

[0050] S51: Determine the circuit sequence of each group of transistors as the arrangement sequence.

[0051] Among them, the circuit order of each group of transistors can be a preset order or the order in which each group of transistors is activated in the circuit, for example, the order of the transistors that are first activated in the circuit of each group of transistors, or the average order of the transistors that are first activated in the circuit of each group of transistors.

[0052] S52: Arrange the character data according to the arrangement order to obtain the physical information data of the chip to be detected.

[0053] By arranging the character data, the physical information data representing the chip can be obtained.

[0054] In this embodiment, the character data may be arranged in the circuit sequence of transistors to accurately obtain the physical information data of the chip.

[0055] In a feasible embodiment, after the step of arranging the character data according to the arrangement order to obtain the physical information data of the chip to be detected in S5, the step further includes:

[0056] The physical information data of the chip to be detected is classified and stored according to the number of bits of the physical information data of the chip to be detected, so as to obtain the physical information data of the chip to be detected corresponding to different types of bit numbers.

[0057] Among them, classified storage according to the number of bits of the physical information data of the chip is conducive to the reasonable storage of the physical information data, and can improve the convenience of querying or calling the stored physical information data.

[0058] In this embodiment, by classifying the physical information data of the storage chip, the confusion of the physical information data storage is reduced, and it is convenient for users to query or call the stored physical information data conveniently.

[0059] See also Figure 3 The second embodiment of the present application provides a chip physical information acquisition device, including:

[0060] A chip acquisition module, used for acquiring a chip to be detected that has been removed from its package; the chip to be detected includes a plurality of groups of transistors;

[0061] A through-hole layer exposing module is used to perform a layer removal process on the chip to be detected to expose the through-hole layer of the chip to be detected;

[0062] An electrical parameter detection module, used for connecting the electrode nodes of each group of transistors located in the through-hole layer through a nanoprobe to detect the electrical parameters of each group of transistors;

[0063] A transistor data acquisition module, used for obtaining character data corresponding to each group of transistors according to electrical parameters of the transistors;

[0064] The physical information data acquisition module is used to obtain the physical information data of the chip to be detected according to the character data corresponding to each group of transistors.

[0065] In a feasible embodiment, the through hole layer exposing module is used to perform mechanical grinding on the chip to be tested to expose the through hole layer of the chip to be tested, thereby exposing electrode nodes of multiple pairs of transistors of the chip to be tested.

[0066] In a feasible embodiment, the through-hole layer exposure module is used to perform plasma focused ion beam microscopy analysis on the chip to be tested to expose the through-hole layer of the chip to be tested, thereby exposing electrode nodes of multiple pairs of transistors of the chip to be tested.

[0067] It should be noted that the chip physical information acquisition device provided in the second embodiment of the present application only uses the division of the above-mentioned functional modules as an example when executing the chip physical information acquisition method. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the chip physical information acquisition device provided in the second embodiment of the present application and the chip physical information acquisition method of the first embodiment of the present application belong to the same concept. The implementation process is detailed in the method embodiment and will not be repeated here.

[0068] A third aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip physical information acquisition method as described above are implemented.

[0069] The fourth aspect of an embodiment of the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the steps of the chip physical information acquisition method as described above when executing the computer program.

[0070] The device embodiments described above are merely illustrative, wherein the components described as separate parts may or may not be physically separated, and the parts displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present application. Ordinary technicians in this field can understand and implement it without creative work.

[0071] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0072] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the function selected in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 function selected in a box or multiple boxes.

[0073] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 steps for the function selected in a box or multiple boxes.

[0074] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0075] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0076] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0077] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0078] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A method for obtaining physical information of a chip, characterized in that: include: Obtaining a chip to be tested that has been removed from its packaging; the chip to be tested includes a plurality of groups of transistors; De-layering the chip to be detected to expose the through-hole layer of the chip to be detected; Connecting electrode nodes of each group of transistors located in the through-hole layer through nanoprobes to detect electrical parameters of each group of transistors; the electrical parameters include Vt of the transistors; According to the size of the electrical parameter Vt of each pair of transistors in each group of transistors, character data corresponding to the binary counting method of each group of transistors are obtained; The character data corresponding to each group of the transistors are sorted according to a preset order to obtain the physical information data of the chip to be detected.

2. The chip physical information acquisition method according to claim 1, characterized in that: The step of performing a layer removal process on the chip to be detected to expose the through-hole layer of the chip to be detected comprises: The chip to be tested is subjected to mechanical grinding to expose the through-hole layer of the chip to be tested, thereby exposing the electrode nodes of multiple pairs of transistors of the chip to be tested.

3. The chip physical information acquisition method according to claim 1, characterized in that: The step of performing a layer removal process on the chip to be detected to expose the through-hole layer of the chip to be detected comprises: The chip to be tested is subjected to plasma focused ion beam microscope analysis to expose the through-hole layer of the chip to be tested, thereby exposing electrode nodes of multiple pairs of transistors of the chip to be tested.

4. The chip physical information acquisition method according to claim 1, characterized in that: The step of obtaining the physical information data of the chip to be detected according to the character data corresponding to each group of transistors comprises: determining the circuit sequence of each group of transistors as an arrangement sequence; The character data are arranged according to the arrangement order to obtain the physical information data of the chip to be detected.

5. The chip physical information acquisition method according to claim 4, characterized in that: After the step of arranging the character data according to the arrangement order to obtain the physical information data of the chip to be detected, the method further includes: The physical information data of the chip to be detected is classified and stored according to the number of bits of the physical information data of the chip to be detected, so as to obtain the physical information data of the chip to be detected corresponding to different types of bit numbers.

6. A device for acquiring chip physical information, characterized in that: include: A chip acquisition module, used for acquiring a chip to be detected that has been removed from its package; the chip to be detected includes a plurality of groups of transistors; A through-hole layer exposing module is used to perform a layer removal process on the chip to be detected to expose the through-hole layer of the chip to be detected; An electrical parameter detection module, used to connect the electrode nodes of each group of transistors located in the through-hole layer through a nanoprobe to detect the electrical parameters of each group of transistors; the electrical parameters include Vt of the transistor; A transistor data acquisition module, used for obtaining the size of the electrical parameter Vt of each pair of transistors in each group of transistors, and obtaining the character data of the binary counting method corresponding to each group of transistors; The physical information data acquisition module is used to sort the character data corresponding to each group of the transistors according to a preset order to obtain the physical information data of the chip to be detected.

7. The chip physical information acquisition device according to claim 6, characterized in that: The through hole layer exposing module is used to perform mechanical grinding on the chip to be detected to expose the through hole layer of the chip to be detected, thereby exposing electrode nodes of multiple pairs of transistors of the chip to be detected.

8. The chip physical information acquisition device according to claim 6, characterized in that: The through hole layer exposure module is used to perform plasma focused ion beam microscope analysis on the chip to be detected, so as to expose the through hole layer of the chip to be detected, thereby exposing electrode nodes of multiple pairs of transistors of the chip to be detected.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the chip physical information acquisition method according to any one of claims 1 to 5 are implemented.

10. A computer device, characterized in that: It comprises a memory, a processor and a computer program stored in the memory and executable by the processor, and when the processor executes the computer program, the steps of the chip physical information acquisition method as described in any one of claims 1 to 5 are implemented.

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