Multi-Clock-Cycle Memory Instruction Protocol

Abstract

Systems and methods for providing memory access commands to a memory circuitry using a multi-clock cycle memory command protocol are described. A command decoder (or controller) of the memory circuitry can efficiently receive a memory access request (or memory command) provided over multiple clock cycles. For example, the command decoder can receive a first portion of a header and address bits of the memory command in a first clock cycle and a second portion of the address bits of the target memory cell in subsequent clock cycles. Thus, the memory circuitry can receive a memory command having one header provided over multiple clock cycles. Such memory commands can efficiently include a high number of address bits received using an input circuitry of the memory circuitry.

Description

BACKGROUND OF THE INVENTION

[0001] This section is intended to introduce the reader to various technical aspects related to aspects of the technology described and / or claimed hereinafter. It is believed that this discussion will help provide background information to the reader to facilitate a better understanding of the various aspects of the disclosure. Accordingly, it is to be understood that these statements are to be read from this perspective and are not an admission of prior art.

[0002] The following generally relates to memory devices and more particularly to providing memory commands for accessing, sensing, and other operations on memory cells. The techniques and methods described herein may be used with ferroelectric memory devices or other types of memory devices. Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the storage elements of the memory device. For example, binary devices have two states typically represented by a logic "1" or a logic "0". In other systems, more than two states may be stored in each storage element. To access the stored information, an electronic device may read or sense the stored state in the storage elements of the memory device. To store information, the electronic device may write or program the state in the storage elements of the memory device.

[0003] There are various types of memory devices, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and the like. Memory devices can be volatile or non-volatile. Non-volatile memory devices (e.g., flash memory) can store data for long periods of time even in the absence of an external power source. Volatile memory devices (e.g., DRAM) can lose their stored state over time unless they are periodically refreshed by an external power source.

[0004] Memory devices may include several storage elements, such as memory cells. Memory cells of a binary memory device may include, for example, a charged or discharged capacitor. However, the charged capacitor of a memory cell may become discharged over time due to leakage current, resulting in the loss of stored information. Certain characteristics of volatile memory may provide performance advantages (e.g., faster read or write speeds), while characteristics of non-volatile memory (e.g., the ability to store data without periodic refreshing) may be advantageous. Some memory devices include memory cells that can be accessed by transistors that conductively couple the memory cells (e.g., capacitors) to word lines or bit lines / digit lines.

[0005] Even so, FeRAM can use a device architecture similar to that of volatile memory, but has non-volatile properties attributable to the use of ferroelectric capacitors as storage elements or memory cells. Thus, FeRAM devices can have improved performance compared to some other non-volatile and volatile memory devices. Some FeRAMs can divide the sensing window of FeRAM memory cells to store 2 states per memory cell, while other FeRAMs can divide the sensing window of FeRAM memory cells to store multiple states (e.g., 3 or 4) per memory cell.

[0006] In addition, different memory devices can use different architectures to arrange memory cells. For example, different memory devices can arrange memory cells in 2-dimensional or 3-dimensional rows and columns. Memory cells can be accessed based on activating the rows and columns of the memory device corresponding to the memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure may be better understood after reading the following detailed description and with reference to the accompanying drawings, in which:

[0008] Figure 1 is a block diagram illustrating certain features of a memory device in accordance with an embodiment of the present disclosure;

[0009] Figure 2 is a bank of a memory device in accordance with an embodiment of the present disclosure Figure 1 ;

[0010] Figure 3A is a first part of a schematic diagram of circuitry associated with at least a portion of a command decoder of a memory device in accordance with an embodiment of the present disclosure and Figure 1 and 2 ;

[0011] Figure 3B is a second part of a schematic diagram of circuitry associated with at least a portion of a command decoder of a memory device in accordance with an embodiment of the present disclosure and Figure 1 and 2 ;

[0012] Figure 4 is a timing diagram depicting an example timing of signals for accessing memory cells of a memory device using a multi-clock cycle memory command protocol; and

[0013] Figure 5 is a diagram depicting an example access command provided using a multi-clock cycle memory command protocol in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] When introducing elements of various embodiments of the present disclosure, the articles "a", "an", "the", and "said" are intended to indicate the presence of one or more of the elements. The terms "comprising", "including", and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. One or more specific embodiments of the embodiments described herein will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation may be described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer-specific goals that may vary between implementations, such as compliance with system-related and business-related constraints. Additionally, it should be understood that this development effort may be complex and time-consuming, but would still be a routine task of design, fabrication, and manufacture for those of ordinary skill in the art.

[0015] A memory device may perform memory operations such as storing data and retrieving stored data. For example, a computing system may include various system components including one or more memory devices. The system components may communicate data (e.g., data bits) to perform system operations. For example, the system may include one or more processing components, one or more memory devices, and other system components. In different embodiments, the computing system may be disposed on a single electronic chip or multiple electronic chips. Additionally, the computing system may be disposed on a single electronic device or multiple electronic devices positioned close to or far from each other.

[0016] In any case, a memory device may include multiple memory components for storing data and retrieving stored data based on access commands (e.g., memory access requests) received from various system components (e.g., a processor). For example, a processor may transmit an access command using several data bits. In different embodiments, a processor may transmit an access command using different communication protocols (e.g., a memory command protocol). For example, a processor may use a memory command protocol based on several communication pins (hereinafter pins) of the memory device. The memory device may receive several data bits corresponding to several pins of the memory device at each rising or falling edge of a clock signal.

[0017] A memory device may include a number of banks, controller circuitry, command decoder circuitry, a clock circuit for providing a clock signal, and other memory components. In some cases, the controller circuitry (hereinafter referred to as the controller) may include the command decoder circuitry (hereinafter referred to as the command decoder). In alternative or additional cases, the command decoder may include separate circuitry disposed between the controller and the bank or between any other feasible locations. Additionally, the memory component may include an input / output interface for communicating with other system components. For example, the input / output interface of some memory components may include pins for receiving access commands from a processor.

[0018] In different embodiments, the memory device may include a different number of banks (e.g., 2 banks, 4 banks, 8 banks, etc.). Each bank may include a number of memory cells arranged in rows and columns. Additionally, in different cases, the bank may include a different number of rows and / or columns of memory cells (e.g., 18 rows, 22 rows, etc.).

[0019] In any case, as will be appreciated, the command decoder may include circuitry for receiving an access command and providing an access instruction to the bank. The command decoder may facilitate accessing a target memory cell by providing the access instruction. The access command may include a request to perform a memory operation on the target memory cell that includes a memory read operation and a memory write operation. In some cases, a processor of a computing system may transmit the access command to the memory device. In different cases, any other feasible processing circuitry may transmit the access command to the memory device.

[0020] As mentioned above, the processor may use a memory command protocol to transmit the access command to the memory device. Additionally, the memory command protocol is determined at least in part based on the number of pins of the memory device. For example, at each rising or falling edge of the clock signal, the command decoder may receive a number of data bits of the access command corresponding to the number of pins. Subsequently, the command decoder may provide an access instruction to activate the corresponding row and column of the target memory cell for accessing the target memory cell (e.g., reading from and / or writing to the target memory cell).

[0021] In view of the foregoing, in different embodiments, the access command may have different lengths or include a different number of data bits. In some cases, each access command may include a header followed by a number of address bits associated with the target memory cell. For example, the header may indicate a read and / or write access instruction to the bank. Additionally, the address bits may include address information of the target memory cell indicating the row, column, and / or bank of the target memory cell.

[0022] In addition, a memory device may access a set of target memory cells in one memory cycle. For example, a memory cycle may correspond to one or more clock cycles. Further, in each memory cycle, the memory device may receive a set of address bits indicating the set of target memory cells. In different embodiments, as will be appreciated, the memory device may receive the set of address bits using one or more access commands.

[0023] The set of address bits may include several data bits corresponding to columns, rows, and / or banks of memory cells in the memory device. For example, in each memory cycle, each set of address bits may include one address bit for each row of memory cells of the memory device for indicating the set of target memory cells.

[0024] In view of the foregoing, in some cases, the set of address bits may include a number of address bits higher than a threshold. The threshold number of address bits may be based on the number of pins of the memory device. Further, the number of address bits of the set of address bits may correspond to the number of rows and / or columns of memory cells of the memory device.

[0025] In some embodiments, a processor may transmit multiple access commands (each including a header and a portion of the set of address bits) to indicate address information of target memory cells. Thus, each access command may include a portion of the set of address bits for accessing the target memory cells. That is, each memory cycle may correspond to multiple access commands, each access command including a respective command header and a portion of the set of address bits, which may jointly provide the address information. In such embodiments, the memory device may receive each access command using a single clock cycle. For example, each clock cycle may correspond to the rising edge and / or falling edge of a clock signal.

[0026] As mentioned above, the number of address bits may correspond to the number of rows, columns, and / or banks of the memory device. In some cases, each address bit may correspond to a respective row and / or bank of the memory device. Further, the number of pins of the memory device may correspond to the number of data bits that the command decoder of the memory device may receive in each clock cycle. Thus, the memory device may receive several access commands using a single clock cycle to receive the set of address bits in each memory cycle.

[0027] In an alternative or additional embodiment, the processor may use a multi-clock cycle memory command protocol to transmit access commands. In such embodiments, the processor may use multiple clock cycles to transmit an access command that includes the set of address bits. For example, the processor may provide a header and a portion of the set of address bits in a first clock cycle. Additionally, the processor may provide the remaining portion of the set of address bits at least in a second clock cycle. In some cases, the access command may use multiple clock cycles (e.g., a second clock cycle, a third clock cycle, a fourth clock cycle, etc.) to provide the remaining portion of the set of address bits.

[0028] In such embodiments, the processor may use multiple clock cycles to provide a header followed by several address bits. Thus, the processor may provide additional address bits based on using one header over multiple clock cycles. Consequently, the memory device may receive each access command over multiple clock cycles. Additionally, each access command may include the set of address bits and correspond to one memory cycle.

[0029] The command decoder of the memory device may receive access commands using a multi-clock cycle memory command protocol. The command decoder may include circuitry for decoding each access command provided using the multi-clock cycle memory command protocol. Thus, the command decoder may provide access instructions to the bank based on receiving and decoding each access command provided using the multi-clock cycle memory command protocol.

[0030] Thus, the memory device may efficiently access the set of target memory cells in the bank based on receiving one header over multiple clock cycles. As discussed above, the number of pins of the bank may correspond to the number of data bits that the bank can receive in each clock cycle. Thus, based on efficiently receiving and decoding address bits with a lower overhead (e.g., one header per multiple clock cycles), the memory device may use a smaller number of pins.

[0031] In one non-limiting example, the memory device may include 7 pins for communicating data bits. Additionally, the bank of the memory device may include 22 rows. Additionally, the memory device may include 8 banks arranged in 2 memory groups. For example, each memory group may include 4 banks. In this example, the access instruction may include 22 address bits corresponding to 22 rows of data in the bank and 4 address bits for identifying the corresponding bank. Thus, the command decoder may receive an access command having 26 address bits to identify the target memory cell. Additionally, the access command may include a header having 2 data bits to indicate a memory read and / or write request to the memory device based on using the multi-clock cycle memory command protocol.

[0032] When using a multi-clock cycle memory command protocol, the command decoder can receive each access command using 28 data bits over multiple clock cycles. As mentioned above, the 28 data bits can include 26 address bits and 2 header data bits. In some cases, in each clock cycle, the bank can receive the data bits of the access instruction at the rising edge and the subsequent falling edge of the clock signal of each clock cycle. Thus, when using a multi-clock cycle memory command protocol, the bank can use 7 pins to receive 28 data bits of each access instruction within 2 clock cycles (each clock cycle including a rising edge and a falling edge).

[0033] In addition, the command decoder can include circuitry for decoding access commands. Thus, the command decoder can use the circuitry to provide access instructions to the bank based on receiving and decoding access commands provided using a multi-clock cycle memory command protocol. Accordingly, the command decoder can facilitate efficient access to the set of target memory cells based on using the circuitry to decode access commands provided using a multi-clock cycle memory command protocol.

[0034] Referring now to the drawings, Figure 1 a simplified block diagram depicting certain features of a memory device 100 (e.g., a memory subsystem of a device) is shown. Specifically, Figure 1 the block diagram depicts a functional block diagram illustrating certain functionality of the memory device 100. According to one embodiment, the memory device 100 can include a random access memory (RAM) device, a ferroelectric RAM (FeRAM) device, a dynamic RAM (DRAM) device, a static RAM (SRAM) device (including a double data rate SRAM device), a flash memory, and / or a 3D memory array, including a phase change memory (PC) device and / or other chalcogenide-based memories, such as a self-selecting memory (SSM). In addition, each memory cell of this 3D memory array can include a corresponding logic storage device (e.g., a capacitor, a resistor, or the resistance of (a) chalcogenide material(s)).

[0035] The memory device 100 can include a number of banks 102 each including one or more memory arrays. Various configurations, organizations, and sizes of the banks 102 on the memory device 100 can be used based on the application and design of the memory device 100 within an electronic system. For example, in different embodiments, the banks 102 can include different numbers of rows and / or columns of memory cells. In addition, each bank 102 can include a number of pins for communicating with other blocks of the memory device 100. For example, each bank 102 can receive one data bit per pin per clock cycle. In addition, the banks 102 can be grouped into multiple memory groups (e.g., two memory groups, three memory groups).

[0036] The memory device 100 may also include a command interface 104 and an input / output (I / O) interface 106. The command interface 104 is configured to provide several signals received from a processor (e.g., the processor subsystem of a device) or a controller (e.g., the memory controller 108). In different embodiments, the memory controller 108 (hereinafter the controller 108) may include one or more processors (e.g., memory processors), one or more programmable logic structures, or any other suitable processing components.

[0037] In some embodiments, the bus 110 may provide a signal path or a group of signal paths to allow bidirectional communication between the controller 108, the command interface 104, and the I / O interface 106. For example, the controller 108 may receive a memory access request from the I / O interface via the command interface 104 and the bus 110. In addition, the controller 108 may provide access commands and / or access instructions for performing memory operations to the command interface 104 via the bus 110.

[0038] Similarly, the external bus 112 may provide another signal path or a group of signal paths to allow bidirectional transmission of signals, such as data signals and access commands (e.g., read / write requests), between the I / O interface 106, the controller 108, the command decoder 120, and / or other components. Thus, the controller 108 may provide various signals (e.g., access commands, access instructions, or other signals) to different components of the memory device 100 to facilitate the transmission and reception of data to be written to or read from the memory bank 102.

[0039] Even so, the command interface 104 may receive different signals from the controller 108. For example, a reset command may be used to reset the command interface 104, status registers, state machines, and the like during power-on. Various test signals may also be provided to the memory device 100. For example, the controller 108 may use such test signals to test the connectivity of different components of the memory device 100. In some embodiments, the command interface 104 may also provide an alarm signal to the controller 108 when an error is detected in the memory device 100. In addition, the I / O interface 106 may be used additionally or alternatively to provide such alarm signals to other system components that are electrically connected to the memory device 100, for example.

[0040] The command interface 104 may also receive one or more clock signals (e.g., an external clock signal) from an external device. In addition, the command interface 104 may include a clock input circuit 114 (CIC) and a command address input circuit 116 (CAIC). The command interface 104 may use the clock input circuit 114 and the command address input circuit 116 to receive input signals (including access commands) to facilitate communication with the memory bank 102 and other components of the memory device 100.

[0041] In addition, the clock input circuit 114 may receive one or more clock signals (e.g., an external clock signal) and generate an internal clock signal (CLK) from the clock signals. In some embodiments, the command interface 104 may provide the CLK to the command decoder 120 and an internal clock generator, such as a delay locked loop (DLL) 118 circuit. The DLL 118 may generate a phase-controlled internal clock signal (LCLK) based on the received CLK. For example, the DLL 118 may provide the LCLK to the I / O interface 106. Subsequently, the I / O interface 106 may use the received LCLK as a clock signal for transmitting read data using the external bus 112.

[0042] The command interface 104 may also provide the internal clock signal CLK to various other memory components. As mentioned above, the command decoder 120 may receive the internal clock signal CLK. In some cases, the command decoder 120 may also receive access commands via the bus 122 and / or through the I / O interface 106 received via the external bus 112. For example, the command decoder 120 may receive access commands transmitted by one or more external devices through the I / O interface 106. In some cases, the processor may transmit access commands.

[0043] The command decoder 120 may decode the access commands and / or memory access requests to provide corresponding access instructions for accessing the target memory cells. For example, the command decoder 120 may provide the access instructions to one or more control blocks 132 associated with the bank 102 via the bus path 126. In some cases, the command decoder 120 may provide the access instructions to the control block 132 in coordination with the DLL 118 via the bus 124. For example, the command decoder 120 may coordinate the generation of the access instructions online (e.g., synchronously) with the CLK and / or LCLK.

[0044] Thus, the command decoder 120 may decode the access commands (e.g., memory access requests) to provide access instructions. In some cases, the command decoder 120 may receive the access commands using the rising edge and / or falling edge of the external clock signal. For example, the processor may transmit access commands using a memory command protocol (e.g., a multi-clock cycle memory command protocol). In addition, the processor may use a specific memory command protocol at least in part based on the number of pins of the memory device 100 or the I / O interface 106, the number of rows and / or columns of the bank 102, and the number of banks 102. Subsequently, the command decoder 120 may provide the access instructions to the bank 102 based on receiving and decoding the access commands.

[0045] Thus, the command decoder 120 may provide access instructions to the bank 102 using one or more clock cycles of CLK via the bus path 126. The command decoder 120 may also transmit various signals to one or more registers 128 via, for example, one or more global routing lines 130. Additionally, the memory device 100 may include other decoders (e.g., a row decoder and a column decoder) to facilitate access to the bank 102, as discussed below.

[0046] In some embodiments, each bank 102 may include a corresponding control block 132. In some cases, each of the control blocks 132 may also provide row decoding and column decoding capabilities based on receiving access instructions. Thus, the control blocks 132 may facilitate access to the memory cells of the corresponding bank 102. For example, the control block 132 may include circuitry (e.g., logic circuitry) for facilitating access to the memory cells of the corresponding bank 102 based on receiving access instructions.

[0047] In some cases, the control block 132 may receive an access instruction and determine the target bank 102 associated with the target memory cell. In certain cases, the command decoder 120 may include the control block 132. Additionally, the control block 132 may also provide timing control and data control functions to facilitate execution of different commands regarding the corresponding bank 102.

[0048] Furthermore, the command decoder 120 may provide register commands to one or more registers 128 to facilitate operation of one or more of the bank 102, the control block 132, and the like. For example, one of the one or more registers 128 may provide instructions for various modes for configuring programmable operations and / or configurations of the memory device 100. The one or more registers 128 may be included in various semiconductor devices to provide and / or define the operation of various components of the memory device 100.

[0049] In some embodiments, the one or more registers 128 may provide configuration information to define the operation of the memory device 100. For example, the one or more registers 128 may include operation instructions for DRAM, synchronous DRAM, FeRAM, chalcogenide memories (e.g., SSM memories, PC memories), or other types of memories. As discussed above, the one or more registers 128 may receive various signals from the command decoder 120 or other components via the one or more global routing lines 130.

[0050] In some embodiments, one or more global wiring lines 130 may include a common data path, a common address path, a common write command path, and a common read command path. The one or more global wiring lines 130 may span the memory device 100 such that each of the one or more registers 128 may be coupled to the global wiring lines 130. Additional registers may involve additional wiring across the semiconductor device (e.g., die) such that the registers are communicatively coupled to the corresponding memory components.

[0051] The I / O interface 106 may include several pins (e.g., 7 pins) for facilitating data communication with external components (e.g., a processing component such as a processor). Specifically, the I / O interface 106 may receive access commands via the pins. Additionally, data stored in the memory cells of the bank 102 may be transferred to and / or retrieved from the bank 102 via the data path 134. The data path 134 may include multiple bidirectional data buses to one or more external devices via the I / O interface 106. For some memory devices (e.g., DDR5 SDRAM memory devices), the I / O signals may be divided into upper and lower bytes; however, this segmentation is not utilized in conjunction with other memory device types.

[0052] Even so, in different embodiments, the memory device 100 may include additional or alternative components. That is, the memory device 100 may include additional or alternative components such as a power supply circuit (for receiving external VDD and VSS signals), read / write amplifiers (for amplifying signals during read / write operations), a temperature sensor (for sensing the temperature of the memory device 100), etc. Thus, it should be understood that the Figure 1 block diagram provided is only to emphasize certain functional features of the memory device 100 to assist in the subsequent detailed description.

[0053] Now referring Figure 2 to, the bank 102 of the memory device 100 according to various examples of the present disclosure will be described. The bank 102 may include several memory cells 200 programmable to store different memory states. In the depicted embodiment, the memory cells 200 may be arranged in multiple rows (e.g., 22 rows, 19 rows, etc.) and multiple columns.

[0054] Memory operations such as reading and writing memory states may be performed on the memory cells 200 by activating or selecting appropriate word lines 202 and digit lines 204. Activating or selecting a word line 202 or a digit line 204 may include applying a voltage to the corresponding line. The word lines 202 and digit lines 204 may include conductive materials.

[0055] For example, the word lines 202 and digit lines 204 can be made of metal (such as copper, aluminum, gold, tungsten, etc.), metal alloys, other conductive materials, or the like. In the depicted embodiment, each row of memory cells 200 is connected to a single word line 202, and each column of memory cells 200 is connected to a single digit line 204. Additionally, each of the memory cells 200 can be associated with a row and a column of the bank 102. Thus, each of the memory cells 200 is connected to a corresponding word line 202 and a corresponding digit line 204.

[0056] By applying a voltage to a single word line 202 and a single digit line 204, a single memory cell 200 can be activated (or accessed) at their intersection. Accessing the memory cell 200 can include performing a read or write operation on the memory cell 200. For example, a read operation can include sensing the charge level from the memory cell 200. The intersection of the word line 202 and the digit line 204 can be referred to as the address of the corresponding memory cell 200. Thus, the command decoder 120 can provide access instructions containing address bits to indicate the word line 202 and the digit line 204 corresponding to the target memory cell 200.

[0057] In some architectures, the memory state storage device (e.g., a capacitor) of the memory cell 200 can be electrically isolated from the digit line by a selection component. The word line 202 can be connected to the selection component and can control the selection component. For example, the selection component can be a transistor and the word line 202 can be connected to the gate of the transistor. Activating the word line 202 can cause an electrical connection or a closed circuit between the capacitor of the memory cell 200 and its corresponding digit line 204. Then the digit line 204 can be activated to read or write to the memory cell 200.

[0058] Thus, accessing the memory cell 200 can be controlled by a corresponding row decoder 206 and a corresponding column decoder 210. As mentioned above, in different embodiments, the controller 108, the command decoder 120, and / or the control block 132 can include the row decoder 206 and / or the column decoder 210. In some instances, the row decoder 206 can receive a row address from the command decoder 120 and can activate an appropriate word line 202 based on the received row address.

[0059] Similarly, the column decoder 210 can receive a column address from the command decoder 120 and activate an appropriate digit line 204. The command decoder 120 can provide the row address and the column address based on receiving and decoding the access command and providing access instructions. For example, the bank 102 can include multiple word lines 202 (labeled WL_1 to WL_M) and multiple digit lines 204 (labeled DL_1 to DL_N), where M and N depend on the array size. Thus, by activating the word line 202 and the digit line 204 (e.g., WL_2 and DL_3), the memory cell 200 can be accessed at their intersection.

[0060] In any case, after access, the memory cell 200 can be read or sensed by the sensing component 208 to determine the stored state of the memory cell 200. For example, after accessing the memory cell 200, the ferroelectric capacitor of the memory cell 200 can discharge a first charge (e.g., dielectric charge) onto its corresponding digit line 204. In other instances, after accessing the memory cell 200, the ferroelectric capacitor of the memory cell 200 can discharge a second or third charge (e.g., polarization charge) onto its corresponding digit line 204. Discharging the ferroelectric capacitor can be based on biasing the ferroelectric capacitor or applying a voltage to the ferroelectric capacitor.

[0061] The discharge can cause a change in the voltage of the digit line 204, and the sensing component 208 can compare the voltage with a reference voltage (not shown) to determine the stored state of the memory cell 200. For example, if the digit line 204 has a voltage higher than the reference voltage, then the sensing component 208 can determine that the stored state in the memory cell 200 is associated with a first predefined memory state. In some cases, the first memory state can include state 1, or can be another value - including other logical values associated with implementing multi-level sensing for storing more than two values (e.g., 3 states per cell or 1.5 bits per cell). The sensing component 208 can include various transistors or amplifiers to detect and amplify the signal difference, which can be referred to as latching. Then, the detected logical state of the memory cell 200 can be output as output 212 through the column decoder 210.

[0062] In some instances, detecting and amplifying the signal difference can include latching the charge sensed in the sensing component 208. An example of this charge can include latching the dielectric charge associated with the memory cell 200. As an example, the sensing component 208 can sense the dielectric charge associated with the memory cell 200. The sensed dielectric charge can be latched in a latch within the sensing component 208 or in a separate latch in electronic communication with the sensing component 208.

[0063] In view of the foregoing, Figure 3A and 3B A schematic diagram depicting a circuit associated with at least a portion of the command decoder 120. Specifically, Figure 3A A first portion of a schematic diagram depicting a circuit associated with at least a portion of the command decoder 120 and Figure 3BDepict the second part. The command decoder 120 may include circuitry 300 for receiving and decoding access commands transmitted using a multi-clock cycle memory command protocol. In some cases, the circuitry 300 may also receive and decode access commands transmitted using other memory command protocols (e.g., a single-clock cycle memory command protocol). Subsequently, the circuitry 300 may provide access instructions to downstream memory components.

[0064] The circuitry 300 may include a first part 300A of the circuitry, a second part 300B of the circuitry, and a third part 300C of the circuitry. The first part 300A of the circuitry and the second part 300B of the circuitry may provide an activation signal 302 (INT_ACT_1P) based on receiving a header 304 (INT_CA_R1<1:0>). For example, when the command decoder 120 is receiving an access command using a multi-clock cycle memory command protocol, the first part 300A of the circuitry and the second part 300B of the circuitry may generate and use the activation signal 302. As will be appreciated, the third part 300C of the circuitry may receive address bits of the access command based on the operation of the first part 300A of the circuitry and the second part 300B of the circuitry and provide the address bits to downstream memory components. In some cases, the downstream memory components may include Figure 1 control block 132 of Figure 1 bank 102 of Figure 2 row decoder 206 and column decoder 210 of

[0065] When using a multi-clock cycle memory command protocol, the memory device 100 may receive access commands using multiple edges of an external clock signal. As mentioned above, each clock cycle of the external clock signal may include a rising edge and a falling edge of the external clock signal. Additionally, in some cases, each memory cycle for performing a memory operation may correspond to one or more clock cycles of the external clock signal. Thus, in certain cases, the circuitry 300 of the command decoder 120 may receive access commands using the external clock signal and provide access instructions for performing a memory operation in one memory cycle based on using an internal clock signal of the memory device 100 (e.g., CLK).

[0066] In view of the foregoing, the inverter 306 of the circuitry 300 may receive a high (or logic 1) chip select signal 308 (INT_CS) associated with a first edge of the external clock signal. For example, the chip select signal 308 may indicate receiving a first access command provided using a multi-clock cycle memory command protocol. The inverter 306 may provide an inverted chip select signal having a logic 0 value to the NOR gate 310. Based on receiving the chip select signal 308, the NOR gate 310 may output a logic 1 value to the NAND gate 312.

[0067] The NAND gate 312 can also receive the header 304 provided by the first edge of an external clock signal using a multi-clock cycle memory command protocol. For example, the header 304 can include two logical 1 values or high data bits. Embodiments of the header 304 are also discussed below with reference to Figure 5 In any case, the NAND gate 312 can provide a logical 0 value to the inverter 314 based on receiving a high signal (or logical 1 value) from the header 304 and the NOR gate 310. The inverter 314 can in turn provide a logical 1 value to the latch circuit 316 (e.g., a flip-flop).

[0068] The latch circuit 316 can also receive an internal memory clock signal 318. In the depicted embodiment, the internal memory clock signal 318 can correspond to the CLK discussed above with respect to Figure 1 The internal memory clock signal 318 can switch between a logical 0 value and a logical 1 value according to the clock frequency. In any case, the latch circuit 316 can provide a logical 1 value in response to receiving a logical 1 value from the inverter 314 and receiving the internal memory clock signal 318 (e.g., the rising edge of the internal memory clock signal 318).

[0069] The latch circuit 316 can provide a logical 1 value to the AND gate 320. The AND gate 320 can also receive the internal memory clock signal 318. Thus, the AND gate 320 can provide a high (or logical 1 value) first internal signal 322 (INT_ACT1) based on receiving the logical 1 value of the latch circuit 316 and the internal memory clock signal 318 (e.g., the rising edge of the internal clock signal 318). The AND gate 320 can provide the first internal signal 322 having a logical 1 value to the first input of the NOR gate 324 and the latch circuit 326 of the third part 300C of the circuit.

[0070] The latch circuit 326 of the third part 300C of the circuit can receive a first part 328 (INT_CA_R1<6:2>) of the address bits and a second part 330 (INT_CA_F1<6:0>) of the address bits based on receiving the first internal signal 322 having a logical 1 value. In some cases, the first part 328 of the address bits can include the address bits of an access command received using the first edge of an external clock signal. For example, when the memory device 100 uses 7 pins to receive data bits, the memory device 100 can receive the header 304 and the first part 328 of the address bits.

[0071] For example, the header 304 may include 2 data bits and the first part 328 of the address bits may include 5 data bits. Additionally, the second part 330 of the address bits may include the address bits of an access command received using a second edge (e.g., a subsequent clock edge) of an external clock signal. For example, the second part 330 of the address bits may include 7 data bits received via 7 pins of the memory device 100. Thus, in one instance, the latch circuit may receive 12 address bits of an access command using the first and second edges of an external clock signal.

[0072] The NOR gate 324 of the first part 300A of the circuit may provide a first signal 332 to the NOR gate 334 of the second part 300B of the circuit. The NOR gate 324 may provide the first signal 332 based on receiving a first internal signal 322 having a logic 1 value and an internal memory clock signal 318. Thus, the NOR gate 324 may provide a logic 0 value as the first signal 332 to the first input of the NOR gate 334. The second input of the NOR gate 334 may be held low or receive a logic 0 value. Therefore, the NOR gate 334 may in turn provide a second signal 336 based on receiving the first signal 332 at the first input and a logic 0 value at the second input. Thus, the NOR gate 334 may provide (or return) a logic 1 value as the second signal 336 to the second input of the NOR gate 324.

[0073] Subsequently, the NOR gate 324 may provide a logic 0 value based on receiving the logic 1 value of the second signal 336. The NOR gate 324 may provide the logic 0 value to the inverter 338. Thus, the inverter 338 may provide a logic 1 value as the activation signal 302. For example, the logic 1 value (e.g., the rising edge of the activation signal 302) of the activation signal 302 may indicate receipt of an access command provided using the first and second edges of an external clock signal.

[0074] Additionally, as will be appreciated, the activation signal 302 may facilitate receipt of the remaining address bits of an access command provided using a multi - clock - cycle memory command protocol for performing a memory operation in one memory cycle. Thus, the memory device 100 may use the circuit 300 to efficiently receive additional address bits of an access command (e.g., each access command) using subsequent edges of an external clock cycle in a memory cycle. In certain cases, based on using a multi - clock - cycle memory command protocol, subsequent edges of an external clock cycle may include only address bits. Such address bits may include information related to the bank address, row address, and / or column address of the target memory cell 200.

[0075] In view of the foregoing, the inverter 338 may provide a logic 1 value of the activation signal 302 (INT_ACT1P) to the NOR gate 310 (e.g., in a feedback scheme). In some cases, the circuit 300 may receive a second chip select signal 308. In such cases, the NOR gate 310 may also receive a logic 0 value from the inverter 306. In any case, the NOR gate 310 may provide a logic 0 value to the NAND gate 312 when receiving the activation signal 302 having a logic 1 value. Accordingly, the NAND gate 312 may provide a logic 1 value to the inverter 314.

[0076] The inverter 314 may in turn provide a logic 0 value to the latch circuit 316. Subsequently, the latch circuit 316 and the AND gate 320 may provide a logic 0 value of the first internal signal 322 to the first input of the NOR gate 324 and the latch circuit 326 of the third part 300C of the circuit. In some cases, the latch circuit 326 may not receive (e.g., input) additional data bits based on receiving the logic 0 value of the first internal signal 322.

[0077] When using one clock cycle to provide an access instruction, the circuit 300 may provide the received address bits to a downstream memory component. For example, the latch circuit 326 may provide a first part 328 and a second part 330 of the address bits to the downstream memory component. However, when using multiple clock cycles (e.g., 2 clock cycles, 3 clock cycles, etc.) to provide an access instruction, the circuit 300 may receive the remaining parts of the address bits based on the operations described herein. Even so, it should be understood that the example embodiments described herein are by way of example and different circuit schemes may perform similar or different functions for receiving the remaining parts of the address bits.

[0078] In any case, the NAND gate 340 may receive the activation signal 302 having a logic 1 value and a reference voltage 342 having a logic 1 value (e.g., VPERI). For example, an internal or external power supply may provide the reference voltage 342. Subsequently, the NAND gate 340 may provide a logic 0 value to the inverter 344 in response to receiving the logic 1 input of the activation signal 302 and the high reference voltage 342. The inverter 344 may in turn provide a logic 1 output to the latch circuit 346 (e.g., a flip-flop). The latch circuit 346 may also receive an internal memory clock signal 318.

[0079] Subsequently, the latch circuit 346 may provide a logic 1 output to the AND gate 348. The AND gate 348 may also receive the internal memory clock signal 318. The AND gate 348 may provide a second internal signal 350 having a logic 1 value. The AND gate 348 may provide the second internal signal 350 to the second input of the NOR gate 334 and the latch circuit 352 of the third part 300C of the circuit. The latch circuit 352 may receive (e.g., input) a third part 354 (INT_CA_R2<6:0>) of the address bits and a fourth part 356 (INT_CA_F2<6:0>) of the address bits based on receiving the second internal signal 350 (INT_ACT2).

[0080] For example, the latch circuit 352 may receive the third part 354 of the address bits at the third edge of the external clock signal and may receive the fourth part 356 of the address bits at the fourth edge of the external clock signal. Additionally, when the memory device 100 includes 7 pins for communicating data bits, the third part 354 of the address bits and the fourth part 356 of the address bits may each include 7 (or up to 7) address bits. Thus, the latch circuit 352 may receive 14 address bits using the third and fourth edges of the external clock signal.

[0081] Accordingly, the NOR gate 334 may receive the second internal signal 350 and the first signal 332 output from the NOR gate 324 of the first part 300A of the circuit. Thus, the NOR gate 334 may provide a logic 0 value as the second signal 336 to the NOR gate 324. Therefore, the NOR gate 324 may provide a logic 1 value based on receiving the first internal signal 322 and the logic 0 value of the second signal 336. Accordingly, the inverter 338 may provide a logic 0 value for the activation signal 302. In some cases, the first part 300A of the circuit may become idle in response to the inverter 338 providing a logic 1 value for the activation signal 302. Additionally, the second part 300B of the circuit may become idle in response to the inverter 338 providing a logic 0 value for the activation signal 302.

[0082] The AND gate 348 may also provide the second internal signal 350 (INT_ACT2) to the inverter string 358. The inverter string 358 may include an even number of inverters. For example, in the depicted embodiment, the inverter string 358 may include 4 inverters. Such inverters may buffer or delay the second internal signal 350. Thus, in different embodiments, different electronic components may be used in place of the inverter string 358. For example, in some cases, the inverter string 358 may include several buffers.

[0083] In any case, the inverter string 358 can delay the second internal signal 350. Subsequently, the inverter string 358 can provide a trigger signal 360 (INT_ACT2_2). The inverter string 358 can provide the trigger signal 360 to the latch circuit 362. The latch circuit 362 can be connected to the outputs of the latch circuits 326 and 352. The first part 328 of the address bits, the second part 330 of the address bits, the third part 354 of the address bits, and the fourth part 356 of the address bits can include the bank address 364 and the row address 366. Thus, based on receiving the trigger signal 360, the latch circuit 362 can receive the bank address 364 and the row address 366 from the latch circuits 326 and 352.

[0084] Thus, the latch circuit 362 can provide the bank address 364 and the row address 366 to the downstream memory component based on receiving the trigger signal 360. For example, the latch circuit 362 can provide the bank address 364 and the row address 366 to the control block 132 of the bank 102 via the bus path 126, as described above with respect to Figure 1 described.

[0085] In different embodiments, the controller 108, the command interface 104, the control block 132, the row decoder 206, the column decoder 210, or a combination of the foregoing memory components (or blocks), and other viable memory components can include the circuit 300. Additionally, it should be understood that the circuit 300 is depicted by way of example and in other cases, the memory device 100 can include different circuits 300 for receiving and decoding access commands provided using a multi-clock cycle memory command protocol to provide access instructions to the downstream memory components.

[0086] In view of the foregoing, Figure 4 is a timing diagram 400 depicting an example timing of signals for accessing the memory cells 200 of the memory device 100 using a multi-clock cycle memory command protocol and the command decoder 120. The timing diagram 400 can include signals received via the external bus 112, signals of the command decoder 120 (e.g., the circuit 300), and signals transmitted via the bus path 126 to access the requested memory cells 200.

[0087] As mentioned above, the memory device 100 can receive an access command 402 (CA<6:0>). In some cases, the memory device 100 can receive the access command 402 via a processing component (e.g., a processor). In any case, the memory device 100 can receive an access command 402 provided using a multi-clock cycle memory command protocol. Thus, as mentioned above, the access command 402 can include the header 304, the first part 328 of the address bits, the second part 330 of the address bits, the third part 354 of the address bits, and the fourth part 356 of the address bits.

[0088] In addition, in some cases, the memory device 100 may receive an access command 402 in accordance with an edge of an external clock signal 404. In some cases, the memory device 100 may receive a header 304 and a first portion 328 of address bits using a first rising edge 406 (R1) of the external clock signal 404, and may receive a second portion 330 of the address bits using a first falling edge 408 (F1) of the external clock signal 404. A first high signal of the external chip select signal 414 may indicate receiving the header 304 and the first portion 328 of the address bits using the first rising edge 406 and receiving the second portion 330 of the address bits using the first falling edge 408.

[0089] Similarly, the memory device 100 may receive a third portion 354 of the address bits using a second rising edge 410 (R2) of the external clock signal 404, and may receive a fourth portion 356 of the address bits using a second falling edge 412 (F2) of the external clock signal 404. In addition, a second high signal of the external chip select signal 414 may indicate receiving the third portion 354 of the address bits using the second rising edge 410 and receiving the fourth portion 356 of the address bits using the second falling edge 412. For example, as described above with respect to Figure 1 the I / O interface 106 of the memory device 100 described above may receive an access command 402. The I / O interface 106 may provide the access command 402 to a command decoder 120 (or circuit 300).

[0090] Referring now to the signals of the command decoder 120, the command decoder 120 may latch a first portion 328 of the address bits and a second portion 330 of the address bits at a first rising edge 416 of an internal memory clock signal 318 based on a first internal signal 322. As mentioned above and depicted in the timing diagram 400, the command decoder 120 may provide the first internal signal 322 based on receiving a first logic 1 value of a chip select signal 308 and the header 304.

[0091] Subsequently, the command decoder 120 may latch a third portion 354 of the address bits and a fourth portion 356 of the address bits at a second rising edge 418 of the internal memory clock signal 318 based on a second internal signal 350. The command decoder 120 may provide the second internal signal 350 based on providing an activation signal 302. As mentioned above, the command decoder 120 may provide the activation signal 302 based on providing the first internal signal 322.

[0092] Accordingly, the command decoder 120 may include a bank address 364 and a row address 366. Subsequently, the command decoder 120 may provide an access instruction 368 for performing the requested memory operation based on the trigger signal 360 to a downstream memory component (e.g., bank 102). The access instruction 368 may include the bank address 364 and the row address 366.

[0093] In one non-limiting example, bank 102 of the memory device 100 may include 22 rows of memory cells 200. Additionally, the memory device 100 may include 8 banks 102 arranged in 2 memory groups. For example, each memory group may include 4 banks 102. Additionally, the memory device 100 may include 7 pins. Accordingly, the memory device 100 may receive 7 data bits at each edge of the external clock signal 404.

[0094] In this example, the access command 402 may include 26 data bits corresponding to the 22-row bank 102 and the target bank 102, including the header 304 and address bits. Thus, using the multi-command memory command protocol, the command decoder 120 may efficiently receive and decode the access command 402 using 26 data bits to identify the target memory cell 200 and perform the requested memory operation. For example, the command decoder 120 may receive one header 304 for performing the requested memory operation in one memory cycle based on multiple (e.g., 2) clock cycles utilizing the external clock signal 404 and / or the internal memory clock signal 318, and efficiently receive and decode the access command 402 via 7 pins for the 22-row addressed bank 102. Accordingly, the memory device may receive and decode memory access requests faster and more efficiently using the multi-clock cycle memory command protocol.

[0095] Figure 5 FIG. 500 is a diagram depicting an example access command 402 provided using the multi-clock cycle memory command protocol. FIG. 500 may depict the use of 7 pins 502 (e.g., CA0, CA1, …, CA6) of the memory device 100 to receive the access command 402. In some embodiments, the I / O interface 106 may include the pins 502.

[0096] In some embodiments, as described above and Figure 5 as depicted in, when receiving the first logic 1 value of the external chip select signal 414, the command decoder 120 (e.g., circuit 300) may receive the header 304 (e.g., high signal H) of the access command 402 and the first part 328 of the address bits at the first rising edge 406 of the external clock signal 404. In the depicted embodiment, the first part 328 of the address bits may include 5 data bits of the row address 366 (e.g., R13, R14, R15, R16, and R17).

[0097] In addition, the command decoder 120 may receive a second portion 330 of the address bits of the access command 402 at the first falling edge 408. In the depicted embodiment, the second portion 330 of the address bits may include 4 data bits indicating the bank address 364 (e.g., BA0, BA1, BG0, and BA2, and BG1 and BA3). The second portion 330 of the address bits may further include 3 data bits of the row address 366.

[0098] When receiving the second logic 1 value of the external chip select signal 414, the command decoder 120 may receive a third portion 354 of the address bits of the access command 402 at the second rising edge 410 of the external clock signal 404. In the depicted embodiment, the third portion 354 of the address bits may include 7 data bits of the row address 366.

[0099] Similarly, when receiving the second logic 1 value of the external chip select signal 414, the command decoder 120 may receive a fourth portion 356 of the address bits of the access command 402 at the second falling edge 412 of the external clock signal 404. In the depicted embodiment, the fourth portion 356 of the address bits may include 7 data bits of the row address 366.

[0100] Considering these technical effects, providing such a memory command protocol may allow for efficient execution of memory operations when using memory devices that include a higher number of rows and / or columns in each bank of a memory array having a constant number of communication pins. For example, the controller may efficiently access the memory cells of a bank having a higher number of rows and / or columns and a lower number of communication pins by providing commands using a higher number of clock cycles. Additionally, in some cases, the controller may be on the host side of a memory host interface; for example, a processor, microcontroller, field programmable gate array (FPGA), application specific integrated circuit (ASIC), or the like may each include a memory controller to facilitate execution of such operations. Further, a communication network may enable data communication therebetween and thus, enable a client device to utilize the hardware resources accessible through the controller.

[0101] At least partially based on user input to the client device, the processing circuitry associated with the memory device may perform one or more operations to transmit one or more memory access requests for accessing the memory cells of multiple rows of data banks arranged as a memory array. Additionally, the controller may use a number of clock cycles to provide commands based on the number of rows of the bank and the number of communication pins of the bank to facilitate an efficient response to the one or more memory access requests.

[0102] Data communicated between the client device and the memory device can be used for various purposes, including but not limited to presenting visualizations, processing operations, calculations, or the like to a user via a graphical user interface (GUI) at the client device. Accordingly, in view of this, the above improvements to the memory, controller operations, and memory operations can manifest as improvements in visualization quality (e.g., display speed, display quality), processing operations, calculations, or the like.

[0103] The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may have various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure.

[0104] Reference is made to the technology presented and claimed herein and applied to tangible material objects and specific examples of a practical nature that clearly improve the art and are thus not abstract, intangible, or purely theoretical. Further, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [function]..." or "step for [performing] [function]...", then it is intended that such elements be construed in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements not be construed in accordance with 35 U.S.C. 112(f).

Claims

1. A memory device, comprising: a plurality of banks, each of the plurality of banks including a plurality of memory cells; and a command decoder circuitry, wherein the command decoder circuitry is configured to receive an access command provided within two clock cycles of an external clock signal to access one or more target memory cells of the plurality of memory cells of the plurality of banks, wherein the command decoder circuitry includes: a first portion including circuitry configured to provide a first signal and an activation signal in response to receiving a header of the access command and a first chip select signal during a first clock cycle of the two clock cycles; a second portion including circuitry configured to provide a second signal in response to receiving the activation signal; and a third portion including circuitry configured to: receive a first portion of address bits of the access command during the first clock cycle of the two clock cycles based on receiving the first signal; receive a second portion of address bits of the access command during a second clock cycle of the two clock cycles based on receiving the second signal; and provide the first portion of the address bits and the second portion of the address bits to access the target memory cell based on receiving a trigger signal associated with the second signal.

2. The memory device according to claim 1, wherein each clock cycle corresponds to a rising edge and a falling edge of the external clock signal, and wherein the memory device is configured to receive data bits at the rising edge and the falling edge of the external clock signal.

3. The memory device according to claim 2, wherein the memory device includes 7 pins for receiving the access command, wherein the memory device is configured to receive 1 data bit using each pin at each rising edge or falling edge of the external clock signal.

4. The memory device according to claim 3, wherein the command decoder circuitry is configured to: receive 2 data bits associated with the header and 12 data bits associated with the first portion of the address bits during the first clock cycle; and receive 14 data bits associated with the second portion of the address bits during the second clock cycle.

5. The memory device according to claim 1, wherein the trigger signal is a delay signal associated with the second signal.

6. The memory device according to claim 1, wherein the banks of the plurality of banks include 22 rows of memory cells.

7. The memory device according to claim 6, wherein the access command includes 22 address bits corresponding to the 22 rows of the banks.

8. A method for memory operation, comprising: receiving, by a command decoder circuitry of a memory system, a header of an access command and a first portion of address bits for performing the memory operation during a first clock cycle of an external clock signal; providing, by the command decoder circuitry, a first signal and an activation signal based on receiving the header; The latch circuitry of the command decoder circuitry latches the first portion of the address bits based on the first signal; The command decoder circuitry provides a second signal and a trigger signal in response to receiving the activation signal; The command decoder circuitry receives the second portion of the address bits of the access command during a second clock cycle of the external clock signal; The command decoder circuitry latches the second portion of the address bits based on the second signal; and The command decoder circuitry provides the first portion and the second portion of the address bits to a downstream memory component for performing the memory operation based on the trigger signal.

9. The method according to claim 8, wherein the memory device comprises 7 pins.

10. The method according to claim 9, wherein each of the first clock cycle and the second clock cycle comprises a rising edge and a falling edge of the external clock signal.

11. The method according to claim 10, wherein the memory system is configured to receive 7 data bits of the access command at the rising edge of each of the first clock cycle and the second clock cycle using the 7 pins, and receive 7 data bits of the access command at the falling edge.

12. The method according to claim 8, wherein the access command comprises 28 data bits, the 28 data bits comprising 2 data bits of the header and 26 address bits.

13. The method according to claim 12, wherein the 26 address bits comprise 22 row address bits corresponding to 22 rows of memory cells of a bank of the memory device.

14. A memory device, comprising: A processor subsystem configured to provide an access command for performing one or more memory operations; A bus; and A memory subsystem communicatively coupled to the processor subsystem via the bus, wherein the memory subsystem comprises: A first portion configured to receive the header of the access command via the bus and provide a first signal in response to receiving the header, wherein the first portion is configured to provide the first signal to: A first NOR gate of the first portion, wherein the first NOR gate is configured to provide a high activation signal to a second NOR gate of the first portion and a second portion of the memory subsystem based on receiving the first signal; and A first latch circuitry of a third portion of the memory subsystem, wherein the first latch circuitry is configured to receive a first address portion of the access command; The second portion configured to provide a second signal in response to receiving the high activation signal, wherein the second portion is configured to provide the second signal to: The first NOR gate of the second part, which is coupled to the first NOR gate of the first part, wherein the first NOR gate of the first part is configured to provide a low activation signal to the second NOR gate of the first part and the second part of the memory subsystem based on receiving the second signal by the first NOR gate of the second part; A delay circuit, wherein the delay circuit is configured to provide a delayed signal of the second signal to a third latch circuit of the third part; and The second latch circuit of the third part, wherein the second latch circuit is configured to receive a second address portion of the access command; and The third part, which includes: The first latch circuit; The second latch circuit; and A third latch circuit, which is configured to provide the first address portion of the access command and the second address portion of the access command based on receiving the delayed signal of the second signal from the delay circuit.

15. The memory device according to claim 14, wherein the first signal transitions to low based on the second NOR gate of the first part receiving the first signal.

16. The memory device according to claim 14, wherein the first address portion and the second address portion of the access command indicate one or more target memory cells for performing the one or more memory operations.

17. The memory device according to claim 14, wherein: The first part of the memory subsystem is configured to become idle in response to the second NOR gate of the first part receiving the high activation signal; and The second part of the memory subsystem is configured to become idle in response to receiving the low activation signal.

18. The memory device according to claim 14, wherein the access command includes 26 data bits, and wherein the memory subsystem is configured to receive the access command using the rising edge and the falling edge of a first clock cycle and the rising edge and the falling edge of a second clock cycle.

19. The memory device according to claim 14, wherein the delay circuit includes a plurality of inverters or buffers.

20. The memory device according to claim 14, wherein the memory subsystem is configured to receive the header and the first address portion of the access command based on a first clock cycle of a clock signal associated with the device, and receive the second address portion of the access command based on a second clock cycle of the clock signal.

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