Sensor node processor and signal processing method

Abstract

The application provides a sensor node processor and a signal processing method. The processor is a K-level processor in a cascade structure; K is a positive integer greater than 1; the processor of each level has smaller calculation complexity and spatial complexity compared with the processor of the next level; in the case that the processing result of the i-th level processor on the to-be-processed data meets the preset requirement, the (i+1)-th level processor is in a non-working state; 1≤i<K. According to the embodiment of the application, the problem that the process power consumption of signal processing is large, the battery needs to be frequently replaced, and the user experience is poor can be solved.

Description

Technical Field

[0001] This application belongs to the field of communication technology, and in particular relates to a sensor node processor and signal processing method. Background Technology

[0002] Sensor nodes can self-organize their networks and utilize wireless communication technology for data forwarding. Each node possesses dual functions: data acquisition and data fusion forwarding. Intelligent sensor nodes also include a digital domain signal processor, which can perform tasks such as classifying, detecting, or regressing the raw input signals.

[0003] In existing technologies, when using sensor nodes to process signals, the computational and spatial complexity requirements for data processing are relatively high, resulting in significant power consumption by the sensor nodes. However, the power modules of the sensor nodes have relatively low power consumption. Therefore, when using existing sensor nodes to complete data processing with high computational and spatial complexity, it is necessary to frequently replace the battery modules of the sensor nodes, which affects the user experience. Summary of the Invention

[0004] This application provides a sensor node processor and a signal processing method to solve the problems of high power consumption, frequent battery replacements, and poor user experience in signal processing.

[0005] In a first aspect, embodiments of this application provide a sensor node processor, which is a cascaded K-level processor; wherein K is a positive integer greater than 1;

[0006] Each level of processor has lower computational and space complexity compared to the level below it.

[0007] If the processor at level i determines that the processing result of the data to be processed meets the preset requirements, the processor at level i+1 is in a non-working state; where 1≤i<K.

[0008] In some possible implementations of the first aspect, the processor at level K+1 is in operation when it is determined that the processing result of the processor at level K does not meet the preset requirements for the data to be processed.

[0009] In some possible implementations of the first aspect, the processors of the first j levels of the multi-level processor perform detection at least in the following manner: zero-crossing rate, positive pulse width, and negative pulse width; where 1≤j<K.

[0010] In some possible implementations of the first aspect, the processors of the later P-level stages of a multi-level processor employ a convolutional neural network architecture; P = Kj.

[0011] In some possible implementations of the first aspect, the convolutional neural network architecture includes convolutional layers and fully connected layers.

[0012] In some possible implementations of the first aspect, the convolutional layer employs a pulsating array structure.

[0013] In some possible implementations of the first aspect, the computational core in the systolic array employs multiplexers and adders.

[0014] In some possible implementations of the first aspect, the number of computational cores is at least one.

[0015] Among some possible implementations of the first aspect, the multi-level processor can be implemented in any of the following ways: application-specific integrated circuits, field-programmable gate arrays, and microcontrollers.

[0016] Secondly, embodiments of this application provide a signal processing method, which is applied to any sensor node processor, wherein the processor is a K-level processor in a cascaded structure, and K is a positive integer greater than 1;

[0017] The methods include:

[0018] Obtain the data to be processed;

[0019] If the processor at level i determines that the processing result of the data to be processed meets the preset requirements, the processor at level i+1 is in a non-working state, where 1≤i<K.

[0020] In the embodiments of this application, since each level of processor has lower computational and space complexity than the next level of processor, when processing data, if the calculation result of the current level of processor can meet the requirements, there is no need to turn on the next level of processor. In this way, the data to be processed can be processed with lower power consumption, thereby saving power consumption. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a sensor node processor structure provided in one embodiment of this application;

[0023] Figure 2 This is a schematic diagram of a sensor node processor structure provided in another embodiment of this application;

[0024] Figure 3This is a schematic diagram of a sensor node processor structure provided in another embodiment of this application;

[0025] Figure 4 This is a schematic diagram of another sensor node processor structure provided in another embodiment of this application;

[0026] Figure 5 This is a schematic diagram of a sensor node processor structure provided in another embodiment of this application;

[0027] Figure 6 This is a schematic diagram of a sensor node processor structure provided in another embodiment of this application. Detailed Implementation

[0028] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0030] Sensor nodes serve as a bridge connecting the physical and intelligent worlds, playing a crucial role in the era of the Internet of Things (IoT). Applications include intelligent voice control systems, bridge safety monitoring systems, and biosignal detection applications in healthcare. In addition to the sensor front-end that interacts with the physical world and the analog front-end that modulates, amplifies, and quantizes electrical signals into digital signals, sensor nodes also include a digital domain signal processor. This processor is capable of performing signal tasks such as classifying, detecting, or regressing the raw input signals.

[0031] High-accuracy digital signal processing involves significant computational and spatial complexity, resulting in substantial power consumption. This fails to meet the requirements of near-sensing nodes for ultra-low power consumption and low computational complexity. Simultaneously, signal processing demands high accuracy and recognition capabilities to provide truly effective information.

[0032] Currently, in existing technologies, when using sensor nodes to process signals, the computational and spatial complexity requirements for data processing are relatively high, resulting in significant power consumption by the sensor nodes. However, the power modules of the sensor nodes have relatively low power consumption. Therefore, when using existing sensor nodes to complete data processing with high computational and spatial complexity, it is necessary to frequently replace the battery modules of the sensor nodes, which affects the user experience.

[0033] To address the problems of the prior art, this application provides a sensor node processor and a signal processing method. The sensor node processor provided in this application will be described first.

[0034] The processor is a cascaded K-level processor; where K is a positive integer greater than 1.

[0035] Each level of processor has lower computational and space complexity compared to the level below it.

[0036] If the processor at level i determines that the processing result of the data to be processed meets the preset requirements, the processor at level i+1 is in a non-working state; where 1≤i<K.

[0037] The processing result can be the result obtained after detecting the data to be processed. For example, when the data to be processed is an electrocardiogram (ECG) signal, the processing result can be "signal normal" or "signal abnormal". Correspondingly, the preset requirement can be that the processing result is "signal normal" or "signal abnormal".

[0038] More specifically, the treatment outcome can also be the type of abnormal electrocardiogram (ECG) signal, such as arrhythmia or sinus rhythm.

[0039] The preset requirement can be the desired processing result of the data to be processed by the user. This requirement can be set by the user according to their needs, and there are no restrictions here.

[0040] As an example, see reference Figure 1 The sensor node processor can be a cascaded three-level processor, which includes three levels of processors (i.e. Figure 1 The first-level processor, second-level processor, and third-level processor in the system.

[0041] Continuing with the example above, taking the ECG signal as the data to be processed, if the user wants to detect whether the ECG signal is abnormal, they would input the ECG signal into... Figure 1 In the first-level processor shown, after processing by the first-level processor, the ECG signal is determined to be an abnormal ECG signal. That is, the processing result meets the user's preset requirements, so the second-level processor does not need to be activated.

[0042] In some embodiments of this application, reference continues to be made to Figure 1 The sensor node processor provided in this application embodiment may further include a data buffer module, which is used to buffer the processing result of the processor of the i-th level on the data to be processed when the processing result of the processor of the i-th level on the data to be processed does not meet the preset requirements, and the processor of the (i+1)-th level can obtain the processing result of the processor of the i-th level on the data to be processed from the buffered data.

[0043] In some embodiments of this application, the data buffer can be a storage space of a specified size reserved in memory for temporary storage of data to be processed. This reserved memory space is called a buffer and is used to store data.

[0044] Continue to refer to Figure 1 The sensor node processor provided in this application embodiment may further include a power gating between the processor at the i-th level and the processor at the i+1-th level.

[0045] In some embodiments of this application, power gating can be used to control whether the processor at level i+1 is in an active or inactive state. Specifically, when the processor at level i+1 needs to process data, the power gating between the processor at level i and the processor at level i+1 is enabled, so that the processor at level i+1 is in an active state; when the processor at level i+1 does not need to process data, the power gating between the processor at level i and the processor at level i+1 is disabled, so that the processor at level i+1 is in an inactive state.

[0046] Continue to refer to Figure 1 The sensor node processor provided in this application embodiment may further include an output integration module, which can be used to integrate and output the processing results of the sensor node processor on the data to be processed.

[0047] In this way, since each level of processor has lower computational and space complexity than the next level of processor, when processing data, if the calculation result of the current level of processor can meet the requirements, there is no need to turn on the next level of processor. This allows the data to be processed to be processed with lower power consumption, thereby saving power.

[0048] In some embodiments, in order to make the data processing results accurate and achieve the results desired by the user, the processor at level (i+1) is in working state when it is determined that the processing result of the processor at level i does not meet the preset requirements.

[0049] As an example, when the data to be processed is an electrocardiogram signal, the processing result is an abnormal signal. When the preset requirement is a normal signal, the processing result does not meet the preset requirement. At this time, the power gating can be controlled to start the next level processor to process the data to be processed.

[0050] In one example, taking an electrocardiogram (ECG) signal as the data to be processed, if a user wants to detect whether the ECG signal is abnormal, and if so, to determine the type of abnormality, the ECG signal is input to... Figure 1 In the first-level processor shown, after processing, the ECG signal is determined to be an abnormal ECG signal. If the processing result does not meet the user's preset requirements, the second-level processor needs to be activated to further detect the abnormal ECG signal and determine that the abnormality type is arrhythmia.

[0051] In some embodiments, to further save power consumption, the processors of the first j levels of the multi-level processor perform detection in at least the following manner: zero-crossing rate, positive pulse width, and negative pulse width; wherein, 1≤j<K.

[0052] Zero-crossing rate, which is the number of times a digital signal crosses zero, is a time-domain characteristic of the characteristic peak of a near-sensor signal. It can characterize the morphological features of the digital signal to some extent and has relatively low computational complexity. It can be implemented using a state machine and NAND gates (rising and falling edge detection).

[0053] Positive and negative pulse widths represent rise and fall times in near-sensing signals, characterizing the spatial features of digital signals with relatively low hardware complexity. They can be implemented using multi-input AND gates.

[0054] To better understand the above embodiments, this application provides a schematic diagram of a processor architecture with the first j levels, as shown below. Figure 2 As shown, the processor in the first j-level can be an ultra-low-power processor based on low computational complexity. The quantizer discretizes the amplitude of the sampled instantaneous value, representing it with the closest available level value using a set of defined voltage levels. Features 1, 2, and 3 can be the zero-crossing rate, positive pulse width, and negative pulse width, respectively. When the data to be processed enters the processor at this level, the feature-based decision logic makes a judgment based on these three features, thereby outputting the data to the output module to achieve the output of the processing result.

[0055] In one example, taking electrocardiogram (ECG) signals as the data to be processed, three threshold decision conditions are set based on the characteristics of the three features (zero-crossing rate, positive pulse width, and negative pulse width) in normal ECG signals, and implemented using logic gates. The zero-crossing rate is set to 4, the positive pulse width duration is greater than 6, and the negative pulse width duration is greater than 4. Based on these threshold decision conditions, abnormal ECG signals can be basically detected.

[0056] Thus, the first j levels of the multi-level processor use at least the following methods for detection: zero-crossing rate, positive pulse width, and negative pulse width. The data to be processed is initially screened using the above three features. The power consumption of the screening process is lower than that of the calculation process, so the initial processing of the data to be processed can be completed with lower power consumption.

[0057] In some embodiments, to make data processing more precise, the processors in the later P-level layers of a multi-level processor can employ a convolutional neural network architecture; P = Kj.

[0058] Convolutional Neural Networks (CNNs) are a type of feedforward neural network that incorporates convolutional computations and has a deep structure. They are one of the representative algorithms of deep learning. CNNs possess representation learning capabilities, enabling them to perform shift-invariant classification of input information according to their hierarchical structure; therefore, they are also known as Shift-Invariant Artificial Neural Networks (SIANNs).

[0059] In some embodiments, to further improve the accuracy of data processing, a convolutional neural network architecture may include convolutional layers and fully connected layers.

[0060] To better understand this approach, the convolutional neural network architecture will be described in detail below.

[0061] In a convolutional neural network, a convolutional layer consists of several convolutional units, and the parameters of each convolutional unit are optimized through the backpropagation algorithm. The purpose of convolution is to extract different features from the input. The first convolutional layer may only extract some one-dimensional signals, such as pulse width intervals and amplitudes. More layers of the network can iteratively extract more complex features from low-level features.

[0062] It should be noted that in convolutional layers, the computational complexity of the underlying fully connected layers can be further reduced by using non-padding computation.

[0063] Fully connected layers can combine all local features into global features, which are then used to calculate the final score for each class.

[0064] As an example, such as Figure 3 As shown, in a convolutional neural network, a convolutional layer consists of multiple convolutional kernels. During data processing, the input data to be processed is first convolved in the kernels. The resulting convolution is then input into a fully connected layer. After the network computation is complete, the data is input into the output layer to complete the processing. It should be noted that the parameters of a convolutional neural network can be quantized with -1 or +1.

[0065] In this way, by processing the data sequentially through convolutional layers and fully connected layers, the accuracy of data processing can be further improved.

[0066] In some embodiments, to improve computational efficiency, the convolutional neural network architecture may employ a systolic array convolutional neural network architecture.

[0067] Specifically, the systolic array structure can be a specific structure within each convolutional kernel of a convolutional layer.

[0068] As an example, a schematic diagram of a pulsating array can be shown as follows: Figure 4 As shown, a systolic array can include multiple computational kernels. During the computation process of the systolic array, the data to be processed is input step by step, passes through several computational kernels in sequence, and the convolution output results are sequentially input into the fully connected layer below.

[0069] In this way, by using a pulsating array structure, data is processed by multiple computing cores, which can process more data at the same time, improve computing efficiency, and thus improve hardware utilization.

[0070] In some embodiments, to simplify computation and thus reduce power consumption, the computational cores in the pulsating array may employ multiplexers and adders, and the number of computational cores may be at least one.

[0071] Among them, a multiplexer (MUX) is a combinational logic circuit with multiple inputs and a single output. In the process of transmitting multiple data, an n-input multiplexer is an n-channel digital switch. It can select one output from n inputs to a common output terminal according to different channel selection control signals.

[0072] An adder is a device that produces the sum of numbers. In electronics, an adder is a digital circuit that performs addition calculations of numbers.

[0073] As an example, a schematic diagram of the computational kernel structure can be shown as follows: Figure 5 As shown. The high-order data from the input data and the parameters of the convolutional neural network are input into the first selector, and the low-order data from the input data are input into the second selector. Specifically, the input data can be -1, +1, or 0.

[0074] It should be noted that the high-order data and low-order data are also called high-order byte and low-order byte, where the high-order data represents the sign bit and the remaining low-order data represents the data bits. The data is encoded in two's complement. For example, for 2-bit data, the highest bit represents -2 and the lowest bit represents 1, so 11 represents -2×1+1×1=-1.

[0075] Therefore, by combining multiplexers and adders, the traditional multiply-adder can be avoided from performing multiplication operations on data. The calculation process is relatively simple and does not require large hardware overhead, thus simplifying the calculation and reducing power consumption.

[0076] In some embodiments, to enhance the applicability of the processor, the multi-level processor may be any of the following: application-specific integrated circuits, field-programmable gate arrays, and microcontrollers.

[0077] Application-specific integrated circuits (ASICs) are proprietary application chips designed and manufactured to meet specific user requirements and specific electronic systems. Their computing power and efficiency can be customized according to the algorithm requirements.

[0078] A field-programmable gate array (FPGA) is a program-driven logic device. Its control program is stored in memory and automatically loaded into the chip for execution after power-on.

[0079] A microcontroller unit (MCU), also known as a single-chip microcomputer, is a chip-level computer that integrates a central processing unit (CPU) with a reduced frequency and specifications, along with peripheral interfaces such as memory, timer, USB, A / D converter, UART, PLC, DMA, and even LCD driver circuitry, onto a single chip. This allows for different combinations of control for various applications.

[0080] This application provides a signal processing method that is applied to any of the above-mentioned sensor node processors. The processors are K-level processors in a cascaded structure, where K is a positive integer greater than 1. Each level of the processor has lower computational and space complexity than the next level of the processor.

[0081] The methods include:

[0082] Obtain the data to be processed;

[0083] If the processor at level i determines that the processing result of the data to be processed meets the preset requirements, the processor at level i+1 is in a non-working state, where 1≤i<K.

[0084] In some embodiments, the data to be processed can be acquired by the first processor; if it is determined that the processing result of the i-th level processor on the data to be processed meets the preset requirements, the processor of the (i+1)-th level is in a non-working state.

[0085] In this way, since each level of processor has lower computational and space complexity than the next level of processor, when processing data, if the calculation result of the current level of processor can meet the requirements, there is no need to turn on the next level of processor. This allows the data to be processed to be processed with lower power consumption, thereby saving power.

[0086] To illustrate this solution more clearly, a specific implementation scenario will be used as an example below. Figure 6 As shown, a low-power two-stage processor architecture for ECG digital signals is presented. First, the first-stage processor is designed, selecting three features: zero-crossing rate, positive pulse width duration, and negative pulse width duration. Based on the characteristics of these three features in normal ECG signals, three threshold decision conditions are set and implemented using logic gates. Specifically, the zero-crossing rate is set to 4, the positive pulse width duration is greater than 6, and the negative pulse width duration is greater than 4. Based on these threshold decision conditions, abnormal ECG signals can be basically detected. Furthermore, a high-performance processor based on convolutional neural networks can be used to determine the type of abnormal ECG signal.

[0087] Secondly, in the second-stage processor design based on convolutional neural networks, the ECG signal input dimension is 32*1, the neural network convolution kernel size is 9, no-padding is used for connection, and the output channel is set to 1. This is because the input ECG digital signal in this example mainly consists of 1, -1, and 0, and increasing the number of convolution channels would lead to data redundancy. The convolution output is activated by a hard limit function and then enters a fully connected layer. The fully connected layer has 18 neurons in the input layer and 4 in the output layer, corresponding to the 4 ECG signal categories. The output layer uses the Softmax function for classification, which is simplified in the hardware implementation to a comparison of signed and unsigned numbers.

[0088] In testing and simulation, this convolutional neural network was able to accurately classify four types of electrocardiogram signals.

[0089] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0090] The functional modules shown in the above-described block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer grids such as the Internet, intranets, etc.

[0091] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0092] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by a computer program or instructions. These programs or instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to create a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0093] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A sensor node processor, characterized by The processor is a K-level processor in a cascaded structure; K is a positive integer greater than 1; The processor of each level has smaller computational complexity and spatial complexity than the processor of the next level; In a case where the processing result of the i-th level processor on the to-be-processed data meets the preset requirement, the (i+1)-th level processor is in a non-working state; 1≤i<K; the to-be-processed data is an electrocardiosignal; and the preset requirement is that the electrocardiosignal is determined as an abnormal electrocardiosignal.

2. The processor of claim 1, wherein, In a case where the processing result of the i-th level processor on the to-be-processed data does not meet the preset requirement, the (i+1)-th level processor is in a working state.

3. The processor of claim 1, wherein, The processor of the first j levels of the K-level processor adopts at least the following parameters for detection: zero-crossing rate, positive pulse width and negative pulse width; 1≤j<K.

4. The processor of claim 3, wherein, The processor of the last P levels of the K-level processor adopts a convolutional neural network architecture; P=K-j.

5. The processor of claim 4, wherein, The convolutional neural network architecture comprises a convolutional layer and a fully connected layer.

6. The processor of claim 5, wherein, The convolutional layer adopts a systolic array structure.

7. The processor of claim 6, wherein, The computing core in the systolic array structure adopts a multiplexer and an adder.

8. The processor of claim 7, wherein, The number of the computing cores is at least one.

9. The processor of any one of claims 1-8, wherein, The K-level processor is implemented in any one of the following manners: an application-specific integrated circuit, a field programmable gate array and a microcontroller.

10. A signal processing method characterized by, The method is applied to the sensor node processor of any one of claims 1-9, the processor being a K-level processor in a cascaded structure; K is a positive integer greater than 1; The processor of each level has smaller computational complexity and spatial complexity than the processor of the next level; The method comprises: obtaining to-be-processed data; In a case where the processing result of the i-th level processor on the to-be-processed data meets the preset requirement, the (i+1)-th level processor is in a non-working state; 1≤i<K; the to-be-processed data is an electrocardiosignal; and the preset requirement is that the electrocardiosignal is determined as an abnormal electrocardiosignal.

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