Priority-based cache line fitting in compressed memory systems of processor-based systems

Abstract

A processor-based compressed memory system includes a memory partitioning circuit for dividing a memory region into data regions with different priority levels. The system also includes a cache line selection circuit for selecting a first cache line from a high-priority data region and a second cache line from a low-priority data region. The system further includes a compression circuit for compressing the cache line to obtain a first compressed cache line and a second compressed cache line. The system also includes a cache line encapsulation circuit for encapsulating the compressed cache line such that the first compressed cache line is written to a first predetermined portion of the candidate compressed cache line, and the second cache line, or a portion of the second compressed cache line, is written to a second predetermined portion of the candidate compressed cache line. The first predetermined portion is larger than the second predetermined portion.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Patent Application Serial No. 17 / 572,471, filed January 10, 2022, entitled "Priority-Based Cached-Line Fitting in Compressed Memory Systems of Processor-Based Systems," the entire contents of which are incorporated herein by reference.

[0003] This application also claims priority to U.S. Patent Application Serial No. 17 / 572,472, filed January 10, 2022, entitled "Priority-Based Cached-Line Fitting in Compressed Memory Systems of Processor-Based Systems," the entire contents of which are incorporated herein by reference. Technical Field

[0004] The disclosed implementations generally relate to memory systems, and more specifically to priority-based cache line fitting in a compressed memory system for processor-based systems. Background Technology

[0005] As applications executed by conventional processor-based systems increase in size and complexity, memory bandwidth can become a constraint on system performance. While available memory bandwidth can be increased by using wider memory communication channels, this approach can be penalized in terms of increased cost and / or additional area required for memory on integrated circuits (ICs). One way to increase memory bandwidth in processor-based systems without increasing the width of memory communication channels is through the use of data compression. Data compression systems can be employed in processor-based systems to store data in compressed formats, thus increasing effective storage capacity without increasing physical storage capacity. In this regard, some conventional data compression systems provide a compression engine to compress data to be written to main system memory. After compression, the compression engine writes the compressed data along with metadata to system memory, which maps the virtual address of the compressed data to the physical address in the system memory where the compressed data is actually stored. However, because the metadata is used for address mapping, memory access incurs additional reads and writes, which negatively impacts system performance. For example, accessing a specific cache line in memory may require accessing additional layers of metadata and address calculations in memory to determine the location of the compressed cache line in memory corresponding to that specific cache line. This increases the complexity, cost, and latency of processor-based systems that employ storage capacity compression. Summary of the Invention

[0006] Therefore, there is a need for systems, methods, and techniques that minimize the overhead of traditional compression systems. The techniques described in this paper can be used to remove metadata from most cache lines, thereby improving the average performance of cache line accesses.

[0007] In one aspect, a method is provided for compressing data in a compressed memory system of a processor-based system. The method includes: dividing a memory region into a plurality of data regions, each data region being associated with a corresponding priority level. The method further includes: (i) selecting a first cache line from a first data region among the plurality of data regions, and (ii) selecting a second cache line from a second data region among the plurality of data regions. The first data region has a higher priority level than the second data region. The method further includes: (i) compressing the first cache line to obtain a first compressed cache line, and (ii) compressing the second cache line to obtain a second compressed cache line. Based on determining that the first cache line is compressible, the method includes: (i) writing the first compressed cache line to a first predetermined portion of the candidate compressed cache line, and (ii) writing the second cache line or a second portion of the second compressed cache line to a second predetermined portion of the candidate compressed cache line. The first predetermined portion is larger than the second predetermined portion.

[0008] In some implementations, the method further includes setting an overflow pointer in a candidate compressed cache line based on determining that (i) a first cache line is incompressible, (ii) a second cache line is incompressible, or (iii) the second compressed cache line does not fit within a second predetermined portion of the candidate compressed cache line. The overflow pointer points to one of a plurality of overflow blocks based on the compression ratio of the second cache line or the size of the second compressed cache line. Each of the plurality of overflow blocks has a different size.

[0009] In some specific implementations, the method further includes: receiving a read request for a first cache line or a second cache line; and in response to receiving the read request: retrieving data from an overflow block among a plurality of overflow blocks based on a determined overflow pointer being set.

[0010] In some specific implementations, the method further includes: setting a first compression ratio control bit in a candidate compressed cache line based on determining that the first cache line is compressible; and writing a first portion of the first cache line into the candidate compressed cache line based on determining that the first cache line is incompressible; writing the remaining portion of the first cache line into an overflow block; resetting the first compression ratio control bit in the candidate compressed cache line; and setting an overflow pointer in the candidate compressed cache line to point to the overflow block.

[0011] In some specific implementations, the method further includes: in response to receiving a read request for a first cache line: retrieving the first cache line from candidate compressed cache lines based on determining that a first compression ratio control bit is set; and retrieving a first portion of the first cache line from candidate compressed cache lines based on determining that the first compression ratio control bit is reset; and retrieving a second portion of the first cache line from an overflow block based on an overflow pointer.

[0012] In some specific implementations, the method further includes: determining that the first cache line is incompressible; writing the second cache line or the second compressed cache line to an overflow block based on whether the second cache line is compressible; and resetting the second compression ratio control bit in the candidate compressed cache line to indicate whether the second cache line is incompressible.

[0013] In some implementations, the method further includes: in response to receiving a read request for a second cache line: retrieving a second cache line or a second compressed cache line from the overflow block based on a second compression ratio control bit.

[0014] In some specific implementations, the method further includes: in response to receiving a cache line write request for a first cache line: compressing the first cache line to obtain a first updated cache line having a first size; writing the first updated cache line into a candidate compressed cache line based on determining that the first size is equal to or less than a first predetermined size of the candidate compressed cache line; performing a read-modify-write operation on the candidate compressed cache line based on the first updated cache line based on determining that the first size is greater than the first predetermined size and equal to or less than a second predetermined size of the candidate compressed cache line; and performing a read-modify-write operation on the candidate compressed cache line based on the first updated cache line and on an overflow block among a plurality of overflow blocks based on determining that the first size is greater than the second predetermined size of the candidate compressed cache line.

[0015] In some implementations, the first predetermined size is half the size of the candidate compressed cache line.

[0016] In some specific implementations, the method further includes: when writing a second portion of a second cache line or a second portion of a second compressed cache line into a second predetermined portion of a candidate compressed cache line, writing an end-of-line index in the candidate compressed cache line to indicate where the second cache line or the second portion of the second compressed cache line is written within the candidate compressed cache line; and calculating a second predetermined size based on the end-of-line index in the candidate compressed cache line.

[0017] In some specific implementations, the method further includes: in response to receiving a cache line write request for a second cache line: compressing the second cache line to obtain a second updated cache line having a second size; performing a read-modify-write operation to write the second updated cache line to the candidate compressed cache line based on determining that the sum of the second size and the size of the first compressed cache line is less than a first predetermined size of the candidate compressed cache line; and performing a first read-modify-write operation to write a first portion of the second updated cache line to the candidate compressed cache line based on determining that the sum of the second size and the size of the first compressed cache line is not less than the first predetermined size of the candidate compressed cache line, (i) performing a first read-modify-write operation to write a first portion of the second updated cache line to the candidate compressed cache line, and (ii) performing a second read-modify-write operation to write the remaining portion of the second updated cache line to the overflow block pointed to by the overflow pointer.

[0018] In some specific implementations, the method further includes: in response to receiving a cache line write request for a first cache line or a second cache line: compressing the first cache line or the second cache line to obtain an updated and compressed cache line with an updated size; and, based on determining that the updated size cannot fit within the overflow block pointed to by the overflow pointer, releasing the overflow pointer and updating the overflow pointer to point to a new overflow block among a plurality of overflow blocks.

[0019] In some specific implementations, the first compressed cache line, the second compressed cache line, and the candidate compressed cache line have the same size.

[0020] In some specific implementations, the first data area and the second data area have the same size.

[0021] In some implementations, the second predetermined portion is less than half the size of the candidate compressed cache line.

[0022] In some implementations, the first compressed cache line and the second compressed cache line are written to the candidate compressed cache line in opposite directions. The first compressed cache line and the second compressed cache line are separated by one or more bytes.

[0023] On the other hand, a processor-based compressed memory system is provided. The compressed memory system includes memory partitioning circuitry configured to divide a memory region into multiple data regions. Each data region is associated with a corresponding priority level. The compressed memory system also includes cache line selection circuitry configured to: (i) select a first cache line from a first data region among the multiple data regions, and (ii) select a second cache line from a second data region among the multiple data regions. The first data region has a higher priority level than the second data region. The compressed memory system also includes compression circuitry configured to: (i) compress the first cache line to obtain a first compressed cache line, and (ii) compress the second cache line to obtain a second compressed cache line. The compressed memory system also includes cache line encapsulation circuitry configured to: based on determining that the first cache line is compressible, (i) write the first compressed cache line to a first predetermined portion of a candidate compressed cache line, and (ii) write the second cache line or a second portion of the second compressed cache line to a second predetermined portion of the candidate compressed cache line. The first predetermined portion is larger than the second predetermined portion.

[0024] In some specific implementations, the cache line encapsulation circuit is further configured to: set an overflow pointer in the candidate compressed cache line based on determining that (i) the first cache line is incompressible, (ii) the second cache line is incompressible, or (iii) the second compressed cache line does not fit within a second predetermined portion of the candidate compressed cache line. The overflow pointer points to one of a plurality of overflow blocks, each of which has a different size, depending on the compression ratio or size of the second compressed cache line.

[0025] In some specific implementations, the cache line encapsulation circuit is also configured to: receive a read request for a first cache line or a second cache line; and in response to receiving the read request: determine that an overflow pointer is set, and retrieve data from an overflow block among a plurality of overflow blocks according to the overflow pointer.

[0026] In some specific implementations, the cache line encapsulation circuit is further configured to: based on determining that the first cache line is compressible: set a first compression ratio control bit in the candidate compressed cache line; and based on determining that the first cache line is incompressible: write a first portion of the first cache line into the candidate compressed cache line; write the remaining portion of the first cache line into an overflow block; reset the first compression ratio control bit in the candidate compressed cache line; and set an overflow pointer in the candidate compressed cache line to point to the overflow block.

[0027] In some specific implementations, the cache line encapsulation circuit is also configured to: in response to receiving a read request for a first cache line: based on determining that a first compression ratio control bit is set: retrieve the first cache line from candidate compressed cache lines; and based on determining that the first compression ratio control bit is reset: retrieve a first portion of the first cache line from candidate compressed cache lines; and retrieve a second portion of the first cache line from an overflow block based on an overflow pointer.

[0028] In some specific implementations, the cache line encapsulation circuit is also configured to: based on determining that the first cache line is incompressible; based on whether the second cache line is compressible, write the second cache line or the second compressed cache line into the overflow block; and reset the second compression ratio control bit in the candidate compressed cache line to indicate whether the second cache line is incompressible.

[0029] In some specific implementations, the cache line encapsulation circuit is also configured to: in response to receiving a read request for a second cache line, retrieve a second cache line or a second compressed cache line from the overflow block based on a second compression ratio control bit.

[0030] In some specific implementations, the cache line encapsulation circuit is further configured to: in response to receiving a cache line write request for a first cache line: compress the first cache line to obtain a first updated cache line having a first size; write the first updated cache line to a candidate compressed cache line based on a first predetermined size that is determined to be equal to or less than the first predetermined size of the candidate compressed cache line; perform a read-modify-write operation on the candidate compressed cache line based on the first updated cache line based on a second predetermined size that is determined to be greater than the first predetermined size and equal to or less than the candidate compressed cache line; and perform a read-modify-write operation on the candidate compressed cache line based on the first updated cache line and on an overflow block among a plurality of overflow blocks based on a second predetermined size that is determined to be greater than the first predetermined size of the candidate compressed cache line.

[0031] In some implementations, the first predetermined size is half the size of the candidate compressed cache line.

[0032] In some specific implementations, the cache line encapsulation circuit is further configured to: when writing a second portion of the second cache line or the second portion of the second compressed cache line into a second predetermined portion of the candidate compressed cache line, write an end-of-line index in the candidate compressed cache line to indicate where the second cache line or the second portion of the second compressed cache line is written within the candidate compressed cache line; and calculate a second predetermined size based on the end-of-line index in the candidate compressed cache line.

[0033] In some specific implementations, the cache line encapsulation circuit is further configured to: in response to receiving a cache line write request for a second cache line: compress the second cache line to obtain a second updated cache line with a second size; perform a read-modify-write operation to write the second updated cache line to the candidate compressed cache line based on the determination that the sum of the second size and the size of the first compressed cache line is less than a first predetermined size of the candidate compressed cache line; and perform a first read-modify-write operation to write a first portion of the second updated cache line to the candidate compressed cache line based on the determination that the sum of the second size and the size of the first compressed cache line is not less than the first predetermined size of the candidate compressed cache line, (i) perform a first read-modify-write operation to write a first portion of the second updated cache line to the candidate compressed cache line, and (ii) perform a second read-modify-write operation to write the remaining portion of the second updated cache line to the overflow block pointed to by the overflow pointer.

[0034] In some specific implementations, the cache line encapsulation circuit is also configured to: in response to receiving a cache line write request for a first cache line or a second cache line: compress the first cache line or the second cache line to obtain an updated and compressed cache line with an updated size; and, based on determining that the updated size cannot fit within the overflow block pointed to by the overflow pointer, release the overflow pointer and update the overflow pointer to point to a new overflow block among multiple overflow blocks.

[0035] In some specific implementations, the first compressed cache line, the second compressed cache line, and the candidate compressed cache line have the same size.

[0036] In some specific implementations, the first data area and the second data area have the same size.

[0037] In some implementations, the second predetermined portion is less than half the size of the candidate compressed cache line.

[0038] In some implementations, the cache line encapsulation circuit is also configured to write the first compressed cache line and the second compressed cache line into the candidate compressed cache line in opposite directions. The first compressed cache line and the second compressed cache line are separated by one or more bytes.

[0039] On the other hand, a processor-based compressed memory system is provided. The compressed memory system includes a storage region comprising multiple cache lines. Each cache line has one of multiple priority levels. The compressed memory system also includes a compressed storage region comprising multiple compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold a portion of a first cache line or a compressed portion of a first cache line having a first priority level in a first direction. Each compressed cache line also includes a second set of data bits configured to hold a portion of a second cache line or a compressed portion of a second cache line having a second priority level lower than the first priority level in a second direction opposite to the first direction. The first set of data bits includes a greater number of bits than the second set of data bits.

[0040] In some implementations, the compressed memory system also includes an overflow storage area comprising multiple overflow bins. Each overflow bin is configured to hold a different number of bytes. Each compressed cache line also includes a set of overflow pointer bits configured to hold a pointer to one of the multiple overflow bins.

[0041] In some specific implementations, each compressed cache line also includes: a first control bit indicating the compression ratio of the first cache line; and a second control bit indicating the compression ratio of the second cache line.

[0042] In some implementations, the compressed memory system also includes an overflow storage region comprising multiple overflow bins, each configured to hold a different number of bytes. Each compressed cache line also includes a set of bits configured to hold the size of one of the overflow bins.

[0043] In some implementations, each compressed cache line also includes an end bit index indicating the end of the second set of data bits.

[0044] In some specific implementations, each overflow container is configured to hold bits of a first cache line and / or bits of a second cache line or a compressed second cache line in a first direction.

[0045] In some specific implementations, the first group of data bits and the second group of data bits are separated by one or more bytes.

[0046] In some implementations, each cache line and each compressed cache line have the same size.

[0047] In some implementations, when the compressed first cache line or the compressed second cache line is not fitted into the compressed cache line, each compressed cache line also includes a set of overflow pointer bits configured to hold a pointer to one of a plurality of overflow bins. The overflow bins are configured to hold bits representing the first cache line, the compressed first cache line, the second cache line, and / or the compressed second cache line.

[0048] In some implementations, the second set of data bits is also configured to hold multiple control bits that indicate an overflow in the compressed cache line and the end of the second set of data bits.

[0049] On the other hand, a non-transitory computer-readable medium is provided. This non-transitory computer-readable medium stores computer-executable instructions thereon, which, when executed by a processor, cause the processor to perform any of the methods described herein.

[0050] Various embodiments of the systems, methods, and apparatuses within the scope of the appended claims each have several aspects, none of which are solely responsible for the properties described herein. Without limiting the scope of the appended claims, it will be understood how various aspects of the various embodiments can be used to achieve higher throughput in the storage device of the memory device, taking into consideration this disclosure and specifically the section entitled "Detailed Description". Attached Figure Description

[0051] To provide a more detailed understanding of this disclosure, reference can be made to the features of various embodiments, some of which are illustrated in the accompanying drawings. However, the drawings only illustrate more relevant features of this disclosure and should therefore not be considered limiting, as the description allows for other valid features.

[0052] Figure 1 This is a schematic diagram based on some specific implementations of an example system with a cached line compression / decompression hardware engine.

[0053] Figure 2A This is a schematic diagram of a compressed storage system 200 based on some specific implementations.

[0054] Figure 2B This illustrates the use of some specific implementations. Figure 2A The diagram shows a sequence of methods for reading cache lines via a compressed memory system.

[0055] Figure 2C This illustrates the use of some specific implementations. Figure 2A The diagram shows a sequence of methods for writing cache lines via a compressed memory system.

[0056] Figure 3 It is a schematic diagram based on some specific implementations of packaging schemes for compressed memory systems.

[0057] Figures 4 to 9 Examples of compressed line layouts based on some specific implementations are shown.

[0058] Figure 10 A flowchart is shown, illustrating an example method for reading high-priority cache lines according to some specific implementations.

[0059] Figure 11 A flowchart is shown, illustrating an example method for reading low-priority cache lines according to some specific implementations.

[0060] Figure 12 A flowchart is shown, illustrating an example method for writing high-priority cache lines according to some specific implementations.

[0061] Figure 13 A flowchart is shown, illustrating an example method for writing low-priority cache lines according to some specific implementations.

[0062] Figure 14 It is a block diagram of a compressed memory system based on some specific implementation examples of processor-based systems.

[0063] As is customary practice, the various features shown in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the various features may be arbitrarily enlarged or reduced. Furthermore, some of the accompanying drawings may not depict all components of a given system, method, or apparatus. Ultimately, similar reference numerals can be used throughout the specification and accompanying drawings to denote similar features. Detailed Implementation

[0064] This document describes numerous details to provide a thorough understanding of the exemplary embodiments shown in the accompanying drawings. However, some embodiments may be practiced without these many specific details, and the scope of the claims is limited only by those features and aspects specifically stated in the claims. Furthermore, well-known methods, components, and circuits have not been described exhaustively to avoid unnecessarily obscuring more relevant aspects of the specific embodiments described herein.

[0065] Figure 1 This is a schematic diagram of an example system 100 with a cache-line compression / decompression hardware engine 110, based on some specific implementation. System 100 includes a chip 102, which in turn includes a processor 104, a Level 2 (L2) cache or L2 tightly coupled memory (TCM) 106, and the compression / decompression hardware engine 110. Processor 104 includes a memory management unit (MMU), a data cache, and an instruction cache. The data cache and instruction cache constitute a Level 1 (L1) cache. The L2 cache or L2 TCM 106 includes L2 controls and L2 cache tags or status modules 108. The system also includes a memory controller 114 for accessing main external memory (e.g., Double Data Rate Dynamic Random Access Memory (DRAM, sometimes referred to as DDR). Although... Figure 1Not shown, but some embodiments may include conventional peripherals, other storage devices, a Fast Peripheral Component Interconnect (PCI) interface, a Direct Memory Access (DMA) controller, and / or an Integrated Memory Controller (IMC). Some embodiments may include two or more processors or processor blocks, and / or a shared Level 3 (L3) cache for storing cache data used by any of the processor blocks in the processor block or shared between each processor block in the processor block. Some embodiments include an internal system bus that allows each processor block in the processor block to access the shared L3 cache and / or other shared resources including memory controller 114. The processor-based system 100 is configured to store cache data in uncompressed form in cache entries in cache memory. A cache entry may be a cache line. For example, the cache memory may be an L2 cache (e.g., L2 cache 106). The cache memory may be dedicated to a processor core in processor 104 or shared among multiple processor cores. Processor-based system 100 includes system memory 112, which includes compressed data regions configured to store data in compressed form in memory entries (which may be memory rows). For example, system memory 112 may include double data rate (DDR) static random access memory (SRAM). Processor 104 is configured to access system memory 112 during read and write operations to execute software instructions and perform other processor operations.

[0066] Figure 2A This is a schematic diagram of a compressed memory system 200 according to some specific implementation. The compressed memory system is configured to compress cached data from cache entries evicted from cache memory and read metadata for accessing physical addresses in the compressed system memory to write the compressed cached data. Providing the ability to store compressed data in compressed data regions (e.g., blocks 202, 204, 206) increases the storage capacity of the processor-based system 100 beyond the physical memory size of the system memory 112. In some specific implementations, the processor 104 uses virtual addressing. Virtual-to-physical address translation is performed to efficiently address the compressed data regions without knowing the compression system or the compressed size of the compressed data regions. In this regard, a compression or decompression engine 212 is provided in the compressed memory system 200 to compress uncompressed data from the processor 104 to be written to the compressed data regions, and to decompress compressed data received from the compressed data regions to provide such data to the processor 104 in uncompressed form. Compression or decompression engine 212 may include compression circuitry configured to compress data from processor 104 to be written to a compressed data region. For example, as... Figure 1As shown, the compression circuitry can be configured to compress a 64-byte (64B) data word into a 48-byte (48B) compressed data word, a 32-byte (32B) compressed data word, or a 16-byte (16B) compressed data word. These compressed data words can be stored in corresponding memory blocks 202 (64B), 204 (48B), 206 (32B), and 204 (16B), each having a size smaller than each of the entire memory entries of the system memory 112. If uncompressed data from the processor 104 cannot be compressed down to the next smaller-sized memory block 125 configured for compressing the memory system 102, such uncompressed data is stored uncompressed across the entire width of one of the memory entries. For example, the width of one of the memory entries can be 64B, and therefore a 64B memory block, such as memory block 202 (64B), can be stored. The compression or decompression engine 212 also includes a decompression circuit configured to decompress compressed data from the compressed data region to be provided to the processor 104.

[0067] However, to provide faster memory access without the need for compression and decompression, a cache memory 214 (e.g., L2 cache 106) is provided. Cache entries in cache memory 214 are configured to store cache data in uncompressed form. Each cache entry may have the same width as each memory entry for performing effective memory read and write operations. Cache entries are accessed by corresponding virtual address (“VA”) tags (e.g., tags stored in L2 cache tag 108) because, as discussed above, the compressed memory system 200 provides processor 104 with more addressable memory space than the physical address space provided in the compressed data region. When processor 104 issues a memory read request for a memory read operation, the virtual address of the memory read request is used to search cache memory 214 to determine if the virtual address matches one of the virtual address tags of the cache entry. If so, a cache hit occurs, and the cache data in the hit cache entry is returned to processor 104 without the need to decompress the cache data. However, because the number of cache entries is less than the number of memory entries, a cache miss may occur if the cache memory 214 does not contain cache data for a memory read request.

[0068] Therefore, continue to refer to Figure 2AIn response to a cache miss, cache memory 214 is configured to provide the virtual address of a memory read request to the compression circuitry to retrieve data from the compressed data region. In this regard, the compression circuitry can first query a metadata cache containing metadata cache entries, each of which contains metadata indexed by a virtual address. Access to the metadata cache is faster than to the compressed data region. Metadata is data, such as pointers, used to access physical addresses (PAs) within the compressed data region to access memory entries containing compressed data with virtual addresses. If the metadata cache contains metadata for the memory read request, the compression circuitry uses the metadata to access the correct memory entry in the compressed data region to provide the corresponding compressed data region to the decompression circuitry. If the metadata cache does not contain metadata for the memory read request, the compression circuitry provides the virtual address of the memory read request to metadata circuitry 210, which contains metadata in the corresponding metadata entry for all virtual address spaces in the processor-based system 100. Therefore, metadata circuitry 210 can be linearly addressed by the virtual address of the memory read request. Metadata is used to access the correct memory entry in the memory entry of the compressed data area in order to provide the corresponding compressed data area to the decompression circuitry.

[0069] Referring again to Figure 2, the decompression circuit receives the compressed data region in response to a memory read request. The decompression circuit decompresses the compressed data region into uncompressed data, which can then be provided to the processor 104. The uncompressed data is also stored in the cache memory 214. However, if the cache memory 214 does not have an available cache entry, it can evict one of the existing cache entries from the compressed data region to make room for the uncompressed data.

[0070] To this end, cache memory 214 first sends the virtual address of the evicted cache entry and uncompressed cache data to the compression circuit. The compression circuit receives the virtual address of the evicted cache entry and the uncompressed cache data. The compression circuit initiates a metadata read operation on the metadata cache to obtain the metadata associated with the virtual address. During, before, or after the metadata read operation, the compression circuit compresses the uncompressed cache data into compressed data to be stored in the compressed data area. If the metadata read operation on the metadata cache results in a cache miss, the metadata cache issues a metadata read operation to the metadata circuit 210 in system memory 112 to obtain the metadata associated with the virtual address. The metadata cache is then paused. Because access to the compressed data area can take much longer than the time that processor 104 can issue a memory access operation, the uncompressed data received from processor 104 for subsequent memory write requests can be buffered in the memory request buffer.

[0071] After metadata is returned from the compressed data region to update the metadata cache, the metadata cache provides the metadata as metadata to the compression circuitry. The compression circuitry determines whether the new compressed size of the compressed data region fits the same block size in the compressed data region as the data previously used to store the virtual address of the evicted cache entry. For example, processor 104 may have updated cached data in the evicted cache entry because it was last stored in the compressed data region. If a new block of memory is needed to store the compressed data region of the evicted cache entry, the compression circuitry recycles the pointer to the current block of memory in the compressed memory system 200 associated with the virtual address of the evicted cache entry into one of the free memory lists (e.g., list 216 of free 64B blocks, list 218 of free 48B blocks, list 220 of free 32B blocks, and list 222 of free 16B blocks) that point to available blocks of memory in the compressed data region. The compression circuit then obtains a pointer from one of the free memory lists to a new available memory block of the desired size in the compressed data region to store the compressed data region of the evicted cache entry. The compression circuit then stores the compressed data region of the evicted cache entry in a memory block within the compressed data region associated with the virtual address of the evicted cache entry determined from the metadata.

[0072] If a new memory block is allocated to the virtual address of the evicted cache entry, the metadata in the metadata cache entry corresponding to the virtual address label in the virtual address label of the evicted cache entry is updated based on the pointer to the new memory block. Then, the metadata cache updates the metadata in the metadata entry corresponding to the virtual address in the metadata cache based on the pointer to the new memory block 125.

[0073] Because the metadata of metadata circuit 210 is stored in system memory 112, metadata circuit 210 may consume excessive amounts of system memory 112, thus negatively impacting system performance. Therefore, it is desirable to minimize the amount of system memory 112 required to store metadata while still providing effective data compression. In this regard, some specific implementations of compressed memory system 200 reduce the metadata size. The techniques described herein can be used for:

[0074] Figure 2A The diagram illustrates uncompressed data linearly indexed via metadata according to some specific implementations. An uncompressed cache line is represented by 3 bytes of metadata, and the metadata points to compressed blocks (e.g., blocks 202, 204, and 206) of sizes 16, 32, 48, or 64 bytes. In some implementations, if an entire uncompressed line is 0, the metadata circuitry 210 marks it without pointing to any compressed block. In some implementations, the compressed memory system 200 includes a register file 208 holding base pointers to blocks 202, 204, and 206, and the metadata circuitry 210 provides offsets from the base pointers for the blocks.

[0075] Figure 2B This illustrates the use of some specific implementations. Figure 2A The diagram illustrates a sequence of methods for reading cache lines using a compressed memory system. After an L2 cache miss, the read address of external memory is sent to a compression or decompression engine 212, which retrieves the cached L2 metadata (if available). If the metadata is not available in the cache, it is read from external memory (e.g., DDR). Based on the metadata, compressed data is retrieved from external memory from a block of compressed data. The compressed data is then decompressed by decompression circuitry, and the uncompressed data is returned to the processor. Using this method, a cache line of 0 (e.g., 64 bytes of 0) requires one read, while other cache lines require two reads: one for metadata and one for the compressed block.

[0076] Figure 2C This illustrates the use of some specific implementations. Figure 2AThe diagram illustrates a sequence of methods for writing cache lines via a compressed memory system. After an L2 cache miss, uncompressed data is sent to compression or decompression engine 212, and compression circuitry compresses the data to a new size. Similar to... Figure 2B If the metadata is not available in the metadata cache, it is retrieved from external storage. If the metadata is available in the metadata cache, it is retrieved from the metadata cache. Depending on the size of the compressed data, a new index for the new size can be retrieved from a free list (e.g., one of lists 216, 218, 220, 222), and the compressed data is written to the compressed data region. In some cases, the old index can be reused, and the metadata is updated in external storage. Using this method, for cache line writes, depending on the size of the compressed block, if the cache line is all 0, the write requires a read-modify-write operation for the metadata; other cache lines require a read-modify-write operation for the metadata and a write operation or a read-modify-write operation for the compressed data.

[0077] Figure 3 The diagram illustrates a specific implementation of a packaging scheme 300 for a compressed storage system that helps avoid additional readings and writing of the metadata described above. Figure 3 A storage region (e.g., compressed data candidates) is shown divided into a high-priority portion 302 and a low-priority portion 304 of equal size. In practice, the storage region can be divided into any number of partitions with different priority levels, and / or the partitions can have unequal amounts of data. A high-priority cache line and a low-priority cache line are selected and compressed to fit within a compressed cache line 306. In cases where the compressed high-priority cache line and the low-priority cache line do not fit within a single compressed cache line, an overflow pointer is maintained in the compressed line, pointing to an overflow block (e.g., overflow bins 308, 310, or 312, each with a different size). To avoid read-modify-write, some implementations use multiple overflow blocks (e.g., overflow bin 32 bytes of data, overflow bin 310 64 bytes of data, and overflow bin 312 96 bytes of data). To improve write performance of the high-priority line, the compressed low-priority line occupies only the lower half of the compressed line.

[0078] Figures 4 to 9 Examples of compressed row layouts based on some specific implementations are shown. These examples are provided for illustrative purposes and should not be construed as meaning that the layout or organization is limited to these examples. See also... Figure 4The compressed line (CL) 400 may include: (i) an HP 402 indicating compressed data for a high-priority cache line; (ii) an LP 404 indicating compressed data for a low-priority cache line; (iii) an HPC 406 indicating whether a high-priority cache line is compressed. For example, 1 indicates compression, and 0 indicates no compression; (iv) an LPC 408 indicating whether a low-priority cache line is compressed. For example, 1 indicates compression, and 0 indicates no compression; (v) an OFB 410 indicating the overflow bin size. For example, 0 indicates 32 bytes, 1 indicates 64 bytes, 2 indicates 96 bytes, and 3 indicates no overflow; (vi) an OFP 412 indicating the overflow pointer index; and / or (vii) an LPE 414 indicating the low-priority end bit index, which indicates where the low-priority compressed data ends. This information can be used to extend high-priority cache lines on the write path. Values ​​can be between 11 and 255. 0 may mean there is no remaining space for HP extension. Specific implementations may use any number of these fields. In some implementations, high-priority compression or decompression begins from the HPC bit toward the OFP, as indicated by arrow 416. In some implementations, low-priority compression or decompression begins from the OFP toward the location pointed to by the LPE (as indicated by arrow 418), and continues from right to left in the overflow region if it has overflow (as indicated by arrow 420). According to some implementations, region 420 of CL is not used by CL, and / or HP 402 and LP 404 are separated by gap 422. Figure 4 In the example shown, 32 bytes are dedicated to HP, and 32 bytes are available for use by HP / LP, with 31 control bits including OFP 412, LPE 414, OFB410, and LPC 408. Depending on the specific implementation, the compressed lines may have slightly different layouts depending on the HP and LP compression sizes, as referenced below. Figures 5 to 10 To be further described. For example, the number of control bits can be reduced (e.g., because there is no overflow, OFP is not needed, and these bits are consumed by LP).

[0079] Figure 5 An example compressed row layout 500 is shown according to some specific implementations when HP is less than 256 bits and low-priority rows are fitted in CL. According to some specific implementations, HPC is set to 1, OFB is set to 0x11, and LPC is set to 1. Only 11 control bits are present (with...). Figure 4 (The 31st position is the opposite).

[0080] Figure 6An example compressed row layout 600 is shown according to some specific implementations when both HP and LP are fitted into a single CL and HP is greater than 255 bits. According to some specific implementations, HPC is set to 1, OFB is set to 0x11, and LPC is set to 1. In this example, HP has been extended into the lower half of the CL.

[0081] Figure 7 An example compressed line layout 700 is shown according to some specific implementations when HP is less than 256 bits and LP has overflow. According to some specific implementations, HPC is set to 1, OFB is any value between 0x0 and 0x2, LPC is set to 1 or 0, and OFP points to overflow block 424.

[0082] Figure 8 An example compressed line layout 800 is shown according to some specific implementations when HP is greater than 255 bits but less than 480 bits and LP has overflow. According to some specific implementations, HPC is set to 1, OFB is set to a value between 0 and 2, LPC is 1 or 0, and OFP points to overflow block 426.

[0083] Figure 9 An example compressed line layout 900 is shown according to some specific implementation when HP equals 512 bits (incompressible) and LP has overflow. According to some specific implementations, HPC is set to 0, OFB is set to a value between 0 and 2, LPC is set to 0 or 1, and OFP points to overflow block 428. Overflow block 428 includes the remaining 32 bits of HP 430, gap 432, and LP 404.

[0084] Example read / write overhead and statistics

[0085] For cache line reads, fitting a high-priority cache line and a low-priority cache line within a compressed cache line requires one read, while other cache lines require two reads: one for the compressed line and one for the overflow block. For cache line writes, fitting a compressed high-priority cache line at 255 bits requires one write, fitting a compressed high-priority cache line from 256 to 480 bits requires one read-modify-write, and other incompressible high-priority cache lines (>480 bits) require one read-modify-write for the compressed line and one read-modify-write for the overflow block; fitting a low-priority cache line within a compressed line requires one read-modify-write, and low-priority cache lines not fitted within a compressed line require one read-modify-write for the compressed line and one read-modify-write for the overflow block.

[0086] The following table shows an example cache line read / write cost and statistics for modem data (50017075 bytes of compressed candidate data).

[0087]

[0088] According to statistics, 84.7% of high-priority cache lines require only one read / one write for cache line reads / writes. In addition, 11% of high-priority cache lines require one read / one read-modify-write for cache line reads / writes. Only 4.3% of high-priority cache lines require two reads / two read-modify-writes for cache line reads / writes. 78.6% of low-priority cache lines require one read / one read-modify-write for cache line reads / writes. 21.4% of low-priority cache lines require two reads / two read-modify-writes for cache line reads / writes.

[0089] The following description Figures 10 to 13 In this diagram, memory reads and writes are indicated by patterns within rectangular boxes, and all other operations (except for the initial block receiving a read or write request) are shown without any patterns. Furthermore, operations predicted to be of high probability are shown as solid lines (i.e., solid arrows indicate high-probability paths), and other paths are shown as dashed lines or dashed arrows. The probabilities of the paths are based on the data distribution of a specific dataset (e.g., modem data).

[0090] Figure 10 A flowchart of an example method 1000 for reading a high-priority cache line, according to some specific implementation, is shown. Method 1000 includes receiving (1002) a request to read HP, and reading (1004) CL. The method also includes determining (1006) whether HPC is equal to 1. If HPC is 1, HP is decompressed. If HPC is not 1, the overflow block pointed to by (1010) OFP is read, and 480 bits are copied (1012) from the compressed line and 32 bits are copied from the OFP block.

[0091] Figure 11A flowchart of an example method 1100 for reading a low-priority cache line according to some specific implementation is shown. Method 1100 includes receiving (1102) a request to read LP, and reading (1104) CL. The method also includes determining (1106) whether OFB is set to 3 (hexadecimal value 0x11). If OFB is set to 3, LP is decompressed from bit 11 (1108) to LPE bits. If OFB is not set to 3, OFP is read (1110) and the bits of LPE from bit 32 to CL are decompressed and bits from the overflow block pointed to by OFP are added (1112).

[0092] Figure 12 A flowchart of an example method 1200 for writing a high-priority cache line is shown according to some specific implementation. The method includes receiving (1202) an HP write request and compressing (1204) the HP line to HPSZ bits. The method also includes determining (1206) whether the HPSZ is less than 256 bits. If the HPSZ is less than 256 bits, HPC is set to 1 and 32 bytes of HP are written (1210). The path through blocks 1202, 1204, 1206, and 1210 forms a short path and results in fast write access to the high-priority cache line. If the HPSZ is not less than 256 bits, CL is read (1208). Then it is determined (1212) whether the HPSZ is less than 511-LPE. If so, CL is updated with HP (1214) and HPC is set to 1, and CL is written (1216). If HPSZ is not less than 511 - LPE, then further determine (1218) whether OFP is set (or check if CL has OFP). If OFP exists, then read OFP (1220). If OFP does not exist, then read the LP content and release OFP (1222). In addition, determine (1224) whether HP is compressible (1224). If HP is compressible, then obtain a new OFP block (1232) with a bit size greater than LPSZ - (480 - HPSZ), update the new OFP with LP (1234), and fill CL with HP and set HPC to 1 (1236). If HP is incompressible, then obtain a new OFP block (1226) with a bit size greater than LPSZ + 32, copy the 32-bit HP overflow and update the new OFP with LP (1228), and fill CL with HP and set HPC to 0 (1230). Subsequently, write OFP (1238) and write CL (1240).

[0093] Figure 13A flowchart of an example method 1300 for writing a low-priority cache line, according to some specific implementation, is shown. Method 1300 includes receiving (1302) an LP write request and compressing the line to LPSZ bits and setting LPC to 1 (1304). The method also includes determining (1306) whether LPSZ is greater than 480 bits. If LPSZ is greater than 480 bits, LPSZ is set to 512 (to indicate no compression) and LPS is set to 0 (1308). If LPSZ is not greater than 480 bits, the compressed line is read (1310). It is further determined (1312) whether HPC is set to 0. If HPC is set to 0, the OFP line is read (1314). It is further determined whether the current block is greater than LPSZ plus 32. If so, OFP is updated (1324). If the current block is not greater than LPSZ + 32, a new OFP block with a bit size greater than LPSZ + 32 is obtained (1318), the 32-bit HP is copied and the new OFP is updated (1320), and the old OFP is pushed into the free list (1322). Subsequently, the OFP is written (1326), the compressed line is updated for OFP, OFB, and LPC (1328), and CL is written (1330). If HPC is not equal to 0 (block 1312), it is further determined (1332) whether the OFP is not set to 0xFF. If not, the OFL is released (1334). If the OFP is set to 0xFF, the HP is decompressed (1336) to find the HP end bit. It is further determined (1338) whether the HP exceeds 32 bytes. If yes, the LPSPACE is set to the HP end bit - 11. If not, the LPSPACE is set to 256 - 11. In either case, further determine whether (1344) LPSZ is less than LPSPACE. If so, encapsulate (1346) the LP into CL, update the compressed line (1348) for (OFP set to 0x11, LPC, and LPE), and write CL (1350). If LPSZ is not less than LPSPACE, obtain an OFP block (1352) with a bit size greater than LPSZ-LPSPACE-20, encapsulate (1354) the LP into OFP and CL, update CL (1356) for (OFP, OFB, LPC, and LPE), write CL (1358), and write OFP (1360).

[0094] Figure 14This is a block diagram of a compressed memory system 1400, based on some specific implementations of a processor-based system. System 1400 includes memory partitioning circuitry 1402 configured to divide a memory region into multiple data regions. Each data region is associated with a corresponding priority level. Memory regions include compressed data candidates and may include data and / or instructions. For example, software images may be linked to different parts. Each part may have a different address range. Memory partitioning circuitry 1402 can be configured to distinguish different data regions based on address ranges. Figure 3 In some specific implementations, the storage area is shown as being divided into high-priority vias 302 and low-priority vias 304. Although in Figure 3 Only two holes or priority levels are shown in the diagram, but in some specific implementations more than two holes (sometimes called data areas) and / or more than two priority levels may be used.

[0095] The compressed memory system 1400 also includes a cache line selection circuit 1404 configured to: (i) select a first cache line from a first data region among a plurality of data regions, and (ii) select a second cache line from a second data region among a plurality of data regions. For example, the address of the cache line can be used by the cache line selection circuit 1404 to determine whether the cache line belongs to the first data region or the second data region. Based on this determination, the cache line selection circuit 1404 can select the first cache line and the second cache line. The first data region has a higher priority level than the second data region. For example, in... Figure 3 In the process, cache lines from high-priority aperture 302 and cache lines from low-priority aperture 304 are selected to form compressed cache line 306.

[0096] The compressed memory system 1400 also includes a compression circuit 1406 configured to: (i) compress a first cache line to obtain a first compressed cache line, and (ii) compress a second cache line to obtain a second compressed cache line. References above may vary depending on the specific implementation. Figure 1 , Figure 2A , Figure 2B and Figure 2C An example of a compression circuit is described.

[0097] The compressed memory system 1400 also includes a cache line encapsulation circuit 1408 configured to: (i) write the first compressed cache line to a first predetermined portion of a candidate compressed cache line, and (ii) write a second cache line or a second portion of a second compressed cache line to a second predetermined portion of the candidate compressed cache line, based on the determination that the first cache line is compressible. The first predetermined portion is larger than the second predetermined portion. For example, Figure 5 The image shows a high-priority cache line of the HP402 that has been compressed and written to indicate a first predetermined portion. Figure 5 The diagram also illustrates a low-priority cache line compressed and written to LP 404 (the second predetermined portion). In some implementations, the first predetermined portion and the second predetermined portion may correspond to two different parts of the compressed cache line. The first predetermined portion is first filled with high-priority compressed data, followed by the second predetermined portion filled with low-priority data. High-priority data may overflow into the second predetermined portion, but low-priority data cannot overflow into the first predetermined portion. In some implementations, the second predetermined portion includes control bits while the first predetermined portion does not. In some implementations, the compressed data is written in different directions (e.g., towards the intersection of the two portions).

[0098] In some specific implementations, the cache line encapsulation circuit 1408 is also configured to: based on determining (i) that the first cache line is incompressible, (ii) that the second cache line is incompressible, or (iii) that the second compressed cache line does not fit within a second predetermined portion of the candidate compressed cache line, set an overflow pointer (e.g., Figure 4 (OFP 412 in the original text). Depending on the compression ratio of the second cache line or the size of the second compressed cache line, the overflow pointer points to one of a plurality of overflow blocks (e.g., one of overflow bins 308, 310, or 312). Each of the plurality of overflow blocks has a different size. For example, overflow bins 308, 310, and 312 hold data of different sizes. In some embodiments, the cache line encapsulation circuit 1408 is also configured to: receive a read request for the first cache line or the second cache line; and in response to receiving the read request: retrieve data from the overflow block among the plurality of overflow blocks according to the overflow pointer, based on determining that the overflow pointer is set. According to some embodiments, the above references... Figure 3 , Figure 4 , Figure 7 , Figure 8 and Figure 9Examples of overflow blocks and overflow logic are described. The above references vary depending on specific implementations. Figure 10 and Figure 11 An example method for reading is described.

[0099] In some specific implementations, the cache line encapsulation circuit 1408 is further configured to: upon determining that the first cache line is compressible, set a first compression ratio control bit (e.g., HPC 406) in the candidate compressed cache line; and upon determining that the first cache line is incompressible, write a first portion of the first cache line to the candidate compressed cache line; write the remaining portion of the first cache line to an overflow block; reset the first compression ratio control bit in the candidate compressed cache line; and set an overflow pointer in the candidate compressed cache line to point to the overflow block. The above references are made according to some specific implementations. Figure 9 An example is described. In some implementations, the cache line encapsulation circuit 1408 is further configured to: in response to receiving a read request for a first cache line; based on determining that a first compression ratio control bit is set; retrieve the first cache line from candidate compressed cache lines; and based on determining that the first compression ratio control bit is reset; retrieve a first portion of the first cache line from candidate compressed cache lines; and retrieve a second portion of the first cache line from an overflow block based on an overflow pointer. In some implementations, the cache line encapsulation circuit 1408 is further configured to: based on determining that the first cache line is incompressible; write a second cache line or a second compressed cache line to an overflow block based on whether the second cache line is compressible; and reset a second compression ratio control bit (e.g., LPC 408) in candidate compressed cache lines to indicate whether the second cache line is incompressible. In some specific implementations, the cache line encapsulation circuit 1408 is also configured to: in response to receiving a read request for a second cache line: retrieve a second cache line or a second compressed cache line from the overflow block based on a second compression ratio control bit. References to the above are made according to various specific implementations. Figure 10 and Figure 11 Example methods for reading high-priority cache lines and low-priority cache lines are described.

[0100] In some implementations, the cache line encapsulation circuit 1408 is further configured to: in response to receiving a cache line write request for a first cache line: (e.g., using compression circuit 1406) compress the first cache line to obtain a first updated cache line of a first size; write the first updated cache line to a candidate compressed cache line based on a first predetermined size determined to be equal to or less than the first predetermined size; perform a read-modify-write operation on the candidate compressed cache line based on the first updated cache line based on a second predetermined size determined to be greater than the first predetermined size and equal to or less than the candidate compressed cache line; and perform a read-modify-write operation on the candidate compressed cache line based on the first updated cache line and on an overflow block among a plurality of overflow blocks based on a second predetermined size determined to be greater than the first predetermined size. In some implementations, the first predetermined size is half the size of the candidate compressed cache line. In some specific implementations, the cache line encapsulation circuit 1408 is further configured to: write an end bit index (e.g., LPE414) in the candidate compressed cache line to indicate where the second cache line or the second portion of the second compressed cache line is written within the candidate compressed cache line when the second portion of the second cache line or the second portion of the second compressed cache line is written; and calculate the second predetermined size based on the end bit index in the candidate compressed cache line.

[0101] In some implementations, the cache line encapsulation circuit 1408 is further configured to: in response to receiving a cache line write request for a second cache line: compress the second cache line to obtain a second updated cache line of a second size; perform a read-modify-write operation to write the second updated cache line to the candidate compressed cache line based on the determination that the sum of the second size and the size of the first compressed cache line is less than a first predetermined size of the candidate compressed cache line; and perform a first read-modify-write operation to write a first portion of the second updated cache line to the candidate compressed cache line based on the determination that the sum of the second size and the size of the first compressed cache line is not less than the first predetermined size of the candidate compressed cache line, (i) perform a first read-modify-write operation to write a first portion of the second updated cache line to the candidate compressed cache line, and (ii) perform a second read-modify-write operation to write the remaining portion of the second updated cache line to the overflow block pointed to by the overflow pointer. In some implementations, for high-priority cache lines, there is no control bit to indicate where the HP ends. In this case, the system decompresses the HP portion to determine this information. In some implementations, this is not true decompression, but rather the end is determined by scanning the HP through the compression bits (a process very similar to decompression). Some implementations reserve 8 to 9 bits to indicate the end of HP, just like on the LP side.

[0102] In some specific implementations, the cache line encapsulation circuit 1408 is further configured to: in response to receiving a cache line write request for a first cache line or a second cache line; compress the first cache line or the second cache line to obtain an updated and compressed cache line with an updated size; and, based on determining that the updated size cannot fit within the overflow block pointed to by the overflow pointer, release the overflow pointer and update the overflow pointer to point to a new overflow block among multiple overflow blocks. According to some specific implementations, the above references... Figure 12 and Figure 13 An example for manipulating the free list is described.

[0103] In some specific implementations, the first compressed cache line, the second compressed cache line, and the candidate compressed cache line have the same size. For example, in Figure 3 In the cache, each cache line from regions 302 and 304 and the compressed cache line 306 has 64 bytes.

[0104] In some specific implementations, the first data region and the second data region have equal sizes. For example, in... Figure 3 In this context, regions 302 and 304 have the same size (e.g., the regions have the same number of cache lines).

[0105] In some implementations, the second predetermined portion is less than half the size of the candidate compressed cache line. The above references are based on some specific implementations. Figures 4 to 9 An example of the layout is described.

[0106] In some implementations, the cache line encapsulation circuit 1408 is also configured to write the first compressed cache line and the second compressed cache line into the candidate compressed cache line in opposite directions. The first compressed cache line and the second compressed cache line are separated by one or more bytes.

[0107] On the other hand, a compressed memory system based on a processor is provided. This compressed memory system includes a storage region comprising multiple cache lines. For example, Figure 3 Two storage regions 302 and 304 are shown. Each cache line has one of a plurality of priority levels. For example, a cache line in region 302 has a higher priority than a cache line in region 304. The compressed memory system also includes a compressed storage region (e.g., a region including compressed cache line 306) comprising a plurality of compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold a portion of a first cache line or a compressed portion of a first cache line having a first priority level in a first direction. For example, according to some specific embodiments, Figure 4 The layout shown illustrates a compressed cache line of an HP 402, including bits for storing high-priority cache lines. Each compressed cache line also includes a second set of data bits configured to hold a portion of a second cache line or a compressed portion of a second cache line having a second priority level lower than the first priority level in a second direction opposite to the first direction. Figure 4 The layout shown illustrates a compressed cache line including an LP 404 for storing bits for low-priority cache lines. The first set of data bits includes more bits than the second set. The HP 402 stores the compressed bits in the opposite direction to the LP 404. Figure 4 The layout in the diagram shows that bits used for high-priority cache lines can occupy HP 402 and region 420, while bits used for low-priority cache lines can occupy only LP 404, which is smaller than HP 402.

[0108] In some implementations, the compressed memory system also includes an overflow storage region comprising multiple overflow bins (e.g., overflow block 426). Each overflow bin is configured to hold a different number of bytes. For example, overflow blocks 308, 310, and 312 each comprise a different number of bytes. Each compressed cache line also includes a set of overflow pointer bits (e.g., OFP 412) configured to hold a pointer to one of the multiple overflow bins.

[0109] In some implementations, each compressed cache line also includes: a first control bit indicating the compression rate of the first cache line (e.g., HPC 406); and a second control bit indicating the compression rate of the second cache line (e.g., LPC 408).

[0110] In some implementations, the compressed memory system also includes an overflow storage area comprising multiple overflow bins. Each overflow bin is configured to hold a different number of bytes. Each compressed cache line also includes a set of bits (e.g., OFB 410) configured to hold the size of one of the overflow bins.

[0111] In some implementations, each compressed cache line also includes an end bit index (e.g., LPE 414) indicating the end of the second set of data bits.

[0112] In some specific implementations, each overflow cache is configured to hold bits of a first cache line and / or bits of a second cache line or a compressed second cache line in a first direction. For example, such as Figure 4 As shown, the overflow compartment 420 is held in the same direction as HP 402.

[0113] In some specific implementations, the first group of data bits and the second group of data bits are separated by one or more bytes. For example, in Figure 4 In the middle, HP 402 and LP 404 are separated by a gap 422.

[0114] In some implementations, each cache line and each compressed cache line have the same size. For example, in Figure 3 In the cache, each cache line 302 and 304, and each compressed cache line 306, consists of 64 bytes.

[0115] In some specific implementations, when the compressed first cache line or the compressed second cache line does not fit within the compressed cache line, each compressed cache line also includes a set of overflow pointer bits. This set of overflow pointer bits is configured to hold a pointer to one of a plurality of overflow bins. The overflow bins are configured to hold bits representing the first cache line, the compressed first cache line, the second cache line, and / or the compressed second cache line. In other words, if... Figure 5 and Figure 6 As shown, OFP 412 is optional and is only used when an overflow occurs. The OFP bit is not used when both compressed cache lines are fitted into the compressed cache line.

[0116] In some implementations, the second set of data bits is also configured to hold multiple control bits that indicate the end of an overflow in a compressed cache line (e.g., OFP 412, OFB 410) and the second set of data bits (e.g., LPE 414).

[0117] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0118] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the claims. As used in the description of embodiments and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that the term “and / or” as used herein refers to and covers any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0119] As used herein, the term "if" can be interpreted as meaning "when," "at," "in response to determination," "according to determination," or "in response to detection," depending on the context. Similarly, the phrases "if determination [the stated precedent is true]," "if [the stated precedent is true]," or "when [the stated precedent is true]" can be interpreted as meaning "in response to determination," "according to determination," "in response to detection," or "in response to detection," depending on the context.

[0120] For purposes of explanation, the foregoing description has been made with reference to specific embodiments. However, the illustrative discussion above is not intended to be exhaustive or to limit the claims to the precise forms disclosed. In light of the foregoing teachings, many modifications and variations are possible. The embodiments have been chosen and described to best explain the operating principles and practical applications, thereby enabling implementation by those skilled in the art.

Claims

1. A method for compressing data in a compressed memory system of a processor-based system, the method comprising: The storage area is divided into multiple data areas, and each data area is associated with a corresponding priority level. (i) Selecting a first cache line from a first data region in the plurality of data regions, and (ii) Selecting a second cache line from a second data region in the plurality of data regions, wherein the first data region has a higher priority level than the second data region; (i) compress the first cache line to obtain a first compressed cache line, and (ii) compress the second cache line to obtain a second compressed cache line; Based on the determination that the first cache line is compressible: (i) write the first compressed cache line to a first predetermined portion of the candidate compressed cache line, and (ii) write the second cache line or a second portion of the second compressed cache line to a second predetermined portion of the candidate compressed cache line, wherein the first predetermined portion is larger than the second predetermined portion; as well as Based on at least one of the following: (i) the first cache line is incompressible, (ii) the second cache line is incompressible, or (iii) the second compressed cache line does not fit within the second predetermined portion of the candidate compressed cache line: An overflow pointer is set in the candidate compressed cache line, wherein the overflow pointer points to one of a plurality of overflow blocks according to the compression ratio of the second cache line or the size of the second compressed cache line, and wherein each of the plurality of overflow blocks has a different size.

2. The method according to claim 1, further comprising: Receive a read request for the first cache line or the second cache line; as well as In response to receiving the read request: Based on the determination that the overflow pointer is set, data is retrieved from the overflow blocks among the plurality of overflow blocks according to the overflow pointer.

3. The method according to claim 1, further comprising: Based on the determination that the first cache line is compressible: Set a first compression ratio control bit in the candidate compressed cache line; as well as Based on the determination that the first cache line is incompressible: Write the first portion of the first cache line into the candidate compressed cache line; Write the remainder of the first cache line to the overflow block; Reset the first compression ratio control bit in the candidate compressed cache line; as well as Set an overflow pointer in the candidate compressed cache line to point to the overflow block.

4. The method according to claim 3, further comprising: In response to receiving a read request for the first cache line: Based on the determination that the first compression ratio control bit is set: Retrieve the first cache line from the candidate compressed cache lines; and Based on the determination that the first compression ratio control bit has been reset: Retrieve the first portion of the first cache line from the candidate compressed cache line; as well as The second portion of the first cache line is retrieved from the overflow block based on the overflow pointer.

5. The method according to claim 3, further comprising: Based on the determination that the first cache line is incompressible: Depending on whether the second cache line is compressible, the second cache line or the second compressed cache line is written into the overflow block; as well as The second compression ratio control bit in the candidate compressed cache line is reset to indicate whether the second cache line is incompressible.

6. The method according to claim 5, further comprising: In response to receiving a read request for the second cache line: The second cache line or the second compressed cache line is retrieved from the overflow block based on the second compression ratio control bit.

7. The method according to claim 1, further comprising: In response to receiving a cache line write request for the first cache line: Compress the first cache line to obtain a first updated cache line of a first size; Based on determining that the first size is equal to or less than the first predetermined size of the candidate compressed cache line, the first updated cache line is written into the candidate compressed cache line; Based on the determination that the first size is greater than the first predetermined size and equal to or less than the second predetermined size of the candidate compressed cache line, a read-modify-write operation is performed on the candidate compressed cache line based on the first updated cache line; as well as Based on the determination that the first size is greater than the second predetermined size of the candidate compressed cache line, a read-modify-write operation is performed on the candidate compressed cache line based on the first updated cache line, and a read-modify-write operation is performed on the overflow block among the plurality of overflow blocks.

8. The method of claim 7, wherein the first predetermined size is half the size of the candidate compressed cache line.

9. The method according to claim 7, further comprising: When writing the second cache line or the second portion of the second compressed cache line into the second predetermined portion of the candidate compressed cache line, an end bit index is written into the candidate compressed cache line to indicate where the second cache line or the second portion of the second compressed cache line is written within the candidate compressed cache line. as well as The second predetermined size is calculated based on the end-bit index in the candidate compressed cache line.

10. The method according to claim 1, further comprising: In response to receiving a cache line write request for the second cache line: Compress the second cache line to obtain a second updated cache line of a second size; Based on the determination that the sum of the second size and the size of the first compressed cache line is less than the first predetermined size of the candidate compressed cache line, a read-modify-write operation is performed to write the second updated cache line into the candidate compressed cache line; as well as Based on the determination that the sum of the second size and the size of the first compressed cache line is not less than the first predetermined size of the candidate compressed cache line, (i) a first read-modify-write operation is performed to write a first portion of the second updated cache line to the candidate compressed cache line, and (ii) a second read-modify-write operation is performed to write the remaining portion of the second updated cache line to the overflow block pointed to by the overflow pointer.

11. The method according to claim 1, further comprising: In response to receiving a cache line write request for either the first cache line or the second cache line: Compress the first cache line or the second cache line to obtain an updated compressed cache line with an updated size; as well as If it is determined that the updated size cannot fit within the overflow block pointed to by the overflow pointer, the overflow pointer is released and updated to point to a new overflow block among the plurality of overflow blocks.

12. The method of claim 1, wherein the first compressed cache line, the second compressed cache line, and the candidate compressed cache line have equal sizes.

13. The method according to claim 1, wherein the first data region and the second data region have equal sizes.

14. The method of claim 1, wherein the second predetermined portion is less than half the size of the candidate compressed cache line.

15. The method of claim 1, wherein the first compressed cache line and the second compressed cache line are written to the candidate compressed cache line in opposite directions, and wherein the first compressed cache line and the second compressed cache line are separated by one or more bytes.

16. A compressed memory system for a processor-based system, the compressed memory system comprising: A memory partitioning circuit, configured to divide a memory region into multiple data regions, each data region being associated with a corresponding priority level; A cache line selection circuit is configured to: (i) select a first cache line from a first data region in the plurality of data regions, and (ii) select a second cache line from a second data region in the plurality of data regions, wherein the first data region has a higher priority level than the second data region; A compression circuit configured to: (i) compress the first cache line to obtain a first compressed cache line, and (ii) compress the second cache line to obtain a second compressed cache line; as well as The cache line encapsulation circuit is configured as follows: Based on the determination that the first cache line is compressible: (i) write the first compressed cache line to a first predetermined portion of the candidate compressed cache line, and (ii) write the second cache line or a second portion of the second compressed cache line to a second predetermined portion of the candidate compressed cache line, wherein the first predetermined portion is larger than the second predetermined portion; as well as Based on at least one of the following: (i) the first cache line is incompressible, (ii) the second cache line is incompressible, or (iii) the second compressed cache line does not fit within the second predetermined portion of the candidate compressed cache line: An overflow pointer is set in the candidate compressed cache line, wherein the overflow pointer points to one of a plurality of overflow blocks according to the compression ratio of the second cache line or the size of the second compressed cache line, and wherein each of the plurality of overflow blocks has a different size.

17. The compressed memory system of claim 16, wherein the cache line encapsulation circuit is further configured to: Receive a read request for the first cache line or the second cache line; and In response to receiving the read request: Based on the determination that the overflow pointer is set, data is retrieved from the overflow blocks among the plurality of overflow blocks according to the overflow pointer.

18. The compressed memory system of claim 16, wherein the cache line encapsulation circuit is further configured to: Based on the determination that the first cache line is compressible: A first compression ratio control bit is set in the candidate compressed cache line; and Based on the determination that the first cache line is incompressible: Write the first portion of the first cache line into the candidate compressed cache line; Write the remainder of the first cache line to the overflow block; Reset the first compression ratio control bit in the candidate compressed cache line; as well as Set an overflow pointer in the candidate compressed cache line to point to the overflow block.

19. The compressed memory system of claim 18, wherein the cache line encapsulation circuit is further configured to: In response to receiving a read request for the first cache line: Based on the determination that the first compression ratio control bit is set: Retrieve the first cache line from the candidate compressed cache lines; and Based on the determination that the first compression ratio control bit has been reset: Retrieve the first portion of the first cache line from the candidate compressed cache line; and The second portion of the first cache line is retrieved from the overflow block based on the overflow pointer.

20. The compressed memory system of claim 19, wherein the cache line encapsulation circuit is further configured to: Based on the determination that the first cache line is incompressible: Depending on whether the second cache line is compressible, the second cache line or the second compressed cache line is written to the overflow block; and The second compression ratio control bit in the candidate compressed cache line is reset to indicate whether the second cache line is incompressible.

21. The compressed memory system of claim 20, wherein the cache line encapsulation circuit is further configured to: In response to receiving a read request for the second cache line: The second cache line or the second compressed cache line is retrieved from the overflow block based on the second compression ratio control bit.

22. The compressed memory system of claim 16, wherein the cache line encapsulation circuit is further configured to: In response to receiving a cache line write request for the first cache line: Compress the first cache line to obtain a first updated cache line of a first size; Based on determining that the first size is equal to or less than the first predetermined size of the candidate compressed cache line, the first updated cache line is written into the candidate compressed cache line; Based on the determination that the first size is greater than the first predetermined size and equal to or less than the second predetermined size of the candidate compressed cache line, a read-modify-write operation is performed on the candidate compressed cache line based on the first updated cache line; as well as Based on the determination that the first size is greater than the second predetermined size of the candidate compressed cache line, a read-modify-write operation is performed on the candidate compressed cache line based on the first updated cache line, and a read-modify-write operation is performed on the overflow block among the plurality of overflow blocks.

23. The compressed memory system of claim 22, wherein the first predetermined size is half the size of the candidate compressed cache line.

24. The compressed memory system of claim 22, wherein the cache line encapsulation circuit is further configured to: When writing the second cache line or the second portion of the second compressed cache line into the second predetermined portion of the candidate compressed cache line, an end-of-line index is written into the candidate compressed cache line to indicate where the second cache line or the second portion of the second compressed cache line is written within the candidate compressed cache line; and The second predetermined size is calculated based on the end-bit index in the candidate compressed cache line.

25. The compressed memory system of claim 16, wherein the cache line encapsulation circuit is further configured to: In response to receiving a cache line write request for the second cache line: Compress the second cache line to obtain a second updated cache line of a second size; Based on the determination that the sum of the second size and the size of the first compressed cache line is less than a first predetermined size of the candidate compressed cache line, a read-modify-write operation is performed to write the second updated cache line into the candidate compressed cache line; and Based on the determination that the sum of the second size and the size of the first compressed cache line is not less than the first predetermined size of the candidate compressed cache line, (i) a first read-modify-write operation is performed to write a first portion of the second updated cache line to the candidate compressed cache line, and (ii) a second read-modify-write operation is performed to write the remaining portion of the second updated cache line to the overflow block pointed to by the overflow pointer.

26. The compressed memory system of claim 16, wherein the cache line encapsulation circuit is further configured to: In response to receiving a cache line write request for either the first cache line or the second cache line: Compress the first cache line or the second cache line to obtain an updated compressed cache line with the updated size; and If it is determined that the updated size cannot fit within the overflow block pointed to by the overflow pointer, the overflow pointer is released and updated to point to a new overflow block among the plurality of overflow blocks.

27. The compressed memory system of claim 16, wherein the first compressed cache line, the second compressed cache line, and the candidate compressed cache line have equal sizes.

28. The compressed memory system of claim 16, wherein the first data region and the second data region have equal sizes.

29. The compressed memory system of claim 16, wherein the second predetermined portion is less than half the size of the candidate compressed cache line.

30. The compressed memory system of claim 16, wherein the cache line encapsulation circuit is further configured to: The first compressed cache line and the second compressed cache line are written to the candidate compressed cache line in the opposite direction, wherein the first compressed cache line and the second compressed cache line are separated by one or more bytes.

31. A non-transitory computer-readable medium having stored thereon computer-executable instructions, which, when executed by a processor, cause the processor to: The storage area is divided into multiple data areas, and each data area is associated with a corresponding priority level. (i) Selecting a first cache line from a first data region in the plurality of data regions, and (ii) Selecting a second cache line from a second data region in the plurality of data regions, wherein the first data region has a higher priority level than the second data region; (i) compress the first cache line to obtain a first compressed cache line, and (ii) compress the second cache line to obtain a second compressed cache line; as well as Based on the determination that the first cache line is compressible: (i) write the first compressed cache line to a first predetermined portion of the candidate compressed cache line, and (ii) write the second cache line or a second portion of the second compressed cache line to a second predetermined portion of the candidate compressed cache line, wherein the first predetermined portion is larger than the second predetermined portion; as well as Based on at least one of the following: (i) the first cache line is incompressible, (ii) the second cache line is incompressible, or (iii) the second compressed cache line does not fit within the second predetermined portion of the candidate compressed cache line: An overflow pointer is set in the candidate compressed cache line, wherein the overflow pointer points to one of a plurality of overflow blocks according to the compression ratio of the second cache line or the size of the second compressed cache line, and wherein each of the plurality of overflow blocks has a different size.

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