Photoelectric in-situ active pixel sensor and manufacturing method thereof

Abstract

The present invention discloses a photoelectric in-situ active pixel sensor, in which a device unit structure is formed on a double-buried SOI substrate. The double-buried SOI substrate includes: a semiconductor main layer, a second dielectric buried layer, a semiconductor middle layer, a first dielectric buried layer and a semiconductor top layer. The photosensitive structure includes a semiconductor middle layer and a first semiconductor epitaxial layer and a first ohmic contact region in contact with the semiconductor middle layer. The first ohmic contact region is connected to the first electrode through a contact hole at the top. Deep trench isolation is also formed on the peripheral side of the device unit structure, and the bottom surface of the deep trench isolation reaches the second dielectric buried layer. A second semiconductor epitaxial layer and a second ohmic contact region are also formed on the outside of the deep trench isolation. The deep trench isolation and the second dielectric buried layer isolate the photosensitive structure from the second semiconductor epitaxial layer and the semiconductor main layer on the peripheral side to suppress crosstalk between adjacent device unit structures. The present invention also discloses a method for manufacturing a photoelectric in-situ active pixel sensor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device technology, and in particular to a photoelectron in-situ active pixel sensor (PISD). The present invention also relates to a method for manufacturing the PISD. Background Art

[0002] To overcome the shortcomings of conventional silicon-compatible image sensors, which primarily include CMOS image sensors (CIS) and charge-coupled devices (CCDs), the inventors proposed a photoactive in-situ pixel sensor (PISD) based on a fully depleted silicon-on-insulator (SOI) substrate. This achieves highly sensitive single-transistor photoactive in-situ pixel sensing. PISD integrates all the necessary functions of an active pixel sensor into a single transistor, including photoelectric conversion, charge integration, amplification, and random gating. This makes it more compact than a conventional CIS.

[0003] However, in a PISD based on a traditional silicon-on-insulator substrate structure, crosstalk between different pixels of the sensor is very serious due to the migration of photoelectrons in the substrate. Therefore, it is necessary to reduce the crosstalk between pixels of the PISD. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a photoelectric in-situ active pixel sensor that can reduce crosstalk between pixels, i.e., device unit structures. To this end, the present invention also provides a method for manufacturing the photoelectric in-situ active pixel sensor.

[0005] In order to solve the above technical problems, the device unit structure of the photoelectric in-situ active pixel sensor provided by the present invention is formed on a double buried SOI (DSOI) substrate.

[0006] The double-buried-layer SOI substrate comprises: a semiconductor main layer, a second dielectric buried layer, a semiconductor middle layer, a first dielectric buried layer and a semiconductor top layer.

[0007] The second dielectric buried layer is formed on the top surface of the semiconductor main layer, the semiconductor intermediate layer is formed on the top surface of the second dielectric buried layer, the first dielectric buried layer is formed on the top surface of the semiconductor intermediate layer, and the semiconductor top layer is formed on the top surface of the first dielectric buried layer.

[0008] The device unit structure includes a MOS transistor and a photosensitive structure.

[0009] The MOS transistor is formed on the semiconductor top layer, and the channel region of the MOS transistor is formed by the semiconductor top layer.

[0010] The photosensitive structure includes the semiconductor intermediate layer, a first semiconductor epitaxial layer and a first ohmic contact region.

[0011] The first semiconductor epitaxial layer passes through the semiconductor top layer and the first dielectric buried layer and contacts the semiconductor middle layer; the first semiconductor epitaxial layer and the semiconductor middle layer both have a lightly doped structure of the second conductivity type.

[0012] The first ohmic contact region is formed in a surface region of the first semiconductor epitaxial layer and has a heavily doped structure of the second conductivity type.

[0013] The first ohmic contact region is connected to a first electrode composed of a front metal layer through a contact hole on the top.

[0014] A deep trench isolation is further formed on the peripheral side of the device unit structure, and the bottom surface of the deep trench isolation reaches the second dielectric buried layer.

[0015] A second semiconductor epitaxial layer and a second ohmic contact region are also formed outside the deep trench isolation.

[0016] The second semiconductor epitaxial layer passes through the semiconductor top layer, the first dielectric buried layer, the semiconductor middle layer and the second dielectric buried layer and contacts the semiconductor main layer; the second semiconductor epitaxial layer and the semiconductor main layer both have a lightly doped structure of the second conductivity type.

[0017] The second ohmic contact region is formed in a surface region of the second semiconductor epitaxial layer and has a heavily doped structure of a second conductivity type.

[0018] The deep trench isolation and the second dielectric buried layer isolate the photosensitive structure from the second semiconductor epitaxial layer and the semiconductor main layer on the peripheral side, so as to suppress crosstalk between adjacent device unit structures.

[0019] A further improvement is that the MOS transistor is formed in the first active region.

[0020] The first active region is located in a surrounding region surrounded by shallow trench isolation or the first active region is located in a surrounding region surrounded by shallow trench isolation and the corresponding deep trench isolation.

[0021] The bottom surface of the shallow trench isolation reaches the first dielectric buried layer.

[0022] A further improvement is that the gate structure of the MOS transistor is a planar gate, the gate structure is formed on the top surface of the semiconductor top layer, and the semiconductor top layer covered by the gate structure serves as the channel region.

[0023] A source region and a drain region heavily doped with the first conductivity type are formed on both sides of the gate structure, and the semiconductor top layer has a lightly doped structure with the second conductivity type.

[0024] A further improvement is that the number of the MOS transistor in the device unit structure is one.

[0025] A further improvement is that, in the exposure working state, the first electrode is connected to a first depletion voltage, the first depletion voltage causes the semiconductor intermediate layer and the first semiconductor epitaxial layer of the photosensitive structure to be depleted and form a first depletion region, and the first depletion voltage also causes the photogenerated carriers of the first conductive type generated in the first depletion region to be transferred to the first interface between the first dielectric buried layer and the semiconductor intermediate layer at the bottom of the MOS transistor, and the photogenerated carriers at the first interface cause the threshold voltage of the MOS transistor to change through the interface coupling effect.

[0026] In a reset state, the first electrode is connected to the second reset voltage to reset the photogenerated carriers in the first depletion region.

[0027] A further improvement is that the second ohmic contact region is connected to a second electrode composed of a front metal layer through a contact hole on the top.

[0028] The gate structure is connected to the gate composed of the front metal layer through a contact hole on the top.

[0029] The source region is connected to a source electrode formed by a front metal layer through a contact hole on the top.

[0030] The drain region is connected to a drain electrode formed by a front metal layer through a contact hole on the top.

[0031] A further improvement is that the doping concentration of the second semiconductor epitaxial layer and the semiconductor main layer is 1E15cm -3 ~1E17cm -3 .

[0032] The doping concentrations of the first semiconductor epitaxial layer and the semiconductor intermediate layer are both 1E15 cm -3 ~1E17cm -3 .

[0033] The doping concentration of the source region and the drain region is 1E19 cm -3 ~1E21cm -3 .

[0034] The doping concentration of the first ohmic contact region and the second ohmic contact region is 1E19 cm -3 ~1E21cm -3.

[0035] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

[0036] To solve the above technical problems, the present invention provides a method for manufacturing a photoelectric in-situ active pixel sensor, comprising the following steps:

[0037] Step 1: providing a double-buried layer SOI substrate and forming a first semiconductor epitaxial layer and a second semiconductor epitaxial layer in selected areas.

[0038] The double-buried-layer SOI substrate comprises: a semiconductor main layer, a second dielectric buried layer, a semiconductor middle layer, a first dielectric buried layer and a semiconductor top layer.

[0039] The second dielectric buried layer is formed on the top surface of the semiconductor main layer, the semiconductor intermediate layer is formed on the top surface of the second dielectric buried layer, the first dielectric buried layer is formed on the top surface of the semiconductor intermediate layer, and the semiconductor top layer is formed on the top surface of the first dielectric buried layer.

[0040] The first semiconductor epitaxial layer passes through the semiconductor top layer and the first dielectric buried layer and contacts the semiconductor middle layer; the first semiconductor epitaxial layer and the semiconductor middle layer both have a lightly doped structure of the second conductivity type.

[0041] The second semiconductor epitaxial layer passes through the semiconductor top layer, the first dielectric buried layer, the semiconductor middle layer and the second dielectric buried layer and contacts the semiconductor main layer; the second semiconductor epitaxial layer and the semiconductor main layer both have a lightly doped structure of the second conductivity type.

[0042] Step 2: forming a deep trench isolation on the peripheral side of the device unit structure, wherein the bottom surface of the deep trench isolation reaches the second dielectric buried layer.

[0043] The second semiconductor epitaxial layer is located outside the deep trench isolation.

[0044] Step 3: forming a MOS transistor of a device unit structure on the top semiconductor layer.

[0045] The channel region of the MOS transistor is composed of the semiconductor top layer.

[0046] Step 4: forming a first ohmic contact region heavily doped with the second conductivity type in the surface region of the first semiconductor epitaxial layer and forming a second ohmic contact region heavily doped with the second conductivity type in the surface region of the second semiconductor epitaxial layer.

[0047] The photosensitive structure of the device unit structure includes the semiconductor intermediate layer, the first semiconductor epitaxial layer and the first ohmic contact region.

[0048] The deep trench isolation and the second dielectric buried layer isolate the photosensitive structure from the second semiconductor epitaxial layer and the semiconductor main layer on the peripheral side, so as to suppress crosstalk between adjacent device unit structures.

[0049] Step 4: forming a contact hole and an electrode composed of a front metal layer, wherein the electrode includes a first electrode connected to the first ohmic contact region through the contact hole.

[0050] A further improvement is that before step 3, the following is also included:

[0051] A shallow trench isolation is formed, wherein the bottom surface of the shallow trench isolation reaches the first dielectric buried layer.

[0052] The MOS transistor is formed in the first active region;

[0053] The first active region is located in a surrounding region surrounded by the shallow trench isolation or the first active region is located in a surrounding region surrounded by the shallow trench isolation and the corresponding deep trench isolation.

[0054] A further improvement is that step three includes the following sub-steps:

[0055] forming a gate structure of the MOS transistor, wherein the gate structure is a planar gate, the gate structure is formed on the top surface of the semiconductor top layer, and the semiconductor top layer covered by the gate structure serves as the channel region; the semiconductor top layer has a lightly doped structure of the second conductivity type;

[0056] A source region and a drain region heavily doped with the first conductivity type are simultaneously formed on both sides of the gate structure. The doping type of the source region is the same as that of the channel region and is opposite to that of the channel region.

[0057] A further improvement is that the number of the MOS transistor in the device unit structure is one.

[0058] A further improvement is that, in an exposure operating state, the first electrode is connected to a first depletion voltage, the first depletion voltage causes the semiconductor intermediate layer and the first semiconductor epitaxial layer of the photosensitive structure to be depleted and form a first depletion region, the first depletion voltage also causes photogenerated carriers of the first conductivity type generated in the first depletion region to be transferred to a first interface between the first dielectric buried layer and the semiconductor intermediate layer at the bottom of the MOS transistor, and the photogenerated carriers at the first interface cause the threshold voltage of the MOS transistor to change through an interface coupling effect;

[0059] In a reset state, the first electrode is connected to the second reset voltage to reset the photogenerated carriers in the first depletion region.

[0060] A further improvement is that in step four, the electrode formed by the front metal layer further includes: a second electrode, a gate, a source and a drain.

[0061] The second ohmic contact region is connected to the second electrode through a contact hole at the top;

[0062] The gate structure is connected to the gate through a contact hole at the top;

[0063] The source region is connected to the source electrode through a contact hole at the top;

[0064] The drain region is connected to the drain electrode through a contact hole at the top.

[0065] A further improvement is that the doping concentration of the second semiconductor epitaxial layer and the semiconductor main layer is 1E15cm -3 ~1E17cm -3 .

[0066] The doping concentrations of the first semiconductor epitaxial layer and the semiconductor intermediate layer are both 1E15 cm -3 ~1E17cm -3 .

[0067] The doping concentration of the source region and the drain region is 1E19 cm -3 ~1E21cm -3 .

[0068] The doping concentration of the first ohmic contact region and the second ohmic contact region is 1E19 cm -3 ~1E21cm -3 .

[0069] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

[0070] The PISD of the present invention adopts a double-buried-layer SOI substrate, wherein the photosensitive structure is located in the semiconductor intermediate layer between the double buried layers. Combined with the deep trench isolation and the setting of the second dielectric buried layer at the bottom, the photosensitive structure and the surrounding semiconductor main layer can be isolated, thereby preventing the photogenerated carriers between adjacent device unit structures from generating crosstalk through the semiconductor main layer. Therefore, the present invention can suppress crosstalk between different pixels.

[0071] In addition, the present invention sets a first ohmic contact area on the surface of the first semiconductor epitaxial layer on the top of the semiconductor intermediate layer of the photosensitive structure and connects the first ohmic contact area to the first electrode formed by the front metal layer through a contact hole. By adjusting the voltage on the first electrode, not only the exposure operation under light can be realized, but also the reset operation after light can be realized. That is, by adjusting the voltage applied to the first electrode, the carriers such as electrons generated in the semiconductor intermediate layer by light can be recombined without being retained in the semiconductor intermediate layer, so the reset operation of the sensor after light can be realized.

[0072] In addition, the present invention can define the first active region corresponding to the MOS transistor formation region through shallow trench isolation or through shallow trench isolation and adjacent deep trench isolation, which can make the entire device unit structure compact and help reduce the device size. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0074] Figure 1 1 is a schematic structural diagram of a photoelectric in-situ active pixel sensor according to a first embodiment of the present invention;

[0075] Figure 2 1 is a schematic structural diagram of a photoelectric in-situ active pixel sensor according to a second embodiment of the present invention;

[0076] Figure 3A-3F Schematic diagram of the device structure in each step of the manufacturing method of the photoelectric in-situ active pixel sensor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0077] like Figure 1 , which is a schematic structural diagram of the optoelectronic in-situ active pixel sensor according to the first embodiment of the present invention; the device unit structure of the optoelectronic in-situ active pixel sensor according to the first embodiment of the present invention is formed on a double-buried layer SOI substrate.

[0078] The double-buried-layer SOI substrate includes: a semiconductor main layer 101 , a second dielectric buried layer 102 , a semiconductor intermediate layer 103 , a first dielectric buried layer 104 and a semiconductor top layer 105 .

[0079] The second dielectric buried layer 102 is formed on the top surface of the semiconductor main layer 101, the semiconductor intermediate layer 103 is formed on the top surface of the second dielectric buried layer 102, the first dielectric buried layer 104 is formed on the top surface of the semiconductor intermediate layer 103, and the semiconductor top layer 105 is formed on the top surface of the first dielectric buried layer 104.

[0080] The device unit structure includes a MOS transistor 201 and a photosensitive structure.

[0081] The MOS transistor 201 is formed on the semiconductor top layer 105 , and a channel region of the MOS transistor 201 is formed by the semiconductor top layer 105 .

[0082] The photosensitive structure includes the semiconductor intermediate layer 103 , a first semiconductor epitaxial layer 1031 and a first ohmic contact region 108 .

[0083] The first semiconductor epitaxial layer 1031 passes through the semiconductor top layer 105 and the first dielectric buried layer 104 and contacts the semiconductor middle layer 103 ; both the first semiconductor epitaxial layer 1031 and the semiconductor middle layer 103 have a lightly doped structure of the second conductivity type.

[0084] The first ohmic contact region 108 is formed in a surface region of the first semiconductor epitaxial layer 1031 and has a heavily doped structure of the second conductivity type.

[0085] The first ohmic contact region 108 is connected to a first electrode formed of a front metal layer through a contact hole 115 on the top.

[0086] A deep trench isolation 106 is further formed on the peripheral side of the device unit structure, and the bottom surface of the deep trench isolation 106 reaches the second dielectric buried layer 102 .

[0087] A second semiconductor epitaxial layer 1011 and a second ohmic contact region 109 are further formed outside the deep trench isolation 106 .

[0088] The second semiconductor epitaxial layer 1011 passes through the semiconductor top layer 105, the first dielectric buried layer 104, the semiconductor middle layer 103 and the second dielectric buried layer 102 and contacts the semiconductor main layer 101; the second semiconductor epitaxial layer 1011 and the semiconductor main layer 101 both have a lightly doped structure of the second conductivity type.

[0089] The second ohmic contact region 109 is formed in a surface region of the second semiconductor epitaxial layer 1011 and has a heavily doped structure of the second conductivity type.

[0090] The deep trench isolation 106 and the second dielectric buried layer 102 isolate the photosensitive structure from the second semiconductor epitaxial layer 1011 and the semiconductor main layer 101 on the peripheral side, so as to suppress crosstalk between adjacent device unit structures.

[0091] In some embodiments, the material of the semiconductor body layer 101 includes silicon, germanium, silicon germanium, gallium nitride, or indium gallium arsenide.

[0092] The material of the semiconductor intermediate layer 103 includes silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenide.

[0093] The material of the semiconductor top layer 105 includes silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenide.

[0094] The material of the first semiconductor epitaxial layer 1031 includes silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenide.

[0095] The material of the second semiconductor epitaxial layer 1011 includes silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenide.

[0096] In some embodiments, the material of the second buried dielectric layer 102 includes insulating materials such as silicon dioxide, aluminum oxide, and hafnium oxide.

[0097] The material of the first dielectric buried layer 104 includes insulating materials such as silicon dioxide, aluminum oxide, and hafnium oxide.

[0098] In the first embodiment of the present invention, the MOS transistor 201 is formed in the first active region.

[0099] The first active region is located in a surrounding area enclosed by the shallow trench isolation 107 and the corresponding deep trench isolation 106 . Figure 1 In the illustrated structure, the deep trench isolation 106 is directly used on one side of the first active area for isolation. This makes the device unit structure more compact and helps reduce the area of ​​the device unit structure. In other embodiments, the first active area can be located within the surrounding area surrounded by the shallow trench isolation 107. In this case, the shallow trench isolation 107 surrounds the first active area. The first semiconductor epitaxial layer 1031 and the first ohmic contact region 108 can be disposed in the area between the shallow trench isolation 107 and the deep trench isolation 106.

[0100] The bottom surface of the shallow trench isolation 107 reaches the first buried dielectric layer 104 .

[0101] In the first embodiment of the present invention, the gate structure of the MOS transistor 201 is a planar gate. The gate structure is formed on the top surface of the semiconductor top layer 105 , and the semiconductor top layer 105 covered by the gate structure serves as the channel region.

[0102] The gate structure includes a stacked gate dielectric layer 110 and a gate conductive material layer 111. In some embodiments, the gate dielectric layer 110 is a gate oxide layer, and the gate conductive material layer is a polysilicon gate. In some embodiments, the gate dielectric layer 110 can also be a high-k dielectric layer, and the gate conductive material layer 111 can be a metal gate.

[0103] A sidewall spacer 112 is formed on the side of the gate structure.

[0104] A source region 113 and a drain region 114, both heavily doped with the first conductivity type, are formed on either side of the gate structure, and the semiconductor top layer 105 has a lightly doped structure with the second conductivity type. In the first embodiment of the present invention, the source region 113 and the drain region 114 are symmetrical and can be interchanged, depending on the voltage applied during use.

[0105] In the first embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type. Therefore, the MOS transistor is NMOS.

[0106] In some embodiments, the doping concentration of the second semiconductor epitaxial layer 1011 and the semiconductor main layer 101 is 1E15cm -3 ~1E17cm -3 .

[0107] The doping concentrations of the first semiconductor epitaxial layer 1031 and the semiconductor intermediate layer 103 are both 1E15 cm -3 ~1E17cm -3 .

[0108] In some embodiments, the doping concentration of the source region 113 and the drain region 114 is 1E19 cm -3 ~1E21cm -3 .

[0109] The doping concentration of the first ohmic contact region 108 and the second ohmic contact region 109 is 1E19 cm -3 ~1E21cm -3 .

[0110] The doping concentration of the semiconductor top layer 105 is set according to the requirements of the channel region of the MOS transistor 201. Since the MOS transistor 201 is an NMOS, the channel region is usually lightly doped with P-type.

[0111] The second ohmic contact region 109 is connected to a second electrode formed of a front metal layer through a top contact hole 115. The potential of the semiconductor body layer 101 can be controlled via the second electrode.

[0112] The gate structure is connected to the gate composed of the front metal layer through the contact hole 115 on the top.

[0113] The source region 113 is connected to the source electrode formed by the front metal layer through a contact hole 115 on the top.

[0114] The drain region 114 is connected to the drain electrode formed by the front metal layer through a contact hole 115 on the top.

[0115] In the first embodiment of the present invention, the number of MOS transistors 201 in the device unit structure is one. The photoelectric in-situ active pixel sensor is a single-transistor active pixel sensor. Therefore, compared with existing CMOS image sensors, which require more than three MOS transistors in the device unit structure, i.e., the pixel unit, the device unit structure of the first embodiment of the present invention can only use one transistor, which also greatly reduces the area of ​​the device unit structure.

[0116] In the first embodiment of the present invention, in an exposure operating state, the first electrode is connected to a first depletion voltage. This first depletion voltage causes depletion of the semiconductor intermediate layer 103 and the first semiconductor epitaxial layer 1031 of the photosensitive structure, forming a first depletion region. The first depletion voltage also causes photogenerated carriers of the first conductivity type generated in the first depletion region to transfer to the first interface between the first dielectric buried layer 104 and the semiconductor intermediate layer 103 at the bottom of the MOS transistor 201. The photogenerated carriers at the first interface cause a change in the threshold voltage of the MOS transistor 201 through an interface coupling effect. Since the first conductivity type in the first embodiment of the present invention is N-type, the photogenerated carriers of the first conductivity type are photogenerated electrons. After the photogenerated electrons accumulate at the first interface, holes are induced at the top interface of the first dielectric buried layer 104. These holes increase the depletion of the NMOS channel region, increasing the threshold voltage of the MOS transistor 201, reducing the output current of the MOS transistor 201, and changing the output voltage, thereby achieving image sensing.

[0117] In the reset state, the first electrode is connected to the second reset voltage to reset the photogenerated carriers in the first depletion region. Therefore, in the first embodiment of the present invention, a reset operation can be performed via the first electrode after illumination, and the reset operation can remove the photogenerated carriers in the first depletion region.

[0118] The first embodiment of the present invention, the PISD, adopts a double-buried-layer SOI substrate, wherein the photosensitive structure is located in the semiconductor intermediate layer 103 between the double buried layers. Combined with the setting of the deep trench isolation 106 and the second dielectric buried layer 102 at the bottom, the photosensitive structure and the semiconductor main layer 101 on the peripheral side can be isolated, thereby preventing the photogenerated carriers between adjacent device unit structures from generating crosstalk through the semiconductor main layer 101. Therefore, the first embodiment of the present invention can suppress crosstalk between different pixels.

[0119] In addition, the first embodiment of the present invention sets a first ohmic contact area 108 on the surface of the first semiconductor epitaxial layer 1031 on the top of the semiconductor intermediate layer 103 of the photosensitive structure and connects the first ohmic contact area 108 to the first electrode formed by the front metal layer through the contact hole 115. By adjusting the voltage on the first electrode, not only the exposure operation under light can be realized, but also the reset operation can be realized after light.

[0120] In addition, the first embodiment of the present invention can define the first active region corresponding to the MOS transistor 201 formation area through shallow trench isolation 107 or through shallow trench isolation 107 and adjacent deep trench isolation 106, which can make the entire device unit structure compact and help reduce the device size.

[0121] like Figure 2 , which is a schematic structural diagram of the photoelectric in-situ active pixel sensor according to the second embodiment of the present invention; the difference from the photoelectric in-situ active pixel sensor according to the first embodiment of the present invention is that in the photoelectric in-situ active pixel sensor according to the second embodiment of the present invention, the first conductive type is P-type and the second conductive type is N-type.

[0122] so, Figure 2 The semiconductor main layer 101a, the semiconductor middle layer 103a, the semiconductor top layer 105a, the first semiconductor epitaxial layer 1031 and the second semiconductor epitaxial layer 1011 are all lightly N-type doped.

[0123] The first ohmic contact region 108 a and the second ohmic contact region 109 a are both heavily N-type doped, ie, N+ doped.

[0124] The MOS transistor 201 a is a PMOS transistor, and both the source region 113 a and the drain region 114 a are heavily P-type doped, ie, P+ doped.

[0125] like Figures 3A to 3F FIG. 1 is a schematic diagram of the device structure in each step of the method for manufacturing a photoelectric in-situ active pixel sensor according to an embodiment of the present invention; the method for manufacturing a photoelectric in-situ active pixel sensor according to an embodiment of the present invention can manufacture various photoelectric in-situ active pixel sensors according to an embodiment of the present invention. Figure 1 The photoelectric in-situ active pixel sensor of the first embodiment of the present invention is used as an example for description. The manufacturing method of the photoelectric in-situ active pixel sensor of the embodiment of the present invention includes the following steps:

[0126] Step 1: Figure 3A As shown, a double buried layer SOI substrate is provided.

[0127] In some embodiment methods, the double-buried SOI substrate can be synthesized by bonding and thinning two SOI substrate wafers.

[0128] The double-buried-layer SOI substrate includes: a semiconductor main layer 101 , a second dielectric buried layer 102 , a semiconductor intermediate layer 103 , a first dielectric buried layer 104 and a semiconductor top layer 105 .

[0129] The second dielectric buried layer 102 is formed on the top surface of the semiconductor main layer 101, the semiconductor intermediate layer 103 is formed on the top surface of the second dielectric buried layer 102, the first dielectric buried layer 104 is formed on the top surface of the semiconductor intermediate layer 103, and the semiconductor top layer 105 is formed on the top surface of the first dielectric buried layer 104.

[0130] like Figure 3B As shown, a first semiconductor epitaxial layer 1031 is formed in a selected region and a second semiconductor epitaxial layer 1011 is formed in a selected region.

[0131] The steps of forming the first semiconductor epitaxial layer 1031 include:

[0132] A photoresist pattern is formed using a photolithography process to define the formation area of ​​the first semiconductor epitaxial layer 1031. The semiconductor top layer 105 and the first dielectric buried layer 104 in the formation area of ​​the first semiconductor epitaxial layer 1031 are etched to expose the semiconductor intermediate layer 103 at the bottom. The etched area is shown in the dotted box 202.

[0133] In some embodiment methods, the etching method for etching the area where the first semiconductor epitaxial layer 1031 is formed can be a dry method or a wet method: dry etching generally uses fluorine-based or halogen element gases, such as SF6, Cl2, etc.; while wet etching generally uses strong acids or strong bases such as HF, NH4HF2 and other solutions.

[0134] Afterwards, epitaxial growth is performed to form the first semiconductor epitaxial layer 1031. The first semiconductor epitaxial layer 1031 passes through the semiconductor top layer 105 and the first buried dielectric layer 104 and contacts the semiconductor intermediate layer 103. Both the first semiconductor epitaxial layer 1031 and the semiconductor intermediate layer 103 have a lightly doped structure of the second conductivity type. During the epitaxial growth of the first semiconductor epitaxial layer 1031, in-situ doping is performed, with the same doping as the semiconductor intermediate layer 103.

[0135] The steps of forming the second semiconductor epitaxial layer 1011 include:

[0136] A photolithography process is used to form a photoresist pattern to define the area where the second semiconductor epitaxial layer 1011 will be formed. The semiconductor top layer 105, the first dielectric buried layer 104, the semiconductor intermediate layer 103, and the second dielectric buried layer 102 in the area where the second semiconductor epitaxial layer 1011 will be formed are then etched to expose the semiconductor body layer 101. The etched area is shown in the dashed box 203. In some embodiments, the etching method for etching the second semiconductor epitaxial layer 1011 can be a dry or wet method. Dry etching generally uses fluorine-based or halogen-based gases, such as SF6 and Cl2, while wet etching generally uses strong acids or bases, such as HF, NH4HF2, or other solutions.

[0137] Afterwards, epitaxial growth is performed to form the second semiconductor epitaxial layer 1011. The second semiconductor epitaxial layer 1011 passes through the semiconductor top layer 105, the first dielectric buried layer 104, the semiconductor intermediate layer 103, and the second dielectric buried layer 102, and contacts the semiconductor main layer 101. The second semiconductor epitaxial layer 1011 and the semiconductor main layer 101 both have a lightly doped structure of the second conductivity type. During the epitaxial growth of the second semiconductor epitaxial layer 1011, in-situ doping is performed, and the doping is the same as that of the semiconductor main layer 101.

[0138] The formation order of the first semiconductor epitaxial layer 1031 and the second semiconductor epitaxial layer 1011 can be interchanged, and the etching processes of the two can be separated and the epitaxial process can be shared.

[0139] In some embodiments, the doping concentrations of the second semiconductor epitaxial layer 1011 and the semiconductor main layer 101 are both 1E15 cm -3 ~1E17cm -3 .

[0140] In some embodiments, the doping concentrations of the first semiconductor epitaxial layer 1031 and the semiconductor intermediate layer 103 are both 1E15 cm -3 ~1E17cm -3 .

[0141] In some embodiments, the material of the semiconductor body layer 101 includes silicon, germanium, silicon germanium, gallium nitride, or indium gallium arsenide.

[0142] The material of the semiconductor intermediate layer 103 includes silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenide.

[0143] The material of the semiconductor top layer 105 includes silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenide, and the thickness is between 5 nm and 500 nm.

[0144] The material of the first semiconductor epitaxial layer 1031 includes silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenide.

[0145] The material of the second semiconductor epitaxial layer 1011 includes silicon, germanium, silicon germanium, gallium nitride or indium gallium arsenide.

[0146] In some embodiments, the second buried dielectric layer 102 is made of insulating materials such as silicon dioxide, aluminum oxide, and hafnium oxide, and has a thickness between 10 nm and 1000 nm.

[0147] The first dielectric buried layer 104 is made of insulating materials such as silicon dioxide, aluminum oxide, and hafnium oxide, and has a thickness between 10 nm and 1000 nm.

[0148] Step 2: Figure 3B As shown, a deep trench isolation 106 is formed on the peripheral side of the device unit structure, and the bottom surface of the deep trench isolation 106 reaches the second dielectric buried layer 102 .

[0149] The second semiconductor epitaxial layer 1011 is located outside the deep trench isolation 106 .

[0150] The deep trench isolation (DTI) 106 formation process includes the following steps:

[0151] Photolithography and opening the DTI window form a photoresist pattern that defines the formation area of ​​the deep trench isolation 106. The photoresist is then used as a mask to etch the semiconductor top layer 105, the first buried dielectric layer 104, the semiconductor intermediate layer 103, the second buried dielectric layer 102, and as far as the semiconductor body layer 101, forming a recessed structure, i.e., a deep trench. Etching can be performed using either dry or wet methods: dry etching generally uses fluorine-based or halogen-based gases, while wet etching generally uses strong acid or strong base solutions.

[0152] Then, silicon dioxide is deposited to fill the groove to form the deep trench isolation 106. The silicon dioxide of the deep trench isolation 106 is usually formed by chemical vapor deposition (CVD).

[0153] The method of the embodiment of the present invention further includes:

[0154] A shallow trench isolation 107 is formed, and the bottom surface of the shallow trench isolation 107 reaches the first buried dielectric layer 104 .

[0155] The shallow trench isolation 107 is formed by a shallow trench isolation process, namely, an STI process.

[0156] The shallow trench isolation 107 is used to define a first active area where the MOS transistor 201 is located;

[0157] In some example methods, the STI process includes:

[0158] Photolithography and opening the STI window form a photoresist pattern that defines the shallow trench isolation 107 formation area. The photoresist is then used as a mask to etch the semiconductor top layer 105 and the first buried dielectric layer 104, as well as the semiconductor intermediate layer 103, to form a recessed structure, i.e., a shallow trench. Etching can be performed using either dry or wet methods: dry etching typically uses fluorine-based or halogen-based gases, while wet etching typically uses strong acid or strong base solutions.

[0159] Then, silicon dioxide is deposited to fill the groove to form the shallow trench isolation 107. The silicon dioxide of the shallow trench isolation 107 is usually formed by chemical vapor deposition (CVD).

[0160] Preferably, the first active region is located in a surrounding area enclosed by the shallow trench isolation 107 and the corresponding deep trench isolation 106. Figure 3B In the cross-sectional view of , one side of the first active region is defined by the deep trench isolation 106, which can make the entire device unit structure more compact and reduce its size.

[0161] In the embodiment method, the first active area can also be located in the surrounding area surrounded by the shallow trench isolation 107. In this way, the shallow trench isolation 107 is present around the first active area, and the first semiconductor epitaxial layer 1031 can also be formed in the area between the shallow trench isolation 107 and the deep trench isolation 106.

[0162] Step 3: forming a MOS transistor 201 of a device unit structure on the semiconductor top layer 105 .

[0163] The channel region of the MOS transistor 201 is composed of the semiconductor top layer 105. The doping of the semiconductor top layer 105 is set according to the requirements of the channel region of the MOS transistor 201, and has a second conductivity type lightly doped structure.

[0164] In the method of the embodiment of the present invention, step three includes the following sub-steps:

[0165] The gate structure of the MOS transistor 201 is formed. The gate structure is a planar gate. The gate structure is formed on the top surface of the semiconductor top layer 105. The semiconductor top layer 105 covered by the gate structure serves as the channel region. The steps of forming the gate structure include:

[0166] like Figure 3CAs shown, a gate dielectric layer 110 and a gate conductive material layer 111 are formed. The gate dielectric layer 110 and the gate conductive material layer 111 are patterned and etched to form the gate structure. In some embodiments, the gate dielectric layer 110 is a gate oxide layer, and the gate conductive material layer 111 is a polysilicon gate.

[0167] In some embodiments, the gate dielectric layer 110 may be a high-k dielectric layer, and the gate conductive material layer 111 may be a metal gate.

[0168] When the gate dielectric layer 110 is a high dielectric constant layer, the material of the high dielectric constant layer includes hafnium oxide or aluminum oxide, etc., which is deposited by an atomic layer deposition system (ALD) and has a thickness generally between 1 nm and 30 nm.

[0169] In some embodiments, the gate conductive material layer 111 can also be a composite layer of a polysilicon layer and a metal. In some embodiments, the gate conductive material layer 111 can have a thickness of 10 nm to 500 nm.

[0170] The patterned etching of the gate structure includes the following steps:

[0171] Photolithography forms a photoresist pattern to open a gate window, that is, the formation area of ​​the gate structure will be covered with photoresist and the photoresist outside the formation area of ​​the gate structure will be removed to form a window. Thereafter, the gate conductive material layer 111 and the gate dielectric layer 110 are etched using the photoresist as a mask to form the pattern of the gate structure. Etching can be done by dry or wet methods; dry etching generally uses fluorine-based or halogen element gases, such as SF6, CHF3, HBr or Cl2; and wet etching generally uses TMAH, KOH and other solutions.

[0172] like Figure 3D As shown, a spacer 112 is then formed on the side of the gate structure.

[0173] In some exemplary methods, the steps of forming the sidewall spacer 112 include:

[0174] Deposit a layer of spacer material, such as silicon nitride, silicon dioxide, or low-k dielectrics such as SiOCN and SiBCN. This deposition can be done using processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).

[0175] Then, etching is performed to form the sidewall spacer 112. The etching generally uses reactive ion etching with vertical directionality. The dry etching can use fluorine-based gases such as SF6, CHF3 or CH3F.

[0176] like Figure 3FAs shown, heavily doped source regions 111 and drain regions 112 are simultaneously formed in the semiconductor top layer 105 on both sides of the gate structure. The doping type of the source region 111 is the same as that of the channel region and opposite to that of the channel region.

[0177] Since the MOS transistor 201 in the photoelectric in-situ active pixel sensor of the first embodiment of the present invention is an NMOS, the source region 111 and the drain region 112 are both heavily N-type doped.

[0178] In some embodiments, the doping concentration of the source region 113 and the drain region 114 is 1E19 cm -3 ~1E21cm -3 .

[0179] The number of the MOS transistor 201 in the device unit structure is one.

[0180] In the embodiment of the present invention, the first ohmic contact region 108 described later is formed before the source region 111 and the drain region 112. Figure 3F As shown, the steps of forming the source region 111 and the drain region 112 include:

[0181] A photoresist pattern is formed by photolithography to open the formation area of ​​the MOS transistor 201, that is, the first active area.

[0182] Afterwards, the semiconductor top layer 105 located on both sides of the gate structure in the first active region is removed using the photoresist and the gate structure as masks.

[0183] Afterwards, epitaxial growth is performed and a second conductive type, ie, P-type, in-situ heavy doping is performed to form the source region 111 and the drain region 112. The doping concentration of the source region 111 and the drain region 112 is 1E19cm -3 to 1E21cm -3 Therefore, in the first embodiment of the present invention, the source region 111 and the drain region 112 are formed by removing the semiconductor top layer 105 and then regrowing it. In some embodiment methods, the material of the source region 112 and the drain region 112 can be the same as the material of the semiconductor top layer 105. In some embodiment methods, the material of the source region 112 and the drain region 112 can be different from the material of the semiconductor top layer 105. For example, the material of the source region 112 and the drain region 112 can be a material that provides stress for the channel region. When the semiconductor top layer 105 is silicon, the material of the source region 112 and the drain region 112 can be SiGe, which can improve the mobility of the channel carriers of the PMOS.

[0184] In some embodiments, the source region 112 and the drain region 112 can also be formed in the semiconductor top layer 105 on both sides of the gate structure in a self-aligned manner by source-drain implantation.

[0185] In some embodiments, the first ohmic contact region 108 may be formed after the source region 111 and the drain region 112 are placed.

[0186] Step 4: Figure 3E As shown, a first ohmic contact region 108 heavily doped with the second conductivity type is formed in the surface region of the first semiconductor epitaxial layer 1031 , and a second ohmic contact region 109 heavily doped with the second conductivity type is formed in the surface region of the second semiconductor epitaxial layer 1011 .

[0187] The photosensitive structure of the device unit structure includes the semiconductor intermediate layer 103 , the first semiconductor epitaxial layer 1031 and the first ohmic contact region 108 .

[0188] In the method of the embodiment of the present invention, the first ohmic contact region 108 and the second ohmic contact region 109 are formed simultaneously by using a photolithography process definition plus ion implantation method.

[0189] In some embodiments, the doping concentration of the first ohmic contact region 108 and the second ohmic contact region 109 is 1E19 cm -3 ~1E21cm -3 .

[0190] The deep trench isolation 106 and the second dielectric buried layer 102 isolate the photosensitive structure from the second semiconductor epitaxial layer 1011 and the semiconductor main layer 101 on the peripheral side, so as to suppress crosstalk between adjacent device unit structures.

[0191] Step 4: Figure 1 As shown, a contact hole 115 and an electrode composed of a front metal layer are formed, and the electrode includes a first electrode connected to the first ohmic contact region 108 through the contact hole 115 .

[0192] In an exposure working state, the first electrode is connected to a first depletion voltage. The first depletion voltage causes the semiconductor intermediate layer 103 and the first semiconductor epitaxial layer 1031 of the photosensitive structure to be depleted and form a first depletion region. The first depletion voltage also causes photogenerated carriers of the first conductivity type generated in the first depletion region to be transferred to a first interface between the first dielectric buried layer 104 and the semiconductor intermediate layer 103 at the bottom of the MOS transistor 201. The photogenerated carriers at the first interface cause the threshold voltage of the MOS transistor 201 to change through an interface coupling effect.

[0193] In a reset state, the first electrode is connected to the second reset voltage to reset the photogenerated carriers in the first depletion region.

[0194] In the method of the embodiment of the present invention, the electrode formed by the front metal layer further includes: a second electrode, a gate electrode, a source electrode, and a drain electrode.

[0195] The second ohmic contact region 109 is connected to the second electrode through a contact hole 115 at the top;

[0196] The gate structure is connected to the gate through a contact hole 115 at the top;

[0197] The source region 113 is connected to the source electrode through a contact hole 115 at the top;

[0198] The drain region 114 is connected to the drain electrode through a contact hole 115 at the top.

[0199] In some embodiment methods, the metal interconnection process includes multiple front metal layers, and each of the front metal layers is isolated by an interlayer film.

[0200] Each of the contact holes 115 passes through the bottom interlayer film. The steps of forming the contact holes 115 include:

[0201] A photoresist pattern is formed by a photolithography process to open the formation area of ​​each contact hole 115.

[0202] Then the interlayer film is etched to form a contact hole opening.

[0203] The contact hole opening is filled with metal and annealed, and finally the metal filled in the contact hole opening forms the contact hole 115. Common metals for the contact hole 115 include aluminum, nickel, titanium, or metal silicides such as nickel silicon and titanium silicon, and the annealing temperature is between 300 degrees and 900 degrees.

[0204] Then, the first front metal layer is formed and patterned.

[0205] In the embodiment of the present invention, the first conductive type is N-type and the second conductive type is P-type, so that Figure 1 The illustrated embodiment is an electrically in-situ active pixel sensor according to a first embodiment of the present invention.

[0206] If the conductivity types of the doping structures are interchanged, the configuration after the interchange is: the first conductivity type is P type, the second conductivity type is N type, then the method of the embodiment of the present invention can produce Figure 2 The second embodiment of the present invention is an electrically in-situ active pixel sensor.

[0207] Unlike the existing PISD based on SOI structure, which has a serious problem of crosstalk between pixels due to the migration of photoelectrons in the substrate silicon layer, i.e., the semiconductor main layer at the bottom of the SOI, the embodiment of the present invention forms a semiconductor intermediate layer located between the double buried layers through an additional dielectric buried layer, such as an oxide buried layer. The photosensitive structure, i.e., the photoelectric conversion structure, is located in the semiconductor intermediate layer, so photogenerated carriers such as electrons are generated in the semiconductor intermediate layer. Since there is a dielectric buried layer, i.e., the second dielectric buried layer, as an isolation structure, between the semiconductor intermediate layer and the bottom semiconductor main layer, it can prevent photogenerated carriers from migrating between the semiconductor main layers, thereby suppressing crosstalk between pixels.

[0208] Moreover, after the semiconductor middle layer is led out through the first ohmic contact area and the first electrode on the top, by adjusting the voltage applied to the first electrode, the carriers such as electrons generated in the semiconductor middle layer by light can be recombined instead of being retained in the semiconductor middle layer, thereby realizing the reset operation of the sensor after light exposure.

[0209] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A photoelectric in-situ active pixel sensor, characterized in that: The device unit structure is formed on a double-buried SOI substrate; The double buried layer SOI substrate comprises: a semiconductor main layer, a second dielectric buried layer, a semiconductor middle layer, a first dielectric buried layer and a semiconductor top layer; The second dielectric buried layer is formed on the top surface of the semiconductor main layer, the semiconductor middle layer is formed on the top surface of the second dielectric buried layer, the first dielectric buried layer is formed on the top surface of the semiconductor middle layer, and the semiconductor top layer is formed on the top surface of the first dielectric buried layer; The device unit structure includes a MOS transistor and a photosensitive structure; The MOS transistor is formed on the semiconductor top layer, and the channel region of the MOS transistor is composed of the semiconductor top layer; The photosensitive structure includes the semiconductor intermediate layer, the first semiconductor epitaxial layer and the first ohmic contact region; The first semiconductor epitaxial layer passes through the semiconductor top layer and the first dielectric buried layer and contacts the semiconductor middle layer; the first semiconductor epitaxial layer and the semiconductor middle layer both have a lightly doped structure of the second conductivity type; The first ohmic contact region is formed in a surface region of the first semiconductor epitaxial layer and has a heavily doped structure of the second conductivity type; The first ohmic contact region is connected to a first electrode consisting of a front metal layer through a contact hole on the top; A deep trench isolation is further formed on the peripheral side of the device unit structure, and the bottom surface of the deep trench isolation reaches the second dielectric buried layer; A second semiconductor epitaxial layer and a second ohmic contact region are also formed outside the deep trench isolation; The second semiconductor epitaxial layer passes through the semiconductor top layer, the first dielectric buried layer, the semiconductor intermediate layer and the second dielectric buried layer and contacts the semiconductor main layer; the second semiconductor epitaxial layer and the semiconductor main layer both have a lightly doped structure of the second conductivity type; The second ohmic contact region is formed in the surface region of the second semiconductor epitaxial layer and has a heavily doped structure of the second conductivity type; The deep trench isolation and the second dielectric buried layer isolate the photosensitive structure from the second semiconductor epitaxial layer and the semiconductor main layer on the peripheral side, so as to suppress crosstalk between adjacent device unit structures.

2. The photoelectric in-situ active pixel sensor according to claim 1, wherein: The MOS transistor is formed in the first active region; The first active area is located in a surrounding area surrounded by shallow trench isolation or the first active area is located in a surrounding area surrounded by shallow trench isolation and the corresponding deep trench isolation; The bottom surface of the shallow trench isolation reaches the first dielectric buried layer.

3. The photoelectric in-situ active pixel sensor according to claim 2, wherein: The gate structure of the MOS transistor is a planar gate, the gate structure is formed on the top surface of the semiconductor top layer, and the semiconductor top layer covered by the gate structure serves as the channel region; A source region and a drain region heavily doped with the first conductivity type are formed on both sides of the gate structure, and the semiconductor top layer has a lightly doped structure with the second conductivity type.

4. The photoelectric in-situ active pixel sensor according to claim 1, wherein: The number of the MOS transistor in the device unit structure is one.

5. The photoelectric in-situ active pixel sensor according to claim 1, wherein: In an exposure working state, the first electrode is connected to a first depletion voltage, the first depletion voltage causes the semiconductor middle layer and the first semiconductor epitaxial layer of the photosensitive structure to be depleted and form a first depletion region, the first depletion voltage also causes photogenerated carriers of the first conductivity type generated in the first depletion region to be transferred to a first interface between the first dielectric buried layer and the semiconductor middle layer at the bottom of the MOS transistor, and the photogenerated carriers at the first interface cause the threshold voltage of the MOS transistor to change through an interface coupling effect; In a reset state, the first electrode is connected to a second reset voltage for resetting the photogenerated carriers in the first depletion region.

6. The photoelectric in-situ active pixel sensor according to claim 3, wherein: The second ohmic contact region is connected to a second electrode consisting of a front metal layer through a contact hole on the top; The gate structure is connected to the gate composed of the front metal layer through a contact hole on the top; The source region is connected to a source electrode composed of a front metal layer through a contact hole on the top; The drain region is connected to a drain electrode formed by a front metal layer through a contact hole on the top.

7. The photoelectric in-situ active pixel sensor according to claim 3, wherein: The doping concentrations of the second semiconductor epitaxial layer and the semiconductor main layer are both 1E15cm -3 ~1E17cm -3 ; The doping concentrations of the first semiconductor epitaxial layer and the semiconductor intermediate layer are both 1E15 cm -3 ~1E17cm -3 ; The doping concentration of the source region and the drain region is 1E19 cm -3 ~1E21cm -3 ; The doping concentration of the first ohmic contact region and the second ohmic contact region is 1E19 cm -3 ~1E21cm -3 .

8. The photoelectric in-situ active pixel sensor according to any one of claims 1 to 7, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

9. A method for manufacturing a photoelectric in-situ active pixel sensor, characterized in that: The steps include: Step 1: providing a double-buried layer SOI substrate and forming a first semiconductor epitaxial layer and a second semiconductor epitaxial layer in a selected area; The double buried layer SOI substrate comprises: a semiconductor main layer, a second dielectric buried layer, a semiconductor middle layer, a first dielectric buried layer and a semiconductor top layer; The second dielectric buried layer is formed on the top surface of the semiconductor main layer, the semiconductor middle layer is formed on the top surface of the second dielectric buried layer, the first dielectric buried layer is formed on the top surface of the semiconductor middle layer, and the semiconductor top layer is formed on the top surface of the first dielectric buried layer; The first semiconductor epitaxial layer passes through the semiconductor top layer and the first dielectric buried layer and contacts the semiconductor middle layer; the first semiconductor epitaxial layer and the semiconductor middle layer both have a lightly doped structure of the second conductivity type; The second semiconductor epitaxial layer passes through the semiconductor top layer, the first dielectric buried layer, the semiconductor intermediate layer and the second dielectric buried layer and contacts the semiconductor main layer; the second semiconductor epitaxial layer and the semiconductor main layer both have a lightly doped structure of the second conductivity type; Step 2: forming a deep trench isolation on the peripheral side of the device unit structure, wherein the bottom surface of the deep trench isolation reaches the second dielectric buried layer; The second semiconductor epitaxial layer is located outside the deep trench isolation; Step 3: forming a MOS transistor of a device unit structure on the top semiconductor layer; The channel region of the MOS transistor is composed of the semiconductor top layer; Step 4: forming a first ohmic contact region heavily doped with the second conductivity type in the surface region of the first semiconductor epitaxial layer and forming a second ohmic contact region heavily doped with the second conductivity type in the surface region of the second semiconductor epitaxial layer; The photosensitive structure of the device unit structure includes the semiconductor intermediate layer, the first semiconductor epitaxial layer and the first ohmic contact region; The deep trench isolation and the second dielectric buried layer isolate the photosensitive structure from the second semiconductor epitaxial layer and the semiconductor main layer on the peripheral side, so as to suppress crosstalk between adjacent device unit structures; Step 4: forming a contact hole and an electrode composed of a front metal layer, wherein the electrode includes a first electrode connected to the first ohmic contact region through the contact hole.

10. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 9, wherein: Before step 3, it also includes: forming a shallow trench isolation, wherein the bottom surface of the shallow trench isolation reaches the first dielectric buried layer; The MOS transistor is formed in the first active region; The first active region is located in a surrounding region surrounded by the shallow trench isolation or the first active region is located in a surrounding region surrounded by the shallow trench isolation and the corresponding deep trench isolation.

11. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 10, wherein: Step 3 includes the following sub-steps: forming a gate structure of the MOS transistor, wherein the gate structure is a planar gate, the gate structure is formed on the top surface of the semiconductor top layer, and the semiconductor top layer covered by the gate structure serves as the channel region; the semiconductor top layer has a lightly doped structure of the second conductivity type; A source region and a drain region heavily doped with the first conductivity type are simultaneously formed on both sides of the gate structure. The doping type of the source region is the same as that of the channel region and is opposite to that of the channel region.

12. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 9, wherein: The number of the MOS transistor in the device unit structure is one.

13. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 9, wherein: In an exposure working state, the first electrode is connected to a first depletion voltage, the first depletion voltage causes the semiconductor middle layer and the first semiconductor epitaxial layer of the photosensitive structure to be depleted and form a first depletion region, the first depletion voltage also causes photogenerated carriers of the first conductivity type generated in the first depletion region to be transferred to a first interface between the first dielectric buried layer and the semiconductor middle layer at the bottom of the MOS transistor, and the photogenerated carriers at the first interface cause the threshold voltage of the MOS transistor to change through an interface coupling effect; In a reset state, the first electrode is connected to a second reset voltage for resetting the photogenerated carriers in the first depletion region.

14. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 11, wherein: In step 4, the electrode formed by the front metal layer further includes: a second electrode, a gate electrode, a source electrode, and a drain electrode; The second ohmic contact region is connected to the second electrode through a contact hole at the top; The gate structure is connected to the gate through a contact hole at the top; The source region is connected to the source electrode through a contact hole at the top; The drain region is connected to the drain electrode through a contact hole at the top.

15. The method for manufacturing a photoelectric in-situ active pixel sensor according to claim 11, wherein: The doping concentrations of the second semiconductor epitaxial layer and the semiconductor main layer are both 1E15cm -3 ~1E17cm -3 ; The doping concentrations of the first semiconductor epitaxial layer and the semiconductor intermediate layer are both 1E15 cm -3 ~1E17cm -3 ; The doping concentration of the source region and the drain region is 1E19 cm -3 ~1E21cm -3 ; The doping concentration of the first ohmic contact region and the second ohmic contact region is 1E19 cm -3 ~1E21cm -3 .

16. The method for manufacturing a photoelectric in-situ active pixel sensor according to any one of claims 9 to 15, wherein: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

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