A VLSI layered routing method and system based on dynamic programming

Abstract

This invention discloses a VLSI layered routing method and system based on dynamic programming, comprising the following steps: establishing a corresponding net border for each net and obtaining the weighted center of each net border; dividing the routing area into n strip regions according to the position of the weighted center of each net border and arranging them; making a decision on the layering of the nets in each strip region according to the arrangement order of the strip regions to obtain the layered routing decision. The above technical solution performs layered routing through nets, makes decisions on net layering, reduces the number of components of the same net being routed across different layers, avoids interference between layers, and reduces routing difficulty; making decisions on the routing layer of the nets in each strip region according to the arrangement order of the strip regions makes the layering more orderly and clear, simplifying the routing complexity of VLSI.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a VLSI layered routing method and system based on dynamic programming. Background Technology

[0002] In Very Large Scale Integration (VLSI) design, routing aims to achieve physical connections between various modules within a defined routing area. It is a crucial step in VLSI physical design, with the most critical step being determining the layer on which each component's routing should reside. In VLSI design, each metal layer has regularly arranged routing tracks. Actual routing must occur within these tracks, satisfying DRC constraints such as linewidth and spacing.

[0003] See patent application CN 116108778 A for a component layering method, apparatus, and medium for digital circuit schematics. This method layers components in a preprocessed netlist based on signal depth, determining the routing level of a component by the depth of the traversal path. For components with multiple traversal paths, the deepest depth is determined as the routing level. Component layering can indeed improve the readability of digital circuit schematics and reduce pin alignment and crossing issues during routing. However, it also increases the complexity of circuit design, especially for larger-scale circuit designs, requiring more time and effort to plan and adjust the layout of each layer and ensure correct connections and signal transmission between layers. It also increases the difficulty of routing, as routing engineers need to interweave routing between different layers, considering connections and signal transmission between layers, and avoiding interference between layers. Summary of the Invention

[0004] Therefore, a VLSI layered routing method based on dynamic programming is needed to solve the problems of high routing complexity and difficulty in existing VLSI systems.

[0005] To achieve the above objectives, this invention provides a VLSI layered routing method based on dynamic programming, which includes the following steps:

[0006] Create a corresponding mesh border for each mesh and obtain the weighted center of each mesh border;

[0007] Based on the position of the weighted center of each wire mesh border, the wiring area is divided into n strip regions and arranged as S1, ..., Si, ..., Sn, where i and n are positive integers, 1≤i≤n;

[0008] The decision on layered cabling is made by layering the wire mesh in each strip area according to the arrangement order of the strip areas.

[0009] Furthermore, the step of establishing a corresponding mesh border for each mesh and calculating the weighted center of each mesh border includes the following steps:

[0010] Create a net border that surrounds all pins in the net based on the pin coordinates of the components within the net;

[0011] Define a point in the wireframe such that the sum of the distances from that point to all pins is minimized; this point is the weighted center of the wireframe.

[0012] Furthermore, the wire mesh border is the smallest area that surrounds all the pins in the wire mesh.

[0013] Furthermore, the wire mesh border is aligned with the wiring channel.

[0014] Further, the step of dividing the wiring area into several strip regions based on the position of the weighted center of each wire mesh border, and arranging them as S1, ..., Si, ..., Sn, where i and n are positive integers, 1 ≤ i ≤ n, includes the following steps:

[0015] Based on the coordinates of the weighted center of all wireframe borders, the wiring area is divided into n strip regions by the horizontal coordinate of the weighted center of the wireframe border. The n strip regions are arranged and denoted as S1, ..., Si, ..., Sn.

[0016] Furthermore, the n strip regions are arranged in ascending order of their horizontal coordinates, denoted as S1, ..., Si, ..., Sn.

[0017] Furthermore, the step of making decisions on the layered wiring of each strip region according to the arrangement order of the strip regions to obtain the layered wiring decision includes the following steps:

[0018] In making decisions for the strip region Si, all possible routing layers for the strip region Si are enumerated. Among the enumerated routing layers, the routing layer with the least intersection with the total area of ​​the net border of the routing layers that have been allocated to the first i-1 strip regions is selected as the routing layer for the strip region Si, and the decision is denoted as Xi.

[0019] Decision Xi is incorporated into decision chain Ti-1 formed by the first i-1 strip regions to form decision chain Ti;

[0020] Until all the bar regions have been decided, forming the final decision chain Tn;

[0021] The decision chain Tn is the hierarchical wiring decision.

[0022] Furthermore, the step of enumerating all possible routing layers for the strip region Si in the decision-making process, and selecting the routing layer with the least intersection area with the total net border area of ​​the routing layers that have been allocated to the previous i-1 strip regions as the routing layer for the strip region Si, denoted as Xi, further includes the following steps:

[0023] Arrange all the wire meshes within the strip region Si;

[0024] The nets within the strip region Si are assigned sequentially according to the arrangement order. All possible routing layers of the current net within the strip region Si are enumerated. Among the enumerated routing layers, the routing layer with the smallest intersection area with the net border of the routing layer of the routing layer of the previous i-1 strip regions that has been assigned nets and the net border of the routing layer of the current strip region Si that has been assigned nets is selected as the routing layer of the current net.

[0025] The process continues until all the wire meshes within the strip region Si are allocated, forming a decision denoted as Xi.

[0026] Furthermore, based on the coordinates of the weighted centers of all the wireframe borders within the strip region Si, the weighted centers of the wireframe borders are arranged from largest to smallest according to their vertical coordinates.

[0027] A VLSI layered routing system based on dynamic programming, implementing the steps of the aforementioned VLSI layered routing method based on dynamic programming.

[0028] Unlike existing technologies, the above-mentioned technical solution uses a net-like approach for layered routing. It makes decisions regarding net layering, reducing the need for components on the same net to be interleaved between different layers, avoiding interference between layers, and reducing routing complexity. The weighted center of the net border is used to find the center point shortest to each pin. By determining the weighted center of the net, the routing area is better divided and planned, making signal transmission more efficient and reliable. Furthermore, the routing layer of the net in each strip region is decided according to the arrangement order of the strip regions, making the layering more orderly and clear. Separating nets in strip regions of different orders decomposes the net layering into multiple relatively independent sub-problems, simplifying the difficulty and complexity of layer planning, reducing interference between nets, increasing the overall density of net routing, and allowing for optimization according to specific needs, thus simplifying the routing complexity of VLSI. Attached Figure Description

[0029] Figure 1 This is a flowchart of a VLSI layered routing method based on dynamic programming according to the present invention;

[0030] Figure 2This is a diagram of the wireframe structure of a VLSI layered routing method based on dynamic programming according to the present invention.

[0031] Figure 3 This is a diagram illustrating the routing region partitioning structure of a VLSI layered routing method based on dynamic programming according to the present invention.

[0032] Figure 4 This is a flowchart illustrating a VLSI layered routing method based on dynamic programming according to the present invention.

[0033] Explanation of reference numerals in the attached figures:

[0034] 10. Mesh border;

[0035] 101. Pin;

[0036] 102. Weighted center of the mesh border. Detailed Implementation

[0037] To explain in detail the technical content, structural features, objectives, and effects of the technical solution, the following description is provided in conjunction with specific embodiments and accompanying drawings.

[0038] In this document, the term "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The term "embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment, nor does it specifically limit its independence or connection with other embodiments. In principle, in this application, as long as there are no technical contradictions or conflicts, the technical features mentioned in each embodiment can be combined in any way to form corresponding implementable technical solutions.

[0039] Unless otherwise defined, the technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the use of related terms herein is merely for the purpose of describing particular embodiments and is not intended to limit this application.

[0040] In the description of this application, the term "and / or" is used to describe the logical relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A exists, B exists, and A and B exist simultaneously. Additionally, the character " / " in this document generally indicates that the preceding and following objects have an "or" logical relationship.

[0041] In this application, terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any actual quantity, hierarchy or order relationship between these entities or operations.

[0042] Unless otherwise specified, the use of terms such as “comprising,” “including,” “having,” or other similar expressions in this application is intended to cover non-exclusive inclusion, which does not exclude the presence of additional elements in a process, method, or product that includes the stated elements, such that a process, method, or product that includes a list of elements may include not only those defined elements but also other elements not expressly listed, or elements inherent to such a process, method, or product.

[0043] Similar to the interpretation in the Patent Examination Guidelines, in this application, expressions such as "greater than," "less than," and "exceeding" are understood to exclude the stated number; expressions such as "above," "below," and "within" are understood to include the stated number. Furthermore, in the description of the embodiments in this application, "multiple" means two or more (including two), and similar expressions related to "multiple" are also interpreted in this way, such as "multiple groups" and "multiple times," unless otherwise explicitly specified.

[0044] In the description of the embodiments of this application, the space-related expressions used, such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "vertical," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," indicate the orientation or positional relationship based on the orientation or positional relationship shown in the specific embodiments or drawings. They are only for the purpose of describing the specific embodiments of this application or for the reader's understanding, and do not indicate or imply that the device or component referred to must have a specific position, a specific orientation, or be constructed or operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0045] Unless otherwise expressly specified or limited, the terms "installation," "connection," "linking," "fixing," and "setting," as used in the description of the embodiments of this application, should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two components or the interaction between two components. For those skilled in the art to which this application pertains, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0046] See Figures 1-4 As shown, this invention provides a VLSI layered routing method based on dynamic programming, which includes the following steps:

[0047] S1. Establish the corresponding mesh border 10 for each mesh and obtain the weighted center 102 of each mesh border;

[0048] S2. Based on the position of the weighted center 102 of each wire mesh border, divide the wiring area into n strip regions and arrange them as S1, ..., Si, ..., Sn, where i and n are positive integers, 1≤i≤n;

[0049] S3. Make decisions on the layered cabling of each strip area according to the arrangement order of the strip areas to obtain the layered cabling decision.

[0050] The aforementioned net refers to a set of line segments representing the connection relationships between components, used to describe the signal transmission path and connection method in a circuit. The aforementioned net border 10 is used to define the boundary frame of the net's routing area. Typically, the routing area of ​​the net is defined as a rectangular or other shaped region. The net border 10 defines the size and shape of the net's routing, ensuring that the routing of the net takes place within the net border 10, avoiding interference or overlap with other nets; that is, the net border 10 is a boundary frame formed by enclosing all pins 101 of the net based on the coordinates of the pins 101 of the components within the net. The weighted center 102 of the aforementioned net border is located in the middle of the net border 10 and is used to divide the wiring area. In some embodiments, a point can be defined in the net border 10 such that the sum of the distances from this point to all pins 101 is minimized. This point is the weighted center 102 of the net border, meaning that the weighted center 102 of the net border is the center of all pins 101 within the net. Specifically, this can be achieved through the following steps: traversing each pin 101 within the net to obtain the coordinates of each pin 101; traversing all points within the net border 10, for each... For each pin 101, calculate the distance between it and the point (using distance metrics such as Euclidean distance or Manhattan distance). Then, sum the distances from each pin 101 to the point to obtain the sum of all distances from pin 101 to the point. Repeat this process until the sum of all distances from pin 101 to the point is minimized and no longer significantly changes. This point can be considered the weighted center 102 of the net border. Note that the weighted center 102 of the net border can be any pin 101 or a blank area. The arrangement of the strip regions can be based on the position of the weighted center 102 of each net border, dividing the routing area into n strip regions, arranged from left to right or top to bottom, and deciding on the net layer within each strip region. Alternatively, it can be determined based on specific design requirements and layout constraints, such as prioritizing net configuration constraints, including pre-configuration constraints such as a net being required to be routed on a certain layer or a net being prohibited from being routed on a certain layer.

[0051] The above-mentioned layered routing using nets makes decisions on net layering, reduces the number of components on the same net being routed across different layers, avoids interference between layers, and reduces routing difficulty. The weighted center 102 of the net border is used to find the center point shortest to each pin 101. By determining the weighted center of the net, the routing area is better divided and planned, making signal transmission more efficient and reliable. Simultaneously, the routing layer of the net in each strip region is decided according to the arrangement order of the strip regions, making the layering more orderly and clear. Separating nets in strip regions of different orders decomposes the net layering into multiple relatively independent sub-problems, simplifying the difficulty and complexity of layer planning, reducing interference between nets, increasing the overall density of net routing, and allowing for optimization according to specific needs, thus simplifying the routing complexity of VLSI.

[0052] See Figure 2 As shown, the net border 10 is preferably the smallest area surrounding all pins 101 in the net. This smallest area can be determined by using a minimum bounding rectangle algorithm to determine the size and shape of the net border 10, ensuring it tightly surrounds all pins 101, minimizing the area of ​​the wiring region, providing more available space for other net layouts and wiring elements, reducing the distance between nets, and simultaneously reducing crosstalk and mutual interference between signal lines, improving signal integrity and anti-interference capabilities, and enhancing wiring efficiency and reliability. Preferably, the net border 10 is aligned with the wiring channel. Aligning the net border 10 with the wiring channel provides a clear boundary, making wiring and maintenance more convenient, while reducing the length and path of signal lines, thereby reducing signal transmission delay and power consumption, and improving signal integrity and system performance.

[0053] See Figure 3 As shown, the above steps, which divide the wiring area into several strip regions based on the position of the weighted center 102 of each wire mesh border and arrange them as S1, ..., Si, ..., Sn, where i and n are positive integers and 1 ≤ i ≤ n, include the following steps:

[0054] Based on the coordinates of the weighted center 102 of all wireframe borders, the wireframe border weighted center 102 is used to divide the wiring area into n strip regions according to the horizontal coordinate. The n strip regions are arranged and denoted as S1, ..., Si, ..., Sn.

[0055] The above-described division of the wiring area into n strip regions based on the horizontal coordinate of the weighted center 102 of the net border refers to assigning the weighted centers 102 of net borders with the same horizontal coordinate to the same strip region, and assigning the weighted centers 102 of net borders with different horizontal coordinates to different strip regions. By dividing the wiring area into n strip regions, wiring space can be utilized more effectively. Each strip region can accommodate at least one set of net borders 10. By closely arranging nets with the same horizontal coordinate, the occupancy of the wiring area can be minimized, improving the utilization rate of wiring space. At the same time, the distance between adjacent net borders 10 can be shortened, reducing the length and path of signal lines, thereby reducing signal transmission delay and power consumption, and improving signal integrity and system performance. Furthermore, it can reduce wiring clutter and conflicts, improve wiring efficiency and accuracy, and contribute to improving the performance, reliability, and maintainability of circuit design.

[0056] See Figure 3 As shown, the arrangement of the above n bar regions prepares for the subsequent decision-making on the layering of the wire mesh within each bar region. The order of arrangement affects the decision-making order for the layering of the bar regions. The arrangement order can be based on the priority of the wire mesh configuration constraints, or it can be based on the magnitude of the horizontal coordinates of the bar regions. For example, the n bar regions can be arranged in ascending order of their horizontal coordinates, denoted as S1, ..., Si, ..., Sn. Making decisions on the layering of the wire mesh within the bar regions in sequence makes the layering more orderly and clear. Separating the wire mesh layers within bar regions of different sequences allows the layering to be decomposed into multiple relatively independent sub-problems, simplifying the difficulty and complexity of the layering planning.

[0057] The above steps for making decisions on the layered cabling of each strip region according to the arrangement order of the strip regions, and obtaining the layered cabling decision, include the following steps:

[0058] In making decisions for strip region Si, all possible routing layers for strip region Si are enumerated. Among the enumerated routing layers, the routing layer with the least intersection area with the routing layers of the first i-1 strip regions that have already been allocated wire meshes is selected as the routing layer for strip region Si, and the decision is denoted as Xi.

[0059] Decision Xi is incorporated into decision chain Ti-1 formed by the first i-1 strip regions to form decision chain Ti;

[0060] Until all the bar regions have been decided, forming the final decision chain Tn;

[0061] The decision chain Tn is the hierarchical wiring decision.

[0062] The above method selects the wiring layer with the least intersection area with the wiring layers that have already been allocated wire meshes in the enumerated wiring layers as the wiring layer for the strip region Si. This can reduce signal interference and crosstalk between different layers and improve the signal transmission quality and reliability.

[0063] The above-mentioned step of making a decision on the strip region Si, which involves enumerating all possible routing layers for the strip region Si and selecting the routing layer with the least intersection area with the total area of ​​the net border 10 of the routing layers that have already been allocated nets in the previous i-1 strip regions, as the routing layer for the strip region Si, and denoted as Xi, further includes the following steps:

[0064] Arrange all the wire meshes within the strip region Si;

[0065] The nets within the strip region Si are allocated sequentially according to the arrangement order. All possible layers of the current net within the strip region Si are enumerated. Among the enumerated routing layers, the routing layer with the least intersection area with the net border 10 of the routing layers of the previous i-1 strip regions that have already allocated nets and the net border 10 of the routing layers of the current strip region Si is selected as the routing layer of the current net.

[0066] The process continues until all the wire meshes within the strip region Si are allocated, forming a decision denoted as Xi.

[0067] Similarly, in the enumerated routing layers, the routing layer whose total area intersects the routing layer with the routing layer with the net border 10 of the routing layer with the net already allocated in the previous i-1 strip regions and the routing layer with the net already allocated in the current strip region Si is selected as the routing layer of the current net. This can reduce signal interference and crosstalk between different layers and improve the signal transmission quality and reliability.

[0068] The sorting of the wire meshes within the aforementioned strip region Si is to prepare for subsequent decisions on the layering of all wire meshes within Si. The order of arrangement affects the decision-making order for all wire mesh layering within region Si. This arrangement can be based on the priority of wire mesh configuration constraints or on the magnitude of the vertical coordinates of the strip region. For example, based on the coordinates of the weighted centers 102 of all wire mesh borders within strip region Si, the weighted centers 102 of the wire mesh borders can be arranged from largest to smallest vertical coordinate. Making decisions on the layering of all wire meshes within strip region Si in sequence makes the layering more orderly and clear. Layering wire meshes of different sequences within the same sequence strip region separately decomposes the wire mesh layering into multiple relatively independent sub-problems, simplifying the difficulty and complexity of layering planning.

[0069] A VLSI layered cabling system based on dynamic programming is provided, implementing the steps of the aforementioned VLSI layered cabling method based on dynamic programming. This system can be adjusted according to specific layering requirements and constraints, flexibly adapting to different design scenarios and layering needs, thereby improving the quality, efficiency, and flexibility of layering.

[0070] It should be noted that although the above embodiments have been described herein, this does not limit the scope of patent protection of the present invention. Therefore, any changes and modifications made to the embodiments described herein based on the innovative concept of the present invention, or equivalent structural or procedural transformations made using the content of the present invention's specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included within the scope of patent protection of the present invention.

Claims

1. A dynamic programming based VLSI hierarchical routing method characterized by, The method comprises the following steps: According to the position of the weighted center of each wire net frame, the wiring area is divided into n strip areas, and the strip areas are arranged and recorded as S1, S2, …, Si, …, Sn, wherein i and n are positive integers, and 1≤i≤n; The step of establishing a corresponding wire net frame according to each wire net and calculating the weighted center of each wire net frame comprises the following steps: A point is defined in the wire net frame, and the point is the weighted center of the wire net frame, which is the shortest distance to all the pins in the wire net frame; The step of arranging the wire nets in each strip area according to the arrangement order of the strip areas and making a decision on the layering of the wire nets to obtain a layering wiring decision comprises the following steps: In the decision-making of the wire nets in the strip area Si, all possible wiring layers of the wire nets in the strip area Si are enumerated, and the wiring layer that intersects the total area of the wire net frames of the wiring layers of the wire nets in the first i-1 strip areas and the wiring layers of the wire nets that have been allocated in the strip area Si is the least is selected as the wiring layer of the strip area Si, and the decision is recorded as Xi; The decision Xi is incorporated into the decision chain Ti-1 of the first i-1 strip areas to form a decision chain Ti; Until all the strip areas have been decided, the final decision chain Tn is formed; The decision chain Tn is the layering wiring decision. The wire net frame is the smallest area that surrounds all the pins in the wire net. The wire net frame is aligned to the wiring channel. The step of dividing the wiring area into strip areas according to the position of the weighted center of each wire net frame and arranging the strip areas recorded as S1, S2, …, Si, …, Sn, wherein i and n are positive integers, and 1≤i≤n, comprises the following steps:

2. The dynamic programming based VLSI hierarchical routing method according to claim 1, wherein, According to the coordinates of the weighted centers of all wire net frames, the wiring area is divided into n strip areas according to the horizontal coordinates of the weighted centers of the wire net frames, and the n strip areas are arranged and recorded as S1, S2, …, Si, …, Sn.

3. The dynamic programming based VLSI hierarchical routing method according to claim 1, wherein, The n strip areas are arranged in ascending order of horizontal coordinates and recorded as S1, S2, …, Si, …, Sn.

4. The dynamic programming based VLSI hierarchical routing method according to claim 1, wherein, The step of enumerating all possible wiring layers of the wire nets in the strip area Si, selecting the wiring layer that intersects the total area of the wire net frames of the wiring layers of the wire nets in the first i-1 strip areas and the wiring layers of the wire nets that have been allocated in the strip area Si as the least in the enumerated wiring layers as the wiring layer of the strip area Si, and recording the decision as Xi further comprises the following steps: The wire nets in the strip area Si are arranged; 5. The dynamic programming based VLSI hierarchical routing method according to claim 4, wherein, The wire nets in the strip area Si are allocated in turn according to the arrangement order, all possible wiring layers of the current wire nets in the strip area Si are enumerated, and the wiring layer that intersects the total area of the wire net frames of the wiring layers of the wire nets in the first i-1 strip areas and the wiring layers of the wire nets that have been allocated in the strip area Si is selected as the wiring layer of the current wire net; 6. The dynamic programming based VLSI hierarchical routing method according to claim 1, wherein, ​ ​ ​ Until all the wire nets in the strip region Si are finished distributing, the decision record is denoted as Xi.

7. The dynamic programming based VLSI hierarchical routing method according to claim 6, wherein, According to the coordinates of the weighted centers of all the wire net borders in the strip region Si, the weighted centers of the wire net borders are arranged in descending order of the longitudinal coordinates.

8. A dynamic programming based VLSI hierarchical routing system, which implements the steps of the dynamic programming based VLSI hierarchical routing method as claimed in any one of claims 1 to 7.

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