A global routing method for analog ICs based on Hanan mesh

Abstract

A global routing method for analog ICs based on Hanan meshes includes: Step 1) Establishing a Hanan mesh based on the vertex coordinates of the layout modules, treating the mesh edges, module edges, and ports of the Hanan mesh as vertices of a graph and establishing connections to generate a graph; Step 2) Generating an initial topology according to the netlist order, using the A* algorithm to find paths on the graph and complete the net connections; Step 3) If the routing success rate of the initial topology cannot be improved after multiple rounds of teardown and rerouting, a topology optimization model is used to predict the routing success rate of the topology to select a better topology for routing. This invention improves the routing success rate of the final global routing scheme for analog ICs by using the A* algorithm for path search on a graph based on Hanan meshes to solve congestion and intersection problems, and by using a topology optimization model to optimize the net topology.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit routing technology, and in particular to a global routing method for analog ICs based on Hanan grids. Background Technology

[0002] Routing is a complex and time-consuming task, and a crucial aspect of IC (Integrated Circuit) design. Global routing networks connect on a coarse-grained mesh graph with capacity constraints, providing a solution for detailed routing. Existing global routers typically use the center point of the Hanan mesh as nodes for pathfinding. However, because the Hanan mesh is non-uniform, with varying spatial resources in the horizontal and vertical directions, it's impossible to accurately predict congestion. Coarse-grained meshes can allow multiple nets to have paths on the same node, presenting not only capacity control issues but also unique intersection problems. Furthermore, topology significantly impacts routing efficiency; a good topology enables routing algorithms to complete routing faster and better, but selecting an optimal topology remains an unresolved issue. Summary of the Invention

[0003] To address the shortcomings of existing technologies, the present invention aims to provide a global routing method for analog ICs based on Hanan grids. This method enables pathfinding on a graph established based on Hanan grids, resolves congestion and crossover issues, optimizes the network topology, and improves the routing success rate of the final global routing solution for analog ICs.

[0004] To achieve the above objectives, the present invention provides a global routing method for analog ICs based on Hanan grids, comprising:

[0005] Step 1) Create a Hanan mesh based on the vertex coordinates of the layout modules, treat the mesh edges, module edges, and ports of the Hanan mesh as vertices of the graph and establish connection relationships to generate the graph;

[0006] Step 2) Generate the initial topology according to the netlist order, and use the A* algorithm to find paths on the graph and complete the net connections;

[0007] Step 3) If the routing success rate of the initial topology cannot be improved after multiple rounds of dismantling and rewiring, then use the topology optimization model to predict the routing success rate of the topology in order to select a better topology for routing.

[0008] Furthermore, step 1) further includes:

[0009] Obtain the vertex coordinates of all modules in the layout, and extend them in the X and Y directions respectively. The extension lines stop when they encounter other modules, forming a Hanan mesh.

[0010] Within the same grid, four edges are connected in pairs; overlapping edges of adjacent grids are connected; overlapping edges of a module edge are connected to overlapping edges of its adjacent grids; and ports are connected to module edges.

[0011] Each connection is weighted by the Euclidean distance between its two endpoints, generating a weighted undirected graph.

[0012] Furthermore, the grid edges of the Hanan grid are assigned a capacity attribute based on their length, representing the maximum number of paths that can be accommodated.

[0013] Further, step 2) further includes: generating an initial topology in sequence according to the netlist information, decomposing the multi-terminal net into two-terminal nets in sequence, and then using the A* algorithm to run the nets on the graph in sequence;

[0014] During the cabling process, the congestion situation is determined by the relationship between the capacity of the grid edge and the capacity required by all the wires running on that grid edge, and the congestion and crossover areas are eliminated through multiple iterations using the cable removal and re-routing technique.

[0015] Furthermore, in step 3), when the routing success rate of the initial topology cannot be improved, the topology is replaced by a topology optimization model for routing, including: randomly generating a new topology, extracting the features of the new topology, using the topology optimization model to predict the routing success rate of the new topology, and routing the topology with a higher predicted value, and randomly generating a new topology again if the predicted value is lower.

[0016] Furthermore, the step of predicting the connectivity of the topology using a topology optimization model further includes:

[0017] By extracting the fly wire length, the existence of the nearest port connection, the existence of the longest port connection, the number of connections of the module with the largest area, the number of connections of the module with the smallest area, and the location of the port in the module for each multi-terminal wire network topology, and quantifying them as topology features, we obtain various feature values.

[0018] The feature values ​​of all topologies of a map are mapped to the final routing rate of that topology. After obtaining a large number of mappings, a linear regression model is trained to obtain the weight of each feature value.

[0019] Based on the weights, after obtaining a new topology, the predicted connectivity of the new topology can be obtained by calculating the feature values ​​of the new topology and multiplying them by the corresponding weights.

[0020] Furthermore, a congestion cost is incorporated into the pathfinding process. The congestion cost is calculated as follows: the capacity value of a vertex in the graph is subtracted from the capacity required by the existing line on the vertex. If the remaining capacity is greater than 0, the congestion cost is 0; otherwise, the remaining capacity is divided by the capacity required by the current network to obtain the congestion cost.

[0021] Furthermore, the pathfinding process incorporates a crossover cost to address situations where crossovers may occur, including: the default inability for horizontal and vertical lines to coexist within a grid; the inability to take two consecutive steps on a path within a grid; determining whether a crossover exists by calculating the difference in the direction of the meeting and separation of two lines that enter the same vertex of the graph and then separate at another vertex; and using the number of crossover lines as the crossover cost of the vertex of the graph once a crossover is determined to exist at a vertex of the graph.

[0022] Furthermore, the pathfinding process incorporates historical costs and employs a dismantling and rewiring technique. In each round, each net is dismantled and rewiring is performed sequentially. Historical costs are set for vertices of the graph that had congestion and intersections in the previous round, so that these vertices can be avoided in the next round of wiring.

[0023] To achieve the above objectives, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to execute the computer program stored in the memory to implement the analog IC global routing method based on Hanan grid as described above.

[0024] To achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program that is loaded and executed by a processor to implement the analog IC global routing method based on Hanan grid as described above.

[0025] The analog IC global routing method based on Hanan grid provided by this invention has the following advantages compared with the prior art:

[0026] A graph based on Hanan grid edges is constructed to reduce the number of path nodes in the search; the A* algorithm is used to find paths on the graph, and the routing rate is improved by solving special congestion and intersection problems; a topology optimization model is adopted to solve the problem that the routing rate cannot be improved due to the poor topology itself.

[0027] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. Attached Figure Description

[0028] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0029] Figure 1 This is a flowchart of a global routing method for analog ICs based on a Hanan grid according to an embodiment of the present invention;

[0030] Figure 2 A graph generated based on a Hanan grid according to an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram illustrating the establishment of connection relationships when creating a graph according to an embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of the cross type according to an embodiment of the present invention;

[0033] Figure 5 A schematic diagram illustrating the method of determining intersection according to an embodiment of the present invention;

[0034] Figure 6 This is a schematic diagram of an electronic device structure according to an embodiment of the present invention. Detailed Implementation

[0035] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0036] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the invention. It should be understood that the accompanying drawings and embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the invention.

[0037] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0038] It should be noted that the concepts of "first" and "second" may be mentioned in this invention only to distinguish different devices, components or parts, and are not used to limit the order of the functions performed by these devices, components or parts or their interdependence.

[0039] It should be noted that the terms "one" and "multiple" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "Multiple" should be understood as two or more.

[0040] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0041] In embodiments of the present invention, a global routing method for analog ICs based on Hanan grids is provided, comprising: establishing a Hanan grid based on the vertex coordinates of the layout modules; generating a graph based on the Hanan grid (a graph is a data structure, which is an undirected graph consisting of a set of vertices and a set of undirected edges connecting the vertices); using the A* algorithm to find paths on the graph and complete the wire connection; training a topology optimization model to predict the routing rate of the topology in order to select a better topology for routing.

[0042] Figure 1 The flowchart of the analog IC global routing method based on Hanan mesh according to an embodiment of the present invention will be referred to below. Figure 1 The embodiments of the present invention will be described in detail.

[0043] First, in step 101, the input data is read to obtain the coordinates of all vertices of the module.

[0044] In step 102, intersecting lines are obtained by extending them to both sides in the X and Y directions, generating a Hanan mesh.

[0045] In steps 101-102, the vertex coordinates of all modules in the layout are obtained, and lines are extended in the X and Y directions respectively. These lines intersect each other and stop extending when they encounter other modules, thus forming a Hanan mesh, as shown below. Figure 2 As shown in (a).

[0046] In step 103, a graph is generated using the Hanan grid.

[0047] In this step, each grid edge, module edge, and port is considered a vertex of the graph. Each vertex has coordinates, which are the coordinates of the center point of the grid edge, module edge, or port. A capacity attribute is assigned to each grid edge based on its length, representing the maximum number of paths that can be accommodated. Four edges within a grid are connected pairwise, and overlapping edges of adjacent grids are also connected, such as... Figure 3 As shown in (a); the module edge establishes a connection with the overlapping edge of its adjacent mesh, as shown in (a). Figure 3 As shown in (b); the Port establishes a connection with the module edge, as shown in (b). Figure 3 As shown in (c). The edges are connected by their midpoints, and the Port and module edges are connected by the center point of the Port and the midpoint of the module edge. Note that, for clarity, Figure 3The spacing between adjacent grid cells has been increased, but the actual spacing between adjacent grid cells is now 0. These connections are weighted by the Euclidean distance between their center points, i.e., the distance cost of the path. For example... Figure 2 As shown in (b), the Hanan grid ultimately generates a weighted undirected graph.

[0048] In embodiments of the present invention, in addition to distance cost, congestion cost needs to be added to the pathfinding process. The calculation method is to subtract the capacity required by the existing line on the graph vertex from the capacity value of the graph vertex. If the remaining capacity is greater than 0, the congestion cost is 0; otherwise, the congestion cost is obtained by dividing the remaining capacity by the current network capacity.

[0049] In step 104, the A* algorithm is used to perform path search on the graph. The graph serves as the map for the A* algorithm search, with graph vertices acting as map points and edge connection weights representing movement costs. The network is connected by finding the path nodes with the lowest costs.

[0050] In the embodiments of the present invention, an initial topology is generated sequentially according to the netlist information. After the multi-end net is decomposed into two-end nets, the A* algorithm is used to run the nets sequentially on the graph. The congestion situation is judged by the relationship between the capacity of the grid edge and the capacity required by all nets running on that grid edge. This solves the problem of cross-jump determination that may occur when different nets run on the same grid edge. Furthermore, the technology of tearing down and re-routing is used to eliminate congested and cross-jumping areas through multiple iterations.

[0051] Each vertex in a graph has a capacity that can accommodate multiple nets simultaneously. If the capacity required by a net exceeds the total capacity of that vertex, the vertex is in a congested state. During an A* search, it should check whether the remaining capacity of the vertex being moved to is sufficient. For vertices with insufficient capacity, a congestion cost should be imposed to limit the movement of A*.

[0052] In addition to congestion, crossover situations can also occur, so the pathfinding process needs to include crossover costs and needs to address situations that may cause crossovers. Figure 4 This is a schematic diagram of the cross type according to an embodiment of the present invention, such as Figure 4 As shown, there are three possible intersection scenarios: The first scenario involves a horizontal line intersecting a vertical line within a grid. The solution is to prevent horizontal and vertical lines from existing simultaneously within the grid. The second scenario involves a vertical line moving within a grid, followed by a horizontal line that doesn't move in a straight line but instead moves two steps along other edges. The solution is to prevent the path from moving twice within a single grid. The third scenario involves two lines meeting at one edge, moving parallel for a distance, and then intersecting at another edge. The solution is to... Figure 5As shown, the direction difference between the meeting and separation of two nets is calculated. If the direction difference is the same, there is no intersection. Otherwise, an intersection will occur. In this case, an intersection cost is set for the edge to be moved in the direction that will cause the intersection, so as to avoid moving in that direction.

[0053] In an embodiment of the present invention, after determining that there is a cross on a graph vertex, the number of cross lines is used as the cross cost of the graph vertex.

[0054] Furthermore, it also includes historical costs. A teardown and rewiring technique is employed, where each network is sequentially dismantled and rewiring in each round. Historical costs are set for graph vertices that experienced congestion and crossovers in the previous round, so that these vertices are avoided as much as possible during the next round of wiring. Therefore, after each round of wiring, historical costs are set for graph vertices in congested and crossover states. During the next round of teardown and rewiring, the A* algorithm incorporates these historical costs when calculating the cost of graph vertices to avoid entering the congested and crossover areas of the previous round.

[0055] In step 105, if the routing success rate cannot be improved, the topology of the multi-terminal network is changed, and a better topology is selected for routing through the trained topology optimization model.

[0056] In embodiments of the present invention, if the connectivity rate still does not improve after multiple rounds of cable removal and redeployment, the topology of the multi-terminal network needs to be changed. The present invention provides a topology optimization model: by extracting the flywire length, the presence or absence of the nearest port connection, the presence or absence of the longest port connection, the number of connections of the module with the largest area, the number of connections of the module with the smallest area, and the location of the port in each multi-terminal network topology as features of the topology, and quantifying these features to obtain individual feature values; mapping the feature values ​​of all topologies in a layout to the final connectivity rate of that topology, after obtaining a large number of correspondences, a linear regression model is trained to obtain the weight of each feature value; based on the obtained weights, after obtaining a new topology, the connectivity rate of the new topology is predicted by multiplying the feature values ​​of the new topology by their corresponding weights.

[0057] The current topology is optimized through multiple rounds of iterative optimization by tearing down and redistributing cables, and a routing success rate is obtained in each round. If the routing success rate does not improve in each round of iteration, a new topology is randomly generated. The routing success rate is predicted by the topology optimization model to determine whether to use this topology for routing. If the predicted value is higher, routing is performed; if the predicted value is lower, a new topology is randomly generated again.

[0058] In embodiments of the present invention, an electronic device is also provided. Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention, such as... Figure 6 As shown, the electronic device of the present invention includes a processor 601 and a memory 602, wherein,

[0059] The memory 602 stores a computer program, which, when read and executed by the processor 601, performs the steps described above in the embodiment of the analog IC global routing method based on Hanan grid.

[0060] In embodiments of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to execute the steps described above in the embodiments of the analog IC global routing method based on Hanan mesh.

[0061] In this embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0062] It will be understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A global routing method for analog ICs based on Hanan meshes, characterized in that, include: Step 1) Create a Hanan mesh based on the vertex coordinates of the layout modules, treat the mesh edges, module edges, and ports of the Hanan mesh as vertices of the graph and establish connection relationships to generate the graph; Step 2) Generate the initial topology according to the netlist order, and use the A* algorithm to find paths on the graph and complete the net connections; Step 3) If the routing success rate of the initial topology cannot be improved after multiple rounds of dismantling and rewiring, then use the topology optimization model to predict the routing success rate of the topology in order to select a better topology for routing. The step of generating a graph by treating the mesh edges, module edges, and ports of the Hanan mesh as vertices of the graph and establishing connections between them includes: The grid edges of the Hanan grid are assigned a capacity property based on their length, representing the maximum number of paths that can be accommodated. Within the same grid, four edges are connected in pairs; overlapping edges of adjacent grids are connected; overlapping edges of a module edge are connected to the adjacent grid edge; and ports are connected to module edges. Among these, the connection between edges is made at the midpoint of the edge, and the connection between a port and a module edge is made at the center point of the port and the midpoint of the module edge. Each connection is weighted by the Euclidean distance between its two endpoints, generating a weighted undirected graph.

2. The analog IC global routing method based on Hanan mesh according to claim 1, characterized in that, Step 1) further includes: Obtain the vertex coordinates of all modules in the layout, and extend them in the X and Y directions respectively. The extension lines stop when they encounter other modules, forming a Hanan mesh.

3. The analog IC global routing method based on Hanan grid according to claim 1, characterized in that, Step 2) further includes: generating an initial topology in sequence according to the netlist information; after decomposing the multi-terminal net into two-terminal nets in sequence, routing the nets on the graph in sequence using the A* algorithm; During the cabling process, the congestion situation is determined by the relationship between the capacity of the grid edge and the capacity required by all the wires running on that grid edge, and the congestion and crossover areas are eliminated through multiple iterations using the cable removal and re-routing technique.

4. The analog IC global routing method based on Hanan mesh according to claim 1, characterized in that, Step 3) When the routing success rate of the initial topology cannot be improved, the topology is replaced by a topology optimization model for routing. This includes: randomly generating a new topology, extracting the features of the new topology, using the topology optimization model to predict the routing success rate of the new topology, and routing the topology with a higher predicted value. If the predicted value is lower, a new topology is randomly generated again.

5. The analog IC global routing method based on Hanan mesh according to claim 1, characterized in that, The step of predicting the connectivity of the topology using a topology optimization model further includes: By extracting the fly wire length, the existence of the nearest port connection, the existence of the longest port connection, the number of connections of the module with the largest area, the number of connections of the module with the smallest area, and the location of the port in the module for each multi-terminal wire network topology, and quantifying them as topology features, we obtain various feature values. The feature values ​​of all topologies of a map are mapped to the final routing rate of that topology. After obtaining a large number of mappings, a linear regression model is trained to obtain the weight of each feature value. Based on the weights, after obtaining a new topology, the predicted connectivity of the new topology can be obtained by calculating the feature values ​​of the new topology and multiplying them by the corresponding weights.

6. The analog IC global routing method based on Hanan mesh according to claim 1, characterized in that, The pathfinding process incorporates a congestion cost, which is calculated as follows: the capacity value of a vertex in the graph is subtracted from the capacity required by the existing lines on that vertex. If the remaining capacity is greater than 0, the congestion cost is 0; otherwise, the remaining capacity is divided by the capacity required by the current network to obtain the congestion cost.

7. The analog IC global routing method based on Hanan mesh according to claim 1, characterized in that, The pathfinding process incorporates a cross-cost to address situations where cross-costs may occur, including: the inability of horizontal and vertical lines to coexist within the default grid; the inability to take two consecutive steps on a path within a grid; determining whether a cross-cost exists by calculating the difference in the direction of the meeting and separation of two lines that enter the same vertex of the graph and then separate at another vertex; and using the number of cross-cost lines as the cross-cost of the vertex of the graph once a cross-cost is determined at a vertex of the graph.

8. The analog IC global routing method based on Hanan mesh according to claim 1, characterized in that, The pathfinding process incorporates historical costs and employs a dismantling and rewiring technique. In each round, each net is dismantled and rewiring is performed sequentially. Historical costs are set for vertices of the graph that had congestion and intersections in the previous round, so that these vertices can be avoided in the next round of wiring.

9. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which is loaded and executed by a processor to implement the analog IC global routing method based on Hanan grid as described in any one of claims 1-8.

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