A two-stage reliability enhancement circuit and response generation method suitable for a response feedback PUF

Abstract

This invention belongs to the field of hardware security technology and discloses a two-stage reliability enhancement circuit and response generation method suitable for Response Feedback Authentication Function (APUF). It includes a delay difference detection circuit and a majority voting circuit. The delay difference detection circuit comprises two identical additional delay modules symmetrically arranged vertically and three arbitrators. The two additional delay modules are respectively connected to the upper and lower delay chains of the APUF and are composed of multiple inverters connected in series. The delay difference between the delay modules is changed by altering the number of inverters. The three arbitrators are used to generate three different responses. The majority voting circuit includes a counter, initially set to 0, which increments by 1 when the APUF response is "1". This invention filters the APUF response delay during the feedback phase, only feeding back responses with larger delay differences. Compared to a pure voting method, this reduces the number of majority votes required for reliability enhancement and improves the efficiency of the authentication protocol.

Description

Technical Field

[0001] This invention belongs to the field of hardware security technology, and in particular relates to a two-stage reliability enhancement circuit and response generation method suitable for response feedback PUF. Background Technology

[0002] Strong Physical Unclonable Functions (PUFs) offer advantages over traditional cryptography, such as lightweight implementation and ease of use, making them a hot research topic for building secure, lightweight, and efficient IoT authentication protocols. Arbiter PUFs (APUFs) are currently one of the mainstream strong PUFs used to build IoT authentication protocols. However, attackers can exploit public information transmission channels and inherent vulnerabilities in strong PUFs to launch various malicious attacks, such as machine learning modeling attacks, thereby threatening IoT security.

[0003] To enhance the nonlinearity between strong PUF excitation and response and improve its resistance to machine learning modeling attacks, researchers have mainly focused on improving the structural nonlinearity of the PUF itself, combining multiple PUFs, and obfuscating the PUF excitation and response. Among these, response feedback, a recently emerging method to improve the nonlinearity and randomness of PUFs, offers advantages such as low hardware resource consumption and resistance to reverse engineering attacks, at the cost of increased response generation time. Reliability is one of the fundamental characteristics of PUFs, determining whether they can stably generate the same response under different environments. Good reliability is a prerequisite for the practicality of PUFs. Increasing the number of response feedbacks increases the nonlinearity of the PUF circuit; however, since the APUF response is not 100% reliable, the introduced noise also increases, making it difficult to guarantee the reliability of the final PUF response.

[0004] Error checking code algorithms based on help data are a widely used response post-processing method. However, this algorithm itself consumes a large amount of hardware resources, and the help data requires non-volatile memory, resulting in prohibitive hardware costs. In addition, majority voting is a common method to improve the reliability of strong PUFs. Its hardware circuit is a counter; when the response is "1", the count value is incremented by 1. By repeatedly evaluating strong PUF responses, the response with the highest frequency is selected, thus filtering out noise. When the introduced noise is small, this method can achieve high reliability with a reasonable number of votes. However, when too much noise is introduced, the number of votes becomes very large, and the response generation time also increases. Bit self-checking is a recently proposed reliable response screening method for APUFs; however, it requires three cycles to generate a single-bit reliable response, increasing authentication time and reducing authentication efficiency. Therefore, how to improve the reliability of response feedback PUFs while simultaneously improving the efficiency of the authentication protocol requires further research. Summary of the Invention

[0005] The purpose of this invention is to provide a two-stage reliability enhancement circuit and response generation method suitable for response feedback PUF, so as to solve the above-mentioned technical problems.

[0006] To address the challenges of improving the reliability of PUF (Power Response Function) responses and the resulting decrease in authentication efficiency, this invention proposes a two-stage reliability enhancement circuit. This circuit improves the reliability of strong PUF responses while reducing the number of majority votes, thereby reducing authentication time and increasing authentication efficiency.

[0007] The specific technical solution of the two-stage reliability enhancement circuit and response generation method applicable to response feedback PUF of the present invention is as follows:

[0008] A two-stage reliability enhancement circuit for a response feedback PUF includes a delay difference detection circuit and a majority voting circuit. The delay difference detection circuit includes two identical additional delay modules symmetrically arranged above and below the APUF and three arbitrators. The two additional delay modules are respectively connected to the upper and lower delay chains of the APUF and are composed of multiple inverters connected in series. The delay difference between the delay modules is changed by changing the number of inverters. The three arbitrators are used to generate three different responses. The majority voting circuit includes a counter. The initial value of the counter is 0. When the APUF response is "1", the counter is incremented by 1.

[0009] Furthermore, the arbitrator includes Arbitrator 1, Arbitrator 2, and Arbitrator 3. Arbitrator 1 is connected to the APUF original path and generates the APUF original response r1. Arbitrator 2 is connected to the upper additional delay module and the lower original path of APUF and generates the delay difference detection response r2. Arbitrator 3 is connected to the lower additional delay module and the upper original path of APUF and generates the delay difference detection response r3.

[0010] Furthermore, in most voting circuits, if the counting result is greater than half of the counting count, the voting result is "1"; otherwise, it is "0". When performing response obfuscation, its input is the XOR result of the delay difference detection responses r2 and r3. When generating the final response, its input is the APUF original response r1.

[0011] This invention also discloses a response generation method for a two-stage reliability enhancement circuit suitable for a response feedback PUF, including an obfuscation stage and a final response generation stage. In the obfuscation stage, the delay difference detection responses r2 and r3 are XORed and input into a majority voting circuit for m votes. If the voting result is "1", it indicates that the original response has high reliability and can be fed back to the excitation side; if the voting result is "0", it indicates that the original response has low reliability and the previous reliable response is fed back to the excitation side. In the final response generation stage, the original APUF response is input into the majority voting circuit for m votes to improve the reliability of the final response.

[0012] Furthermore, according to the APUF response generation principle, when the delay difference is greater than 0, the response is "1"; when the delay difference is less than 0, the response is "0". Let the delay of the upper link of the APUF be D1, the delay of the lower link be D2, and the delay of the additional delay unit be ΔD. If r2 and r3 have the same sign, then their delay difference is greater than 0. Further, let the original delay of the upper path of the APUF be D1, and the original delay of the lower path be D2. Arbitrator 1 generates the original response r1, with a corresponding delay difference of D1-D2. Assuming the delay of the additional delay module is ΔD, the upper path delay is D1+ΔD. Arbitrator 2 generates the response r2, with a corresponding delay difference of D1+ΔD-D2. The lower path delay is D2+ΔD. Arbitrator 3 generates the response r3, with a corresponding delay difference of...

[0013] D1-D2-ΔD,

[0014] If both r2 and r3 are greater than 0, then:

[0015]

[0016] If both r2 and r3 are less than 0, then:

[0017]

[0018] Therefore, when r2 and r3 have the same sign, the absolute value of the delay difference between the upper and lower paths of the APUF is greater than ΔD, and the delay difference corresponding to the original response r1 will be fed back to the excitation side. If r2 and r3 have opposite signs, they will be discarded.

[0019] Furthermore, in the response feedback confusion stage, the XOR result of the delay difference detection responses r2 and r3 is input into the majority voting circuit for m votes. The voting result is the reliability flag rf. If rf is 1, the reliability of the original response r1 is high enough, and it will participate in the feedback; if rf is 0, the reliability of the original response r1 is not high enough, and the previous reliable response will participate in the feedback. The initial value of the feedback bit is 0. In the final response generation stage, the response is input into the majority voting circuit for m votes to generate the final response R.

[0020] The two-stage reliability enhancement circuit and response generation method applicable to response feedback PUF of the present invention have the following advantages:

[0021] Because this invention filters APUF response delays during the feedback phase, only feeding back responses with large delay differences, it reduces the number of majority votes required to improve reliability compared to the pure voting method, thus improving the efficiency of the authentication protocol. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the delay difference detection circuit structure of the present invention;

[0023] Figure 2 This is a schematic diagram of the two-stage reliability enhancement circuit structure of the present invention;

[0024] Figure 3 This is a schematic diagram of the noise area of ​​the present invention. Detailed Implementation

[0025] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides a two-stage reliability enhancement circuit and response generation method applicable to response feedback PUF.

[0026] This invention provides a two-stage reliability enhancement circuit suitable for response feedback PUF, comprising a delay difference test circuit (DDTC) and a majority voting circuit.

[0027] The delay difference detection circuit includes two identical additional delay modules symmetrically arranged vertically and three arbiters. The two additional delay modules are connected to the upper and lower delay chains of the APUF, respectively, and consist of multiple inverters connected in series. The delay difference between the delay modules can be changed by altering the number of inverters. The three arbiters generate three different responses. Arbitrator 1, Arbitrator 2, and Arbitrator 3 are used to generate the original APUF response r1. Arbitrator 2 is connected to the upper additional delay module and the lower original APUF path, generating the delay difference detection response r2. Arbitrator 3 is connected to the lower additional delay module and the upper original APUF path, generating the delay difference detection response r3.

[0028] Most voting circuits include a counter, initially set to 0. The counter increments by 1 when the APUF response is "1". If the count is greater than half the total count, the vote is "1"; otherwise, it is "0". When performing response obfuscation, the input is the XOR result of the delay difference detection responses r2 and r3. When generating the final response, the input is the original APUF response r1.

[0029] The response generation process of the PUF based on response feedback in this invention can generally be divided into an obfuscation stage and a final response generation stage. In the obfuscation stage, the delay difference detection responses r2 and r3 are XORed and input into a majority voting circuit for m rounds of voting. If the voting result is "1", it indicates that the original response has high reliability and can be fed back to the excitation side. If the voting result is "0", it indicates that the original response has low reliability, and the previous reliable response is fed back to the excitation side. In the final response generation stage, the original APUF response is input into the majority voting circuit for m rounds of voting to improve the reliability of the final response.

[0030] Figure 1 This is a delay difference detection circuit. Two identical additional delay modules are connected after the upper and lower delay chains of the APUF, and three arbitrators are used to generate different responses. Assuming the original delay of the upper path of the APUF is D1, and the original delay of the lower path is D2, link ① represents the original delay difference, and arbitrator one generates the original response r1, with a corresponding delay difference of D1-D2. Assuming the delay of the additional delay modules is ΔD, then the delay of the upper path ② is D1+ΔD, and arbitrator two generates the response r2, with a corresponding delay difference of D1+ΔD-D2. The delay of the lower path ③ is D2+ΔD, and arbitrator three generates the response r3, with a corresponding delay difference of...

[0031] D1-D2-ΔD.

[0032] If both r2 and r3 are greater than 0, then:

[0033]

[0034] If both r2 and r3 are less than 0, then:

[0035]

[0036] Therefore, when r2 and r3 have the same sign, the absolute value of the delay difference between the upper and lower paths of the APUF is greater than ΔD. The sign of the delay difference corresponding to the original response r1 is not easily affected by external noise, thus it has high reliability and can be fed back to the excitation side. If r2 and r3 have opposite signs, it means that the reliability of the response r1 is not high enough, and it should be discarded.

[0037] Figure 2 This is a two-stage reliability enhancement circuit, consisting of a delay difference detection unit (DDTC) and a majority voting circuit. In the response feedback confusion stage, the XOR result of the delay difference detection responses r2 and r3 is input to the majority voting circuit for m rounds of voting. The voting result is the reliability flag rf. If rf is 1, the original response r1 has sufficient reliability and will participate in the feedback. If rf is 0, the original response r1 has insufficient reliability, and the previous reliable response will participate in the feedback, with the feedback bit initially set to 0. In the final response generation stage, the response is input to the majority voting circuit for m rounds of voting to generate the final response R.

[0038] Figure 3 This diagram illustrates the noise area of ​​three response parameters. Generally, the uplink / downlink delay difference in APUF follows a mean of 0 and a variance of σ. 2 The normal distribution N(0,σ) 2 The additional noise follows a normal distribution. σ noise =ασ (0≤α≤1). The noise area of ​​the three responses is as follows: Figure 3 As shown, S1, S2, and S3 represent the noise areas of responses r1, r2, and r3, respectively. A larger S1 area indicates lower response reliability. After screening, the delay difference of r1 is greater than ΔD, indicating generally high reliability, close to 100%. According to the delay difference detection circuit mechanism, one of the responses r2 and r3 has a smaller delay difference and lower reliability. Therefore, the PUF noise source shifts from r1 to r2 and r3, and the noise area changes from S1 to S2+S3. Clearly, a larger ΔD results in a smaller S2+S3, higher reliability of r2 and r3, fewer required votes, shorter response generation time, and higher authentication efficiency. When S2+S3 is less than S1, the number of votes required to improve reliability is less than the number of votes required, thus improving authentication efficiency while increasing the reliability of the response feedback PUF.

[0039] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A response generation method for a two-stage reliability enhancement circuit suitable for response feedback PUF, characterized in that, It includes an obfuscation phase and a final response generation phase. In the obfuscation phase, the response is detected by the delay difference. and The original response is XORed and input into the majority voting circuit for m votes. If the voting result is "1", it indicates that the original response has high reliability and can be fed back to the excitation side; if the voting result is "0", it indicates that the original response has low reliability and the previous reliable response is fed back to the excitation side; in the final response generation stage, the original APUF response is input into the majority voting circuit for m votes. In the response feedback confusion phase, the delay difference detection response will be used. and The result of the OR operation is input into the majority voting circuit for m votes, and the voting result is the reliability flag. ,like If the value is 1, then the original response If the reliability is high enough, it will participate in the feedback; if If it is 0, then the original response If the reliability is not high enough, the previous reliable response will participate in the feedback. The initial value of the feedback bit is 0. In the final response generation stage, the input majority voting circuit performs m votes to generate the final response R.

2. The response generation method according to claim 1, characterized in that, According to the APUF response generation principle, when the latency difference is greater than 0, the response is "1"; when the latency difference is less than 0, the response is "0". Let the APUF uplink latency be... The downlink latency is The additional delay unit delay size is ,like and If they have the same sign, then the delay difference between the two is greater than 0.

3. The response generation method according to claim 1, characterized in that, Let the delay of the original path above APUF be... The original delay of the path below is The arbitrator generates the original response. The corresponding delay difference is Assuming the additional delay module has a delay size of... The path delay above is The response is generated by Arbitrator 2. The corresponding delay difference is The path below is delayed. The response is generated by arbitrator three. The corresponding delay difference is , like and If all are greater than 0, then: like and If all are less than 0, then: Therefore, when and When the signs are the same, the absolute value of the delay difference between the upper and lower paths of APUF is greater than 1. Original response The corresponding delay difference will be fed back to the excitation side, if and If the sign is different, then discard it.

4. A circuit for implementing the response generation method as described in any one of claims 1-3, characterized in that, The system includes a delay difference detection circuit and a majority voting circuit. The delay difference detection circuit includes two identical additional delay modules symmetrically arranged above and below, and three arbitrators. The two additional delay modules are respectively connected to the upper and lower delay chains of the APUF and are composed of multiple inverters connected in series. The delay difference between the delay modules is changed by changing the number of inverters. The three arbitrators are used to generate three different responses. The majority voting circuit includes a counter. The initial value of the counter is 0. The counter is incremented by 1 when the APUF response is "1".

5. The circuit according to claim 4, characterized in that, The arbitrator includes Arbitrator 1, Arbitrator 2, and Arbitrator 3. Arbitrator 1 is connected to the APUF raw path and generates the APUF raw response. The second arbitrator is connected to the upper additional delay module and the lower original path of the APUF, generating a delay difference detection response. The arbitrator is connected to the additional delay module below and the original path above the APUF, generating a delay difference detection response. .

6. The circuit according to claim 4, characterized in that, In most voting circuits, the voting result is "1" if the count result is greater than half the count count, and "0" otherwise. When response confusion is performed, the input is the delay difference detection response. and The XOR result is used to generate the final response, with the original APUF response as its input. .

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