Electronic equipment performance optimization method and electronic equipment

Abstract

The present application discloses a method for optimizing the performance of an electronic device and an electronic device. When the wake-up time of a target algorithm is reached at the current moment, the screen state of the electronic device is detected; the target algorithm is encapsulated into a code segment that can be independently run in a bare metal operating environment; when the screen state of the electronic device is an off-screen state, the system state of the electronic device is determined; when the system state of the electronic device is a dormant state, the target algorithm is run in a bare metal operating environment. When the target algorithm is run in a bare metal operating environment, there is no need to start the operating system, which can avoid the power consumption introduced by the operating system scheduling, thereby keeping the electronic device running at low power consumption.

Description

Technical Field

[0001] The present application belongs to the field of terminal technology, and in particular relates to an electronic device performance optimization method and electronic device. Background Art

[0002] With the development of wearable devices, wearable devices not only have basic functions such as calling and taking pictures, but also support third-party applications (such as music, maps, etc.), sports services, health services, etc. For example, after a user wears a wearable device, the wearable device can monitor the user's steps, calories, heart rate, blood oxygen, sleep and other sports and health data.

[0003] Compared with mobile phones, wearable devices are smaller in size, so the battery and hardware resources of wearable devices are very tight. Therefore, how to improve the performance of wearable devices under the conditions of limited battery and hardware resources is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present application provides a method for optimizing the performance of an electronic device and an electronic device, which can improve the comprehensive performance of the electronic device under conditions of limited battery and hardware resources.

[0005] In a first aspect, the present application provides a method for optimizing the performance of an electronic device, which is applied to an electronic device, and the method includes: when the wake-up time of a target algorithm is reached at a current moment, detecting the screen state of the electronic device; the target algorithm is encapsulated into a code segment that can be independently run in a bare metal operating environment; when the screen state of the electronic device is an off state, determining the system state of the electronic device; when the system state of the electronic device is a sleep state, running the target algorithm in a bare metal operating environment.

[0006] When the screen state of an electronic device is off and the system state is in sleep state, the electronic device is in low-power operation state. In this case, the target algorithm is run in a bare metal operation environment without starting the operating system, which can avoid the power consumption introduced by the operating system scheduling, thereby keeping the electronic device running at low power. In addition, when the target algorithm is run in a bare metal operation environment, the target algorithm can be quickly awakened, run, and completed once. After the target algorithm completes a calculation process, the MCU immediately enters sleep state, thereby reducing the operating power consumption of the electronic device.

[0007] In one implementable manner, the method further includes: running the target algorithm in an operating system operating environment when the screen state of the electronic device is a screen-on state, or when the screen state of the electronic device is a screen-off state and the system state of the electronic device is a running state.

[0008] When the screen state of the electronic device is the screen-on state, or the screen state of the electronic device is the screen-off state and the system state of the electronic device is the running state, the operating system of the electronic device has been pulled up. That is, in this case, the operating system of the electronic device is in a normal running state, not in a low power running state.

[0009] Among them, the power consumption consumed by the normal operation of the operating system of the electronic device is much greater than the power consumption consumed by running the target algorithm in the operating system operating environment. Therefore, when the screen state of the electronic device is the screen-on state, or the screen state of the electronic device is the screen-off state and the system state of the electronic device is the operating state, whether the target algorithm is run in the operating system operating environment or in the bare metal operating environment, it does not contribute much to the reduction of power consumption of the electronic device. Therefore, when the screen state of the electronic device is the screen-on state, the target algorithm can be run in the operating system operating environment.

[0010] In an implementable manner, the running of the target algorithm in the bare metal operating environment includes: performing a first operation process using the target algorithm to obtain first operation data; the computing power overhead of the first operation process is less than a computing power threshold;

[0011] A digital signal processor DSP is called to perform a second operation processing to obtain second operation data; the computing power overhead of the second operation processing is greater than or equal to the computing power threshold.

[0012] In this way, the operation speed of the target algorithm can be accelerated.

[0013] In one possible implementation, the target algorithm is an algorithm that has a usage frequency higher than a frequency threshold and can be run in a screen-off state.

[0014] In this way, by encapsulating algorithms that often need to be run when the screen is off (for example, pedometer algorithms, wrist-raise screen-lighting algorithms, etc.) into code segments that can run independently in a bare-metal operating environment, the power consumption of electronic devices can be minimized.

[0015] In one implementable manner, the electronic device includes a first memory and a second memory, and the read and write speed of the first memory is greater than the read and write speed of the second memory; the method also includes: when the screen state of the electronic device is a bright screen state, in response to an interface switching operation input by a user, performing a drawing operation in the first memory to obtain N decomposed images; wherein N is a positive number greater than 1; wherein each of the decomposed images is an image corresponding to a local area of ​​a target display image; after each drawing operation, sending a decomposed image to the second memory; performing image stitching processing on the N decomposed images in the second memory to obtain a target display image; and sending the target display image to the screen of the electronic device.

[0016] Exemplarily, the first memory may be an on-chip SRAM, and the second memory may be an off-chip SRAM. In this way, a complete target display image is obtained by N drawing processes. After each decomposed image is drawn, the decomposed image obtained this time is sent to the off-chip SRAM. In this way, it can always be maintained that only one decomposed image occupies the storage space of the on-chip SRAM. In this way, compared with the solution of drawing the target display image in the on-chip SRAM at one time, (1-1 / N) on-chip SRAM storage space can be saved.

[0017] In an implementable manner, the first memory includes a first drawing buffer area and a second drawing buffer area; performing N drawing operations in the first memory to obtain N decomposed images includes: performing the i-th drawing operation in the first drawing buffer area, and sending the i-th decomposed image to the second memory; wherein i is a positive integer greater than 0 and less than N; performing the i+1-th drawing operation in the second drawing buffer area, and sending the i+1-th decomposed image to the second memory.

[0018] In this way, the decomposed image can be alternately drawn in the first drawing buffer area and the second drawing buffer area, thereby improving the drawing efficiency.

[0019] In one implementable manner, the electronic device includes a first memory and a second memory, and the read and write speed of the first memory is greater than the read and write speed of the second memory; the method also includes: when the screen state of the electronic device is a bright screen state, in response to an interface switching operation input by a user, detecting whether the current business scenario meets the high-performance business scenario; wherein the high-performance business scenario is a scenario with operating performance requirements higher than preset requirements; when the current business scenario does not meet the high-performance business scenario, setting the color depth of the cached image stored in the first memory to the first color depth; when the current business scenario meets the high-performance business scenario, setting the color depth of the cached image stored in the first memory to the second color depth, and the second color depth is less than the first color depth.

[0020] In this way, when the current business scenario does not meet the high-performance business scenario, the color depth of the cache image stored in the on-chip SRAM can be set to the first color depth to improve the display effect. When the current business scenario meets the high-performance business scenario, by reducing the color depth of the cache image stored in the on-chip SRAM to the second color depth, the cache image in the on-chip SRAM can be reduced. In this way, the saved on-chip SRAM storage space can be used to run more programs and improve the operating speed of the electronic device.

[0021] In one achievable manner, the cached image is a decomposed image and / or a target display image.

[0022] In one implementation, the electronic device includes a first memory and a second memory, and the read and write speed of the first memory is greater than the read and write speed of the second memory; the method also includes: receiving a request to run a first application; the run request includes a first storage space required to run the first application; when the remaining storage space of the first memory is greater than or equal to the first storage space, running the first application in the first memory; when the remaining storage space of the first memory is less than the first storage space, migrating the memory segment corresponding to the second application in the first memory to the second memory, and running the first application in the first memory; wherein the performance priority of the second application is lower than the performance priority of the first application.

[0023] In this way, when the performance priority of the loaded first application is higher than that of the second application in the on-chip SRAM, the memory segment corresponding to the second application can be migrated to the off-chip SRAM to free up the on-chip SRAM space for the first application with higher performance priority.

[0024] In one achievable manner, the task pointer of the second application is remapped to a physical address corresponding to the second application in the second memory.

[0025] In a second aspect, the present application provides an electronic device, comprising a memory and a processor; the memory and the processor are coupled; the memory is used to store computer program code, the computer program code comprises computer instructions, and when the processor executes the computer instructions, the electronic device executes a method as described in any one of the first aspects.

[0026] In a third aspect, the present application provides a chip system, comprising a processor; the processor is coupled to a memory, the memory is used to store computer program code, the computer program code comprises computer instructions, and when the processor executes the computer instructions, the method described in any one of the first aspects is executed.

[0027] In a fourth aspect, the present application provides a computer-readable storage medium, characterized in that a computer program or instructions is stored in the computer-readable storage medium, and when the computer program or instructions are executed on a computer, the computer executes the method as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application;

[0029] Figure 2A schematic diagram of a software architecture of an electronic device provided in an embodiment of the present application;

[0030] Figure 3 A framework diagram of a power consumption performance optimization method provided in an embodiment of the present application;

[0031] Figure 4 A flowchart of a power consumption performance optimization method provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of an image loading process provided in an embodiment of the present application;

[0033] Figure 6 A flowchart of the first memory optimization method provided in the embodiment of the present application;

[0034] Figure 7 The framework of the first memory optimization method provided in the embodiment of the present application Figure 1 ;

[0035] Figure 8 The framework of the first memory optimization method provided in the embodiment of the present application Figure 2 ;

[0036] Fig. 9 A flowchart of the second memory optimization method provided in the embodiment of the present application;

[0037] Fig.10 A flowchart of a third memory optimization method provided in an embodiment of the present application;

[0038] Fig.11 A framework diagram of a third memory optimization method provided in an embodiment of the present application;

[0039] Fig.12 A structural block diagram of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] With the development of wearable devices, wearable devices not only have basic functions such as calling and taking pictures, but also support third-party applications (such as music, maps, etc.), sports services, health services and other functions. For example, after a user wears a wearable device, the wearable device can monitor the user's steps, calories, heart rate, blood oxygen, sleep and other sports and health data. Furthermore, wearable devices can synchronize sports, health and other data to the user's mobile phone, so that the user can view the relevant data through the mobile phone, improving the user experience.

[0041] Compared with mobile phones, wearable devices are smaller in size, so the battery and hardware resources of wearable devices are very tight. For example, taking a smart watch as an example, its battery capacity is only 451mAh, the CPU frequency is 160MHz, the on-chip static random access memory (SRAM) is 2.5MB, the on-chip read-only memory (ROM) is 4MB, and the off-chip SRAM is 32MB.

[0042] Among them, on-chip SRAM is usually a memory embedded inside a chip such as a microprocessor or microcontroller. It is tightly integrated with the processor core and can be directly connected through an internal bus and control signals. Since the on-chip SRAM interacts directly with the processor core, its access speed is very fast and can support the processor's read and write operations more efficiently. Off-chip SRAM is usually an external memory connected to a microprocessor or microcontroller chip through an external interface (such as an address bus, a data bus, and a control bus). Generally, the read and write performance of on-chip SRAM is 3-10 times that of off-chip SRAM. In other words, the same instruction or application runs faster on the on-chip SRAM than on the off-chip SRAM.

[0043] It can be seen that, limited by the storage space of the on-chip SRAM and the battery capacity, wearable devices are more sensitive to power consumption and memory overhead. To support wearable devices to better run the above-mentioned functions such as calling, taking pictures, third-party applications, sports services, and health services, and improve user experience. The embodiment of the present application provides a performance optimization solution, which can at least reduce resource overhead and optimize the power consumption of wearable devices; or, it can optimize the memory resources of wearable devices.

[0044] The performance optimization solution provided in the embodiments of the present application can be applied to the user's electronic device. Exemplarily, in some embodiments, the electronic device may include a wearable device such as a smart watch and a smart bracelet. In other embodiments, the electronic device may also include an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a vehicle-mounted device, a smart home device, and other portable electronic devices.

[0045] like Figure 1 As shown, the embodiment of the present application takes the electronic device 100 as a wearable device (such as a smart watch) as an example to illustrate the structure of the electronic device 100 provided in the embodiment of the present application. Figure 1As shown, the electronic device 100 may include a wireless communication module 110, a display screen 120, a sensor module 121, a processor 130, an internal memory 140, an external memory 141, a power management module 150, a battery 160, a charging management module 170, an antenna, etc.

[0046] The wireless communication module 110 can provide wireless communication solutions including WLAN (such as (wirelessfidelity, Wi-Fi) network), Bluetooth (bluetooth, BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), nearfield communication technology (nearfield communication, NFC), infrared technology (infrared, IR), etc. applied to the electronic device 100.

[0047] The wireless communication module 110 may be one or more devices integrating at least one communication processing module. The wireless communication module 110 receives electromagnetic waves via an antenna, modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 130. The wireless communication module 110 may also receive a signal to be sent from the processor 130, modulate the frequency of the signal, amplify the signal, and convert it into electromagnetic waves for radiation via the antenna.

[0048] The display screen 120 is used to display images, GUI interactive interfaces, etc. The display screen 120 includes a display panel and a touch panel.

[0049] The processor 130 may include one or more processing units. For example, the processor 130 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU).

[0050] In some embodiments, the processor 130 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0051] It is understandable that the interface connection relationship between the modules illustrated in the embodiment of the present application is only a schematic illustration and does not constitute a structural limitation on the wearable device 100. In other embodiments of the present application, the wearable device 100 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0052] The charging management module 170 is used to receive charging input from a charger, where the charger can be a wireless charger or a wired charger.

[0053] The power management module 150 is used to connect the battery 160, the charging management module 170 and the processor 130. The power management module 150 receives input from the battery 160 and / or the charging management module 170, and supplies power to the processor 130, the internal memory 140, the external memory interface 220 and the wireless communication module 110. The power management module 150 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc.

[0054] The wireless communication function of the electronic device 100 can be implemented through an antenna and a wireless communication module 110 , etc.

[0055] The internal memory 140 can be used to store computer executable program codes, which include instructions. The internal memory 140 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device 100 (such as audio data, image data, a phone book, etc.), etc. In addition, the internal memory 140 may include an on-chip SRAM, an on-chip ROM, etc. The processor 110 executes various functional applications and data processing of the electronic device 100 by running instructions stored in the internal memory 140 and / or instructions stored in a memory provided in the processor.

[0056] The electronic device 100 may further include a sensor module 121. The sensor module 121 may include a pressure sensor, a gyroscope sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.

[0057] It is to be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0058] The methods in the following embodiments can all be implemented in the electronic device 100 having the above hardware structure.

[0059] Figure 2 A schematic diagram of the software architecture of an electronic device 100 provided in an embodiment of the present application.

[0060] like Figure 2 As shown, the software composition of the electronic device 100 may have a multi-layer structure. The layers communicate with each other through software interfaces. Different layers may include one or more functional modules. The functional modules in multiple layers may be used to cooperate to implement one or more functions of the electronic device 100.

[0061] It is understandable that an operating system may be running in the electronic device 100. For example, the operating system may be based on For example, the operating system may be a micro operating system customized for a wearable electronic device or a portable electronic device.

[0062] The operating system running in the electronic device 100 can provide the processing capability of the kernel. For example, the operating system can provide capabilities such as storage, tasks, data transmission in a bus (such as inter-process communication (IPC)), and task interruption.

[0063] like Figure 2 As shown, the configuration and operation of the software in each layer can be implemented based on the operating environment provided by the operating system running in the electronic device 100.

[0064] like Figure 2 As shown, the electronic device 100 may include an application layer (which may be referred to as the application layer for short), an application framework layer (which may be referred to as the framework layer for short), algorithms and internal libraries, a hardware abstraction layer (HAL), a kernel layer and a hardware driver layer, etc.

[0065] The application layer and the framework layer can interact through the framework application programming interface (API). The algorithms and internal libraries can interact with the kernel layer through the Cortex microcontroller software interface standard (CMSIS) API, and the algorithms and internal libraries can interact with the HAL layer through the HAL API.

[0066] Among them, the application layer may include a series of application packages. As an example, the application layer may include application packages for watch management such as device management, OTA upgrade, and dial management. The application layer may also include map applications, music applications, navigation applications, and other functional applications provided by third-party developers. The application layer may also include communication applications such as information, contacts, and calls. The application layer may also include applications such as mobile phone positioning, voice assistants, and personal affairs centers that support interconnection and interoperability with other devices. The application layer may also include other functional applications such as sports health, wallet applications, and manufacturing.

[0067] It is understandable that if Figure 2 The configuration in the application layer shown is only an example. In other implementations, the application layer in the electronic device 100 may include more or fewer application programs, so as to support various functions of the electronic device 100 through different application programs.

[0068] Below the application layer may be a framework layer. The framework layer provides an application programming interface (API) and a programming framework for the application programs in the application layer. The application framework layer includes some predefined functions.

[0069] In this example, the framework layer can provide meta-capability cross-platform execution environment (ACE), user interface (UI) framework, system basic service capabilities, underlying software service capabilities, sports health service capabilities, hardware service capabilities, etc. Each framework and capability can correspond to an entity or logic module in the framework layer.

[0070] The ACE UI framework may include an ACE application development framework. The ACE application development framework may provide a variety of application development logics to facilitate the development of software development and design by development designers in the ACE application development framework. The ACE UI framework may also include a UI tool (UI kit). The UI tool may provide image rendering processing capabilities. In some embodiments, the UI tool may be used to execute image rendering instructions indicated by an application program in the application layer.

[0071] In some other embodiments, the ACE UI framework may further include a touchGFX framework. As a graphical user interface (GUI) framework, the touchGFX framework can execute image rendering instructions issued by an application independently or in conjunction with a UI tool.

[0072] The basic service capabilities of the system may include communication services and audio services. Among them, communication services may include message services, call services, interconnection services, contact services, etc. Audio services may include music playback services, audio management services, voice broadcast services, music control services, etc.

[0073] The underlying software service capabilities can include basic services, manufacturing, and device management. Basic services can provide log services, file systems, NV management, exception logging, dual-machine communication, memory management, system wake-up, and other capabilities. Manufacturing can include manufacturing-related functions. For example, production services, aging services, etc. Device management can include device control, display management, Bluetooth management, etc.

[0074] Sports health service capabilities may include sports services and health services. Sports services may include exercise services, daily activity services, data storage and synchronization services, training status assessment services, etc. Health services may include heart rate services, sleep services, breathing services, heart health services, etc.

[0075] Hardware service capabilities may include various service support capabilities. For example, hardware service capabilities may include positioning services, Bluetooth / Bluetooth low energy (BLE) services, Near Field Communication (NFC) services, and other capabilities.

[0076] The framework layer may include algorithms and internal libraries, which may include multiple functional functions and interfaces, and the framework layer implements corresponding functions by calling the multiple functional functions and interfaces.

[0077] Exemplarily, the algorithm and internal library may include an algorithm library and a basic library. Among them, the algorithm library may include a motion algorithm, and the motion algorithm may calculate the user's motion data (for example, step frequency, etc.). Optionally, the algorithm library may also include an activity detection algorithm, a gesture algorithm (the gesture algorithm may calculate the user's wrist-raising gesture), a dimming algorithm, a wearing detection algorithm, a breathing algorithm, a skipping algorithm, a heart rate algorithm, a sleep algorithm, a physiological cycle algorithm, a blood pressure algorithm, a pressure algorithm, a body temperature algorithm, an audio algorithm, etc., which are not limited in this application. The basic library may include barcode-related algorithm functions, a basic C library, etc.

[0078] In this example, the algorithm and the internal library may also include a communication protocol stack. The communication protocol stack may include various protocol data for supporting the communication capability of the device. For example, the communication protocol stack may include a Bluetooth protocol stack, a BLE protocol stack, etc.

[0079] The kernel layer may include memory, tasks, interprocess communication (IPC), and interrupts of Lite OS.

[0080] The HAL layer may include one or more abstract modules of entity components. The application can call the corresponding entity component and obtain data by issuing instructions to the abstract module in the entity component.

[0081] Exemplarily, the HAL may include software abstract modules for physical components such as board support packages (BSP), NFC, liquid crystal display (LCD), Bluetooth, flash, and touch panel (TP). The HAL layer may also include hardware abstract modules corresponding to sensor components provided in electronic devices. For example, hardware abstract modules corresponding to acceleration sensors, gyroscope sensors, etc.

[0082] The electronic device 100 may also include a hardware driver layer. The hardware driver layer may include drivers for one or more hardware components. When an application needs to call a hardware component set in the electronic device, an instruction may be sent to a driver module set in the corresponding hardware driver layer, so that the driver module converts the software instruction into an instruction that can be directly transmitted to the hardware component, thereby realizing control and data transmission of the hardware component.

[0083] Exemplarily, the hardware driver layer may include a BSP driver, an LCD driver, a TP driver, a flash driver, an NFC driver, a Bluetooth driver, a sensor driver, and the like.

[0084] It should be noted that the application layer can communicate with the framework layer by calling the framework API. The framework layer can also call the corresponding API implementation when it needs to call the algorithm and the internal library function to communicate with the kernel layer or the hardware abstraction layer. For example, the API for calling the kernel layer may include CMSIS API, and the HAI API may be used when calling HAL.

[0085] It should be noted that the above Figure 2 The description and examples do not constitute a limitation on the electronic device 100 involved in the present application. In other embodiments, the electronic device 100 may also have more or less hardware or software components. The embodiments of the present application do not limit the specific components of the electronic device.

[0086] The power consumption performance optimization solution provided in the embodiment of the present application is described below.

[0087] The power consumption performance optimization solution provided in the embodiment of the present application includes two operating environments. The first operating environment is an operating system (OS) operating environment (also referred to as an OS state), and the second operating environment is a bare metal operating environment (also referred to as a bare metal state).

[0088] The OS operating environment refers to the overall environment provided by the operating system for the application program to run. For example, the OS operating environment can provide a system call interface for the application program, and the application program can access system resources and services through the system call, and the OS operating environment can provide process / thread management to reasonably schedule the running of the application program, etc.

[0089] Exemplary, combined Figure 2 and Figure 3 As shown (see Figure 3The process of waking up the motion algorithm in the algorithm library, running the motion algorithm and putting the motion algorithm to sleep in the OS running environment can be implemented in the following way: the motion application in the application layer can interact with the motion service in the framework layer by calling the preset application program interface API, the motion service can interact with the underlying software service, the underlying software service can interact with the sensor hardware abstraction module in the HAL layer, the sensor hardware abstraction module can interact with the sensor driver in the hardware driver layer, and the sensor driver can be used to drive the sensor in the hardware layer to collect the sensor data of the user during the movement.

[0090] The underlying software service can register a callback function with the target sensor (hereinafter, the target sensor is an acceleration sensor as an example) when the electronic device is powered on and initialized. The function of the callback function is to enable the target sensor to return the data it collects (for example, the acceleration data collected by the acceleration sensor) to the underlying software service at a preset frequency. The acceleration sensor can use the periodic scheduler (for example, scheduler_tick) and the chip internal system interrupt to trigger the call back function, and return the collected data to the underlying software service through the sensor hardware abstraction module. The underlying software service can send the acceleration data to the motion service. The motion service can call the API provided by the motion algorithm of the algorithm library to send the user's acceleration data to the motion algorithm. The motion algorithm calculates the number of steps of the user based on the user's acceleration data. When the motion algorithm completes a round of operations, the OS can call the idle thread and determine whether to switch the motion algorithm to a dormant state through the idle thread to enter the next waiting wake-up process. For example, the idle thread can check whether the task queue is empty for a long time. If it is empty for a long time, it can be determined that the motion algorithm processing chip (for example, the motion algorithm processing chip can be a microcontroller unit (MCU)) enters a dormant state.

[0091] It can be seen that the process of waking up the motion algorithm, running the motion algorithm and putting the motion algorithm to sleep in the OS running environment involves operations such as scheduling of multiple threads, function callbacks, and sleep logic judgments, and its power consumption is relatively high.

[0092] The bare metal operating environment refers to an operating environment that can run applications directly on the hardware platform without the support of the OS operating environment. Specifically, the independent address segment technology can be used, that is, the corresponding algorithm can be encapsulated into a code segment that can be run in the bare metal operating environment. The code segment that can be run in the bare metal operating environment can be understood as an internal function, that is, it can directly perform function calculations based on the input data and then output the calculation results.

[0093] For example, Figure 3 As shown (see Figure 3The process of waking up the motion algorithm in the algorithm library, running the motion algorithm and putting the motion algorithm to sleep in the bare metal operating environment can be implemented in the following way: the acceleration data collected by the target sensor (taking the target sensor as an accelerometer as an example) can be directly fed back to the motion service through the sensor hardware abstraction module. The motion service can directly call the motion algorithm of the algorithm library. The motion algorithm calculates the number of steps of the user based on the acceleration data of the user. When the motion algorithm completes a round of calculations, the MCU can directly enter the sleep state.

[0094] It can be seen that compared with the OS operating environment, in the bare metal operating environment, there is no need to wait for the OS to schedule the motion algorithm thread, wake up the motion algorithm, and run the motion algorithm. In the bare metal operating environment, there is no need to wait for the idle thread to determine the sleep state and put the motion algorithm processing chip into sleep state. In this way, in the bare metal operating environment, the motion algorithm can be quickly woken up, run, and enter the sleep state immediately after the motion algorithm completes a calculation process, thereby reducing the operating power consumption of the electronic device.

[0095] In the embodiment of the present application, some algorithms in the algorithm library only run in the screen-on state, and some algorithms can run in both the screen-on and screen-off states. For example, the pressure algorithm in the algorithm library only runs in the screen-on state. The motion algorithm, gesture algorithm, breathing algorithm, rope skipping algorithm, heart rate algorithm, sleep algorithm, etc. in the algorithm library can run in both the screen-on and screen-off states.

[0096] In addition, some algorithms in the algorithm library are used frequently, for example, the step counting algorithm in the motion algorithm and the wrist-raising screen-lighting algorithm in the gesture algorithm are all high-frequency algorithms. Other algorithms in the algorithm library, such as the pressure algorithm, rope skipping algorithm, and running algorithm, may be triggered based on the user's actual operation scenarios, and their usage frequencies are usually much lower than the step counting algorithm in the motion algorithm and the wrist-raising screen-lighting algorithm in the gesture algorithm.

[0097] Based on this, the embodiments of the present application can encapsulate algorithms that are run in both the screen-on and screen-off states and are used frequently (for example, algorithms whose usage frequency is higher than the frequency threshold belong to algorithms with higher frequencies) into code segments that can be run in a bare metal operating environment to minimize the power consumption of the electronic device. For example, the embodiments of the present application can encapsulate a pedometer algorithm and / or a wrist-raise screen-on algorithm into code segments that can be run in a bare metal operating environment.

[0098] In the embodiment of the present application, the algorithm encapsulated into a code segment that can be run in a bare metal environment can be referred to as a target algorithm. For example, the target algorithm can include a step counting algorithm and / or a wrist-raising screen-lighting algorithm.

[0099] Among them, the step counting algorithm can be used to calculate the number of steps based on the user's sensor data, and the wrist-raising screen-lighting algorithm is used to identify whether the user raises his wrist based on the user's sensor data. If the wrist-raising action is identified, the screen is lit.

[0100] For the specific implementation schemes of the pedometer algorithm and the wrist-raise screen-lighting algorithm, please refer to the relevant technologies and will not be described in detail here.

[0101] In the embodiments of the present application, each algorithm is usually not always in operation, but is provided with a corresponding operation cycle. Exemplarily, the target algorithm is awakened once every 2 seconds for operation, and after the target algorithm is completed, the MCU enters a dormant state. After 2 seconds, the target algorithm is awakened again for operation. In this way, the target algorithm is periodically awakened-run-sleep.

[0102] Among them, the power consumption performance optimization method provided by the embodiment of the present application can be adopted in each wake-up-run-sleep process of the target algorithm.

[0103] Figure 4 The following is a flowchart of a method for optimizing power consumption performance provided in an embodiment of the present application. Figure 3 and 4 As shown, the method may include the following steps:

[0104] S201, sensors of electronic devices collect sensor data of users.

[0105] Among them, different sensors can collect different sensor data. For example, after the user touches the screen, the touch sensor can collect pressure data. For another example, the acceleration sensor can collect acceleration data. Pressure data, acceleration data and other data can all be called sensor data.

[0106] The sensor data can be used by various algorithms in the algorithm library for motion detection, gesture recognition, etc. As an external device of an electronic device, the sensor can be connected to the chip of the electronic device through interfaces such as SPI and I2C.

[0107] In one possible implementation, the chip of the electronic device may include a direct memory access (DMA) controller. The DMA controller may automatically collect sensor data through interfaces such as SPI and I2C, and move the sensor data to an on-chip SRAM.

[0108] S202, when the current moment reaches the wake-up time of the target algorithm, detecting the screen status of the electronic device.

[0109] The screen status of an electronic device includes a screen-on status and a screen-off status.

[0110] The embodiments of the present application do not limit the specific implementation method of detecting the screen state. In some embodiments, the detection of the screen state of the electronic device can be implemented in the following manner: since the screen can light up the screen in response to the screen lighting instruction sent by the application framework layer, the screen state of the electronic device is the screen-on state. Based on this, the embodiments of the present application can detect whether the screen of the electronic device receives the screen lighting instruction, and when it is detected that the screen of the electronic device receives the screen lighting instruction, it is determined that the screen state is the screen-on state. When it is not detected that the screen of the electronic device receives the screen lighting instruction, the screen state is determined to be the screen-off state.

[0111] It should be noted that the above embodiment is only illustrative of detecting whether the screen of an electronic device receives a screen lighting instruction, and does not limit the method of detecting the screen state of the electronic device. For example, other parameters or instructions of the electronic device that can characterize the screen state of the electronic device can also be detected.

[0112] S203: When the screen state of the electronic device is off, detect the system state of the electronic device.

[0113] Among them, when the screen state is the bright screen state, the system state of the electronic device is in the running state. For example, when the screen state is the bright screen state, on the one hand, responding to user input and keeping the user interface updated in real time requires the main process of the operating system and the application to be in the running state. On the other hand, since the UI algorithm involved in updating the user interface is relatively complex and is not suitable for running in a bare metal operating environment, the UI-related algorithm needs to run in the OS operating environment.

[0114] When the screen is in an off state, the system state of the electronic device may be in a running state or in a sleep state.

[0115] Exemplarily, when the screen is off, a music application is running in the background of the electronic device. In this case, the system state of the electronic device is in a running state.

[0116] As another example, when the screen is in an off state, no application is running in the background of the electronic device. In this case, the system state of the electronic device is in a dormant state.

[0117] In some embodiments, when the screen state of the electronic device is off, detecting the system state of the electronic device can be implemented in the following manner: it can be determined whether the background of the electronic device includes an application process. If the background of the electronic device includes an application process, it can be determined that the system state of the electronic device is in a running state. If the background of the electronic device does not include an application process, it can be determined that the system state of the electronic device is in a dormant state.

[0118] It should be noted that the above embodiment is only used as an example to illustrate whether the background of the electronic device includes an application process, and does not limit the method of determining the system state of the electronic device. For example, other parameters or instructions of the electronic device that can characterize the system state of the electronic device can also be detected.

[0119] S204, when the system state of the electronic device is a sleep state, running the target algorithm in a bare metal running environment.

[0120] S205, when the screen state of the electronic device is the screen-on state, or when the screen state of the electronic device is the screen-off state and the system state of the electronic device is the running state, running the target algorithm in the OS running environment.

[0121] When the screen state of an electronic device is off and the system state is in sleep state, the electronic device is in low-power operation state. In this case, the target algorithm is run in a bare metal operation environment without starting the operating system, which can avoid the power consumption introduced by the operating system scheduling, thereby keeping the electronic device running at low power. In addition, when the target algorithm is run in a bare metal operation environment, the target algorithm can be quickly awakened, run, and completed once. After the target algorithm completes a calculation process, the MCU immediately enters sleep state, thereby reducing the operating power consumption of the electronic device.

[0122] When the screen state of the electronic device is the screen-on state, or the screen state of the electronic device is the screen-off state and the system state of the electronic device is the running state, the operating system of the electronic device has been pulled up. That is, in this case, the operating system of the electronic device is in a normal running state, not in a low power running state.

[0123] Among them, the power consumption consumed by the normal operation of the operating system of the electronic device is much greater than the power consumption consumed by running the target algorithm in the OS operating environment. Therefore, when the screen state of the electronic device is the screen-on state, or the screen state of the electronic device is the screen-off state and the system state of the electronic device is the operating state, whether the target algorithm is run in the OS operating environment or in the bare metal operating environment, the contribution to the reduction of power consumption of the electronic device is not large. Therefore, in the embodiment of the present application, when the screen state of the electronic device is the screen-on state, the target algorithm can be run in the OS operating environment.

[0124] It should be noted that the target algorithm in the embodiment of the present application can be run in both a bare metal environment and an OS operating environment, while other algorithms in the algorithm library except the target algorithm can only be run in an OS operating environment.

[0125] It should also be noted that, whether the target algorithm is run in a bare metal environment or in an OS operating environment, the target sensor data can be used as the input of the target algorithm for calculation and processing to obtain calculation results.

[0126] The embodiment of the present application does not limit the specific implementation method of using the target sensor data as the input of the target algorithm to perform calculation processing.

[0127] In some embodiments, the target algorithm includes an operation process with a relatively small computing power cost (which may be referred to as a first operation process) and an operation process with a relatively large computing power cost (which may be referred to as a second operation process). Exemplarily, the computing power cost of the first operation process is less than the computing power threshold, and the computing power cost of the second operation process is greater than or equal to the computing power threshold. For example, the second operation process includes operation processes such as filtering algorithms and matrix algorithms.

[0128] In the embodiment of the present application, in order to improve the operation speed of the target algorithm, after the target sensor data is input into the target algorithm, the target algorithm is used to perform a first operation process to obtain the first operation data. The DSP is called to perform a second operation process to obtain the second operation data. After the DSP calculates, the calculated second operation data can be fed back to the target algorithm. Finally, the target algorithm can obtain an operation result based on the first operation data and the second operation data. For example, the operation result is the number of steps of the user.

[0129] Similarly, the above implementation method can also be used to use the target sensor data as the input of the target algorithm, run the target algorithm in the OS operating environment, and output the operation results, which will not be repeated here.

[0130] The difference is that when the target algorithm is run in the OS running environment, a dedicated process is required to schedule the DSP to perform the second operation processing. In addition, in some embodiments, the DSP can be scheduled in an asynchronous scheduling manner to perform the second operation processing.

[0131] The target sensor data refers to the sensor data that the target algorithm needs to use when calculating the target data. For example, for a pedometer algorithm, the target sensor data may include sensor data collected by an acceleration sensor, a gyroscope sensor, and the like.

[0132] The power consumption performance optimization method provided in the embodiment of the present application is described below in combination with the hardware and software of the electronic device.

[0133] like Figure 3 As shown, the power consumption performance optimization method provided by the embodiment of the present application can be implemented in the following manner: first, the sensor data can be moved to the on-chip SRAM through the DMA controller, and the chip wake-up is triggered by the trigger. Then, when the wake-up time of the target algorithm is reached at the current moment, the sensor hardware abstraction module detects the screen status of the electronic device and the system status of the electronic device.

[0134] When the screen is off and the system is in sleep mode, the sensor data is directly transmitted to the motion service. Then, the motion service sends the sensor data to the target algorithm, so that the target algorithm can be run in the bare metal environment. When the target algorithm calculation is completed, the MCU can immediately enter sleep mode.

[0135] When the screen is on or off, and the system is running, the sensor hardware abstraction module can transmit the sensor data to the underlying software service through the serial softbus, and then the underlying software service sends the sensor data to the target algorithm through the motion service. In this process, the OS wake-up service is required to wake up the motion algorithm thread, and then schedule the target algorithm through the motion algorithm thread. When the target algorithm calculation is completed, the OS can call the idle thread and determine whether to switch the motion algorithm thread to the sleep state through the idle thread to enter the next waiting wake-up process.

[0136] In summary, the power consumption performance optimization method provided in the embodiment of the present application can run the target algorithm in a bare metal operating environment when the screen state of the electronic device is off and the system state is in a dormant state, so that there is no need to wake up the operating system, thereby maintaining low power consumption of the electronic device. In addition, running the target algorithm in a bare metal operating environment can quickly wake up the target algorithm, run the target algorithm, and make the target algorithm complete a calculation process, and then the MCU immediately enters a dormant state, thereby reducing the operating power consumption of the electronic device.

[0137] The following is a description of the memory resource optimization method provided in the embodiment of the present application.

[0138] Since the performance of the on-chip SRAM (which can be called the first memory) in the electronic device is better than that of the off-chip SRAM (which can be called the second memory), but the storage space of the on-chip SRAM is very small (for example, the on-chip SRAM is only 2.5MB), therefore, how to improve the operating performance of the electronic device by allocating the limited on-chip SRAM memory resources is a problem that needs to be solved urgently in the industry.

[0139] Based on this technical problem, the embodiments of the present application can provide the following three memory optimization solutions. The three memory optimization solutions that can be provided by the embodiments of the present application are described below.

[0140] When the screen state of the electronic device is in the bright screen state, it is usually necessary to execute an image loading process to display a corresponding image on the screen.

[0141] For example, Figure 5 As shown, in one implementable manner, the image loading process can be implemented in the following manner: the UI engine moves the image resources to be loaded from the off-chip SRAM to the on-chip SRAM. Afterwards, the drawing thread in the UI engine can perform the drawing operation of the first image frame in the on-chip SRAM, and store the drawn first image frame in the first frame buffer (Frame buffer1) of the on-chip SRAM. Afterwards, the first image frame in the first frame buffer can be sent to the screen for display (this process can be called a display sending operation). When performing the display sending operation, the drawing thread can perform the drawing operation of the second image frame in the on-chip SRAM, and store the drawn second image frame in the second frame buffer (Framebuffer2) of the on-chip SRAM. Afterwards, the second image frame in the second frame buffer is sent to the screen for display. It can be seen that in this scheme, the image frames stored in the first frame buffer or the second frame buffer are all complete display sending images. That is to say, in this scheme, the on-chip SRAM storage space occupied by the first frame buffer and the second frame buffer is at least the space occupied by a complete display sending image.

[0142] The first memory optimization solution provided in the embodiment of the present application can optimize Figure 5 The occupancy of the on-chip SRAM storage space by the first frame buffer area and the second frame buffer area in the image loading process is shown.

[0143] Figure 6 This is the first memory optimization solution provided in the embodiment of the present application. Figure 6 As shown, the method may include the following steps:

[0144] S301, when the screen state of the electronic device is in the bright screen state, in response to the interface switching operation input by the user, N drawing operations are performed in the on-chip SRAM to obtain N decomposed images; wherein N is a positive number greater than 1.

[0145] In the embodiment of the present application, the interface switching operation can be the interface switching of different application programs, or the switching operation of different interfaces under the same application program.

[0146] Exemplarily, after the user touches the application control on the screen of the electronic device, an interface switching operation is triggered to switch the current interface to the application interface.

[0147] In the embodiment of the present application, when drawing a user interface, i.e., a target display image, a complete target display image is obtained by N times of drawing. Each time, a partial area of ​​the target display image is drawn. That is, each decomposed image is an image corresponding to a partial area of ​​the target display image.

[0148] The embodiment of the present application does not limit the specific value of N. For example, N can be any value from 2 to 9.

[0149] S302, after each drawing operation, a decomposed image is sent to an off-chip SRAM.

[0150] That is to say, after each decomposition image is drawn, the decomposition image obtained this time is sent to the off-chip SRAM. In this way, only one decomposition image can always occupy the storage space of the on-chip SRAM. Figure 5 The solution shown can save (1-1 / N) on-chip SRAM storage space.

[0151] S303, performing image stitching processing on the N decomposed pictures in the off-chip SRAM to obtain a target display image.

[0152] S304, sending the target display image to the screen of the electronic device, and displaying the target display image on the screen.

[0153] Exemplary, combined Figure 6 and Figure 7 In the embodiment of the present application, the first frame buffer Frame buffer1 and the second frame buffer Frame buffer2 are moved to the off-chip SRAM, and the first rendering buffer Renderbuffer1 and the second rendering buffer Render buffer2 are configured in the on-chip SRAM. Correspondingly, the rendering thread draws a partial area of ​​the target loaded image in the on-chip SRAM each time to obtain a decomposed image. Then, after each decomposed image is obtained, the decomposed image is sent to the first frame buffer Frame buffer1 of the off-chip SRAM for storage. Afterwards, the multiple decomposed images stored in the first frame buffer Frame buffer1 can be stitched to obtain a complete display image. The display image is then sent to the screen for display.

[0154] Similarly, when the target display image in the first frame buffer Frame buffer1 is displayed on the screen, the decomposed image corresponding to the next display image can be drawn by the drawing thread, and the decomposed image corresponding to the next target display image is sent to the second frame buffer Frame buffer2 of the off-chip SRAM for storage. Afterwards, the multiple decomposed images obtained by storing Frame buffer2 in the second frame buffer can be spliced ​​to obtain a complete display image.

[0155] In one possible implementation, N drawing operations are performed in the on-chip SRAM to obtain N decomposed images, which can be implemented in the following manner: the i-th drawing operation is performed in the first drawing buffer area, and the i-th decomposed image is sent to the first frame buffer area; wherein i is a positive integer greater than 0 and less than N. The i+1-th drawing operation is performed in the second drawing buffer area, and the i+1-th decomposed image is sent to the first frame buffer area.

[0156] For example, Figure 7 As shown, the UI engine moves the image resources that need to be loaded from the off-chip SRAM to the on-chip SRAM through DMA. Then, the drawing thread can draw the first decomposed image in the first drawing buffer Render buffer1. After drawing the first decomposed image, the first decomposed image in the first drawing buffer1 can be moved to the first frame buffer Frame buffer1 in the off-chip SRAM through DMA. At the same time, the drawing thread can draw the second decomposed image in the second drawing buffer2. After drawing the second decomposed image, the second decomposed image in the second drawing buffer2 can be moved to the first frame buffer Frame buffer1 in the off-chip SRAM through DMA.

[0157] According to the above-mentioned processing of the first decomposed image and the second decomposed image, the processing is repeated. When Framebuffer1 obtains all the decomposed images and splices them based on all the decomposed images, a complete target display image is obtained. Further, the target display image can be transmitted to the screen.

[0158] Similarly, referring to the above process flow, the second frame buffer Frame buffer2 can obtain all decomposed images, and after splicing based on all the obtained decomposed images, a complete image for display is obtained.

[0159] It should be noted that the UI engine in the electronic device in the above embodiment can support drawing and rendering processing of a partial area in the image to ensure that a complete display image can be obtained by splicing all decomposed images.

[0160] In some embodiments, the first memory optimization solution described above can be used in some high-performance business scenarios. High-performance business scenarios refer to scenarios where the operating performance requirements are higher than the preset requirements. For example, high-performance business scenarios may include multi-threaded concurrent business scenarios, foreground high-performance application running and other business scenarios.

[0161] Exemplarily, a multi-threaded concurrent business scenario may be a scenario where multiple applications are running in the background of an electronic device. For example, the background of an electronic device simultaneously runs applications such as music, sports health, and navigation. In this case, if the interface needs to be refreshed, the first memory optimization method provided in the above embodiment may be adopted. In this way, by reducing the occupation of the on-chip SRAM space by sending and displaying images, these concurrent threads can be run in the on-chip SRAM as much as possible.

[0162] In another exemplary embodiment, high-performance applications may be predefined. In this way, when the application running in the foreground of the electronic device is a high-performance application, the first memory optimization method provided in the above embodiment may be adopted. In this way, the high-performance application may be run in the on-chip SRAM as much as possible by reducing the occupation of the on-chip SRAM space by the transmitted image.

[0163] The embodiments of the present application do not limit the specific implementation method of identifying high-performance business scenarios. For example, the operating performance requirements of the current business scenario can be determined based on the number of applications running in the background and the performance attributes of each application. If the operating performance requirements of the current business scenario are higher than the preset requirements, the current business scenario can be determined to be a high-performance business scenario. Otherwise, it can be determined that the current business scenario is not a high-performance business scenario.

[0164] Exemplarily, if the number of applications running in the background is identified to be more than 3, the current business scenario can be determined to be a high-performance business scenario. If the applications running in the foreground are identified to include high-performance applications, the current business scenario can be determined to be a high-performance business scenario.

[0165] In summary, the solution provided in the embodiment of the present application ( Figure 7 As shown in the scheme, since part of the display image is drawn in the on-chip SRAM each time, the on-chip SRAM storage space occupied by the first drawing buffer area and the second drawing buffer area is only 1 / N of the storage space occupied by a complete display image. Figure 5 The solution shown in the embodiment of the present application can reduce the occupancy of the on-chip SRAM during the image loading process. In this way, the saved on-chip SRAM storage space can be used to run more programs, thereby improving the operating speed of the electronic device.

[0166] It should be noted that the above embodiment is only described by taking the first frame buffer area and the second frame buffer area as an example to move to the off-chip SRAM, and does not limit the memory optimization solution. Figure 8 As shown, the first frame buffer Frame buffer1 or the second frame buffer Frame buffer2 can also be moved to an off-chip SRAM. In this way, the on-chip SRAM includes the first frame buffer Frame buffer1, the first rendering buffer Render buffer1 and the second rendering buffer Render buffer2, and the off-chip SRAM includes the second frame buffer Frame buffer2.

[0167] Fig. 9 This is the second memory optimization solution provided in the embodiment of the present application. Fig. 9 As shown, the method may include the following steps:

[0168] S401, when the screen state of the electronic device is in the bright screen state, in response to the interface switching operation input by the user, detecting whether the current business scenario meets the high-performance business scenario.

[0169] Among them, the specific implementation method of detecting whether the current business scenario meets the high-performance business scenario can be found in the description of the above embodiment, which will not be repeated here.

[0170] S402: When the current service scenario does not meet the high-performance service scenario, the color depth of the cache image stored in the on-chip SRAM is set to a first color depth.

[0171] S403, when the current business scenario meets the high-performance business scenario, setting the color depth of the cache image stored in the on-chip SRAM to a second color depth, wherein the second color depth is smaller than the first color depth.

[0172] The same cache image can obtain different color depths by using different color encoding methods. The cache images with different color depths occupy different storage spaces, wherein the greater the color depth of the same cache image, the greater the storage space it occupies.

[0173] Exemplarily, the first color depth may be a 24-bit color depth obtained by the color encoding method RGB888, and the second color depth may be a 16-bit color depth obtained by the color encoding method RGB565. In this way, the storage space occupied by the cache image of the second color depth is smaller than the storage space occupied by the cache image of the first color depth.

[0174] In this way, in the embodiment of the present application, when the current business scenario does not meet the high-performance business scenario, the color depth of the cache image stored in the on-chip SRAM can be set to the first color depth to improve the display effect. When the current business scenario meets the high-performance business scenario, by reducing the color depth of the cache image stored in the on-chip SRAM to the second color depth, the cache image in the on-chip SRAM can be reduced. In this way, the saved on-chip SRAM storage space can be used to run more programs and improve the operating speed of the electronic device.

[0175] For example, Figure 5 As shown, for a solution in which the on-chip SRAM includes a first frame buffer Frame buffer 1 and a second frame buffer Frame buffer 2, when the current business scenario meets the high-performance business scenario, the color depth of the display image stored in the first frame buffer Frame buffer 1 and the second frame buffer Frame buffer 2 can be set to the second color depth.

[0176] Another exemplary example is Figure 7 As shown, for a solution in which the on-chip SRAM includes a first rendering buffer 1 and a second rendering buffer 2, when the current business scenario meets the high-performance business scenario, the color depth of the decomposed image stored in the first rendering buffer 1 and the second rendering buffer 2 can be set to the second color depth.

[0177] Another exemplary example is Figure 8 As shown, for a solution in which the on-chip SRAM includes a first frame buffer Frame buffer1 (or a second frame buffer Frame buffer2), a first rendering buffer Render buffer1, and a second rendering buffer Render buffer2, the color depth of the display image stored in the first frame buffer Frame buffer1 and the decomposed image stored in the first rendering buffer Render buffer1 and the second rendering buffer Render buffer2 can be set to the second color depth.

[0178] Fig.10 This is the third memory optimization solution provided in the embodiment of the present application. Fig.10 As shown, the method may include the following steps:

[0179] S501: Receive a request to execute a first application.

[0180] When loading the first application, a request may first be made to allocate storage space required for running the first application, ie, the first storage space, to the first application.

[0181] In some embodiments, the execution request may include the first storage space and the performance priority corresponding to the first application.

[0182] For example, the required operating performance requirements of the applications in the electronic device may be pre-ranked, wherein the application with a higher required operating performance requirement has a higher corresponding performance priority.

[0183] S502, determine whether the remaining storage space of the on-chip SRAM is greater than or equal to the first storage space.

[0184] S503, when the remaining storage space of the on-chip SRAM is smaller than the first storage space, migrate the memory segment corresponding to the second application in the on-chip SRAM to the off-chip SRAM, and run the first application in the on-chip SRAM.

[0185] The performance priority of the second application is lower than the performance priority of the first application.

[0186] The memory segment corresponding to the second application may include a running cache and / or a code segment corresponding to the second application.

[0187] After migrating the memory segment corresponding to the second application in the on-chip SRAM to the off-chip SRAM, remap the task pointer corresponding to the second application. Specifically, map the task pointer corresponding to the second application to the new position of the migrated memory segment in the off-chip SRAM.

[0188] Similarly, if the memory segment corresponding to the first application in the off-chip SRAM is migrated to the on-chip SRAM, the task pointer corresponding to the first application is also remapped. Specifically, the task pointer corresponding to the first application is mapped to the new position of the migrated memory segment in the on-chip SRAM.

[0189] S504: When the remaining storage space of the on-chip SRAM is greater than or equal to the first storage space, run the first application program in the on-chip SRAM.

[0190] In this way, when the performance priority of the loaded first application is higher than that of the second application in the on-chip SRAM, the memory segment corresponding to the second application can be migrated to the off-chip SRAM to free up the on-chip SRAM space for the first application with higher performance priority.

[0191] For example, Fig.11As shown, memory segment 1 is the memory segment corresponding to the first application, memory segment 2 is the memory segment corresponding to the second application, and memory segment 3 is the memory segment corresponding to the third application. Among them, the performance priority can be sorted as follows: the first application is higher than the third application, and the third application is higher than the second application. In this way, memory segment 2 in the on-chip SRAM can be moved to the on-chip SRAM, and memory segment 1 in the off-chip RAM can be moved to the on-chip RAM. Specifically, memory segment 2 in the on-chip SRAM can be released first, and then memory segment 2 can be copied to the off-chip RAM. Next, memory segment 1 in the off-chip SRAM can be released, and then memory segment 1 can be copied to the on-chip RAM.

[0192] It should be noted that if the remaining storage space is still insufficient to store the memory segment 1 after the memory segment 2 in the on-chip SRAM is moved to the on-chip SRAM, the memory segment 3 in the on-chip SRAM may also be moved to the off-chip SRAM.

[0193] It should also be noted that the three memory optimization solutions provided in the embodiments of the present application can be applied to electronic devices independently or in combination, and the embodiments of the present application are not limited to this.

[0194] For example, based on the third memory optimization solution, if the application program running in the on-chip SRAM includes image drawing related threads, the first memory optimization solution and / or the second memory optimization solution can be further combined to further reduce the occupation of the on-chip SRAM storage space by the sent display image and / or decomposed image in the on-chip SRAM. In this way, the saved on-chip SRAM storage space can be used to run more programs and improve the operating speed of the electronic device.

[0195] It should also be noted that the power consumption performance optimization solution and the three memory optimization solutions provided in the embodiments of the present application can be applied to electronic devices independently or in combination, and the embodiments of the present application do not limit this.

[0196] The various method embodiments described in this document may be independent solutions or may be combined according to internal logic, and these solutions all fall within the protection scope of this application.

[0197] It can be understood that, in the above-mentioned various method embodiments, the methods and operations implemented by the electronic device can also be implemented by components (such as chips or circuits) that can be used in the electronic device.

[0198] The above embodiments introduce the performance optimization method provided by the present application. It is understandable that, in order to realize the above functions, the electronic device includes a hardware structure and / or software module corresponding to each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application.

[0199] The embodiment of the present application further provides a processing device, which includes at least one processor and a communication interface. The communication interface is used to provide information input and / or output to the at least one processor, and the at least one processor is used to execute the method in the above method embodiment.

[0200] It should be understood that the above-mentioned processing device can be a chip. Fig.12 , Fig.12 A structural block diagram of a chip provided in an embodiment of the present application. Fig.12 The chip shown may be a general-purpose processor or a dedicated processor. The chip 600 may include at least one processor 601. The at least one processor 601 may be used to support the technical solution corresponding to any of the above embodiments.

[0201] Optionally, the chip 600 may further include a transceiver 602, which is used to accept the control of the processor 601 and to support the technical solution corresponding to any of the above embodiments. Fig.12 The chip 600 shown may further include a storage medium 603. Specifically, the transceiver 602 may be replaced by a communication interface, and the communication interface provides information input and / or output for the at least one processor 601.

[0202] It should be noted that Fig.12The chip 600 shown can be implemented using the following circuits or devices: one or more field programmable gate arrays (FPGA), programmable logic devices (PLD), application specific integrated circuits (ASIC), system on chip (SoC), central processor unit (CPU), network processor (NP), digital signal processor (DSP), micro controller unit (MCU), controller, state machine, gate logic, discrete hardware components, any other suitable circuits, or any combination of circuits capable of performing the various functions described throughout the present application.

[0203] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0204] It should be noted that the processor in the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method embodiment can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor can be combined and performed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0205] It can be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0206] According to the method provided in the embodiments of the present application, the embodiments of the present application also provide a computer program product, which includes: a computer program or instructions, when the computer program or instructions are run on a computer, the computer executes the method of any one of the embodiments of the method.

[0207] According to the method provided in the embodiments of the present application, the embodiments of the present application also provide a computer storage medium, which stores a computer program or instructions. When the computer program or instructions are run on a computer, the computer executes the method of any one of the embodiments of the method.

[0208] According to the method provided by an embodiment of the present application, an embodiment of the present application also provides an electronic device, including a memory and a processor; the memory and the processor are coupled; the memory is used to store computer program code, and the computer program code includes computer instructions. When the processor executes the computer instructions, the electronic device executes the method of any one of the embodiments of the method embodiment.

[0209] According to the method provided in the embodiment of the present application, the embodiment of the present application also provides a chip system, which includes a processor, the processor is coupled to a memory, and is used to execute a computer program or instruction stored in the memory. When the computer program or instruction is executed, the chip system can implement all or part of the steps in the method embodiment. The chip system can be composed of a chip, or it can include a chip and other discrete devices.

[0210] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0211] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

[0212] The computer storage medium, computer program product, and electronic device provided in the above-mentioned embodiments of the present application are all used to execute the method provided above. Therefore, the beneficial effects that can be achieved can refer to the corresponding beneficial effects of the method provided above, and will not be repeated here.

[0213] It should be understood that in each embodiment of the present application, the execution order of each step should be determined by its function and internal logic, and the size of the sequence number of each step does not mean the order of execution and does not limit the implementation process of the embodiment.

[0214] Each part of this specification is described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments of the device, computer storage medium, computer program product, and electronic device, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

[0215] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0216] The above-described embodiments of the present application do not constitute a limitation on the protection scope of the present application.

Claims

1. A method for optimizing electronic equipment performance, characterized in that: The method is applied to an electronic device, and the method comprises: When the wake-up time of the target algorithm is reached at the current moment, the screen state of the electronic device is detected; the target algorithm is encapsulated into a code segment that can be independently run in a bare metal operating environment; When the screen state of the electronic device is off, determining the system state of the electronic device; When the system state of the electronic device is a dormant state, the target algorithm is run in a bare metal operating environment; the bare metal operating environment refers to an operating environment for running an application on a hardware platform without support from an operating system operating environment; the operating system operating environment refers to an operating environment provided by the operating system to the application; Among them, running the target algorithm in a bare metal operating environment includes: using the target algorithm to perform a first operation processing to obtain first operation data; the computing power overhead of the first operation processing is less than the computing power threshold; calling a digital signal processor DSP to perform a second operation processing to obtain second operation data; the computing power overhead of the second operation processing is greater than or equal to the computing power threshold.

2. The method according to claim 1, characterized in that The method further comprises: When the screen state of the electronic device is a screen-on state, or when the screen state of the electronic device is a screen-off state and the system state of the electronic device is a running state, the target algorithm is run in an operating system running environment.

3. The method according to claim 1, characterized in that The target algorithm is an algorithm whose usage frequency is higher than a frequency threshold and can be run in the screen-off state.

4. The method according to claim 1, characterized in that The electronic device comprises a first memory and a second memory, the read and write speed of the first memory is greater than the read and write speed of the second memory; the method further comprises: When the screen state of the electronic device is in the bright screen state, in response to the interface switching operation input by the user, a drawing operation is performed in the first memory to obtain N decomposed images; wherein N is a positive number greater than 1; wherein each of the decomposed images is an image corresponding to a local area of ​​the target display image; After each drawing operation, sending a decomposed image to the second memory; Performing image stitching processing on the N decomposed images in the second memory to obtain a target display image; The target display image is sent to the screen of the electronic device.

5. The method according to claim 4, characterized in that The first memory includes a first drawing buffer area and a second drawing buffer area; performing N drawing operations in the first memory to obtain N decomposed images includes: Performing an i-th drawing operation in the first drawing buffer area, and sending an i-th decomposed image to the second memory; wherein i is a positive integer greater than 0 and less than N; The second drawing buffer area performs the (i+1)th drawing operation and sends the (i+1)th decomposed image to the second memory.

6. The method according to claim 4, characterized in that The electronic device comprises a first memory and a second memory, the read and write speed of the first memory is greater than the read and write speed of the second memory; the method further comprises: When the screen state of the electronic device is in the bright screen state, in response to the interface switching operation input by the user, detecting whether the current business scenario meets the high-performance business scenario; wherein the high-performance business scenario is a scenario with a running performance requirement higher than a preset requirement; When the current business scenario does not meet the high-performance business scenario, setting the color depth of the cached image stored in the first memory to the first color depth; When the current business scenario meets the high-performance business scenario, the color depth of the cached image stored in the first memory is set to a second color depth, and the second color depth is smaller than the first color depth.

7. The method according to claim 6, characterized in that The cached image is a decomposed image and / or a target display image.

8. The method according to claim 1, characterized in that The electronic device comprises a first memory and a second memory, the read and write speed of the first memory is greater than the read and write speed of the second memory; the method further comprises: receiving a running request of a first application program; the running request including a first storage space required for running the first application program; When the remaining storage space of the first memory is greater than or equal to the first storage space, running the first application in the first memory; When the remaining storage space of the first memory is smaller than the first storage space, the memory segment corresponding to the second application in the first memory is migrated to the second memory, and the first application is run in the first memory; wherein the performance priority of the second application is lower than the performance priority of the first application.

9. The method according to claim 8, characterized in that The task pointer of the second application is remapped to a physical address corresponding to the second application in the second memory.

10. An electronic device, characterized in that: It comprises a memory and a processor; the memory and the processor are coupled; the memory is used to store computer program code, the computer program code comprises computer instructions, and when the processor executes the computer instructions, the electronic device executes the method as described in any one of claims 1-9.

11. A chip system, characterized in that: The chip system includes a processor; the processor is coupled to a memory, the memory is used to store computer program code, the computer program code includes computer instructions, and when the processor executes the computer instructions, the method as described in any one of claims 1-9 is executed.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program or instruction. When the computer program or instruction is executed on a computer, the computer executes the method according to any one of claims 1 to 9.

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