A 3D silicon-based capacitor and its preparation method

Abstract

The present invention belongs to the technical field of silicon-based capacitors, and specifically relates to a 3D silicon-based capacitor and a preparation method thereof. The 3D silicon-based capacitor provided by the present invention is provided with a groove on the upper surface of the substrate layer, which increases the length of the first dielectric layer in the vertical direction, so that the effective area of ​​the capacitor of the first dielectric layer in the groove becomes larger, thereby increasing the effective area of ​​the capacitor per unit volume, improving the chip utilization rate, and increasing the capacitor capacitance density. In the present invention, the first dielectric layer and the second dielectric layer are connected in series to form a T-shaped capacitor, and the present invention uses a dielectric connection layer to protect the inside of the device, and can also be used as a third dielectric layer to connect the first dielectric layer and the second dielectric layer in series, and the electrodes of the capacitor are distributed at both ends of the total dielectric layer, so that the dielectric connection layer, the first dielectric layer and the second dielectric layer form an interconnected and uninterrupted overall continuous dielectric layer, thereby improving the chip utilization rate and increasing the capacitor capacitance density.

Description

Technical Field

[0001] The present invention belongs to the technical field of silicon-based capacitors, and in particular relates to a 3D silicon-based capacitor and a preparation method thereof. Background Art

[0002] Compared to traditional capacitors, silicon-based capacitors offer high stability and maintain consistent performance at high temperatures, making them an excellent choice for harsh environments such as aviation, military, and mining. Furthermore, compared to traditional capacitors, silicon-based capacitors facilitate device miniaturization, improve production efficiency, reduce costs, and lower power consumption, making them a key trend in semiconductor process development.

[0003] At present, silicon-based capacitors generally use advanced photolithography, deep silicon etching, chemical vapor deposition (CVD), physical vapor deposition (PVD) and other processes to prepare high capacitance density and low loss capacitors on silicon-based substrates. Among them, deep silicon etching technology is used to make high aspect ratio trenches on silicon-based substrates, which can increase the area of ​​capacitor electrodes and increase the capacitance value per unit volume of silicon-based capacitors. The dielectric layer of silicon-based capacitors generally uses chemical vapor deposition to generate high-quality dielectric layers. Selecting a dielectric material or a combination of several dielectric materials can achieve the desired capacitance density and breakdown field strength. However, the planar structure silicon capacitors made by the above-mentioned semiconductor process still have the disadvantages of low capacitance density and large volume. Summary of the Invention

[0004] The object of the present invention is to provide a 3D silicon-based capacitor and a preparation method thereof. The 3D silicon-based capacitor chip provided by the present invention has a higher utilization rate and a larger capacitance density.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] The present invention provides a 3D silicon-based capacitor, comprising:

[0007] A substrate layer, wherein the upper surface of the substrate layer is inwardly recessed and has a plurality of grooves arranged in an array;

[0008] a first polysilicon conductive layer, wherein the first polysilicon conductive layer covers an upper surface of the substrate layer;

[0009] a first dielectric layer located on an upper surface of the first polysilicon conductive layer, the first dielectric layer comprising a plurality of first dielectric units arranged in an array and separated from each other, each first dielectric unit covering a position of the groove and extending out of the notch;

[0010] a second polysilicon conductive layer located on a portion of an upper surface of the first dielectric unit, the second polysilicon conductive layer comprising a plurality of second polysilicon conductive units arranged in an array, each of the second polysilicon conductive units filling a groove position of the first dielectric unit and extending out of the notch;

[0011] a second dielectric layer located on a portion of the upper surface of the first dielectric layer and a portion of the surface of the second polysilicon conductive layer, the second dielectric layer comprising a plurality of second dielectric units arranged in an array, each second dielectric unit having a first through hole defined at a position corresponding to the groove region;

[0012] a connection layer located on a portion of the upper surface of the first polysilicon conductive layer and a portion of the surface of the second dielectric layer, and in contact with a portion of the surface of the first dielectric layer, wherein the connection layer has a second through hole provided in a region corresponding to the first through hole, the second through hole being coaxial with the first through hole, and having a diameter greater than that of the first through hole;

[0013] a dielectric connection layer located on a portion of the upper surface of the first polysilicon conductive layer, a surface of the connection layer, and a portion of the upper surface of the second dielectric layer, wherein the dielectric connection layer is provided with a third through hole in a region corresponding to the first through hole, the third through hole being coaxial with the first through hole, and having a diameter smaller than that of the second through hole and greater than or equal to that of the first through hole;

[0014] a metal anode layer located on the upper surface of the dielectric connection layer, filling the area where the first through hole and the third through hole are formed, and contacting the upper surface of the portion of the second polysilicon conductive layer located at the bottom of the first through hole, wherein the metal anode layer is continuous;

[0015] A metal cathode layer is located on the lower surface of the substrate layer.

[0016] Preferably, the first polysilicon conductive layer is N-type doped low-resistivity polysilicon or P-type doped low-resistivity polysilicon; the thickness of the first polysilicon conductive layer is The resistivity of the first polysilicon conductive layer is less than or equal to 0.005 ohm.cm.

[0017] Preferably, the second polysilicon conductive layer is N-type doped low-resistivity polysilicon or P-type doped low-resistivity polysilicon; the thickness of the second polysilicon conductive layer is The resistivity of the second polysilicon conductive layer is less than or equal to 0.005 ohm.cm.

[0018] Preferably, the connecting layer is metal Al, N-type doped low-resistivity polysilicon or P-type doped low-resistivity polysilicon; the thickness of the metal Al is 1000~3000A; the thickness of the N-type doped low-resistivity polysilicon or P-type doped low-resistivity polysilicon is 1000~3000A, and the resistivity is less than or equal to 0.005ohm.cm.

[0019] Preferably, when the connecting layer is metal Al, the first polysilicon conductive layer and the second polysilicon conductive layer are low-resistivity polysilicon of the same doping type, both of which are N-type doped or both of which are P-type doped;

[0020] When the connecting layer is N-type doped low-resistivity polysilicon, the first polysilicon conductive layer and the second polysilicon conductive layer are both N-type doped low-resistivity polysilicon;

[0021] When the connecting layer is P-type doped low-resistivity polysilicon, the first polysilicon conductive layer and the second polysilicon conductive layer are both P-type doped low-resistivity polysilicon.

[0022] Preferably, the substrate layer is P-type low-resistivity conductive silicon or N-type low-resistivity conductive silicon; the resistivity of the substrate layer is 0.002-0.004 ohm.cm; the crystal orientation of the substrate layer is <100> ; The thickness of the substrate layer is 100 to 150 μm.

[0023] Preferably, the materials of the first dielectric layer and the second dielectric layer independently include one or more of SiO2, Si3N4, HfO2, TiO2 and Al2O3.

[0024] Preferably, the thickness of the first dielectric layer and the second dielectric layer are independently

[0025] Preferably, the material of the dielectric connection layer is silicon oxide or silicon nitride; the thickness of the dielectric connection layer is

[0026] Preferably, the metal anode layer is a multilayer film; the multilayer film includes an Au film and a TiW film, or an Au film, a TiW film and a Ni film; the thickness of the Au film is greater than 2 μm.

[0027] Preferably, the metal cathode layer is a multilayer film; the multilayer film includes an Au film and a TiW film, or an Au film, a TiW film and a Ni film; the thickness of the Au film is greater than 1 μm.

[0028] The present invention provides a method for preparing a 3D silicon-based capacitor according to the above technical solution, comprising the following steps:

[0029] Patterning the upper surface of the substrate to obtain grooves;

[0030] Depositing a first polysilicon thin film on the inner surface of the groove and the upper surface of the substrate except the groove, and then performing a first annealing process on the first polysilicon thin film after high-temperature doping or ion implantation to obtain a first polysilicon conductive layer;

[0031] depositing a first dielectric film on the surface of the first polysilicon conductive layer;

[0032] Depositing a second polysilicon film on the surface of the first dielectric film, then performing high-temperature doping or ion implantation on the second polysilicon film, followed by a second annealing process, and then performing a patterning process to obtain a second polysilicon conductive layer, thereby obtaining a first semi-finished product;

[0033] performing patterning on the first dielectric film of the first semi-finished product to obtain a first dielectric layer, thereby obtaining a second semi-finished product; depositing a second dielectric film on the surface of the second semi-finished product and performing patterning to obtain a second dielectric layer, thereby obtaining a third semi-finished product;

[0034] Depositing a connection layer thin film on the surface of the third semi-finished product, performing a third annealing treatment and then performing a patterning treatment to obtain a connection layer, thereby obtaining a fourth semi-finished product;

[0035] depositing a third dielectric film on the surface of the fourth semi-finished product, and obtaining a dielectric connection layer after patterning, thereby obtaining a fifth semi-finished product;

[0036] preparing a metal anode layer on the surface of the fifth semi-finished product to obtain a sixth semi-finished product;

[0037] The substrate is thinned to obtain a substrate layer, and a metal cathode layer is prepared on the lower surface of the substrate layer to obtain the 3D silicon-based capacitor.

[0038] Preferably, after obtaining the first semi-finished product, the preparation method of the third semi-finished product is replaced by:

[0039] A second dielectric film is deposited on the surface of the first semi-finished product to obtain a second semi-finished product; the first dielectric film and the second dielectric film of the second semi-finished product are patterned to obtain a first dielectric layer and a second dielectric layer to obtain a third semi-finished product.

[0040] Preferably, the connecting layer film is a metal Al film or a third polysilicon film;

[0041] When the connecting layer film is a metal Al film, the holding temperature of the third annealing treatment is 350-400° C.;

[0042] When the connecting layer thin film is a third polysilicon thin film, after the third polysilicon thin film is obtained and before the third annealing treatment is performed, the method further includes: performing high-temperature doping or ion implantation on the third polysilicon thin film; when the connecting layer thin film is the third polysilicon thin film, the holding temperature of the third annealing treatment is ≥950°C;

[0043] The holding temperature of the first annealing treatment and the second annealing treatment is ≥950°C.

[0044] The present invention provides a 3D silicon-based capacitor. Figure 1 This is a cross-sectional schematic diagram of the 3D silicon-based capacitor provided by the present invention and a schematic diagram of the series connection between the first dielectric layer, the second dielectric layer and the dielectric connection layer inside the 3D silicon-based capacitor, Figure 1 The black arrows in FIG. 1 indicate the direction of the series connection between the first dielectric layer, the second dielectric layer, and the dielectric connection layer. Figure 1 As shown, on the one hand: the 3D silicon-based capacitor provided by the present invention is provided with a groove (groove) on the substrate layer, which increases the length of the first dielectric layer in the vertical direction, so that the effective area of ​​the capacitor of the first dielectric layer in the groove becomes larger, thereby increasing the effective area of ​​the capacitor per unit volume, improving the chip utilization rate, and increasing the capacitor capacitance density. On the other hand: in the present invention, the first dielectric layer and the second dielectric layer are connected in series to form a T-shaped capacitor, and the upper surface of the substrate layer of the present invention uses a dielectric connection layer to protect the inside of the device, and can also serve as a third dielectric layer to connect the first dielectric layer and the second dielectric layer in series, and the electrodes of the capacitor are distributed at both ends of the total dielectric layer (first dielectric layer, second dielectric layer and dielectric connection layer), so that the dielectric connection layer, the first dielectric layer and the second dielectric layer form an interconnected and uninterrupted overall continuous dielectric layer, thereby improving the chip utilization rate and increasing the capacitor capacitance density. In summary, the 3D silicon-based capacitor provided by the present invention, on the one hand, adopts a groove structure provided on the surface of the substrate layer to increase the effective capacitance area of ​​the capacitor plate, and on the other hand, adopts a series connection of dielectric layers to form a continuous three-dimensional vertical dielectric layer capacitor, which can significantly improve the chip utilization rate and increase the capacitor capacitance density. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic cross-sectional view of a 3D silicon-based capacitor provided by the present invention and a schematic diagram of the series connection between the first dielectric layer, the second dielectric layer, and the dielectric connection layer within the 3D silicon-based capacitor;

[0046] Figure 2 Schematic diagram of the structure of the groove on the substrate in an embodiment of the present invention;

[0047] Figure 3 This is a schematic structural diagram of a first polysilicon conductive layer prepared in an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of the structure of depositing a first dielectric film in an embodiment of the present invention;

[0049] Figure 5 A schematic structural diagram of a first semi-finished product prepared in accordance with an embodiment of the present invention;

[0050] Figure 6 A schematic structural diagram of a second semi-finished product prepared in accordance with an embodiment of the present invention;

[0051] Figure 7 A schematic structural diagram of a third semi-finished product prepared according to an embodiment of the present invention;

[0052] Figure 8 A schematic structural diagram of a fourth semi-finished product prepared according to an embodiment of the present invention;

[0053] Figure 9 A schematic structural diagram of a fifth semi-finished product prepared according to an embodiment of the present invention;

[0054] Figure 10 A schematic structural diagram of a sixth semi-finished product prepared according to an embodiment of the present invention;

[0055] Figure 11 This is a schematic diagram of the structure after the substrate is thinned in an embodiment of the present invention;

[0056] Figure 12 A schematic diagram of the structure of a 3D silicon-based capacitor prepared in an embodiment of the present invention;

[0057] In the figure: 1 is the substrate layer, 2 is the groove, 3a is the first polysilicon conductive layer, 3b is the second polysilicon conductive layer, 4a is the first dielectric layer, 4b is the second dielectric layer, 5 is the connecting layer, 6 is the dielectric connecting layer, 7 is the metal anode layer, and 8 is the metal cathode layer. DETAILED DESCRIPTION

[0058] The present invention provides a 3D silicon-based capacitor, comprising:

[0059] A substrate layer, wherein the upper surface of the substrate layer is inwardly recessed and has a plurality of grooves arranged in an array;

[0060] a first polysilicon conductive layer, wherein the first polysilicon conductive layer covers an upper surface of the substrate layer;

[0061] a first dielectric layer located on an upper surface of the first polysilicon conductive layer, the first dielectric layer comprising a plurality of first dielectric units arranged in an array and separated from each other, each first dielectric unit covering a position of the groove and extending out of the notch;

[0062] a second polysilicon conductive layer located on a portion of an upper surface of the first dielectric unit, the second polysilicon conductive layer comprising a plurality of second polysilicon conductive units arranged in an array, each of the second polysilicon conductive units filling a groove position of the first dielectric unit and extending out of the notch;

[0063] a second dielectric layer located on a portion of the upper surface of the first dielectric layer and a portion of the surface of the second polysilicon conductive layer, the second dielectric layer comprising a plurality of second dielectric units arranged in an array, each second dielectric unit having a first through hole defined at a position corresponding to the groove region;

[0064] a connection layer located on a portion of the upper surface of the first polysilicon conductive layer and a portion of the surface of the second dielectric layer, and in contact with a portion of the surface of the first dielectric layer, wherein the connection layer has a second through hole provided in a region corresponding to the first through hole, the second through hole being coaxial with the first through hole, and having a diameter greater than that of the first through hole;

[0065] a dielectric connection layer located on a portion of the upper surface of the first polysilicon conductive layer, a surface of the connection layer, and a portion of the upper surface of the second dielectric layer, wherein the dielectric connection layer is provided with a third through hole in a region corresponding to the first through hole, the third through hole being coaxial with the first through hole, and having a diameter smaller than that of the second through hole and greater than or equal to that of the first through hole;

[0066] a metal anode layer located on the upper surface of the dielectric connection layer, filling the area where the first through hole and the third through hole are formed, and contacting the upper surface of the portion of the second polysilicon conductive layer located at the bottom of the first through hole, wherein the metal anode layer is continuous;

[0067] A metal cathode layer is located on the lower surface of the substrate layer.

[0068] In the present invention, unless otherwise specified, all preparation raw materials / components are commercially available products well known to those skilled in the art.

[0069] The 3D silicon-based capacitor provided by the present invention includes a substrate layer, the upper surface of which is inwardly recessed and provided with a plurality of grooves arranged in an array. In the present invention, the substrate layer is preferably P-type low-resistivity conductive silicon or N-type low-resistivity conductive silicon; the resistivity of the substrate layer is preferably 0.002 to 0.004 ohm.cm; the crystal orientation of the substrate layer is preferably <100> ; The thickness of the substrate layer is preferably 100-150 μm. The shape of the groove is preferably circular, elliptical, rectangular, cross-shaped or clover-shaped. The aspect ratios of several of the grooves are preferably the same. The sizes of several of the grooves are preferably the same. In the present invention, the size of the groove is related to the process capability of the equipment and the capacity of the device design, and the process capability determines the size and depth of the groove. In a specific embodiment of the present invention, the side length of the rectangular groove is preferably 1-3 μm, and the diameter of the circular groove is preferably 1-3 μm. The depth of the groove is preferably 20-60 μm. In the present invention, the larger the design capacity of the device and the worse the process capability, the more groove arrays are required.

[0070] The 3D silicon-based capacitor provided by the present invention comprises a first polysilicon conductive layer, which covers the upper surface of the substrate layer. In the present invention, the first polysilicon conductive layer is preferably N-type doped low-resistivity polysilicon or P-type doped low-resistivity polysilicon; the thickness of the first polysilicon conductive layer is preferably The resistivity of the first polysilicon conductive layer is preferably less than or equal to 0.005 ohm.cm.

[0071] The 3D silicon-based capacitor provided by the present invention includes a first dielectric layer located on the upper surface of the first polysilicon conductive layer, the first dielectric layer is composed of a plurality of first dielectric units arranged in an array and separated from each other, each first dielectric unit covers the position of a groove and extends out of the notch. In the present invention, the material of the first dielectric layer preferably includes one or more of SiO2, Si3N4, HfO2, TiO2 and Al2O3. When the material of the first dielectric layer is preferably two or more of the above materials, it is a stack of film layers formed by the above materials respectively. The thickness of the first dielectric layer is preferably

[0072]

[0073] The 3D silicon-based capacitor provided by the present invention includes a second polysilicon conductive layer located on the upper surface of the first dielectric unit portion, the second polysilicon conductive layer is composed of a plurality of second polysilicon conductive units arranged in an array, each of the second polysilicon conductive units fills the groove position of a first dielectric unit and extends out of the notch. In the present invention, the second polysilicon conductive layer is preferably N-type doped low-resistivity polysilicon or P-type doped low-resistivity polysilicon; the thickness of the second polysilicon conductive layer is preferably The resistivity of the second polysilicon conductive layer (3b) is preferably less than or equal to 0.005 ohm.cm.

[0074] The 3D silicon-based capacitor provided by the present invention includes a second dielectric layer located on a portion of the upper surface of the first dielectric layer and a portion of the surface of the second polysilicon conductive layer. The second dielectric layer is composed of a plurality of second dielectric units arranged in an array, and each second dielectric unit is provided with a first through hole at a position corresponding to the groove area. In the present invention, the material of the second dielectric layer preferably includes one or more of SiO2, Si3N4, HfO2, TiO2 and Al2O3. When the material of the second dielectric layer is preferably two or more of the above materials, it is a stack of film layers formed by the above materials respectively. The thickness of the second dielectric layer is preferably

[0075] The 3D silicon-based capacitor provided by the present invention includes a connection layer located on a portion of the upper surface of the first polysilicon conductive layer and a portion of the surface of the second dielectric layer, and in contact with a portion of the surface of the first dielectric layer. The connection layer is provided with a second through-hole in a region corresponding to the first through-hole. The second through-hole is coaxial with the first through-hole, and the diameter of the second through-hole is greater than the diameter of the first through-hole. In the present invention, the connection layer is preferably metal Al, N-type doped low-resistivity polysilicon, or P-type doped low-resistivity polysilicon; the thickness of the metal Al is preferably 1000 to 3000 Å. The thickness of the N-type doped low-resistivity polysilicon or P-type doped low-resistivity polysilicon is preferably 1000 to 3000 Å, and the resistivity is less than or equal to 0.005 ohm.cm. As a specific embodiment of the present invention, the connection layer is metal Al.

[0076] In the present invention, when the connecting layer is metal Al, the first polysilicon conductive layer and the second polysilicon conductive layer are low-resistivity polysilicon of the same doping type, both being N-type doped or both being P-type doped. When the connecting layer is N-type doped low-resistivity polysilicon, the first polysilicon conductive layer and the second polysilicon conductive layer are both N-type doped low-resistivity polysilicon. When the connecting layer is P-type doped low-resistivity polysilicon, the first polysilicon conductive layer and the second polysilicon conductive layer are both P-type doped low-resistivity polysilicon.

[0077] The 3D silicon-based capacitor provided by the present invention includes a dielectric connection layer located on a portion of the upper surface of the first polysilicon conductive layer, the surface of the connection layer, and a portion of the upper surface of the second dielectric layer. The dielectric connection layer is provided with a third through hole in the area corresponding to the first through hole. The third through hole is coaxial with the first through hole, and the diameter of the third through hole is smaller than the diameter of the second through hole and greater than or equal to the diameter of the first through hole. In the present invention, the material of the dielectric connection layer is preferably silicon oxide or silicon nitride; the thickness of the dielectric connection layer is preferably

[0078] The 3D silicon-based capacitor provided by the present invention includes a metal anode layer located on the upper surface of the dielectric connection layer, filling the area formed by the first through hole and the third through hole, and contacting the upper surface of the second polysilicon conductive layer located at the bottom of the first through hole. The metal anode layer is continuous. In the present invention, the metal anode layer is preferably a multilayer film; the multilayer film preferably includes an Au film and a TiW film, or an Au film, a TiW film and a Ni film; the thickness of the Au film is greater than 2μm. The thickness of the TiW film or the Ni film is preferably As a specific embodiment of the present invention, along the aspect away from the upper surface of the substrate layer, the metal anode layer is a TiW film and an Au film stacked in sequence, or a TiW film, a Ni film and an Au film stacked in sequence.

[0079] The 3D silicon-based capacitor provided by the present invention includes a metal cathode layer located on the lower surface of the substrate layer. In the present invention, the metal cathode layer is preferably a multilayer film; the multilayer film preferably includes an Au film and a TiW film, or an Au film, a TiW film and a Ni film; the thickness of the Au film is preferably greater than 1 μm. The thickness of the TiW film or the Ni film is preferably As a specific embodiment of the present invention, along the aspect away from the lower surface of the substrate layer, the metal cathode layer is a TiW film and an Au film stacked in sequence, or a TiW film, a Ni film and an Au film stacked in sequence.

[0080] The present invention provides a method for preparing a 3D silicon-based capacitor according to the above technical solution, comprising the following steps:

[0081] Patterning the upper surface of the substrate to obtain grooves;

[0082] Depositing a first polysilicon thin film on the inner surface of the groove and the upper surface of the substrate except the groove, and then performing a first annealing process on the first polysilicon thin film after high-temperature doping or ion implantation to obtain a first polysilicon conductive layer;

[0083] depositing a first dielectric film on the surface of the first polysilicon conductive layer;

[0084] Depositing a second polysilicon film on the surface of the first dielectric film, then performing high-temperature doping or ion implantation on the second polysilicon film, followed by a second annealing process, and then performing a patterning process to obtain a second polysilicon conductive layer, thereby obtaining a first semi-finished product;

[0085] performing patterning on the first dielectric film of the first semi-finished product to obtain a first dielectric layer, thereby obtaining a second semi-finished product; depositing a second dielectric film on the surface of the second semi-finished product and performing patterning to obtain a second dielectric layer, thereby obtaining a third semi-finished product;

[0086] Alternatively, a second dielectric film is deposited on the surface of the first semi-finished product to obtain a second semi-finished product; the first dielectric film and the second dielectric film of the second semi-finished product are patterned to obtain a first dielectric layer and a second dielectric layer to obtain a third semi-finished product;

[0087] Depositing a connection layer thin film on the surface of the third semi-finished product, performing a third annealing treatment and then performing a patterning treatment to obtain a connection layer, thereby obtaining a fourth semi-finished product;

[0088] depositing a third dielectric film on the surface of the fourth semi-finished product, and obtaining a dielectric connection layer after patterning, thereby obtaining a fifth semi-finished product;

[0089] preparing a metal anode layer on the surface of the fifth semi-finished product to obtain a sixth semi-finished product;

[0090] The substrate is thinned to obtain a substrate layer, and a metal cathode layer is prepared on the lower surface of the substrate layer to obtain the 3D silicon-based capacitor.

[0091] The present invention performs patterning on the upper surface of the substrate to obtain grooves. The thickness of the substrate is preferably 300 to 600 μm. Before the patterning process, the present invention preferably performs polishing on both surfaces of the substrate. The patterning process preferably includes photolithography and dry deep silicon etching. In a specific embodiment of the present invention, the patterning process preferably includes: growing an oxide layer on the upper surface of the substrate, then coating a photoresist on the surface of the oxide layer, using the oxide layer and the photoresist as a hard mask and a soft mask respectively, then dry etching the grooves, and finally removing the mask layer, wherein the mask layer is the oxide layer and the photoresist.

[0092] After forming the groove, the present invention deposits a first polysilicon thin film on the inner surface of the groove and on the remaining upper surface of the substrate excluding the groove. The first polysilicon thin film is then subjected to high-temperature doping or ion implantation followed by a first annealing treatment to obtain a first polysilicon conductive layer. In the present invention, the deposition method for the first polysilicon thin film is preferably chemical vapor deposition. The holding temperature of the first annealing treatment is preferably ≥950°C to obtain a first low-resistivity doped polycrystalline conductive layer. The first low-resistivity doped polycrystalline conductive layer is the first polysilicon conductive layer.

[0093] After obtaining the first polysilicon conductive layer, the present invention deposits a first dielectric film on the surface of the first polysilicon conductive layer. The deposition method of the first dielectric film is preferably chemical vapor deposition.

[0094] After obtaining the first dielectric film, the present invention deposits a second polysilicon film on the surface of the first dielectric film, and then performs a second annealing treatment on the second polysilicon film after high-temperature doping or ion implantation, and then performs a patterning treatment to obtain a second polysilicon conductive layer, thereby obtaining a first semi-finished product. In the present invention, the deposition method of the second polysilicon film is preferably chemical vapor deposition. The holding temperature of the second annealing treatment is preferably ≥950°C. After the second annealing treatment and before performing the patterning treatment, the present invention preferably performs chemical mechanical polishing (CMP) on the product after the second annealing to obtain a second low-resistivity doped polycrystalline conductive layer. The second low-resistivity doped polycrystalline conductive layer is patterned to obtain the second polysilicon conductive layer.

[0095] After obtaining the first semi-finished product, the present invention performs patterning on the first dielectric film of the first semi-finished product to obtain a first dielectric layer, thereby obtaining a second semi-finished product; and depositing a second dielectric film on the surface of the second semi-finished product, performing patterning to obtain a second dielectric layer, thereby obtaining a third semi-finished product.

[0096] Alternatively, after obtaining the first semi-finished product, the present invention deposits a second dielectric film on the surface of the first semi-finished product to obtain a second semi-finished product; and patterning the first dielectric film and the second dielectric film of the second semi-finished product to obtain a first dielectric layer and a second dielectric layer to obtain a third semi-finished product.

[0097] In the present invention, when the first dielectric layer and the second dielectric layer are prepared, the etching in the patterning process is preferably dry etching.

[0098] After obtaining the third semi-finished product, the present invention deposits a connecting layer film on the surface of the third semi-finished product, performs a patterning process after the third annealing treatment, obtains a connecting layer, and obtains a fourth semi-finished product. In the present invention, the connecting layer film is preferably a metal Al film or a third polysilicon film. When the connecting layer film is a metal Al film, the holding temperature of the third annealing treatment is preferably 350 to 400°C. When the connecting layer film is a third polysilicon film, after obtaining the third polysilicon film, before performing the third annealing treatment, the present invention preferably further includes: high-temperature doping or ion implantation of the third polysilicon film; when the connecting layer film is a third polysilicon film, the holding temperature of the third annealing treatment is preferably ≥950°C.

[0099] After obtaining the fourth semi-finished product, the present invention deposits a third dielectric film on the surface of the fourth semi-finished product, obtains a dielectric connection layer after patterning, and obtains a fifth semi-finished product.

[0100] After obtaining the fifth semi-finished product, the present invention prepares a metal anode layer on the surface of the fifth semi-finished product to obtain a sixth semi-finished product.

[0101] After obtaining the sixth semi-finished product, the present invention preferably thins the substrate of the sixth semi-finished product to obtain a substrate layer, and forms a metal cathode layer on the lower surface of the substrate layer to obtain the 3D silicon-based capacitor. The thinning method is preferably chemical mechanical polishing (CMP). The metal cathode layer is preferably formed by evaporation or sputtering.

[0102] The photoresist used in the patterning process involved in the preparation method of the 3D silicon-based capacitor provided by the present invention is preferably a positive photoresist.

[0103] The 3D silicon-based capacitor provided by the present invention is a three-dimensional capacitor structure with a small occupied area and high unit volume utilization rate. It is suitable for semiconductor process technology and is conducive to device integration and miniaturization.

[0104] In order to further illustrate the present invention, the technical solutions provided by the present invention are described in detail below in conjunction with the embodiments, but they should not be construed as limiting the scope of protection of the present invention.

[0105] Example 1

[0106] Figure 1 A schematic cross-sectional view of the 3D silicon-based capacitor provided in this embodiment and a schematic diagram of the series connection between the first dielectric layer, the second dielectric layer, and the dielectric connection layer within the 3D silicon-based capacitor, Figure 1 The black arrows in FIG. 1 indicate the direction of the series connection between the first dielectric layer, the second dielectric layer, and the dielectric connection layer. Figure 1As shown, the 3D silicon-based capacitor provided in this embodiment includes: a substrate layer 1; a groove 2 (trench) located on the upper surface of the substrate layer 1; a first low-resistivity doped polycrystalline conductive layer (first polysilicon conductive layer 3a) formed on the surface of the substrate layer 1 and the bottom of the groove 2; a first dielectric layer 4a located on the first low-resistivity doped polycrystalline conductive layer; a second low-resistivity doped polycrystalline conductive layer (second polysilicon conductive layer 3b) located on the first dielectric layer; a second dielectric layer 4b located on the second low-resistivity doped polycrystalline conductive layer; a connecting layer 5 located on the second dielectric layer 4b, connected to the first low-resistivity doped polycrystalline conductive layer 3a and serving as an electrode plate of the second dielectric layer 4b; a dielectric connecting layer 6 located on the connecting layer 5; a device metal anode layer 7 located on the dielectric connecting layer 6; and a device metal cathode layer 8 located on the lower surface of the substrate after polishing and thinning.

[0107] The 3D silicon-based capacitor provided in this embodiment utilizes a larger effective capacitance area of ​​the first dielectric layer 4a within the trench 2, thereby increasing chip utilization and capacitance density. Furthermore, the first dielectric layer 4a and the second dielectric layer 4b are connected in series to form a T-shaped capacitor, which is also connected in series with the dielectric connection layer. This increases the vertical length of the dielectric layer, resulting in higher chip utilization and capacitance density.

[0108] Figures 2 to 12 This is a flow chart of the 3D capacitor preparation method provided in this embodiment. Figures 2 to 12 As shown, the preparation method provided in this embodiment includes the following steps:

[0109] The two surfaces of the silicon wafer (substrate) are polished, and an oxide layer is first grown before photolithography on the upper surface of the substrate, and then a photoresist (positive photoresist) is coated on the oxide layer. The oxide layer and the photoresist are used as a hard mask layer and a soft mask layer respectively, and then a dry Bosch process is used for deep silicon etching to form a uniform and continuous high aspect ratio trench 2. The shape of the trench 2 is circular, elliptical, rectangular, cross-shaped or clover-shaped. The specific shape of the trench 2 in this embodiment is as follows Figure 2 The dimensions and aspect ratios of the continuous trenches on the substrate are consistent.

[0110] In this embodiment, a doped low-resistivity polysilicon thin film conductive layer of a certain uniform thickness is formed on the surface of the substrate and the bottom of the trench by surface low-pressure chemical vapor deposition. The doped low-resistance polysilicon can be diffused and ion implanted at high temperature, and then annealed at a high temperature RTA of above 950°C. Figure 3 .

[0111] In this embodiment, a first dielectric film is formed on the top by surface low-pressure chemical vapor deposition and patterned etching. The first dielectric film can be composed of one or a combination of SiO2, Si3N4, HfO2, TiO2 or Al2O. The appropriate dielectric layer and dielectric layer combination are selected according to the breakdown field strength and capacitance density requirements, such as Figure 4 .

[0112] The present invention deposits a polysilicon film of a certain uniform thickness on top of the first dielectric film by surface low-pressure chemical vapor deposition. The doped low-resistance polysilicon film can be obtained by high-temperature diffusion and ion implantation, and annealed at RTA above 950°C. The obtained structure is chemically mechanically polished (CMP) and patterned to form a second low-resistivity polysilicon conductive layer, namely, the second polysilicon conductive layer 3b. Figure 5 .

[0113] The present invention etches the first dielectric film to facilitate the subsequent connection between the connecting layer 5 and the first polysilicon conductive layer 3a. Figure 6 .

[0114] The present invention deposits one or more of SiO2, Si3N4, HfO2, TiO2 or Al2O on the second polysilicon conductive layer 3b, and the patterned etching result is used as the second dielectric layer 4b. Figure 7 .

[0115] The connecting layer film of the present invention is a magnetron sputtered metal Al film or a chemical vapor deposited polysilicon film. The doped low-resistance polysilicon film can be obtained by high-temperature diffusion and ion implantation. When the connecting layer film is a metal Al film, the annealing temperature is 350-400°C and the holding time is 30 minutes. The connecting layer 5 forms an ohmic contact with the first polysilicon conductive layer 3a. When the connecting layer 5 is doped low-resistivity polysilicon, the annealing temperature is >950°C.

[0116] The present invention patterns the connecting layer film to form the connecting layer 5, such as Figure 8 .

[0117] The present invention deposits silicon oxide or silicon nitride on the surface by chemical vapor deposition, and etches to form an anode window to obtain a dielectric connection layer 6, such as Figure 9 .

[0118] The present invention forms a metal anode layer 7 by sputtering TiW / Au or TiW / Ni / Au or electroplating gold on the upper surface of the substrate. Figure 10 .

[0119] The present invention chemically mechanically polishes (CMP) the lower surface of the substrate to a thickness of 100 to 150 μm to obtain a substrate layer 1, such as Figure 11 .

[0120] In the present invention, gold is evaporated or sputtered on the lower surface of the substrate layer 1 to form another electrode of the capacitor, thereby obtaining a metal cathode layer 8. Figure 12 .

[0121] As can be seen from the above examples, the present invention, on the one hand, increases the effective capacitance area of ​​the capacitor plates by adding trench structures to the surface of the silicon substrate; on the other hand, it forms a three-dimensional vertical dielectric layer capacitor by connecting dielectric layers in series, thereby increasing chip utilization and capacitance density. Furthermore, the three-dimensional capacitor structure provided by the present invention occupies a small area and has a high unit volume utilization, making it suitable for semiconductor manufacturing processes and facilitating device integration and miniaturization.

[0122] Although the above embodiment provides a detailed description of the present invention, it is only a part of the embodiments of the present invention, not all of the embodiments. Other embodiments can be obtained based on this embodiment without creativity, and these embodiments all fall within the scope of protection of the present invention.

Claims

1. A 3D silicon-based capacitor, characterized in that: include: A substrate layer (1), wherein the upper surface of the substrate layer (1) is inwardly recessed and provided with a plurality of grooves (2) arranged in an array; a first polysilicon conductive layer (3a), the first polysilicon conductive layer (3a) covering the upper surface of the substrate layer (1); a first dielectric layer (4a) located on the upper surface of the first polysilicon conductive layer (3a), the first dielectric layer (4a) consisting of a plurality of first dielectric units arranged in an array and separated from each other, each first dielectric unit covering a groove position and extending out of the notch; a second polysilicon conductive layer (3b) located on the upper surface of the first dielectric unit portion, the second polysilicon conductive layer (3b) consisting of a plurality of second polysilicon conductive units arranged in an array, each of the second polysilicon conductive units filling a groove position of the first dielectric unit and extending out of the notch; a second dielectric layer (4b) located on a portion of the upper surface of the first dielectric layer (4a) and a portion of the surface of the second polysilicon conductive layer (3b), the second dielectric layer (4b) being composed of a plurality of second dielectric units arranged in an array, each second dielectric unit being provided with a first through hole at a position corresponding to the groove (2) region; a connection layer (5) located on a portion of the upper surface of the first polysilicon conductive layer (3a) and a portion of the surface of the second dielectric layer (4b), and in contact with a portion of the surface of the first dielectric layer (4a); the connection layer (5) is provided with a second through hole in a region corresponding to the first through hole, the second through hole and the first through hole being coaxial, and the diameter of the second through hole being greater than the diameter of the first through hole; a dielectric connection layer (6) located on a portion of the upper surface of the first polysilicon conductive layer (3a), a surface of the connection layer (5), and a portion of the upper surface of the second dielectric layer (4b), wherein the dielectric connection layer (6) is provided with a third through hole in a region corresponding to the first through hole, the third through hole and the first through hole being coaxial, and the diameter of the third through hole being smaller than the diameter of the second through hole and being greater than or equal to the diameter of the first through hole; a metal anode layer (7) located on the upper surface of the dielectric connection layer (6), filling the area formed by the first through hole and the third through hole, and contacting the upper surface of a portion of the second polysilicon conductive layer (3b) located on the bottom surface of the first through hole, wherein the metal anode layer (7) is continuous; A metal cathode layer (8) is located on the lower surface of the substrate layer (1).

2. The 3D silicon-based capacitor according to claim 1, wherein: The first polysilicon conductive layer (3a) is N-type doped low-resistivity polysilicon or P-type doped low-resistivity polysilicon; the thickness of the first polysilicon conductive layer (3a) is The resistivity of the first polysilicon conductive layer (3a) is less than or equal to 0.005 ohm.cm.

3. The 3D silicon-based capacitor according to claim 1, wherein: The second polysilicon conductive layer (3b) is N-type doped low-resistivity polysilicon or P-type doped low-resistivity polysilicon; the thickness of the second polysilicon conductive layer (3b) is The resistivity of the second polysilicon conductive layer (3b) is less than or equal to 0.005 ohm.cm.

4. The 3D silicon-based capacitor according to claim 1, wherein: The connecting layer (5) is metal Al, N-type doped low-resistivity polysilicon or P-type doped low-resistivity polysilicon; the thickness of the metal Al is The thickness of the N-type doped low-resistivity polysilicon or the P-type doped low-resistivity polysilicon is Resistivity is less than or equal to 0.005ohm.cm.

5. The 3D silicon-based capacitor according to any one of claims 1 or 4, characterized in that: When the connecting layer (5) is metal Al, the first polysilicon conductive layer (3a) and the second polysilicon conductive layer (3b) are low-resistivity polysilicon of the same doping type, both being N-type doped or both being P-type doped; When the connecting layer (5) is N-type doped low-resistivity polysilicon, the first polysilicon conductive layer (3a) and the second polysilicon conductive layer (3b) are both N-type doped low-resistivity polysilicon; When the connecting layer (5) is P-type doped low-resistivity polysilicon, the first polysilicon conductive layer (3a) and the second polysilicon conductive layer (3b) are both P-type doped low-resistivity polysilicon.

6. The 3D silicon-based capacitor according to claim 1, wherein: The substrate layer (1) is P-type low-resistivity conductive silicon or N-type low-resistivity conductive silicon; the resistivity of the substrate layer (1) is 0.002-0.004 ohm.cm; the crystal orientation of the substrate layer (1) is <100> ; The thickness of the substrate layer (1) is 100 to 150 μm.

7. The 3D silicon-based capacitor according to claim 1, wherein: The materials of the first dielectric layer (4a) and the second dielectric layer (4b) independently include one or more of SiO2, Si3N4, HfO2, TiO2 and Al2O3.

8. The 3D silicon-based capacitor according to claim 1 or 3, characterized in that: The thickness of the first dielectric layer (4a) and the second dielectric layer (4b) are independently 9. The 3D silicon-based capacitor according to claim 1, wherein: The material of the dielectric connection layer (6) is silicon oxide or silicon nitride; the thickness of the dielectric connection layer (6) is 10. The 3D silicon-based capacitor according to claim 1, wherein: The metal anode layer (7) is a multilayer film; the multilayer film includes an Au film and a TiW film, or an Au film, a TiW film and a Ni film; the thickness of the Au film is greater than 2 μm.

11. The 3D silicon-based capacitor according to claim 1, wherein: The metal cathode layer (8) is a multilayer film; the multilayer film includes an Au film and a TiW film, or an Au film, a TiW film and a Ni film; the thickness of the Au film is greater than 1 μm.

12. The method for preparing a 3D silicon-based capacitor according to any one of claims 1 to 11, characterized in that: The following steps are involved: Patterning the upper surface of the substrate to obtain a groove (2); Depositing a first polysilicon thin film on the inner surface of the groove (2) and the upper surface of the substrate other than the groove (2), then subjecting the first polysilicon thin film to high-temperature doping or ion implantation and then to a first annealing treatment to obtain a first polysilicon conductive layer (3a); depositing a first dielectric film on the surface of the first polysilicon conductive layer (3a); Depositing a second polysilicon film on the surface of the first dielectric film, then performing high-temperature doping or ion implantation on the second polysilicon film, followed by a second annealing process, and then performing a patterning process to obtain a second polysilicon conductive layer (3b), thereby obtaining a first semi-finished product; The first dielectric film of the first semi-finished product is subjected to patterning treatment to obtain a first dielectric layer (4a), thereby obtaining a second semi-finished product; a second dielectric film is deposited on the surface of the second semi-finished product and subjected to patterning treatment to obtain a second dielectric layer (4b), thereby obtaining a third semi-finished product; Depositing a connection layer thin film on the surface of the third semi-finished product, performing a third annealing treatment and then performing a patterning treatment to obtain a connection layer (5), thereby obtaining a fourth semi-finished product; Depositing a third dielectric film on the surface of the fourth semi-finished product, patterning the film to obtain a dielectric connection layer (6), thereby obtaining a fifth semi-finished product; preparing a metal anode layer (7) on the surface of the fifth semi-finished product to obtain a sixth semi-finished product; The substrate is thinned to obtain a substrate layer (1), and a metal cathode layer (8) is prepared on the lower surface of the substrate layer (1) to obtain the 3D silicon-based capacitor.

13. The preparation method according to claim 12, characterized in that After obtaining the first semi-finished product, the preparation method of the third semi-finished product is replaced by: A second dielectric film is deposited on the surface of the first semi-finished product to obtain a second semi-finished product; the first dielectric film and the second dielectric film of the second semi-finished product are patterned to obtain a first dielectric layer (4a) and a second dielectric layer (4b), thereby obtaining a third semi-finished product.

14. The preparation method according to claim 12, characterized in that The connecting layer film is a metal Al film or a third polysilicon film; When the connecting layer film is a metal Al film, the holding temperature of the third annealing treatment is 350-400° C.; When the connecting layer thin film is a third polysilicon thin film, after the third polysilicon thin film is obtained and before the third annealing treatment is performed, the method further includes: performing high-temperature doping or ion implantation on the third polysilicon thin film; when the connecting layer thin film is the third polysilicon thin film, the holding temperature of the third annealing treatment is ≥950°C; The holding temperature of the first annealing treatment and the second annealing treatment is ≥950°C.

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