A weak optical communication frame synchronization method and system suitable for clock synchronization failure

Abstract

The present invention discloses a frame synchronization method and system for weak optical communication applicable to clock synchronization failure, wherein the method steps include: designing a frame structure for a weak optical communication system in which clock synchronization fails; sampling the weak optical communication signal received by the weak optical communication system based on the designed frame structure to obtain a sampling result; searching for an optimal start sequence based on the sampling result; and completing frame synchronization based on the optimal start sequence. The present invention provides an efficient frame synchronization method and system for searching for synchronization positions based on a fixed frame bit sequence and a reward and punishment mechanism. The present invention can be used for scenarios in which clock synchronization fails in weak optical communication systems; at the same time, the designed synchronization frame length is relatively low, and does not require large hardware resources.

Description

Technical Field

[0001] The present invention belongs to the technical field of optical communications, and in particular relates to a weak optical communication frame synchronization method and system applicable to clock synchronization failure. Background Art

[0002] Weak-light communication systems (such as deep-space optical communications, underwater optical communications, and ultraviolet optical communications) typically use photon counters or photon-counting devices similar to photomultiplier tubes as receivers. Because the received light intensity signal is extremely weak, it must be represented by a discrete number of photons, making it impossible for the receiver to detect a continuous waveform. Traditional clock synchronization is difficult in this situation, and time synchronization of the received signal can only be achieved through specialized frame synchronization schemes. Therefore, a frame synchronization scheme with high tolerance to clock errors is needed. Summary of the Invention

[0003] In order to solve the technical problems in the above background, the present invention proposes an efficient frame synchronization method for searching the synchronization position based on a fixed frame bit sequence and a reward and punishment mechanism. First, the frame structure sent by the system consists of three parts: a frame header, information data and a frame tail. An irregular pilot signal is designed as a synchronization frame header. After the signal is received, the number of photons received within a single bit time is weighted at each sampling point starting from the moment of reception. The weight of the sampling point corresponding to the bit value of 1 is 1 (reward), and conversely, the weight of the sampling point corresponding to the bit value of 0 is -1 (penalty). The total number of weighted sampling points each time is the product of the number of frame header bits and the number of single-bit sampling points. Then, the time of the weighted sampling point is continuously postponed, and the weighted results are compared to search for an optimal starting time as the synchronization start time, ultimately achieving efficient frame synchronization of the weak optical communication link.

[0004] To achieve the above object, the present invention provides a weak optical communication frame synchronization method applicable to clock synchronization failure, comprising the following steps:

[0005] Design frame structure for weak optical communication systems with clock synchronization failure;

[0006] Based on the designed frame structure, the weak light communication signal received by the weak light communication system is sampled to obtain a sampling result;

[0007] Based on the sampling results, searching for an optimal starting sequence;

[0008] Based on the optimal start sequence, frame synchronization is completed.

[0009] Preferably, the frame length in the designed frame structure satisfies:

[0010]

[0011] Where L represents the frame length; e clock is the clock crystal oscillator error, unit: ppm; ebit Indicates the number of bits allowed to mismatch in each frame, and represents the frame synchronization scheme's tolerance to clock errors.

[0012] Preferably, in the designed frame structure, the pilot sequence is composed of a sequence alternating between 0 and 1, and the structure of the pilot sequence satisfies that the number of bit 1s in the sequence obtained by performing a bitwise AND operation on the sequence and its shift sequence is less than the number of bit 1s in the pilot sequence.

[0013] Preferably, discrete photoelectrons are used to characterize the received weak optical communication signal, and the number of photoelectrons detected within each bit duration follows a Poisson distribution.

[0014] Preferably, after receiving the weak optical communication signal, starting from the moment of reception, the number of photons received within a single bit time is weighted at each sampling point; sampling is performed based on the designed pilot sequence, and the sampling method includes:

[0015] When the pilot bit value corresponding to the sampling point is 1, the corresponding weight is 1. When the pilot bit value is 1, the corresponding weight is -1. The total number of weighted sampling points each time is the product of the number of frame header bits and the number of single-bit sampling points. Finally, the weighted result will be obtained.

[0016] The present invention also provides a weak optical communication frame synchronization system suitable for clock synchronization failure, the system is used to implement the above method, including: a design module, a sampling module, a search module and a synchronization module;

[0017] The design module is used to design a frame structure for a weak optical communication system with clock synchronization failure;

[0018] The sampling module is used to sample the weak light communication signal received by the weak light communication system based on the designed frame structure to obtain a sampling result;

[0019] The search module is used to search for an optimal start sequence based on the sampling result;

[0020] The synchronization module is used to complete frame synchronization based on the optimal start sequence.

[0021] Preferably, the frame length in the designed frame structure satisfies:

[0022]

[0023] Where L represents the frame length; e clock is the clock crystal oscillator error, unit: ppm; e bit Indicates the number of bits allowed to mismatch in each frame, and represents the frame synchronization scheme's tolerance to clock errors.

[0024] Preferably, in the designed frame structure, the pilot sequence is composed of a sequence alternating between 0 and 1, and the structure of the pilot sequence satisfies that the number of bit 1s in the sequence obtained by performing a bitwise AND operation on the sequence and its shift sequence is less than the number of bit 1s in the pilot sequence.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] This invention provides an efficient frame synchronization method and system for searching for synchronization positions based on a fixed frame bit sequence and a reward and penalty mechanism. This invention can address clock synchronization failure scenarios in weak optical communication systems. The designed synchronization frame length is relatively low, eliminating the need for significant hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 Schematic diagram of a method flow in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the received photon count results according to an embodiment of the present invention;

[0030] Figure 3 This is a simulation diagram showing how the weighted value changes with the start time during synchronization according to an embodiment of the present invention;

[0031] Figure 4 FIG. 4 is a diagram showing how synchronization performance varies with transmit power according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] Example 1

[0035] like Figure 1 FIG. 1 is a flow chart of the method of this embodiment, and the steps include:

[0036] S1. Design a frame structure for a weak optical communication system with clock synchronization failure.

[0037] In the case of clock synchronization failure in a weak optical communication system (hereinafter referred to as the communication system), the design of its frame structure needs to consider the impact of clock error. The design of the frame length must take into account the clock error of the device. The signal rate is R, the frame length is L, and each frame has a certain cumulative error. In order to ensure that the accumulated error of one frame length does not cross the frame header of the next frame when waiting for a certain period of time to synchronize again during the subsequent synchronization calculation process, the frame length L needs to meet the following requirements:

[0038]

[0039] Where, e clock is the clock crystal oscillator error, unit: ppm; e bit Indicates the number of bits allowed to mismatch in each frame, which characterizes the fault tolerance of the frame synchronization scheme to clock errors. For example, if the simulation uses an RTC clock crystal with a frequency accuracy of ±5ppm and requires that the number of mismatched bits in each frame cannot exceed 0.1 bits, then e clock 5ppm, e bit is 0.1. Simplifying the above formula, we can finally get the frame length L that needs to satisfy:

[0040]

[0041] Based on this frame length, the frame structure designed in this embodiment is shown in Table 1. The sequences on either side of the information data portion are the frame header and frame trailer, respectively. The pilot signal is used as the data frame header for synchronization, with a length of N1, while the frame trailer serves as a guard interval with a length of N2.

[0042] Table 1

[0043] <![CDATA[Synchronous frame header N1]]> <![CDATA[Information data L-N1-N2]]> <![CDATA[All-zero frame tail N2]]>

[0044] In the designed frame structure, the pilot sequence consists of a sequence alternating between 0s and 1s. The structure of this pilot sequence must satisfy the following requirement: the number of 1 bits in the sequence obtained by bitwise ANDing this sequence with its shifted version is significantly smaller than the number of 1 bits in the original pilot sequence. This means that when this sequence is bitwise ANDed with any of its own shifted versions (i.e., a new sequence obtained by shifting each element in the sequence a certain number of positions to the left or right), the resulting number of 1 bits should be significantly smaller than the number of 1 bits in the original pilot sequence. This design improves the recognizability of the synchronization signal, making it easier for the receiver to lock onto the correct synchronization position by identifying the difference between the pilot sequence and its shifted version.

[0045] S2. Based on the designed frame structure, the weak light communication signal received by the weak light communication system is sampled to obtain a sampling result.

[0046] Set T b Indicates bit duration, each bit is sampled n times during the duration, and the duration of each sampling point is After sampling, the number of photons corresponding to each sampling time is obtained. Figure 2 The figure shows the number of photons received by the PMT after the weak optical signal is attenuated by the channel. The signal rate is 1Mbps, the sampling rate is 250Mbps, the transmission power is 200mW, the path loss is 85dB, and the average photon number of the background noise is λ. b =1.

[0047] And by Figure 2 This indicates that when a communication system's transmitter transmits a synchronization signal using OOK modulation, the weak optical signal attenuates through the channel, leaving the signal received by the communication system's receiver with discrete characteristics. Therefore, due to the extremely weak light intensity, the signal received by the communication system can be characterized by discrete photons.

[0048] The number of photoelectrons detected within each bit duration follows a Poisson distribution. Let represent the bit duration, the number of samples within each bit duration, and the duration of each sampling point. After sampling, the number of photons corresponding to each sampling time is obtained, and the sampling result is obtained.

[0049] Depend on Figure 3 The following is a simulation diagram of the weighted value changing with the start time during synchronization. Among them, the signal rate is 1Mbps, the sampling rate is 250Mbps, the path loss is 85dB, and the average number of photons in the background noise is λ b =1, synchronization frame header length N1 = 32 bits, frame tail length N2 = 16 bits. The pilot sequence is designed as {1,0,1,0,0,1,0,0,0,1,0,0,0,0,1,0,0,0,0,0,1,1,0,1,1,0,0,0,0,0,0}. In this embodiment, there is a 100-bit no-signal transmission state before the frame is sent. Figure 3 The weighted value reaches its highest value around 100 bits and a significant peak appears, which is the synchronization moment.

[0050] S3. Based on the sampling results, search for the optimal starting sequence.

[0051] After the signal is received, starting from the reception time t=t0, the number of photons received within a single bit time is weighted at each sampling point. For the pilot sequence designed in the above steps, sampling is performed according to the following rules: if the pilot bit value corresponding to the sampling point is 1, the corresponding weight is 1 (reward); if the pilot bit value is 1, the corresponding weight is -1 (penalty); the total number of weighted sampling points each time is the product of the number of frame header bits and the number of single-bit sampling points, and the weighted result will be obtained in the end. Then, the sampling point time for starting weighting is continuously postponed, and the weighting is restarted each time the time of one code chip is postponed. Finally, the weighted results are compared. As Figure 2 As shown in Figure 1, the weighted value changes with the start time during synchronization, reaching a maximum value with a sharp peak when reaching the synchronization position. When the weighted result exceeds a certain threshold for the first time and reaches a peak within a certain range, it is determined to be the optimal start sequence time, i.e., the synchronization position.

[0052] S4. Complete frame synchronization based on the optimal start sequence.

[0053] After the first synchronization is successful, wait until there is one bit duration left before the end of one frame, and then perform the next synchronization; the duration of one bit is Second.

[0054] like Figure 4 The figure shows the synchronization performance changing with the transmission power. Among them, the signal rate is 1Mbps, the sampling rate is 250Mbps, the path loss is 85dB, and the average number of photons in the background noise is λ b =1, synchronization frame header length N1 = 32 bits, frame tail length N2 = 16 bits. The pilot sequence is designed to be {1,0,1,0,0,1,0,0,0,1,0,0,0,0,1,0,0,0,0,0,1,1,0,1,1,0,0,0,0,0,0}. Clock crystal oscillator error e clock =5ppm, the number of mismatched bits allowed in each frame is e bit =0.1. Figure 4 It can be seen that when the signal attenuation level remains unchanged, as the signal transmission power increases, the synchronization performance gradually improves, and a high success rate can still be achieved even when the light intensity is extremely weak.

[0055] Example 2

[0056] The present invention also provides a weak light communication frame synchronization system suitable for clock synchronization failure, comprising: a design module, a sampling module, a search module and a synchronization module; the design module is used to design a frame structure for the weak light communication system with clock synchronization failure; the sampling module is used to sample the weak light communication signal received by the weak light communication system based on the designed frame structure to obtain a sampling result; the search module is used to search for an optimal start sequence based on the sampling result; and the synchronization module is used to complete frame synchronization based on the optimal start sequence.

[0057] The frame length in the designed frame structure satisfies:

[0058]

[0059] Where L represents the frame length; e clock is the clock crystal oscillator error, unit: ppm; e bit Indicates the number of bits allowed to mismatch in each frame, and represents the frame synchronization scheme's tolerance to clock errors.

[0060] In the designed frame structure, the pilot sequence consists of a sequence alternating between 0s and 1s. The structure of the pilot sequence satisfies the following requirement: the number of bits 1 in the sequence obtained by performing a bitwise AND operation on the pilot sequence and its shifted sequence is much smaller than the number of bits 1 in the original pilot sequence.

[0061] The embodiments described above are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by persons skilled in the art should fall within the scope of protection defined by the claims of the present invention.

Claims

1. A weak light communication frame synchronization method suitable for clock synchronization failure, characterized in that the steps include: Design a frame structure for a weak optical communication system with clock synchronization failure. The frame length in the designed frame structure meets the following requirements: Where L represents the frame length; e clock is the clock crystal oscillator error, unit: ppm; e bit Indicates the number of bits allowed to mismatch in each frame, characterizing the frame synchronization scheme's tolerance to clock errors. In the designed frame structure, the pilot sequence consists of a sequence alternating between 0s and 1s. The structure of the pilot sequence satisfies the following conditions: the number of 1 bits in the sequence obtained by performing a bitwise AND operation on the pilot sequence and its shifted sequence is less than the number of 1 bits in the pilot sequence. Based on the designed frame structure, the weak light communication signal received by the weak light communication system is sampled to obtain a sampling result; Based on the sampling results, an optimal starting sequence is searched; the steps include: after receiving a weak optical communication signal, starting from the moment of reception, weighting the number of photons received within a single bit time at each sampling point; sampling based on a designed pilot sequence, wherein the sampling method includes: when the pilot bit value corresponding to the sampling point is 1, the corresponding weight is 1; when the pilot bit value is -1, the corresponding weight is -1, and the total number of weighted sampling points each time is the product of the number of frame header bits and the number of single-bit sampling points, and finally a weighted result is obtained; then, the sampling point time for starting weighting is continuously postponed, and the weighting is restarted each time the sampling point time is postponed by one code chip time; Based on the optimal start sequence, frame synchronization is completed.

2. The weak optical communication frame synchronization method applicable to clock synchronization failure according to claim 1, characterized in that: Discrete photoelectrons are used to characterize the received weak optical communication signal, and the number of photoelectrons detected within each bit duration follows a Poisson distribution.

3. A weak optical communication frame synchronization system suitable for clock synchronization failure, the system is used to implement the method according to any one of claims 1-2, characterized in that: include: Design module, sampling module, search module and synchronization module; The design module is used to design a frame structure for a weak optical communication system with clock synchronization failure; the frame length in the designed frame structure satisfies: Where L represents the frame length; e clock is the clock crystal oscillator error, unit: ppm; e bit Indicates the number of bits allowed to mismatch in each frame, characterizing the frame synchronization scheme's tolerance to clock errors. In the designed frame structure, the pilot sequence consists of a sequence alternating between 0s and 1s. The structure of the pilot sequence satisfies the following conditions: the number of 1 bits in the sequence obtained by performing a bitwise AND operation on the pilot sequence and its shifted sequence is less than the number of 1 bits in the pilot sequence. The sampling module is used to sample the weak light communication signal received by the weak light communication system based on the designed frame structure to obtain a sampling result; The search module is used to search for an optimal start sequence based on the sampling result. The process includes: after receiving the weak optical communication signal, starting from the moment of reception, weighting the number of photons received in a single bit time at each sampling point; sampling based on the designed pilot sequence, the sampling method includes: when the pilot bit value corresponding to the sampling point is 1, the corresponding weight is 1, when the pilot bit value is -1, the corresponding weight is -1, the total number of weighted sampling points each time is the product of the number of frame header bits and the number of single-bit sampling points, and finally a weighted result is obtained; then the sampling point time for starting weighting is continuously postponed, and the weighting is restarted each time the sampling point time is postponed by one code chip time; The synchronization module is used to complete frame synchronization based on the optimal start sequence.

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