Reading margin parameter extraction method and guiding optimization memory method and device

Abstract

The application provides a read margin parameter extraction method and a guidance optimization memory method and device. The read margin parameter extraction method comprises the following steps: obtaining a test data set of a memory cell set of a memory; the test data set comprises statistical characteristics of test parameters of the memory cell set, and the statistical characteristics of the test parameters reflect storage state fluctuations of the memory cell set; a memory feature set of the memory cell set under different storage conditions is extracted; according to the memory feature set, the statistical characteristics of the test parameters are statistically distributed and superimposed to obtain storage state statistical characteristics of the memory cell set; and read margin parameters are extracted according to the storage state statistical characteristics and a decision threshold set. The application comprehensively scans a test data set of a memory device, analyzes read margin characteristic responses of the memory device under different storage conditions, and finds a global optimal decision threshold, so that the read accuracy of the memory is optimal.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory technology, in particular to a read margin parameter extraction method and a guiding optimization memory method and device. BACKGROUND

[0002] Memory constitutes an important component of digital systems such as computers. Among them, semiconductor memory is a storage device manufactured based on semiconductor materials, and the basic unit of composition is a storage unit. A plurality of storage units are arranged to form a storage array, and the storage array is further organized into a Bank. A plurality of Banks are further combined into a Bank Group to provide greater storage capacity and higher performance. These Bank Groups and other necessary circuit elements are integrated together in a memory chip to form the memory device we actually use.

[0003] Among the various levels of memory devices, due to the influence of non-ideal factors such as PVT (process, voltage, temperature) fluctuations, the physical value reflected by the storage state of the storage unit will exhibit a specific statistical distribution characteristic. When different read methods are implemented on the same storage array set under the same conditions of memory device process, working environment, etc., due to the overlap of the statistical distribution of the storage state, i.e., the overlapping part of the physical value range of different storage states, it makes the read decision becomes difficult when using the read decision threshold for decision. Because the read decision needs to judge whether the storage unit is in the "0" state or the "1" state according to the physical value, if the physical value range of the two states has overlap, it may lead to misjudgment.

[0004] In the read process of the memory, the read margin can reflect the degree of overlap of the statistical distribution of the values under different storage states in the read method, which determines the probability of errors caused by decision in the read process, and further reflects the accuracy and stability of the read operation on data, and thus is an important parameter for measuring the stability and reliability of the memory read.

[0005] Among the technologies known to the inventor, the invention patent with the patent number CN101458954A proposes a scheme to correct different storage state errors to increase the read margin and improve the reliability of semiconductor memory. However, this method is suitable for a specific type of memory or specific operating conditions, and different correction strategies are needed for different types of memory or different working environments, so it is subject to certain limitations. SUMMARY

[0006] The application provides a read margin parameter extraction method and device, solves the problem of limited read margin parameter extraction for different types of memories or different working environments, and provides a read margin parameter guiding memory optimization method and device on this basis.

[0007] To achieve the above object, the application adopts the following technical solutions:

[0008] In a first aspect, a read margin parameter extraction method is provided, including the following steps:

[0009] Obtaining a test data set of a memory cell set of a memory; wherein the test data set includes statistical characteristics of test parameters of the memory cell set, and the statistical characteristics of the test parameters reflect storage state fluctuations of the memory cell set;

[0010] Extracting a memory feature set of the memory cell set under different storage conditions based on the test data set; wherein a memory feature refers to a mapping relationship between the statistical characteristics of the test parameters and the storage state fluctuation characteristics;

[0011] According to the memory feature set, the statistical distribution of the statistical characteristics of the test parameters is superimposed to obtain storage state statistical characteristics of the memory cell set;

[0012] According to the storage state statistical characteristics and a decision threshold set, a read margin parameter is extracted.

[0013] In a first possible implementation manner of the first aspect, the memory cell of the memory includes a transistor with extremely low leakage current, the memory cell stores a charge amount in the gate terminal of one of the transistors, the memory cell has at least two storage states, the storage states are mapped to different charge amounts stored in the memory cell, the memory cell has quasi-non-volatility, that is, the retention time of the stored charge amount is greater than one hundred seconds, and the storage states fluctuate;

[0014] A plurality of the memory cells form a memory cell set;

[0015] The reading of the stored charge amount is implemented by applying a voltage to the source-drain terminal of the transistor and then reading the corresponding source-drain current.

[0016] Based on any one of the possible implementation manners of the first aspect, in a second possible implementation manner of the first aspect, the sources of the storage state fluctuations include at least one of the following factors: storage condition change, parasitic effect, manufacturing process non-uniformity, noise and read string interference;

[0017] The storage condition includes temperature, process, working voltage, storage state holding time, and selection of storage state value of the storage unit.

[0018] In any of the possible implementation manners of the first aspect, in a third possible implementation manner of the first aspect, the test data set of the storage unit set of the memory is obtained, including the following steps:

[0019] The test process is performed under different conditions of the test target and environment, test conditions and object test parameters are set, and a test method is selected.

[0020] The test process is performed on the storage unit set under the test conditions, and statistical characteristics of the test parameters are obtained.

[0021] The test method includes simulation and actual measurement of the storage circuit or integrated circuit device, and the test parameters include voltage, current, capacitance, resistance, and conductance.

[0022] The test data set includes a parameter curve describing the parameter composition of the memory.

[0023] In any of the possible implementation manners of the first aspect, in a fourth possible implementation manner of the first aspect, the read margin parameter is extracted according to the storage state statistical characteristics and the decision threshold set, specifically including the following steps:

[0024] The decision threshold set is set according to the storage state statistical characteristics, and each storage state corresponds to at least one decision threshold region.

[0025] For each storage state, the corresponding read margin is calculated according to the set decision threshold set and the storage state statistical characteristics, and a decision read margin set is obtained based on the read margins of all storage states.

[0026] The read margin parameter is obtained based on the decision read margin set, and the read margin parameter is the minimum value in the decision read margin set under the same group of storage states.

[0027] The second aspect provides a read margin parameter extraction device, including:

[0028] The data acquisition module is configured to obtain a test data set of a storage unit set of a memory. The test data set includes statistical characteristics of test parameters of the storage unit set, and the statistical characteristics of the test parameters reflect fluctuations in storage states of the storage unit set.

[0029] a memory feature extraction module configured to extract a memory feature set of the memory cell set under different storage conditions based on the test data set, wherein the memory feature refers to a mapping relationship between a statistical characteristic of the test parameter and the storage state fluctuation feature;

[0030] a storage state statistical characteristic base calculation module configured to superimpose a statistical distribution of the statistical characteristic of the test parameter according to the memory feature set to obtain a storage state statistical characteristic of the memory cell set;

[0031] a read margin parameter extraction module configured to extract a read margin parameter according to the storage state statistical characteristic and a decision threshold set.

[0032] In a third aspect, a read margin parameter guided optimization memory method is provided, including the following steps:

[0033] extracting a statistical characteristic set of the storage state of the memory cell set within a retention time, wherein the retention time is a time period during which data is stored and kept valid;

[0034] providing an alternative decision threshold set through the statistical characteristic set, wherein the alternative decision threshold set is determined by a maximum likelihood function of the statistical characteristic set of the storage state within the retention time under different storage conditions;

[0035] extracting an optimal decision threshold set based on the alternative decision threshold set, wherein the optimal decision threshold set makes the read margin response feature of the memory cell within the retention time optimal; the read margin response feature reflects a response degree of the memory read margin parameter under different decision thresholds;

[0036] determining a global optimal decision threshold according to the optimal decision threshold set.

[0037] In a first possible implementation manner of the third aspect, the read margin parameter guided optimization memory method further includes the following steps:

[0038] specifying the global optimal decision threshold;

[0039] extracting a main source of the storage state fluctuation according to the memory feature set;

[0040] implementing different suppression methods on the main source of the storage state fluctuation;

[0041] extracting a corresponding read margin parameter for each of the suppression methods;

[0042] evaluating an effect of the corresponding suppression method through the read margin parameter;

[0043] The method for suppressing the best corresponding read margin parameter is the best method for suppressing the main source of the storage state fluctuation.

[0044] According to any one of the possible implementation manners of the third aspect, in a second possible implementation manner of the third aspect, the global optimal decision threshold is determined according to the optimal decision threshold set, and specifically includes the following steps:

[0045] A set of storage conditions and a set of alternative decision thresholds are specified.

[0046] A read margin response feature evaluation model is established.

[0047] Each alternative decision threshold is applied to the set of storage units, and a read margin response feature is extracted, to obtain a set of alternative decision threshold read margin response features.

[0048] The evaluation model is input with the set of storage conditions and the set of alternative decision thresholds and the corresponding set of read margin response features, and outputs an alternative decision threshold that matches the optimal read margin response feature as the global optimal decision threshold.

[0049] In a fourth aspect, a read margin parameter guided optimization memory device is provided, including:

[0050] A statistical property extraction module is configured to extract a set of statistical properties of storage states of a set of storage units within a retention time, wherein the retention time is a time period during which data is stored and kept valid.

[0051] An alternative decision threshold determination module is configured to provide a set of alternative decision thresholds based on the set of statistical properties, wherein the set of alternative decision thresholds is determined by a maximum likelihood function of the set of statistical properties of storage states within the retention time under different storage conditions.

[0052] An optimal decision threshold determination module is configured to extract a set of optimal decision thresholds based on the set of alternative decision thresholds, wherein the set of optimal decision thresholds makes the read margin response feature of the set of storage units within the retention time optimal; and the read margin response feature reflects the response degree of the memory read margin parameter under different decision thresholds.

[0053] A global optimal decision threshold determination module is configured to determine a global optimal decision threshold based on the set of optimal decision thresholds.

[0054] In a fifth aspect, an electronic device is provided, including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the computer program is executed by the processor to implement the steps of the read margin parameter extraction method or the read margin parameter guided optimization memory method.

[0055] Compared with the related art known to the inventors, the present application provides a read margin parameter extraction method, and applies the read margin parameter to guide optimization of a semiconductor memory. By comprehensively scanning a test data set of a memory device, a read margin parameter is extracted after fitting a test data set statistical characteristic according to a memory device feature set; and read margin response characteristics of the memory device under different storage conditions are analyzed to find a globally optimal decision threshold, so that the read accuracy of the memory is optimal. Meanwhile, the present application evaluates the main source of the storage state fluctuation through the memory device feature set, guides improvement of the device process and circuit design performance of the memory, and is a new, reliable and feasible means, which helps to meet the performance requirements of the memory device in various application scenarios, and has important significance for improving the performance and reliability of the memory device. BRIEF DESCRIPTION OF DRAWINGS

[0056] Figure 1 A schematic flow chart of a read margin parameter extraction method according to an embodiment of the present application is provided.

[0057] Figure 2 A schematic flow chart of another read margin parameter extraction method according to an embodiment of the present application is provided.

[0058] Figure 3 A schematic flow chart of still another read margin parameter extraction method according to an embodiment of the present application is provided.

[0059] Figure 4 A schematic flow chart of a read margin parameter guided optimization memory method according to an embodiment of the present application is provided.

[0060] Figure 5 A schematic flow chart of another read margin parameter guided optimization memory method according to an embodiment of the present application is provided.

[0061] Figure 6 A schematic structure diagram of a 2T0C memory cell structure according to an embodiment of the present application is provided.

[0062] Figure 7 A schematic structure diagram of a read margin parameter extraction device according to an embodiment of the present application is provided.

[0063] Figure 8 A schematic structure diagram of a read margin parameter guided optimization memory device according to an embodiment of the present application is provided.

[0064] Figure 9 A schematic structure diagram of an electronic device according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0065] In order to further clarify the technical means and effects taken by the present application to achieve the intended purpose, the technical solutions in the embodiments of the present application are described clearly below. In the following description, specific details such as specific system structures, techniques, etc. are presented in order to fully understand the present application, but the skilled in the art should understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known methods for extracting read margin parameters and electronic devices are omitted to avoid unnecessary details that hinder the description of the present application.

[0066] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to be limiting of the present application. As used in the specification and the appended claims of the application, the singular forms "a", "an" and "the" are intended to include both the singular and the plural forms, e.g., "one or more", unless the context clearly indicates otherwise.

[0067] Firstly, the application scenarios of the embodiments of the present application are introduced.

[0068] The common semiconductor storage devices on the market at present include magnetic hard disks, random access memories (RAMs), read-only memories (ROMs), dynamic memories (DRAMs), synchronous dynamic memories (SDRAMs), ferroelectric memories (FeRAMs), magnetic memories (MRAMs), resistive memories (RRAMs), flash memories (FLASHs) and phase change memories (PCMs), etc. These semiconductor storage devices can be divided into volatile memories, non-volatile memories and quasi-non-volatile memories. The non-volatile memories can maintain their stored logic states for a long time, and the internal stored data will not be lost even when the external power supply is turned off; unlike this, the volatile memories will lose the stored states over time, and need to be refreshed regularly, and will lose the stored data when the power supply is turned off. The data retention performance of the quasi-non-volatile memories is between that of the volatile memories and that of the quasi-non-volatile memories, and the data retention time of the storage cells therein is greater than or equal to one hundred seconds after power failure or power supply turn-off, and is much smaller than that of the non-volatile memories.

[0069] A storage cell is the smallest unit for storing and retrieving data in a semiconductor memory. It is the basic building block of a semiconductor memory, used to store binary bit information. A storage cell can be composed of different types of integrated circuit devices, such as transistors, magnetic tunnel junctions, memristors, etc. The storage physical quantity in a storage cell can be divided into voltage type, resistance type, charge type, etc. according to different storage cell structures and different integrated circuit devices constituting the storage cell. The storage cell set refers to the overall set of all storage cells in the memory, which can macroscopically reflect the storage characteristics of the memory.

[0070] Semiconductor memory stores information by storing different states within a memory cell, and a single memory cell can support two or more states. The states in a memory cell can be programmed in binary, which can support a multi-bit binary number, i.e., n memory states where n is an integer greater than zero. Depending on the number of binary states that can be stored in the memory cell, it can be classified as a single-bit binary memory, which only supports programming two memory states, represented by a logical "1" or a logical "0", or a multi-bit binary memory, which can support storing a multi-bit binary data state where n is greater than one, i.e., storing multi-bit information. Components of an electronic device can read or sense the stored states in the memory device in order to access the stored information. To store information, components of an electronic device can write or program states to the memory device.

[0071] The core of a semiconductor memory chip is a memory array for storing data, which is typically organized in rows and columns of memory cells with a set of address lines and data lines. The address lines are used to select a particular row and column, thereby selecting a target memory cell, and the data lines are used to read or write data.

[0072] A Bank in a memory is a logical unit within a memory, containing a group of associated memory cells or memory arrays, and it is a basic organization unit in a memory. Each Bank has independent control circuitry and signal lines, allowing it to perform read, write, or refresh operations independently in the same or multiple consecutive cycles, so that memory cells in different Banks can operate in parallel, improving the efficiency and performance of the memory. Multiple Banks can be combined into a Bank Group. Banks in the same Bank Group share some control signals and data paths.

[0073] A single semiconductor memory chip is typically composed of a memory module, address lines and data lines, logic control module, read / write circuitry, and auxiliary circuitry; the memory module contains multiple Bank Groups or multiple Banks for storing data. Reliability issues of a single memory chip are mainly reflected in process reliability, which is determined by analyzing the relationship between integrated circuit reliability and process, and determining the requirements of corresponding process conditions and process parameters from the perspective of reliability.

[0074] Semiconductor memory chips are usually produced in batches, and are manufactured in the same production cycle with consistent manufacturing processes and production parameters, and these chips have the same design specifications and similar performance characteristics, so for the same batch of memory chips, the reliability performance of the products after applying different processes is mainly evaluated comprehensively.

[0075] A read operation on a memory is performed by a read circuit. The read circuit includes modules such as a read decision circuit, a read decision threshold, an error correction code (ECC) decoding circuit, an error correction circuit, and modules shared with other circuit structures of the memory such as an address decoder, a data input / output (I / O) circuit, and the like. The function of the read operation is to obtain the data stored in a specified memory cell and transfer it to the data I / O module. The implementation steps of the read operation include address decoding, selecting a target memory cell, data reading, outputting data, and the like. Among them, the data reading step is implemented by a read decision circuit. Specifically, the read decision circuit compares the sample signal read from the selected memory cell with the read decision threshold to determine the state of the data stored in the memory cell, and then outputs the quantized result. The read decision threshold is an important criterion for the read decision circuit to distinguish between different discrete states of the received read-out sample signal. Fluctuations in the read decision threshold will result in incorrect decisions during the data reading process, and then output quantized signals different from the data stored in the selected memory cell. The ratio of the number of error quantized signals output by a certain memory array set to the total number of output quantized signals is called the read error rate of the memory array set.

[0076] The effect of the data reading step is affected by factors such as the selection of the read decision circuit, the selection of the read decision threshold, the quantization method, and the selection of the error correction coding scheme. The implementation steps of the data reading using a specific read decision circuit, read decision threshold, quantization method, and error correction coding scheme are called a read method. For the same memory array set, different read methods result in different read error rates.

[0077] Among the various levels of a memory device, there are common effects caused by PVT fluctuations, such as:

[0078] The leakage current present in the memory cell causes the memory cell to be unable to maintain its correct storage state for a long time. The parasitic parameters of capacitance and resistance in the memory cell level affect the response time and stability of the memory cell. A larger capacitance can cause an increase in the time required for read and write operations, while resistance can affect signal transmission and stability.

[0079] When performing read or write operations on a memory array, signal transmission can cause crosstalk between adjacent memory cells, which can change the storage state of the memory cell and cause interference or errors during data reading. The cross-coupling effect between different rows or columns of the memory array can cause interference in signal transmission in the memory array during read or write operations, affecting the accuracy and stability of the data.

[0080] Since the address lines of the memory's Bank are shared with the partial data path, when the Banks are affected by interference, it can affect the normal operation of other Banks, reducing the reliability of the entire Bank Group. In contrast, the mutual influence and effect between the Bank Groups is small, so the disturbance of a certain Bank Group has less impact on the remaining Bank Groups.

[0081] A single memory chip or memory chips of the same production batch can be affected by voltage noise from the power supply or external electromagnetic interference during circuit operation, as well as radiation from natural or man-made sources, which can cause bit flips or failures in the memory.

[0082] The effects caused by PVT fluctuations and the like are different in different types of memory devices, because different types of memory have different semiconductor materials, physical structures, and working principles. For example, volatile memory DRAM stores data by changing the charge stored in the storage cell capacitor, and PVT fluctuations can cause the leakage of stored charge to accelerate, affecting the retention time of the storage cell, reducing the memory read margin, and causing storage data loss and errors; or for example, non-volatile memory MRAM stores data based on the magnetic tunnel junction storage cell using the tunneling magnetoresistance effect, and PVT fluctuations can affect the state switching of the magnetic tunnel junction magnetic layer and the change in magnetism, reducing the read margin, and thus causing storage data errors.

[0083] The read margin can reflect the degree of overlap of the statistical distribution of the values in different storage states in the read method, that is, the smaller the degree of overlap of the distribution, the larger the read margin, and the lower the probability of false decision; on the contrary, the smaller the read margin, the higher the probability of false decision, and thus reflecting the accuracy and stability of the data read operation. In one aspect, the read margin can reflect the read reliability of the semiconductor memory under the read method, that is, when the read margin is large, the read accuracy of the memory is high, and the read method is more reliable. In another aspect, the read margin parameter can also reflect the stability and accuracy of the data that the memory chip can maintain when implementing the read method, and is not easily affected by external environment or internal changes, and has higher reliability. In addition, the read margin is of great significance to the yield of semiconductor memory chips. For memory chips of the same production batch, the higher the read margin, the less the manufactured memory chips are affected by PVT fluctuations and the like, and the higher the read accuracy.

[0084] Therefore, the embodiment of the present application proposes a read margin parameter extraction method, which is suitable for extracting read margin parameters of memory devices in different types of memories or different working environments. The degree of influence of non-ideal factors on semiconductor memories is grasped by extracting read margin, and further, the corresponding read method of semiconductor memories is guided to implement, so as to make the accuracy of reading the highest. In particular, the embodiment is best for the implementation effect of non-volatile memory.

[0085] Please refer to Figure 1 , Figure 1 The schematic flow chart of the read margin parameter extraction method of the embodiment of the present application is shown as an example but not limited, as shown in Figure 1 The method comprises the following steps:

[0086] In step 110, a test data set of a memory storage unit set is obtained. The test data set includes test parameter statistical characteristics of the storage unit set, and the statistical characteristics of the test parameters reflect the storage state fluctuation of the storage unit set.

[0087] The above-mentioned memory can include volatile memory, non-volatile memory and quasi-non-volatile memory. The quasi-non-volatile memory involves special advanced storage technology. Compared with general volatile memory and non-volatile memory, the storage unit of the quasi-non-volatile memory contains a transistor with extremely low leakage current, the amount of charge stored in the storage unit is stored in the gate end of the transistor, there are at least two storage states of the storage unit, the storage states are mapped to different amounts of charge stored in the storage unit, the retention time of the storage unit to the stored charge is greater than one hundred seconds, the stored charge will gradually decrease with the increase of storage time, and the storage state fluctuates. A plurality of storage units form a storage unit set. By applying voltage to the source and drain of the transistor, the read of the stored charge is implemented by reading the corresponding source and drain current.

[0088] That is, in terms of leakage current characteristics: the quasi-nonvolatile memory has extremely low leakage current, and is more than five orders of magnitude lower than the source-drain end leakage current of a common silicon-based MOS transistor. In terms of storage cell structure, the memory stores data in the form of electric charges in the gate end of a transistor in the storage cell, which is referred to as a read transistor, and the structure has a read-write separation feature, making data storage and reading more efficient and flexible. In terms of data reading method: a transistor in the memory device controls the inflow or outflow of electric charges to the gate end of the read transistor; the reading of the electric charges in the gate end of the read transistor is achieved by obtaining the source-drain current flowing through the read transistor; and the stored data has the feature of non-destructive reading, that is, the original storage state is not destroyed after reading the data. In terms of storage state: the storage cell of the memory has two or more storage states; and the amount of electric charges stored in the storage cell gradually decreases with the increase of storage time. Moreover, the effect of data retention and reading of the storage cell is affected by changes in storage conditions, parasitic effects, manufacturing process non-uniformity, noise, and read string interference. The parasitic effects include the effects of storage array parasitic parameters, gate-source capacitance, and gate-drain capacitance.

[0089] Specifically, the storage state of the storage cell in the memory is not fixed, but has certain changes or fluctuations, that is, the storage state fluctuates, which may be the result of the combined action of multiple factors. In general, the relative amount of stored electric charges gradually decreases with the increase of retention time, for example, due to changes in the parameters of the memory device, changes in the storage conditions, and the like. In order to describe such fluctuations, a set of distribution functions is usually used to help us understand how the storage state changes under different conditions, that is, the storage state fluctuations of the set of storage cells can be described by the statistical characteristics of the test parameters. The storage state fluctuations affect the effect of data retention and reading of the storage cell. When the storage state fluctuation is large, the data retention effect may be poor, and errors are more likely to occur when reading the data. The sources of the storage state fluctuations mainly include the following aspects:

[0090] Changes in the storage conditions of the memory affect the state of the storage cell; the storage conditions include the working environment and working conditions of the memory, and specifically, the storage conditions can include the selection of temperature, process, working voltage, storage state retention time, and storage state value of the storage cell.

[0091] Parasitic effects: as described above, the parasitic effects of storage array parasitic parameters, gate-source capacitance, gate-drain capacitance, and the like also affect the storage state.

[0092] Manufacturing process non-uniformity: the non-uniformity in the manufacturing process can cause fluctuations in the parameters of the transistors in the storage cell, such as threshold voltage, carrier mobility, sub-threshold slope, and the like, thereby affecting the storage state.

[0093] Noise is also an important factor causing the fluctuation of storage state. Noise can come from errors in the writing process, read decision errors introduced by the read circuit, miswriting errors caused by the read operation, etc. Noise can interfere with normal read and write operations, resulting in data errors or loss.

[0094] In addition, read crosstalk is also an important factor causing the fluctuation of storage state. Read crosstalk can come from interference current flowing through the side path outside the read key electrical path during the read process, etc. Read crosstalk can interfere with the decision-making process in the read operation, resulting in data errors.

[0095] Due to the existence of storage state fluctuation, noise and read crosstalk, the size of the read margin will directly affect the accuracy of data reading. From the distribution function describing the fluctuation of storage state, we can obtain the information of this read margin, so as to understand the performance characteristics of the memory.

[0096] Therefore, in this step, the test data set needs to be obtained by setting different test conditions and parameters to obtain comprehensive and accurate test results. The test data set is formed by setting specific test conditions and test parameters to test the storage unit set under different test targets and environmental conditions, and obtaining the statistical characteristics of the test parameters. That is, the statistical characteristics of multiple groups of test parameters constitute the test data set.

[0097] Referring to Figure 2 , obtaining a test data set of a storage unit set of a memory, comprising the following steps:

[0098] Step 111, test process, setting test conditions and object test parameters under different conditions of test targets and environments, and selecting a test method.

[0099] Step 112, implementing the test process on the storage unit set under the test conditions to obtain the statistical characteristics of the test parameters.

[0100] It can be understood that the above test process, that is, setting test conditions and object test parameters under different conditions of test targets and environments, and selecting test methods. The storage state fluctuation can be extracted by the test process, that is, the statistical characteristics of the test parameters can be obtained by implementing the test process on the storage cell set under the test conditions. The statistical characteristics of the test parameters of the storage cell set reflect the storage state fluctuation characteristics of the test parameters. The test conditions can include a combination of multiple test conditions, ensuring that the statistical characteristics of the test parameters obtained can fully reflect the statistical characteristics of the test parameters of the storage cell set. The test method can include storage circuit or integrated circuit device simulation, actual measurement results, that is, the test can not only be based on a theoretical model, but also based on actual physical hardware, thereby ensuring the accuracy and reliability of the test results. The test parameters can include integrated circuit device parameters such as operating voltage, current, transistor threshold voltage, gate-source capacitance, transconductance, etc. The data set of the test parameters includes parameter curves such as output characteristic curves, transfer characteristic curves, and retention time curves of the memory, which can be used to describe the parameter composition of the memory.

[0101] In step 120, a set of memory characteristics of the storage cell set under different storage conditions is extracted based on the test data set. Wherein, the memory characteristic refers to the mapping relationship between the statistical characteristics of the test parameters and the storage state fluctuation characteristics.

[0102] The set of memory device characteristics is a set of characteristics reflecting the relationship between the storage state fluctuation and the test parameters, which contains one or more memory device characteristic descriptions that can reflect the relationship between the statistical characteristics of the test parameters of the storage cell set in the test data set and the storage state characteristics. The memory characteristic description includes a characteristic description of continuous change of the memory characteristic within a sampling time; the memory device characteristic can be understood as the mapping relationship between the statistical characteristics of one or more test parameters and the storage state characteristics in the test data set of the storage cell set.

[0103] In some embodiments, the set of memory characteristics is a channel description of the storage cell set, which is embodied in the form of formulas describing the storage state, storage state writing and reading, etc. The memory characteristic is affected by the performance, characteristics and parameters of the storage cell set, including: storage type, storage structure, storage level, storage capacity, read-write speed, reliability, etc.

[0104] In step 130, according to the set of memory characteristics, the statistical distribution of the statistical characteristics of the test parameters is superimposed to obtain the statistical characteristics of the storage state of the storage cell set.

[0105] After extracting the memory device feature set of a certain memory device, according to the memory feature, the statistical characteristics of one or more test parameters can be superimposed to obtain the storage state statistical characteristics of the memory cell set. This kind of storage state statistical characteristics can be described by a set of storage state distribution functions, so as to more accurately understand and predict the change of the storage state.

[0106] When considering distribution superposition, it is first necessary to consider whether there is mutual independence between different memory device parameters, for example, if the parameters are mutually independent, then we can directly superimpose; if there is a dependent relationship, it needs to be processed or converted first. Secondly, whether there is a boundary condition or limitation, the condition may limit the range or method of superposition. Finally, different distribution superposition methods are suitable for different situations, for example, convolution, mixed distribution and other methods are suitable for different statistical problems.

[0107] Step 140, extracting a read margin parameter according to the storage state statistical characteristics and a set of decision thresholds.

[0108] The read margin parameter can be defined as a quantitative index of the error tolerance degree of the storage state in the memory cell when reading the data in the memory, which reflects the degree to which the state of the memory cell can deviate from its ideal value without being misjudged in the reading process.

[0109] Referring to Figure 3 , extracting a read margin parameter according to the storage state statistical characteristics and a set of decision thresholds, specifically including the following steps:

[0110] Step 141, setting a set of decision thresholds according to the storage state statistical characteristics; wherein each storage state corresponds to at least one decision threshold region.

[0111] Step 142, for each storage state, calculating its corresponding read margin according to the set of decision thresholds, and obtaining a set of decision read margins based on the read margins of all storage states;

[0112] Step 143, obtaining a read margin parameter based on the set of decision read margins; wherein the read margin parameter is the minimum value in the set of decision read margins under the same set of storage states.

[0113] It should be understood that the read margin is determined by the storage state statistical characteristics and the set of decision thresholds, and the set of decision thresholds includes one or more decision thresholds, which are used to divide the source-drain current value flowing through the transistor into multiple decision threshold regions by artificial setting, so as to judge the state of the memory cell. In the implementation process, the set of decision thresholds is set according to the memory feature set, specifically, each storage state corresponds to one or more decision threshold regions, for example, for n-bit storage, there are 2n The number of decision threshold sets should be no less than 2 n The statistical characteristics of each storage state are determined by the decision threshold corresponding to the decision threshold region in which the storage state is located, and the read margin of the storage state is determined by the statistical characteristics. Based on the read margins of all storage states, a decision read margin set is formed, and the read margin parameter is the minimum value in the decision read margin set of the same group of storage states. This parameter can reflect the correctness of the programming of the decision threshold for a group of storage states, and can also reflect the characteristics of the memory.

[0114] The read margin parameter can represent the stability of the memory device parameters under certain storage conditions. Through the extraction process of the read margin parameter, the extraction of the memory parameters and the guidance of the optimization of the memory can be assisted. The read margin parameter can also be used for the evaluation of the reliability of the integrated circuit device process of the memory and the parameters required for the optimization of the structure of the memory unit and the memory array, and the read / write circuit. The storage conditions reflect the working environment and working conditions of the semiconductor memory, such as the selection of the above-mentioned temperature, process, working voltage, storage state retention time, storage state value of the storage unit, etc. When the read margin parameter is maximum, the corresponding storage condition is optimal. Through the read margin parameter, the semiconductor memory can be guided to set the optimal storage condition.

[0115] Through the extraction of the read margin parameter, the reliability parameters of the semiconductor memory can be extracted and analyzed. The reliability parameters of the semiconductor memory can be basic reliability parameters, such as average maintenance interval time reflecting the use requirements, average failure interval time for design, etc. They can also be mission reliability parameters, such as average critical failure interval time, mission reliability, etc. They can also be durability parameters, such as service life, storage life, etc.

[0116] Therefore, referring to FIG. 4, the read margin parameter guidance optimization memory method provided by the embodiments of the present application, Figure 4 is a schematic flowchart of the read margin parameter guidance optimization memory method of the embodiments of the present application, which is used as an example but is not limited, as shown in the figure, Figure 4 the method extracts the read margin parameter of the storage unit to select the optimal read decision threshold, so as to realize the reliability evaluation, selection and optimization of the semiconductor memory, including the following steps:

[0117] Step 210, extracting a set of statistical characteristics of the storage state of the set of storage units within the retention time.

[0118] The retention time refers to the period of time during which the data can be kept valid without being changed or lost after being written into the storage unit, that is, the period of time during which the data is stored and kept valid.

[0119] Step 220, providing a set of alternative decision thresholds through the set of statistical characteristics.

[0120] The set of alternative decision thresholds is determined by the maximum likelihood function of the set of statistical characteristics of the storage state over the retention time under different storage conditions. The selection of the decision threshold affects the read performance and reliability of the memory, and therefore the selection of the alternative set needs to consider various storage state factors.

[0121] In some embodiments, the set of alternative decision thresholds is selected based on the comprehensive performance of area, power consumption, time delay, and matching with the storage unit.

[0122] In step 230, the optimal decision threshold set is extracted from the set of alternative decision thresholds, wherein the optimal decision threshold set has the optimal read margin response characteristic of the storage unit over the retention time.

[0123] The optimal decision threshold set is one of the set of alternative decision thresholds, and the optimal decision threshold set refers to the decision threshold set that has the optimal maximum likelihood function of the set of statistical characteristics of the storage state under different storage conditions. The optimal decision threshold set has the lowest read decision error rate.

[0124] The memory read margin parameter is related to the decision threshold, i.e., different selection of the decision threshold will result in changes in the read margin response characteristic, which is a dependent variable and is a set of curves composed of a set of data, reflecting the response degree of the memory read margin parameter under different decision thresholds.

[0125] In some embodiments, the read margin response characteristic is not fixed but changes over time, especially the retention time. Therefore, during the evaluation and optimization process, the read margin response characteristic needs to be sampled at different time points or time periods. The sampling time refers to the specific time point or time period selected when evaluating the read margin response characteristic. The sampling time of the read margin response characteristic is not longer than the retention time. It should be understood that the statistical characteristics of the storage state are different under different retention times; further, the statistical characteristics of the storage state have different optimal decision threshold sets under different retention times; further, for a certain decision threshold set, the read margin response characteristic is different under different retention times.

[0126] In step 240, the global optimal decision threshold is determined according to the optimal decision threshold set.

[0127] The read margin response characteristic can not only guide the selection, design and optimization of the set of alternative decision thresholds, but also guide the optimization of memory device features to make the read margin response characteristic of the set of memory cells better. When the optimal set of decision thresholds is applied to the statistical characteristics of the storage state, the maximum likelihood ratio of the resulting read result is best, that is, the maximum likelihood ratio. In other words, by selecting the best decision threshold, we can maximize the probability of correctly reading the state of the memory cell and minimize the possibility of read error. The likelihood ratio is an indicator of the likelihood of a hypothesis being true relative to another hypothesis, which is used here to evaluate the pros and cons of the decision threshold. By maximizing the likelihood ratio, we can ensure that the selected decision threshold is optimal and can most accurately reflect the actual state of the memory cell.

[0128] Referring to Figure 5 According to the optimal set of decision thresholds, a global optimal decision threshold is determined, specifically including the following steps:

[0129] Step 241, a set of storage conditions and a set of alternative decision thresholds are specified.

[0130] Step 242, a read margin response characteristic evaluation model is established.

[0131] Step 243, each alternative decision threshold is applied to the set of memory cells, and the read margin response characteristic is extracted to obtain a set of alternative decision threshold read margin response characteristics.

[0132] Step 244, the set of storage conditions and the set of alternative decision thresholds and their corresponding set of read margin response characteristics are input into the evaluation model; the alternative decision threshold that matches the optimal read margin response characteristic is output as the global optimal decision threshold.

[0133] The read margin response characteristic of the memory has a guiding effect on the setting of the decision threshold. By evaluating the read margin response characteristic under different storage conditions, a global optimal decision threshold is provided in the information theory boundary that combines channel quantization with actual storage circuits.

[0134] By establishing an evaluation model for the read margin response characteristic, optimizing the memory structure and error correction algorithm, and understanding and controlling the read margin, manufacturers can ensure the reliability of the memory during the process and production process. By adjusting the manufacturing process and using appropriate testing methods, the reliability of the memory can be maximized to provide reliable read margin under different environments, thereby improving the performance and stability of the memory.

[0135] Further, in some embodiments, the method for guiding the optimization of the memory of the present application also includes the following steps:

[0136] Step 250, a global optimal decision threshold is specified.

[0137] First, a globally optimal decision threshold is determined for determining the current range required for reading. The globally optimal decision threshold will be adjusted according to the specific memory chip and the reading current distribution to ensure that the storage state can be accurately identified during reading.

[0138] Step 260, according to the set of memory characteristics, extract the main source of storage state fluctuation.

[0139] After specifying the globally optimal decision threshold, analyze the main source of storage state fluctuation, which includes manufacturing deviation of memory device, noise, temperature change or other external interference factors, etc. Through the analysis of the set of memory characteristics, determine the key factor source affecting the storage state fluctuation.

[0140] Step 270, different suppression methods are implemented for the main source of storage state fluctuation.

[0141] In this step, after determining the key factor source affecting the storage state fluctuation, a set of different suppression methods are implemented for the fluctuation source. For example, in some possible examples, temperature compensation measures can be taken for temperature change; process adjustment and control can be taken for manufacturing deviation; and filter or enhanced signal processing algorithm can be taken for noise.

[0142] Step 280, extract the corresponding reading margin parameter for each suppression method; evaluate the effect of the corresponding suppression method through the reading margin parameter.

[0143] By implementing each suppression method and extracting the corresponding reading margin parameter, the suppression effect is evaluated. By comparing the reading margin parameters under different suppression methods, it can be determined which method is the best for reducing the storage state fluctuation.

[0144] Step 290, determine the best suppression method corresponding to the reading margin parameter, which is the best suppression method for the main source of storage state fluctuation.

[0145] Finally, according to the evaluation result, determine the best suppression method, which is the most effective method for reducing the storage state fluctuation under given conditions. This best suppression means will become the best processing method for the main source of storage state fluctuation, thereby improving the reading accuracy and reliability of the memory.

[0146] Through the above steps, the storage state fluctuation can be reduced according to the reading margin parameter to achieve the purpose of guiding the optimization of the memory.

[0147] In summary, the embodiments of the present application analyze the performance of the memory device under different conditions by comprehensively scanning the test data set of the memory device to find the optimal read margin. Specifically, the method first collects parameter curve data of the memory device under various test conditions, and by analyzing these data, especially the disturbance form and its distribution characteristics of the memory device, the test data set is accurately fitted with the storage disturbance distribution, thereby obtaining the distribution curve of the memory device and the corresponding fitting curve distribution parameters. Based on this, the read margin of the memory device under different conditions is further calculated, and it is determined which conditions have the best read margin. In general, the method selects the memory device with superior performance by accurately adjusting and optimizing the read parameters. Not only does it consider how to maximize the read margin, but it also ensures that the disturbance is within an acceptable range, thereby ensuring that the memory device can maintain optimal read performance under various operating conditions. It is a new, reliable and feasible means that helps to meet the performance requirements of the memory device in various application scenarios, and has important significance for improving the performance and reliability of the memory device.

[0148] For example, the following is an example of a quasi-nonvolatile memory based on an amorphous oxide thin film transistor (AOSFET).

[0149] See Figure 6 The storage unit is a two-transistor (2T0C) unit and a storage unit set. The memory device is a memory device with four-port characteristics. Specifically, the memory storage unit can be a 2T0C gain unit structure, and the storage unit structure of the memory device is composed of two transistors. The operating principle based on this kind of unit structure is as follows: the switch of the write-in tube 101 is controlled by the write word line 106, the size of the write-in data is controlled by the write bit line 107, and the write-in tube 101 establishes a storage level for the storage node 102 in a transmission tube mode; the gate of the read-out tube 103 constitutes part of the storage node, and one end of the active region is connected to the read word line 104 and the other end is connected to the read bit line 105. The storage node level changes due to different write-in values, which is equivalent to a small signal added to the gate end of the read-out tube 103. The source-drain region of the read-out tube 103 is connected to a constant operating voltage in various operating modes, which is equivalent to biasing the read-out tube 103 at a constant level. Therefore, the read-out tube 103 constitutes a common-source amplifier, which is a current source structure in terms of the read bit line, and the gain unit is named accordingly. When the unit uses different types of MOS tubes, only the selection of the operating voltage will be affected, and the above-mentioned unit operating principle is consistent.

[0150] For example, the transistor is an amorphous oxide semiconductor thin film transistor (AOS-FET). The test data set of the memory device is scanned, and the data set is a plurality of memory device parameter curves obtained by testing the memory device under different conditions. Each group of test conditions includes a combination of a plurality of test conditions.

[0151] The test parameters of the test conditions include, but are not limited to, voltage, current, capacitance, resistance, conductance. For example, the test parameters in some embodiments can be transistor drain-source voltage, gate-source voltage, gate-drain voltage, transistor drain-source current, transistor transconductance, transistor gate oxide capacitance, overlap capacitance, transistor resistance, transconductance, etc. which can be used to describe various parameters of a memory device model.

[0152] For example, for a 2T0C memory cell with an amorphous oxide thin film transistor (AOS-FET) as the transistor, the following tests can be performed to generate the test data set. The specific test methods listed below are only a part of the test parameters in the example:

[0153] 1) When Vds=0.05V, test the change of drain-source current Ids with gate voltage at different voltages Vgs, i.e., to test the transfer characteristic curve at different body bias voltages.

[0154] 2) When Vgs=0.5V, test the change of drain-source current Ids with gate voltage at different voltages Vds, i.e., to test the output characteristic curve at different body bias voltages.

[0155] 3) Set Delay 100ms to start writing, set the write time to 1ms, set the read word line voltage to 0.5V, set the read bit line voltage to 0.05V, and write at different write word line voltages; after writing is completed, set the write bit line voltage to 0V and the write word line voltage to the holding voltage, and the holding voltage is -2.6V; during writing and reading, the read bit line voltage is always 0.05V, and after each test, the charge of the storage node is completely discharged before the next test; i.e., to test the curve of read current and storage node voltage changing with time at different write word line voltages.

[0156] 4) Connect the source and drain, and test the change of gate oxide capacitance Cox with Vgs=Vds at different frequencies, i.e., to test the curve of gate oxide capacitance changing with voltage at different frequencies.

[0157] In the acquisition of memory device parameter test data sets, the set acquisition method can be formula calculation, simulation results. For example, in one instance, in order to obtain the charge-current curve required by the four-port memory device, the data can be extracted from the voltage-current curve and the voltage-charge curve, and then the charge-current curve can be calculated. Similarly, the charge can also be calculated by voltage and capacitance. It can be understood that for different groups of test conditions, multiple current-voltage curves will be obtained. The set of multiple current-voltage curves constitutes the test data set of the integrated circuit device for the extracted parameters. By providing curve data under multiple groups of different test conditions, the characteristics of the device and the information required for parameter extraction can be more comprehensively explored.

[0158] After providing the memory device test data set, the memory device and the memory device feature are extracted, the possible errors and disturbance effects are analyzed, and the disturbance distribution is extracted or the disturbance distribution curve is fitted to obtain the type and distribution parameters of the disturbance distribution.

[0159] The error source and type of the 2T0C memory cell based on amorphous oxide thin film transistor are analyzed by feature extraction, which is divided into three parts, the first part is the write error, the second part is the retention error, and the third part is the read error. First, the write error, due to the existence of parasitic capacitance in the memory cell, the capacitive coupling effect will cause the decrease of the storage charge, and the error of "1" to "0" may occur; secondly, after the memory is written, it enters the data retention state, at this time there is a problem of leakage current, the storage capacitor will lose charge with the passage of time, and the leakage charge will dominate the error of "1" to "0". Since the occurrence of retention error is a one-way error from high charge to low charge, retention error is asymmetric; finally, when the charge stored in the memory cell decreases due to leakage, the crosstalk existing in the storage array when the adjacent memory cells are operated will cause the decay of the charge on the bit line to flip, causing a read error of bit flipping. In addition to the read decision error, there is also a read decision error. Since the read decision error is a continuous distribution problem, and the remaining errors are discrete probability problems, the read decision error is separated out, and the storage state distribution problem caused by environmental thermal fluctuations and process deviation is analyzed.

[0160] The storage unit can have channel charge injection effect. When the transistor is turned on, there is a channel at the interface. After the transistor is turned off, the charge originally present in the channel flows out through the source and drain, and the charge injected into the input terminal is absorbed by the input signal source and does not cause errors, but the injected charge injected into the storage node changes the storage charge and causes errors. Secondly, in the process of preparation, due to the influence of temperature, electric field intensity, impurities and doping concentration, the area of the dielectric layer deviates, resulting in errors in the overlapping capacitance. Similarly, the channel carrier mobility and threshold voltage and other parameters will also be disturbed. In combination with the storage test data set, the distribution of the above-mentioned storage parameters is extracted, or the distribution curve is fitted, to obtain the characteristics of the statistical characteristics of the storage parameters. According to different distribution characteristics, different distribution functions are selected, and the corresponding distribution characteristic parameters are extracted.

[0161] After extracting the statistical characteristics of the storage parameters, the statistical characteristics of the storage parameters need to be distributed and superimposed. For distribution superposition, whether there is mutual independence between the disturbances needs to be considered, and the read current of the storage unit is analyzed, which includes considering the multiplicative and additive of the disturbance factors. According to the relationship between the storage device parameters affected by the disturbance, the distribution is superimposed. At this time, the mathematical method of probability statistics is needed. Different distribution superposition methods are suitable for different situations. Convolution, mixed distribution and other methods may be suitable for different statistical problems.

[0162] The disturbance distribution is a normal distribution, and the read result obtained after superimposing each disturbance factor can be approximately a Gaussian distribution. Therefore, the parameters (mean and variance under normal distribution) of the fitting curve are extracted from the data set distribution curve, and the read margin is calculated. The read margin is defined in the present application as the degree of overlap of the distribution curves of different storage states.

[0163] The read margin of a storage unit can be calculated by the formula

[0164]

[0165] The calculation result is ref, where ref can be the reference current / voltage / resistance value when reading the storage unit, μ0 and μ1 are the means of the distributions corresponding to the storage states "0" and "1", respectively, and σ0 and σ1 are the variances of the distributions corresponding to the storage states "0" and "1", respectively.

[0166] The read margin is in units of "sigma", which refers to the multiple of the standard deviation, and it reflects the ability of the storage unit to correctly read data under certain conditions. The larger the read margin, the higher the stability and reliability of the storage unit when reading data, which means that even under different environmental conditions or interference, the storage unit can accurately read data, reducing the possibility of errors. On the contrary, the smaller the read margin, the more likely it is that the storage unit is more susceptible to interference or errors when reading data. This can lead to data reading errors or instability, increasing the risk of system errors. Therefore, a larger read margin is beneficial to the stability and reliability of the storage unit, while a smaller read margin may increase the risk of data reading errors.

[0167] After determining the read margin of the storage unit, a comprehensive scan is performed on the read margin data set to select the maximum value and determine the corresponding storage condition and acceptable range of disturbance.

[0168] The storage condition can include the storage state of each memory (such as voltage, current, resistance value), and the acceptable range of disturbance is within the interval of the maximum value of the read margin to 6σ, because 6σ represents six times the standard deviation, which is commonly used to measure the performance, quality or stability of a process. In the field of quality management and production, 6σ is generally considered a high level of standard, meaning that the defect rate of the product or process is very low, with high stability and quality.

[0169] The read margin changes with various non-ideal factors, such as the read margin of volatile memory decays as the storage data retention time increases. At this time, the time item is added to the read margin for analysis. Under different retention times, the distribution of storage states in the memory device also changes, so the margin also changes. The decay curve of retention time and read margin can be drawn to find the appropriate memory refresh time.

[0170] The embodiments of the present application also provide a read margin parameter extraction device corresponding to the read margin parameter extraction method of the embodiments, comprising:

[0171] The data acquisition module 1001 is configured to acquire a test data set of a storage unit set of a memory; wherein the test data set includes statistical characteristics of test parameters of the storage unit set, and the statistical characteristics of the test parameters reflect the storage state fluctuation of the storage unit set;

[0172] The memory feature extraction module 1002 is configured to extract a memory feature set of the storage unit set under different storage conditions based on the test data set; wherein the memory feature refers to the mapping relationship between the statistical characteristics of the test parameters and the storage state fluctuation characteristics;

[0173] The storage state statistical property calculation module 1003 is configured to superimpose statistical distributions of statistical properties of the test parameters according to the set of memory characteristics, to obtain storage state statistical properties of the set of storage units.

[0174] The read margin parameter extraction module 1004 is configured to extract read margin parameters according to the storage state statistical properties and a set of decision thresholds.

[0175] The present application also provides a read margin parameter guiding method for optimizing a memory device, which corresponds to the read margin parameter guiding method for optimizing a memory device of the present application, and includes the following steps:

[0176] The statistical property extraction module 2001 is configured to extract a set of statistical properties of storage states of the set of storage units within a retention time; wherein the retention time is a time period during which data is stored and kept valid.

[0177] The alternative decision threshold determination module 2002 is configured to provide a set of alternative decision thresholds through the set of statistical properties; wherein the set of alternative decision thresholds is determined by a maximum likelihood function of the set of statistical properties of storage states within the retention time under different storage conditions.

[0178] The optimal decision threshold determination module 2003 is configured to extract a set of optimal decision thresholds based on the set of alternative decision thresholds, wherein the set of optimal decision thresholds makes read margin response characteristics of the storage units within the retention time optimal; the read margin response characteristics reflect response degrees of the memory read margin parameters under different decision thresholds.

[0179] The globally optimal decision threshold determination module 2004 is configured to determine a globally optimal decision threshold according to the set of optimal decision thresholds.

[0180] The present application also provides an electronic device, which includes a memory 1009, a processor 1010, and a computer program stored in the memory 1009 and capable of running on the processor 1010, wherein the computer program is executed by the processor to implement the steps of the read margin parameter extraction method or the read margin parameter guiding method for optimizing a memory device of the above-mentioned embodiments.

[0181] The memory 1009 can be used to store software programs and various data. The memory 1009 can mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area can store an operating system, application programs or instructions required by at least one function (such as a sound playing function, an image playing function, etc.), and the like.

[0182] The processor 1010 can include one or more processing units; optionally, the processor integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to operating systems, user interfaces, and applications, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It can be understood that the above-mentioned modem processor can also not be integrated into the processor.

[0183] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusions, so that a process, method, article, or device that includes a list of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent in such a process, method, article, or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the process, method, article, or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, but can also include performing functions in a substantially simultaneous manner or in reverse order, for example, the described method can be performed in an order different from that described, and various steps can also be added, omitted, or combined. In addition, features described with reference to certain examples can be combined in other examples.

[0184] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be realized by means of software and the necessary general hardware platform, of course, they can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, or network equipment, etc.) execute the methods described in various embodiments of the present application.

[0185] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above-mentioned specific embodiments, the above-mentioned specific embodiments are only illustrative, not limiting, and those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the protection scope of the claims.

Claims

1. A method for extracting margin parameters, characterized in that, Includes the following steps: Obtain a test dataset of the set of storage cells of the memory; wherein the test dataset includes statistical characteristics of test parameters of the set of storage cells, and the statistical characteristics of the test parameters reflect the storage state fluctuation of the set of storage cells; Based on the test dataset, a set of memory features is extracted from the set of storage cells under different storage conditions; wherein, the memory features refer to the mapping relationship between the statistical characteristics of the test parameters and the storage state fluctuation characteristics; Based on the memory feature set, the statistical characteristics of the test parameters are statistically superimposed to obtain the storage state statistical characteristics of the memory cell set. Read margin parameters are extracted based on the storage state statistical characteristics and decision threshold set.

2. The method for extracting read margin parameters according to claim 1, characterized in that, The memory cell contains a transistor with extremely low leakage current. The memory cell stores a charge at the gate of one of the transistors. The memory cell has at least two storage states, which are mapped to different amounts of charge stored in the memory cell. The memory cell is quasi-nonvolatile, that is, the storage time of the stored charge is greater than one hundred seconds. The storage states fluctuate. The plurality of the storage units constitute a storage unit set; The amount of stored charge is read by applying a voltage to the source and drain terminals of the transistor and then reading the corresponding source and drain current.

3. The method for extracting read margin parameters according to claim 1, characterized in that, The sources of the storage state fluctuations include at least one of the following factors: changes in storage conditions, parasitic effects, non-uniformity in the manufacturing process, noise, and read crosstalk; The storage conditions include the selection of temperature, process, operating voltage, storage state retention time, and storage state value of the storage unit.

4. The method for extracting read margin parameters according to claim 1, characterized in that, The process of obtaining the test dataset of the set of storage cells in the memory includes the following steps: The testing process involves setting test conditions and object test parameters, and selecting test methods under different test objectives and environmental conditions. The test process is performed on the storage unit set under the test conditions to obtain the statistical characteristics of the test parameters; The testing method includes simulation and actual measurement of storage circuits or integrated circuit devices; the test parameters include voltage, current, capacitance, resistance, and conductance. The test dataset includes parametric curves that describe the composition of the memory parameters.

5. The method for extracting read margin parameters according to claim 1, characterized in that, The step of extracting the read margin parameter based on the storage state statistical characteristics and the decision threshold set specifically includes the following steps: A set of decision thresholds is set based on the statistical characteristics of storage states; wherein each storage state corresponds to at least one decision threshold region; For each storage state, its corresponding read margin is calculated based on the set of decision thresholds and the statistical characteristics of the storage state, and a decision read margin set is obtained based on the read margins of all storage states. A read margin parameter is obtained based on the decision read margin set; wherein, the read margin parameter is the minimum value in the decision read margin set under the same storage state.

6. A margin parameter extraction device, characterized in that, include: A data acquisition module is used to acquire a test dataset of a set of storage units in the memory; wherein the test dataset includes statistical characteristics of test parameters of the set of storage units, and the statistical characteristics of the test parameters reflect the storage state fluctuation of the set of storage units. The memory feature extraction module is used to extract a set of memory features of the set of memory cells under different storage conditions based on the test dataset; wherein, the memory features refer to the mapping relationship between the statistical characteristics of the test parameters and the storage state fluctuation characteristics; The storage state statistical characteristic base calculation module is used to statistically distribute and superimpose the statistical characteristics of the test parameters according to the memory feature set to obtain the storage state statistical characteristics of the storage unit set. The read margin parameter extraction module is used to extract read margin parameters based on the storage state statistical characteristics and the decision threshold set.

7. A method for optimizing memory by reading margin parameters, characterized in that, Includes the following steps: Extract a set of statistical characteristics of the storage state of the storage unit set during the retention time; wherein, the retention time is the period during which data is stored and remains valid; The set of statistical characteristics provides a set of alternative decision thresholds; wherein, the set of alternative decision thresholds is determined by the maximum likelihood function of the set of statistical characteristics of the storage state during the retention time under different storage conditions. The optimal decision threshold set is extracted based on the candidate decision threshold set, wherein the optimal decision threshold set optimizes the read margin response characteristics of the memory cell during the hold time; the read margin response characteristics reflect the response degree of the memory read margin parameter under different decision thresholds; The global optimal decision threshold is determined based on the set of optimal decision thresholds.

8. The read margin parameter-guided memory optimization method according to claim 7, characterized in that, The guided memory optimization method further includes the following steps: Specify the global best decision threshold; Based on the memory feature set, the main sources of the memory state fluctuations are extracted; Different suppression methods are applied to the main sources of the storage state fluctuations; For each of the aforementioned suppression methods, extract the corresponding read margin parameters; The effectiveness of the suppression method is evaluated by the read margin parameter. The optimal suppression method corresponding to the read margin parameter is the optimal suppression method for the main source of the storage state fluctuation.

9. The read margin parameter-guided memory optimization method according to claim 7 or 8, characterized in that, Determining the global optimal decision threshold based on the optimal decision threshold set involves the following steps: Specify the set of storage conditions and the set of alternative decision thresholds; Establish a read margin response characteristic evaluation model; Each candidate decision threshold is applied to the set of memory cells, and the read margin response features are extracted to obtain the candidate decision threshold read margin response feature set. The evaluation model is input with the set of storage conditions and the set of alternative decision thresholds and their corresponding set of read margin response features; the alternative decision threshold that matches the best read margin response feature is the global best decision threshold.

10. Reading margin parameters to guide the optimization of memory devices, characterized in that, include: The statistical characteristic extraction module is used to extract the statistical characteristic set of the storage state of the storage unit set during the retention time; wherein, the retention time is the period during which the data is stored and remains valid; The alternative decision threshold determination module is used to provide an alternative decision threshold set through the statistical characteristic set; wherein, the alternative decision threshold set is determined by the maximum likelihood function of the statistical characteristic set of the storage state during the retention time under different storage conditions; The optimal decision threshold determination module is used to extract the optimal decision threshold set based on the candidate decision threshold set, wherein the optimal decision threshold set makes the read margin response characteristics of the memory cell optimal during the hold time; the read margin response characteristics reflect the response degree of the memory read margin parameter under different decision thresholds; The global best decision threshold determination module is used to determine the global best decision threshold based on the set of best decision thresholds.

11. An electronic device, characterized in that, The electronic device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the method as described in any one of claims 1 to 5 or 7 to 9.

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