Address data writing method and device, electronic equipment and storage medium

Abstract

A method and device for writing address data, an electronic device and a storage medium. The method for writing address data is used to write address data into N storage units. The address data includes N sub-data, and each of the N storage units is provided with at least two memories. The method for writing address data includes: in response to the addresses of x sub-data in the N sub-data corresponding to a first storage unit in the N storage units, writing the x sub-data into the at least two memories of the first storage unit in parallel; reading a first sub-data from y sub-data stored in the at least two memories of the first storage unit; and writing the first sub-data into the first storage unit. The method for writing address data reduces the back pressure on the data input end, solves the problem of multiple sub-data writing conflicts at the hardware level, and improves the parallel processing efficiency of the computing device.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the computer field, such as a method for writing address data, a method for writing multiple sets of address data, an address data writing apparatus, an electronic device, and a storage medium. Background Technology

[0002] As computing devices become increasingly powerful and the amount of data to be processed grows ever larger, central processing units (CPUs) and coprocessors are rapidly evolving. The most common coprocessor is the graphics processing unit (GPU), primarily handling computations related to graphics display. Later, GPUs were used to handle general-purpose computing tasks, leading to the development of general-purpose computing on graphics processing units (GPGPUs). With the advancement of artificial intelligence, neural network processing units (NPUs) specifically designed to accelerate neural network computations have further emerged. GPUs, GPGPUs, NPUs, and other computing devices possess powerful parallel computing capabilities, enabling them to handle multiple computational tasks simultaneously, making them particularly suitable for processing large datasets and complex tasks. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a method for writing address data, used to write the address data into N storage units, wherein the address data includes N sub-data, each of the N storage units corresponds to at least two memories, and N is an integer greater than 1. The method for writing the address data includes: responding to the address of x sub-data in the N sub-data corresponding to a first storage unit in the N storage units, writing the x sub-data in parallel into at least two memories of the first storage unit, wherein x is an integer greater than 1 and less than or equal to N; reading a first sub-data from y sub-data stored in the at least two memories of the first storage unit, wherein y is an integer greater than or equal to x; and writing the first sub-data into the first storage unit.

[0004] For example, in the address data writing method provided in at least one embodiment of this disclosure, the number of at least two memories of the first storage unit is greater than or equal to x, and the step of writing the x sub-data in parallel to the at least two memories of the first storage unit includes: writing the x sub-data in parallel to x memories of the at least two memories of the first storage unit.

[0005] For example, in the address data writing method provided in at least one embodiment of this disclosure, each of the at least two memories of each storage unit includes multiple storage depths, and each of the multiple storage depths has the same data bit width as each of the N sub-data.

[0006] For example, in the address data writing method provided in at least one embodiment of this disclosure, reading the first sub-data from y sub-data stored in at least two memories of the first storage unit includes: selecting the first memory among the at least two memories based on the polling order of the at least two memories; selecting the first sub-data according to the storage order of at least one sub-data stored in the first memory; and reading the first sub-data.

[0007] For example, the address data writing method provided in at least one embodiment of this disclosure further includes: responding to the fact that the addresses of Nx sub-data (excluding the x sub-data) among the N sub-data correspond one-to-one with the Nx storage units among the N storage units, writing the Nx sub-data into the memory of the Nx storage units accordingly; reading multiple second sub-data from multiple sub-data stored in the memory of multiple second storage units (excluding the first storage unit) among the N storage units; and writing the first sub-data and the multiple second sub-data in parallel into the first storage unit and the corresponding second storage unit based on the address correspondence.

[0008] For example, in the address data writing method provided in at least one embodiment of this disclosure, the step of writing the first sub-data and the plurality of second sub-data in parallel to the first storage unit and the corresponding second storage unit based on the address correspondence includes: writing the first sub-data to the first storage unit, and writing the plurality of second sub-data to the corresponding second storage units respectively.

[0009] For example, in the address data writing method provided in at least one embodiment of this disclosure, at least one sub-data is stored in the memory of z storage units other than the Nx storage units among the plurality of second storage units, and the number of the plurality of second sub-data is equal to N-x+z, where z is a positive integer less than or equal to x-1.

[0010] For example, in the method for writing address data provided in at least one embodiment of this disclosure, the storage unit includes a storage bank or a group of storage banks.

[0011] At least one embodiment of this disclosure also provides a method for writing multiple sets of address data, used to write the multiple sets of address data into N storage units in multiple loop cycles, wherein each set of address data includes N sub-data, each of the N storage units corresponds to at least two memories, and N is an integer greater than 1. The method for writing multiple sets of address data includes: in each loop cycle of the multiple loop cycles, in response to the address of x sub-data in each set of address data corresponding to a first storage unit in the N storage units, writing the x sub-data in parallel into at least two memories of the first storage unit, wherein x is an integer greater than 1 and less than or equal to N; reading a first sub-data from y sub-data stored in the at least two memories of the first storage unit, wherein y is an integer greater than or equal to x; and writing the first sub-data into the first storage unit.

[0012] For example, in the method for writing multiple sets of address data provided in at least one embodiment of this disclosure, the multiple cycle periods include the first cycle period to the Mth cycle period, where M is an integer greater than 1. In the kth cycle period of the multiple cycle periods, the y sub-data stored in at least two memories of the first storage unit includes the x sub-data and the yx sub-data stored in the at least two memories in the first cycle period to the (k-1)th cycle period, where k is an integer greater than 1 and less than M.

[0013] At least one embodiment of this disclosure also provides an address data writing device for writing the address data into N storage units, wherein the address data includes N sub-data, each of the N storage units corresponds to at least two memories, and N is an integer greater than 1. The address data writing device includes: a first writing module configured to, in response to the address of x sub-data in the N sub-data corresponding to a first storage unit in the N storage units, write the x sub-data in parallel into at least two memories of the first storage unit, wherein x is an integer greater than 1 and less than or equal to N; a reading module configured to read a first sub-data from y sub-data stored in the at least two memories of the first storage unit, wherein y is an integer greater than or equal to x; and a second writing module configured to write the first sub-data into the first storage unit.

[0014] For example, in the address data writing apparatus provided in at least one embodiment of this disclosure, the number of at least two memories of the first storage unit is greater than or equal to x, and the first writing module is further configured to write the x sub-data in parallel to x memories of the at least two memories of the first storage unit.

[0015] For example, in the address data writing device provided in at least one embodiment of this disclosure, the reading module includes a selection submodule and a reading submodule. The selection submodule is configured to select a first memory among the at least two memories based on the polling order of the at least two memories, and to select the first sub-data according to the storage order of at least one sub-data stored in the first memory. The reading submodule is configured to read the first sub-data.

[0016] For example, in the address data writing device provided in at least one embodiment of this disclosure, the first writing module is further configured to, in response to the fact that the addresses of Nx sub-data (excluding the x sub-data) among the N sub-data correspond one-to-one with the Nx storage units among the N storage units, write the Nx sub-data into the memory of the Nx storage units accordingly; the reading module is further configured to read multiple second sub-data from multiple sub-data stored in the memory of multiple second storage units (excluding the first storage unit) among the N storage units; and the second writing module is further configured to, based on the address correspondence, write the first sub-data and the multiple second sub-data in parallel into the first storage unit and the corresponding second storage unit.

[0017] At least one embodiment of this disclosure also provides an electronic device. The electronic device includes: a processor; and a memory including one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules are used to implement the address data writing method provided in any embodiment of this disclosure or the method for writing multiple sets of address data provided in any embodiment of this disclosure.

[0018] At least one embodiment of this disclosure also provides a storage medium storing non-transitory computer-readable instructions, which, when executed by a computer, implement the address data writing method provided in any embodiment of this disclosure or the multi-set address data writing method provided in any embodiment of this disclosure. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0020] Figure 1A This is a schematic diagram of a storage unit organization method;

[0021] Figure 1B A schematic diagram illustrating another method of organizing storage units;

[0022] Figure 2 An exemplary flowchart illustrating a method for writing address data provided in at least one embodiment of this disclosure;

[0023] Figure 3 A schematic diagram illustrating an example of a method for writing address data provided in at least one embodiment of this disclosure;

[0024] Figure 4 Another exemplary flowchart of the method for writing address data provided in at least one embodiment of this disclosure;

[0025] Figure 5 An exemplary flowchart illustrating a method for writing multiple sets of address data provided in at least one embodiment of this disclosure;

[0026] Figure 6A A schematic diagram illustrating an example of a method for writing multiple sets of address data provided in at least one embodiment of this disclosure;

[0027] Figure 6B A schematic diagram illustrating another example of a method for writing multiple sets of address data provided in at least one embodiment of this disclosure;

[0028] Figure 7 A schematic block diagram of an address data writing device provided for at least one embodiment of the present disclosure;

[0029] Figure 8 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure;

[0030] Figure 9 A schematic block diagram of another electronic device provided for at least one embodiment of this disclosure; and

[0031] Figure 10 This is a schematic diagram of a storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0034] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0035] To improve computational efficiency, computing devices need to be able to execute multiple load / store instructions in parallel during each cycle. Internally, computing devices include shared memory, multi-level caches, and other storage devices. To enable high-bandwidth parallel access to storage devices, the storage device is divided into equal-sized storage units that can be accessed in parallel. Writing to multiple addresses can be performed in parallel on multiple independent storage units. For example, multiple independent storage units can be organized in a multi-banking manner, where each storage unit can be a bank or a bank group containing multiple banks.

[0036] Figure 1A This is a schematic diagram of a storage unit organization method. Figure 1B This is a schematic diagram of another storage unit organization method.

[0037] For example, such as Figure 1A and Figure 1BAs shown, the internal storage device 110 can be the internal storage device of a computing device (CPU, GPU, GPGPU, or NPU, etc.), and the internal storage device 110 is interconnected with the external storage device 130 via the bus 120. For example, the internal storage device 110 can be various types of memory, cache, etc., and the external storage device 130 can be Double Data Rate Synchronous Dynamic Random Access Memory (DDR), High Bandwidth Memory (HBM), etc. The embodiments disclosed herein are not limited in this regard.

[0038] For example, such as Figure 1A As shown, taking a bank as a storage unit, the internal storage device 110 includes N banks (bank 0, bank 1, ..., bank N-1), where N is an integer greater than 1. For example, when the computing device needs to access or store data in multiple banks, it sends a corresponding request to the bus 120 to read address data from the external storage device 130. This address data contains multiple sub-data items, and the addresses of the sub-data items correspond to the banks in the internal storage device 110 to be accessed or stored. After reading back the address data, based on the correspondence between the addresses of each sub-data item in the address data and each bank, the returned sub-data items are written to the corresponding banks for subsequent access or storage operations.

[0039] For example, such as Figure 1B As shown, taking a bank group as an example of storage units, the internal storage device 110 includes N bank groups (bank group 0, bank group 1, ..., bank group N-1), and each bank group includes n banks (bank 0, bank 1, ..., bank n-1), where N and n are both integers greater than 1. For example, when the computing device needs to access or store data from multiple bank groups, Figure 1B and Figure 1A The difference in the memory access process is that the address of the sub-data corresponds to the memory bank group to be accessed or stored in the internal storage device 110, and the sub-address contained in the sub-data corresponds to the memory bank to be accessed or stored in the memory bank group; after reading back the address data, according to the correspondence between the address of each sub-data in the address data and each memory bank group, the returned sub-data is written to the corresponding memory bank group; in each memory bank group, the sub-address in the sub-data is further written to the corresponding memory bank in parallel for subsequent access or storage operations.

[0040] For example, in Figure 1A and Figure 1BIn the example, under normal circumstances, the returned multiple sub-data correspond one-to-one with the multiple storage banks / storage bank groups to be accessed or stored; when the addresses of two or more sub-data correspond to the same storage bank / storage bank group, a write conflict, also known as a bank conflict, will occur, that is, the two or more sub-data cannot be written to the corresponding same storage bank / storage bank group at the same time.

[0041] For example, in multiple cycle periods, multiple sets of address data need to be retrieved. When a write conflict occurs between sub-data 1 and sub-data 2 in one set of address data, in the current cycle, sub-data 1 can only be written in parallel with other sub-data besides sub-data 2 to the corresponding memory bank / memory bank group. Sub-data 2 can only be written to the corresponding memory bank / memory bank group alone in the next cycle period. On the one hand, in the current cycle period, since sub-data 1 and sub-data 2 cannot be written simultaneously, the unwritten sub-data 2 will generate back pressure on bus 120, affecting the overall performance of the hardware device. On the other hand, because an extra cycle is added to write sub-data 2 separately, the bandwidth of the storage device is reduced by half. For situations where write conflicts occur frequently, this will greatly reduce the bandwidth of the storage device.

[0042] Write collisions are a frequent occurrence on the transmission links of computing devices. As the number of processing cores in a computing device increases, the data access to storage units in the storage device also increases accordingly, thereby increasing the likelihood of write collisions, reducing the bandwidth of the storage device, significantly increasing data access time, and reducing the parallel processing efficiency of the computing device.

[0043] In some cases, a suitable swizzle algorithm can be used to handle write collisions. For example, different swizzle patterns can be used for the addresses of different sub-data items, and the write addresses corresponding to the storage units in the storage device can be reallocated through hashing or other methods. This ensures that the addresses of x sub-data items that have written collisions (i.e., the addresses of x sub-data items written to the same storage unit, where x is an integer greater than 1) are reassigned to x different storage units. This approach requires software intervention, and when reading data from the storage unit, dehazing also needs to be considered in software, significantly increasing software complexity.

[0044] At least one embodiment of this disclosure provides a method for writing address data, used to write address data into N storage units, wherein the address data includes N sub-data, each of the N storage units corresponds to at least two memories, and N is an integer greater than 1. The method for writing address data includes: responding to the address of x sub-data in the N sub-data corresponding to a first storage unit in the N storage units, writing x sub-data in parallel into at least two memories of the first storage unit, wherein x is an integer greater than 1 and less than or equal to N; reading a first sub-data from y sub-data stored in the at least two memories of the first storage unit, wherein y is an integer greater than or equal to x; and writing the first sub-data into the first storage unit.

[0045] At least one embodiment of this disclosure also provides a method for writing multiple sets of address data, used to write multiple sets of address data into N storage units in multiple cycle cycles; in each cycle cycle, the address data writing method of the above embodiment can be implemented for each set of address data.

[0046] At least one embodiment of this disclosure also provides an address data writing device, an electronic device, and a storage medium for implementing the address data writing method or the multiple address data writing method of the above embodiments.

[0047] The method, apparatus, electronic device, and storage medium provided in at least one embodiment of this disclosure, by setting at least two memories for each storage unit, can first write multiple sub-data that have write conflicts into the memory of the corresponding storage unit, reducing back pressure on the data input end, and without the need for software intervention, thereby solving the problem of multiple sub-data write conflicts at the hardware level and improving the parallel processing efficiency of computing devices.

[0048] At least one embodiment of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals will be used to refer to the same elements described in different drawings.

[0049] Figure 2 An exemplary flowchart of a method for writing address data provided in at least one embodiment of this disclosure.

[0050] For example, such as Figure 2 As shown, at least one embodiment of this disclosure provides a method for writing address data, used to write address data into N memory cells. For example, the address data includes N sub-data, and each of the N memory cells corresponds to at least two memory locations, where N is an integer greater than 1. For example, the method for writing address data includes the following steps S110~S130:

[0051] Step S110: In response to the address of x sub-data in N sub-data corresponding to the first storage unit in N storage units, write x sub-data in parallel to at least two storage units of the first storage unit, where x is an integer greater than 1 and less than or equal to N;

[0052] Step S120: Read the first sub-data from the y sub-data stored in at least two memories of the first storage unit, where y is an integer greater than or equal to x;

[0053] Step S130: Write the first sub-data into the first storage unit.

[0054] For example, the storage device can be divided into multiple independent storage units as N storage units provided in at least one embodiment of this disclosure. For example, the storage device can be memory, various levels of cache, etc., specifically implemented as Static Random-Access Memory (SRAM), Dynamic Random-Access Memory (DRAM), etc.; the storage units in the storage device can be storage banks or storage bankgroups, etc. The embodiments of this disclosure do not limit the type and number of storage devices and storage units. For example, each sub-data in the address data contains an address, which corresponds to a specific storage unit; by writing the sub-data to the corresponding storage unit, data can be accessed or stored in that storage unit based on the address of the sub-data; the data bit width and type of the address data and its contained sub-data, as well as the correspondence between the address of the sub-data and the storage unit, can be selected according to actual needs, and the embodiments of this disclosure do not limit this.

[0055] For example, in step S110, when the addresses of x sub-data points simultaneously correspond to the first storage unit, the x sub-data points need to be written to the first storage unit at the same time, which will result in a write conflict. When the storage unit is a storage bank or a group of storage banks, the write conflict can be a storage bank conflict. For example, before writing the x sub-data points to the first storage unit, the x sub-data points can be written in parallel to at least two memories of the first storage unit, thereby avoiding back pressure on the data input terminal caused by the sub-data points that have a write conflict.

[0056] For example, the memory can be an external memory of the corresponding memory unit, such as being located before the corresponding memory unit; the memory can also be located in other places according to actual needs, and the embodiments of this disclosure do not limit this.

[0057] For example, in step S120, for the address data input in the current cycle, x sub-data are written in parallel to at least two memories of the first storage unit; if there are still sub-data that were not written in the previous cycle in the memory of the first storage unit, then the number y of sub-data currently stored in the memory is greater than x; if there are no sub-data that were not written in the previous cycle in the memory of the first storage unit, then the y sub-data currently stored in the memory are the x sub-data written in the current cycle.

[0058] For example, in step S120, since only one sub-data can be written to the first storage unit at a time, the first sub-data is selected from the y sub-data stored in the memory of the first storage unit in a specific order and read.

[0059] For example, in step S130, the first sub-data read is further written into the first storage unit, thereby completing the data writing of the first storage unit in the current cycle.

[0060] In some examples, the number of at least two memories in the first memory unit is greater than or equal to x. For example, Figure 2 Step S110 may further include step S111: writing x sub-data in parallel to x memories in at least two memories of the first memory unit.

[0061] For example, in step S111, the number of at least two memories in the first storage unit is equal to the number of sub-data that may cause write conflicts. For example, if at most two sub-data may be written to the first storage unit simultaneously in each cycle, then the number of memories in the first storage unit is set to 2.

[0062] For example, in step S111, when the addresses of x sub-data correspond to the first storage unit at the same time, x memories of the first storage unit are selected so that the x sub-data are written in parallel to the selected x memories, thereby ensuring that the x sub-data will not backpressure the data input terminal.

[0063] In some examples, each of the at least two memories in each memory cell includes multiple memory depths, and each of the multiple memory depths has the same data bit width as each of the N sub-data. For example, the data bit width of the sub-data can be 32 bits, 64 bits, 128 bits, etc., and the embodiments of this disclosure are not limited thereto.

[0064] For example, if each memory in each storage cell can only store one piece of data, and write conflicts occur in the write links of the sub-data in multiple adjacent cycle cycles, the next piece of data may fail to be written to that memory. For instance, by setting multiple depths in each memory of each storage cell, sub-data that has experienced write conflicts in multiple adjacent cycle cycles can be written to that memory, thus avoiding the situation where sub-data cannot be written to that memory.

[0065] In some examples, Figure 2 Step S120 may further include steps S121 to S123:

[0066] Step S121: Select the first memory from at least two memories based on the polling order of at least two memories;

[0067] Step S122: Select the first sub-data according to the storage order of at least one sub-data stored in the first memory;

[0068] Step S123: Read the first sub-data.

[0069] For example, in step S121, in order to select the first sub-data in a specific order from the y sub-data stored in the memory of the first storage unit, a first memory can be selected according to a specific polling order to read the first sub-data from the first memory. For example, the polling order can be determined according to a round-robin (RR) scheduling strategy, or other polling orders can be selected according to actual needs. The embodiments of this disclosure do not limit this.

[0070] For example, in step S122, after selecting the first memory, the first sub-data can be selected according to the storage order of the sub-data in the first memory. For example, if there is still sub-data in the first memory that has not been written in the previous cycle, the sub-data with the earliest storage time can be selected as the first sub-data, or other sub-data in the storage order can be selected as the first sub-data; other selection rules can also be set according to actual needs, and the embodiments of this disclosure do not limit this.

[0071] For example, in step S123, the first sub-data selected in step S122 is further read to... Figure 2 In step S130, the first sub-data read is written into the first storage unit.

[0072] Figure 3 This is a schematic diagram illustrating an example of a method for writing address data provided in at least one embodiment of this disclosure. For example, Figure 3 for Figure 2 A specific example of steps S110 to S130.

[0073] For example, such as Figure 3 As shown, taking the first storage unit as an example with two memories (memory 0 and memory 1), each memory includes 4 storage depths, and each storage depth has the same data bit width as each sub-data. For example, memory 0 includes depths 0-0, 0-1, 0-2, and 0-3, and memory 1 includes depths 1-0, 1-1, 1-2, and 1-3.

[0074] For example, such as Figure 3 As shown, in Figure 2 In step S110, if the addresses of sub-data 0 and sub-data 1 in the address data both correspond to the first storage unit, then sub-data 0 and sub-data 1 are written to memory 0 and memory 1 in parallel. For example, specifically, step S111 is executed, writing sub-data 0 to memory 0 and sub-data 1 to memory 1. For example, if there is no other sub-data in memory 0 or memory 1, then sub-data 0 or sub-data 1 is written to the first depth of memory 0 or memory 1 (i.e., depth 0-0 or depth 1-0); if there is still sub-data in memory 0 or memory 1 that was not written in the previous cycle, for example, if there is other sub-data in depth 0-0 and depth 0-1 of memory 0, then sub-data 0 is written to depth 0-2.

[0075] For example, such as Figure 3 As shown, in Figure 2 In step S120, since only one sub-data can be written to the first storage unit at a time, the first sub-data is selected from the y sub-data stored in memory 0 and memory 1 in a specific order, and then read. For example, in step S121, the first memory is selected according to the polling order of memory 0 and memory 1, following a polling scheduling strategy. Specifically, memory 0 is selected as the first memory in the first cycle, memory 1 is selected as the first memory in the second cycle, memory 0 is selected as the first memory again in the third cycle, and so on.

[0076] For example, such as Figure 3 As shown, further, in step S122, after selecting the first memory, the first sub-data can be selected according to the storage order of the sub-data in the first memory. For example, specifically, taking memory 0 as the first memory, if the sub-data in multiple cycle periods are stored in depths 0-0, 0-1, and 0-2 respectively according to the storage order, then the sub-data with the earliest storage time (i.e., the sub-data in depth 0-0) is selected as the first sub-data. For example, combining steps S121 and S122, in Figure 3In the example, the first sub-data can be selected by polling in the order of depth 0-0, 1-0, 0-1, 1-1, 0-2, 1-2, 0-3, 1-3.

[0077] For example, such as Figure 3 As shown, further, step S123 is executed to read the first sub-data, so as to... Figure 2 In step S130, the first sub-data read is written into the first storage unit.

[0078] The address data writing method provided in at least one embodiment of this disclosure, by setting at least two memories for each memory unit, can first write multiple sub-data that have write conflicts into the memory of the corresponding memory unit, reducing back pressure on the data input end, and without the need for software intervention, thereby solving the problem of multiple sub-data write conflicts at the hardware level and improving the parallel processing efficiency of the computing device.

[0079] It should be noted that, Figure 3 The address data writing method and the settings of storage unit, memory, depth, polling mode, etc. shown are only exemplary. The specific settings can be selected according to actual needs. The embodiments disclosed herein do not limit this.

[0080] Figure 4 Another exemplary flowchart illustrates a method for writing address data provided in at least one embodiment of this disclosure. For example, Figure 4 Is Figure 2 Based on this, here is an example of writing Nx sub-data, excluding x sub-data, into the corresponding storage unit in parallel.

[0081] For example, the address data writing method provided in at least one embodiment of this disclosure further includes the following steps S140~S160:

[0082] Step S140: In response to the fact that the addresses of the Nx sub-data (excluding x sub-data) in the N sub-data correspond one-to-one with the Nx storage units in the N storage units, write the Nx sub-data into the memory of the Nx storage units accordingly;

[0083] Step S150: Read multiple second sub-data from multiple sub-data stored in the memory of multiple second storage units other than the first storage unit among N storage units;

[0084] Step S160: Based on the address correspondence, write the first sub-data and multiple second sub-data into the first storage unit and the corresponding second storage unit in parallel.

[0085] For example, in step S140, if the addresses of Nx sub-data (excluding x sub-data) in the address data correspond one-to-one with the Nx storage units in the N storage units, that is, there is no write conflict problem for the Nx sub-data (excluding x sub-data), then the Nx sub-data are first written to the memory of the Nx storage units instead of being written directly to the storage units.

[0086] For example, in step S150, the N storage units include a first storage unit and multiple second storage units other than the first storage unit. Multiple second sub-data are read from the multiple sub-data stored in the memory of the multiple second storage units. For example, if the number of multiple second storage units is N-1, in the current cycle, since the number of Nx sub-data written is less than the number of second storage units N-1, there may be a situation where one or more second storage units are not written with sub-data in the current cycle (i.e., a skipped cycle occurs); therefore, the number of multiple second sub-data read may be less than the number of multiple second storage units.

[0087] For example, a memory that responds to z memory cells other than Nx memory cells in a plurality of second memory cells stores at least one sub-data, the number of the plurality of second sub-data equal to N-x+z, where z is a positive integer less than or equal to x-1.

[0088] For example, specifically, for z memory cells (i.e., the empty second memory cells) out of Nx memory cells, if the memory of the z memory cells contains one or more sub-data (e.g., sub-data not written in previous cycles), then this sub-data is also treated as second sub-data and written to the corresponding memory cells in parallel with other second sub-data. In this case, the number of multiple second sub-data is equal to N-x+z. For example, in other cases, if the memory of the z empty memory cells does not contain sub-data, then the second sub-data is read only from the memory of the Nx second memory cells that have never been empty.

[0089] For example, in step S160, the address of the first sub-data corresponds to the first storage unit, and the address of each second sub-data also has a corresponding second storage unit. The first sub-data and multiple second sub-data are written in parallel (i.e., simultaneously) to their corresponding storage units. Specifically, in some examples, step S160 may further include step S161: writing the first sub-data to the first storage unit, and writing multiple second sub-data to their respective second storage units.

[0090] It should be noted that, in at least one embodiment of this disclosure, Figure 4 Step S140 and Figure 2Step S110 can be executed simultaneously, that is, N sub-data are written in parallel into the memory of the corresponding storage unit; Figure 4 Step S150 and Figure 2 Step S120 can also be executed simultaneously, that is, the first sub-data and multiple second sub-data are read from N-x+1 memories in parallel; Figure 4 Step S160 and Figure 2 Step S130 can also be executed simultaneously, that is, the first sub-data and multiple second sub-data are written to the corresponding storage units in parallel; or, for Figure 4 and Figure 2 The execution order of each step can also be set according to actual needs, and the embodiments disclosed herein do not limit this.

[0091] The address data writing method provided in at least one embodiment of this disclosure first writes all the sub-data of the address data into the memory of the corresponding storage unit. For x sub-data that have a write conflict in the current cycle, x-1 sub-data other than the first sub-data can also be temporarily stored in the memory. This allows them to be written into the corresponding storage unit together with the sub-data in the memory in subsequent cycles, thus achieving write-by-error. Compared with adding one or more cycles to write the x-1 sub-data that have a conflict separately, the address data writing method provided in at least one embodiment of this disclosure improves the write bandwidth of the storage device and increases the efficiency of data processing.

[0092] Figure 5 An exemplary flowchart of a method for writing multiple sets of address data provided in at least one embodiment of this disclosure.

[0093] For example, such as Figure 5 As shown, at least one embodiment of this disclosure also provides a method for writing multiple sets of address data, used to write multiple sets of address data into N memory units in multiple cycle periods. For example, each set of address data in the multiple sets of address data includes N sub-data, and each of the N memory units corresponds to at least two memory units, where N is an integer greater than 1. For example, the method for writing multiple sets of address data includes the following steps S210~S230:

[0094] Step S210: In each of the multiple loop cycles, in response to the address of x sub-data in N sub-data of each set of address data corresponding to the first memory cell in N memory cells, the x sub-data are written in parallel to at least two memory cells of the first memory cell, where x is an integer greater than 1 and less than or equal to N;

[0095] Step S220: Read the first sub-data from the y sub-data stored in at least two memories of the first storage unit, where y is an integer greater than or equal to x;

[0096] Step S230: Write the first sub-data into the first storage unit.

[0097] For example, in Figure 5 In the multi-set address data writing method shown, in each loop cycle, the writing method of each set of address data is the same as... Figure 2 The same, that is, Figure 5 Steps S210 to S230 correspond to respectively Figure 2 For steps S110~S130, please refer to the previous text for details. Figure 2 The descriptions of steps S110 to S130 will not be repeated here. Furthermore, for Figure 4 Steps S140 to S150 also apply. Figure 5 The method for writing multiple sets of address data shown in the diagram, and the specific execution method in each loop cycle, are the same as those described earlier. Figure 4 The description is the same as above, so I will not repeat it here.

[0098] It should be noted that the number of multiple cycles and the duration of each cycle can be set according to the actual situation, and the embodiments disclosed herein do not impose any restrictions on this.

[0099] In some examples, multiple cycle periods include cycle 1 through cycle M, where M is an integer greater than 1. For example, in the k-th cycle of multiple cycle periods, the y sub-data stored in at least two memories of the first storage unit includes x sub-data and yx sub-data stored in at least two memories in cycle 1 through cycle (k-1), where k is an integer greater than 1 and less than M.

[0100] For example, in the k-th cycle, the y sub-data stored in the memory of the first storage unit includes the x sub-data that have a write conflict in the current cycle, and may also include yx sub-data that were not written in previous cycles. That is, in the k-th cycle, if there are still sub-data that were not written in previous cycles in the memory of the first storage unit, then the number y of the sub-data currently stored in the memory is greater than x, and if there are no other sub-data in the memory of the first storage unit, then the number y of the sub-data currently stored in the memory is equal to x.

[0101] Figure 6A This is a schematic diagram illustrating an example of a method for writing multiple sets of address data provided in at least one embodiment of this disclosure. Figure 6B This is a schematic diagram of another example of a method for writing multiple sets of address data provided in at least one embodiment of this disclosure. For example, Figure 6A and Figure 6B for Figure 2The provided address data writing method and Figure 5 Two specific examples of methods for writing multiple sets of address data are provided.

[0102] For example, such as Figure 6A and Figure 6B As shown, the multiple loop cycles include loop cycles 1 to M. For the k-th loop cycle (where k = 1, 2, ..., M), the k-th group of address data is written to 8 memory units (memory unit 0, memory unit 1...memory unit 7, where N=8). For example, the k-th group of address data includes 8 sub-data (sub-data 0, sub-data 1...sub-data 7). For example, assume that the memory unit is a group of memory banks, and each memory unit includes 4 memory banks. For example, assume that in each loop cycle, at most 2 sub-data may be written to each memory unit simultaneously, and set the number of memories in each memory unit to 2; furthermore, set each memory to include 4 memory depths, and each memory depth is the same as the data bit width of each sub-data.

[0103] For example, such as Figure 6A As shown, taking the first loop (where k = 1) as an example, no sub-data has been written to any of the eight memory locations. For example, in Figure 2 Step S110 or Figure 5 In step S210, since the addresses of sub-data 0 and sub-data 1 in the first group of address data both correspond to memory cell 0 (i.e., the first memory cell), sub-data 0 and sub-data 1 are written in parallel to memory 0-0 and memory 0-1. For example, specifically, sub-data 0 is written to the first depth of memory 0-0, and sub-data 1 is written to the first depth of memory 0-1.

[0104] For example, such as Figure 6A As shown, with Figure 2 Step 110 synchronously, in Figure 4 In step S140, since the addresses of sub-data 2 to sub-data 7 in the first group of address data correspond one-to-one with storage units 2 to 7, meaning there is no write conflict for sub-data 2 to sub-data 7, sub-data 2 to sub-data 7 are written to storage units 2 to 7 accordingly. For example, as... Figure 6A As shown, during this cycle, storage unit 1 was idle.

[0105] For example, such as Figure 6A As shown, in Figure 2 Step S120 or Figure 5In step S220, since only one sub-data can be written to storage unit 0 at a time, the first sub-data is selected from the two sub-data stored in memory 0-0 and memory 0-1 (here y = 2) in a specific order, and the first sub-data is read. For example, memory 0-0 is selected as the first memory in a polling manner, sub-data 0 is selected as the first sub-data, and sub-data 0 (i.e., the first sub-data) is read.

[0106] For example, such as Figure 6A As shown, with Figure 2 Step 120 synchronously, in Figure 4 In step S150, storage units 1 to 7 are used as 7 second storage units. Six second sub-data (i.e., second sub-data 0 to second sub-data 5) are read from the six sub-data (i.e., sub-data 2 to sub-data 7) stored in the memory of storage units 1 to 7. Since storage unit 1 is empty and no other sub-data is stored in storage unit 1, the number of second sub-data 6 is less than the number of second storage units 7.

[0107] For example, such as Figure 6A As shown, in Figure 2 Step S130 or Figure 5 In step S230, the read sub-data 0 (i.e., the first sub-data) is written to storage unit 0 (i.e., the first storage unit); synchronously, in Figure 4 In step S160, the read sub-data 2 to sub-data 7 (i.e., second sub-data 0 to second sub-data 5) are written in parallel to the corresponding storage units 2 to storage units 7.

[0108] For example, such as Figure 6A As shown, the sub-address in each sub-data corresponds to the storage bank to be accessed or stored in the storage unit; further, in storage unit 0 and storage units 2-7, the sub-addresses in the first sub-data and the second sub-data are written in parallel to the corresponding storage banks (storage banks 0-3 and storage banks 8-31) for subsequent access or storage operations.

[0109] Depend on Figure 6A As can be seen from the example, assuming the bandwidth of the storage device is 1kB (that is, the bit width of each group of address data is 1kB), since storage cell 1 is idle in the first cycle, the bandwidth of the storage device is reduced by only 1 / 8kB; if an additional cycle is added to write the conflicting sub-data 1 separately, the bandwidth of the storage device will be reduced by half; thus, it can be seen that the address data writing method provided in at least one embodiment of this disclosure has little impact on the write bandwidth of the storage device.

[0110] For example, such as Figure 6BAs shown, taking the second loop (where k = 2) as an example, memory units 0-1 of memory cell 0 contain the sub-data 1 that was not written in the first loop, while the other 7 memory units do not store any other sub-data. For example, as Figure 6B As shown, in Figure 2 Step S110 or Figure 5 In step S210, since the addresses of sub-data 6' and sub-data 7' in the second set of address data simultaneously correspond to storage unit 7 (i.e., the first storage unit), sub-data 6' and sub-data 7' are written in parallel to memory 7-0 and memory 7-1. For example, specifically, sub-data 6' is written to the first depth of memory 7-0, and sub-data 7' is written to the first depth of memory 7-1.

[0111] For example, such as Figure 6B As shown, with Figure 2 Step 110 synchronously, in Figure 4 In step S140, it is assumed that the addresses of sub-data 0' to sub-data 5' in the second group of address data correspond one-to-one with storage units 1 to 6, that is, there is no write conflict problem for sub-data 0' to sub-data 5'. Therefore, sub-data 0' to sub-data 5' are written to storage units 1 to 6 accordingly. For example, as... Figure 6B As shown, during this cycle, storage cell 0 was left empty.

[0112] For example, such as Figure 6B As shown, in Figure 2 Step S120 or Figure 5 In step S220, since only one sub-data can be written to storage unit 7 at a time, the first sub-data is selected from the two sub-data stored in memory 7-0 and memory 7-1 (here y = 2) in a specific order, and the first sub-data is read. For example, memory 7-0 is selected as the first memory in a polling manner, sub-data 6' is selected as the first sub-data, and sub-data 6' (i.e., the first sub-data) is read.

[0113] For example, such as Figure 6B As shown, with Figure 2 Step 120 synchronously, in Figure 4 In step S150, storage units 0 to 6 are used as seven second storage units. For example, specifically, since the memory 0-1 of storage unit 0 stores sub-data 1 that was not written in the first cycle, sub-data 1 can be selected as the second sub-data 0' in the current cycle. For example, at this time, the memory of storage units 0 to 6 stores seven sub-data (i.e., sub-data 1 and sub-data 0' to sub-data 5'), and sub-data 1 and sub-data 0' to sub-data 5' are read as seven second sub-data (i.e., second sub-data 0' to second sub-data 6').

[0114] For example, such as Figure 6B As shown, in Figure 2 Step S130 or Figure 5 In step S230, the read sub-data 6' (i.e., the first sub-data) is written into storage unit 7 (i.e., the first storage unit); synchronously, in Figure 4 In step S160, the read sub-data 1 and sub-data 0' to sub-data 5' (i.e., second sub-data 0' to second sub-data 6') are written in parallel to the corresponding storage units 0 to 6.

[0115] For example, such as Figure 6B As shown, the sub-address in each sub-data corresponds to the storage bank to be accessed or stored in the storage unit; further, in storage units 0 to 7, the sub-addresses in the first sub-data and the second sub-data are written in parallel to the corresponding storage banks (storage banks 0 to 31) for subsequent access or storage operations.

[0116] Depend on Figure 6B As illustrated in the example, assuming the bandwidth of the storage device is 1kB (i.e., the bit width of each group of address data is 1kB), in the second loop, although storage cell 0 is left unused, its memory 0-1 stores the sub-data 1 that was not written in the first loop cycle. Ultimately, storage cells 0-7 are all written with their corresponding sub-data, and the bandwidth of the storage device remains 1kB, thus ensuring the bandwidth of the storage device. Therefore, for sub-data that was not written in previous loop cycles, it can be written to the corresponding storage cell along with sub-data in other memories in subsequent loop cycles, thus achieving write-on-error. Compared to adding one or more loop cycles to write the conflicting x-1 sub-data separately, the address data writing method provided in at least one embodiment of this disclosure improves the write bandwidth of the storage device and increases the efficiency of data processing.

[0117] It should be noted that, Figure 6A and Figure 6B The methods for writing multiple sets of address data and the settings of storage units, memory, etc. shown are merely exemplary. The specific settings can be selected according to actual needs, and the embodiments disclosed herein do not impose any limitations on them.

[0118] Figure 7 A schematic block diagram of an address data writing apparatus provided for at least one embodiment of the present disclosure.

[0119] For example, such as Figure 7As shown, at least one embodiment of this disclosure provides an address data writing device for writing address data to N memory cells and writing multiple sets of address data to N memory cells in multiple cycle periods. For example, the address data (equivalent to each set of address data in the multiple sets of address data) includes N sub-data, and each of the N memory cells corresponds to at least two memory locations, where N is an integer greater than 1. For example, the address data writing device 200 includes a first writing module 210, a reading module 220, and a second writing module 230.

[0120] For example, the first write module 210 is configured to, in response to the address of x sub-data out of N sub-data corresponding to the first memory cell among N memory cells, write x sub-data in parallel to at least two memories of the first memory cell, where x is an integer greater than 1 and less than or equal to N. That is, the first write module 210 can be configured to perform, for example... Figure 2 The steps S110 or shown Figure 5 The step S210 is shown.

[0121] For example, read module 220 is configured to read first sub-data from y sub-data stored in at least two memories of the first storage unit, where y is an integer greater than or equal to x. That is, read module 220 can be configured to perform, for example... Figure 2 The steps S120 shown or Figure 5 The step S220 is shown.

[0122] For example, the second write module 230 is configured to write the first sub-data to the first storage unit. That is, the second write module 230 can be configured to perform, for example... Figure 2 The steps S130 or shown Figure 5 The step S230 shown.

[0123] In some examples, the number of at least two memories of the first storage unit is greater than or equal to x. For example, the first write module 230 is also configured to write x sub-data in parallel to x memories of at least two memories of the first storage unit.

[0124] In some examples, each of the at least two memories in each memory cell includes multiple memory depths, and each of the multiple memory depths has the same data bit width as each of the N sub-data.

[0125] In some examples, the read module 220 includes a selection submodule 221 and a read submodule 222 (not shown in the figure). For example, the selection submodule 221 is configured to select a first memory from at least two memories based on the polling order of at least two memories, and to select first sub-data in the storage order of at least one sub-data stored in the first memory; the read submodule 222 is configured to read the first sub-data.

[0126] In some examples, the first write module 210 is further configured to write the Nx sub-data items into the memory of the Nx memory units, in response to the fact that the addresses of the Nx sub-data items (excluding x sub-data items) correspond one-to-one with the addresses of the Nx memory units. That is, the first write module 210 can also be configured to perform, for example... Figure 4 The step S140 shown.

[0127] For example, the read module 220 is further configured to read multiple sub-data from multiple sub-data stored in the memory of multiple second storage units other than the first storage unit among N storage units. That is, the read module 220 can also be configured to perform, for example... Figure 4 The step S150 shown.

[0128] For example, the second write module 230 is further configured to write the first sub-data and multiple second sub-data in parallel to the first storage unit and the corresponding second storage unit based on the address correspondence. That is, the second write module 230 can also be configured to perform, for example... Figure 4 The step S160 shown.

[0129] For example, the second write module 230 is further configured to write the first sub-data into the first storage unit and to write multiple second sub-data into their respective second storage units.

[0130] For example, in response to z memory cells other than Nx memory cells in a plurality of second memory cells, at least one sub-data is stored in the memory, and the number of the plurality of second sub-data cells is equal to N-x+z, where z is a positive integer less than or equal to x-1.

[0131] In some examples, a storage unit includes a storage bank or a group of storage banks.

[0132] In some examples, multiple cycle periods include cycle 1 through cycle M, where M is an integer greater than 1. For example, in the k-th cycle of multiple cycle periods, the y sub-data stored in at least two memories of the first storage unit includes x sub-data and yx sub-data stored in at least two memories in cycle 1 through cycle (k-1), where k is an integer greater than 1 and less than M.

[0133] Due to the above description, for example Figures 2-6B The details of the address data writing method and the multiple address data writing method shown have already described the operation of the address data writing device 200. Therefore, for the sake of brevity, they will not be repeated here. For relevant details, please refer to the above description. Figures 2-6B The description.

[0134] It should be noted that, Figure 7 The modules described above in the address data writing device 200 shown can be configured as software, hardware, firmware, or any combination thereof to perform specific functions. For example, these modules may correspond to dedicated integrated circuits, pure software code, or modules combining software and hardware. As an example, see [reference needed]. Figure 7 The device described may be a PC computer, tablet device, personal digital assistant, smartphone, web application or other device capable of executing program instructions, but is not limited thereto.

[0135] Furthermore, although the address data writing device 200 described above is divided into modules for performing corresponding processes, those skilled in the art will understand that the processes performed by each module can also be performed without any specific module division in the device or without clear boundaries between the modules. In addition, the above references... Figure 7 The address data writing device 200 described is not limited to the modules described above, but may also include other modules (e.g., reading module, control module, etc.) as needed, or the above modules may be combined.

[0136] At least one embodiment of this disclosure also provides an electronic device, which includes a processor and a memory; the memory includes one or more computer program modules; the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include a method for implementing the method for writing address data or a method for writing multiple sets of address data provided in the embodiments of this disclosure described above.

[0137] Figure 8 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0138] For example, such as Figure 8As shown, the electronic device 300 includes a processor 310 and a memory 320. For example, the memory 320 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 310 is used to execute the non-transitory computer-readable instructions, which, when executed by the processor 310, can perform one or more steps of the address data writing method or multiple sets of address data writing method described above. The memory 320 and the processor 310 can be interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0139] For example, processor 310 can be a central processing unit (CPU), graphics processing unit (GPU), general-purpose graphics processing unit (GPGPU), digital signal processor (DSP), or other processing unit with address data writing capability and / or program execution capability, such as field-programmable gate array (FPGA); for example, the central processing unit (CPU) can be an x86, RISC-V, or ARM architecture. Processor 310 can be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 300 to perform desired functions.

[0140] For example, memory 320 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable optical disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and processor 310 may run one or more computer program modules to implement various functions of electronic device 300. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0141] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the electronic device 300 can be referred to the description above of the address data writing method or multiple address data writing method provided in at least one embodiment of this disclosure, and will not be repeated here.

[0142] Figure 9 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0143] For example, such as Figure 9As shown, the electronic device 400 is, for example, suitable for implementing the address data writing method or the multiple address data writing method provided in the embodiments of this disclosure. It should be noted that... Figure 9 The illustrated electronic device 400 is merely an example and does not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0144] For example, such as Figure 9 As shown, electronic device 400 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 41, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 42 or a program loaded from storage device 48 into random access memory (RAM) 43. RAM 43 also stores various programs and data required for the operation of electronic device 400. Processing device 41, ROM 42, and RAM 43 are interconnected via bus 44. Input / output (I / O) interface 45 is also connected to bus 44. Typically, the following devices can be connected to I / O interface 45: input devices 46 including, for example, touch screens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 47 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 48 including, for example, magnetic tapes, hard disks, etc.; and communication devices 49. Communication device 49 allows electronic device 400 to communicate wirelessly or wiredly with other electronic devices to exchange data.

[0145] Although Figure 9 An electronic device 400 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 400 may alternatively implement or have more or fewer devices.

[0146] For detailed descriptions and technical effects of the electronic device 400, please refer to the above descriptions of the address data writing method and the method of writing multiple sets of address data, which will not be repeated here.

[0147] Figure 10 This is a schematic diagram of a storage medium provided for at least one embodiment of the present disclosure.

[0148] For example, such as Figure 10 As shown, storage medium 500 stores non-transitory computer-readable instructions 510. For example, when non-transitory computer-readable instructions 510 are executed by a computer, one or more steps of a method for writing address data or multiple sets of address data as described above are performed.

[0149] For example, this storage medium 500 can be applied to Figure 8In the illustrated electronic device 300, for example, the storage medium 500 can be the memory 320 within the electronic device 300. For example, a description of the storage medium 500 can be found here. Figure 8 The corresponding description of the memory 320 in the illustrated electronic device 300 will not be repeated here.

[0150] The following points need to be clarified regarding this disclosure:

[0151] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0152] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0153] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for writing address data, used to write the address data into N storage units, wherein, The address data includes N sub-data, and each of the N storage units corresponds to at least two memory locations, where N is an integer greater than 1. The method for writing the address data includes: In response to the address of x sub-data in the N sub-data corresponding to the first storage unit in the N storage units, before writing the x sub-data into the first storage unit, the x sub-data are written in parallel into at least two memories of the first storage unit, where x is an integer greater than 1 and less than or equal to N; Read the first sub-data from y sub-data stored in at least two memories of the first storage unit, where y is an integer greater than or equal to x; Write the first sub-data into the first storage unit; Wherein, reading the first sub-data from y sub-data stored in at least two memories of the first storage unit includes: Based on the polling order of the at least two memories, the first memory among the at least two memories is selected; The first sub-data is selected according to the storage order of at least one sub-data stored in the first memory; Read the first sub-data.

2. The method for writing address data according to claim 1, wherein, The number of at least two memories in the first storage unit is greater than or equal to x. The step of writing the x sub-data into at least two memories of the first storage unit in parallel includes: The x sub-data are written in parallel to x memories in at least two memories of the first storage unit.

3. The method for writing address data according to claim 1, wherein, Each of the at least two memories in each storage unit includes multiple storage depths, and each of the multiple storage depths has the same data bit width as each of the N sub-data.

4. The method for writing address data according to claim 1 further includes: In response to the fact that the addresses of the Nx sub-data (excluding the x sub-data) among the N sub-data correspond one-to-one with the Nx storage units among the N storage units, the Nx sub-data are written into the memory of the Nx storage units accordingly; Read multiple second sub-data from multiple sub-data stored in the memory of multiple second storage units other than the first storage unit among the N storage units; Based on the address correspondence, the first sub-data and the plurality of second sub-data are written in parallel into the first storage unit and the corresponding second storage unit.

5. The method for writing address data according to claim 4, wherein, The step of writing the first sub-data and the plurality of second sub-data into the first storage unit and the corresponding second storage unit in parallel based on the address correspondence includes: Write the first sub-data into the first storage unit, and The plurality of second sub-data are written into their respective second storage units.

6. The method for writing address data according to claim 4, wherein, In response to the memory storing at least one sub-data in z of the plurality of second storage units other than the Nx storage units, the number of the plurality of second sub-data is equal to N-x+z, where z is a positive integer less than or equal to x-1.

7. The method for writing address data according to any one of claims 1-6, wherein, The storage unit includes a storage cell or a group of storage cells.

8. A method for writing multiple sets of address data, used to write the multiple sets of address data into N storage units in multiple loop cycles, wherein, Each set of address data includes N sub-data, and each of the N storage units corresponds to at least two memory locations, where N is an integer greater than 1. The method for writing the multiple sets of address data includes: In each of the plurality of cycle cycles, the address of x sub-data in response to N sub-data of each set of address data corresponds to the first storage unit among the N storage units. Before writing the x sub-data to the first storage unit, the x sub-data is written in parallel to at least two memories of the first storage unit, where x is an integer greater than 1 and less than or equal to N. Read the first sub-data from y sub-data stored in at least two memories of the first storage unit, where y is an integer greater than or equal to x; Write the first sub-data into the first storage unit; Wherein, reading the first sub-data from y sub-data stored in at least two memories of the first storage unit includes: Based on the polling order of the at least two memories, the first memory among the at least two memories is selected; The first sub-data is selected according to the storage order of at least one sub-data stored in the first memory; Read the first sub-data.

9. The method for writing multiple sets of address data according to claim 8, wherein, The plurality of cycle periods include cycle 1 to cycle M, where M is an integer greater than 1. In the kth cycle of the plurality of cycle periods, the y sub-data stored in at least two memories of the first storage unit includes the x sub-data and the yx sub-data stored in the at least two memories in the 1st to k-1st cycle periods, where k is an integer greater than 1 and less than M.

10. An address data writing device, used to write the address data into N storage units, wherein, The address data includes N sub-data, and each of the N storage units corresponds to at least two memory locations, where N is an integer greater than 1. The address data writing device includes: The first write module is configured to respond to the address of x sub-data in the N sub-data corresponding to the first storage unit in the N storage units, and to write the x sub-data in parallel to at least two memories of the first storage unit before writing the x sub-data to the first storage unit, wherein x is an integer greater than 1 and less than or equal to N; The read module is configured to read a first sub-data from y sub-data stored in at least two memories of the first storage unit, where y is an integer greater than or equal to x; The second write module is configured to write the first sub-data into the first storage unit; The reading module includes a selection submodule and a reading submodule. The selection submodule is configured to select the first memory among the at least two memories based on the polling order of the at least two memories, and to select the first sub-data according to the storage order of at least one sub-data stored in the first memory; The reading submodule is configured to read the first sub-data.

11. The address data writing device according to claim 10, wherein, The number of at least two memories in the first storage unit is greater than or equal to x. The first writing module is further configured to write the x sub-data in parallel to x memories in at least two memories of the first storage unit.

12. The address data writing device according to claim 10, wherein, The first write module is further configured to, in response to the fact that the addresses of Nx sub-data (excluding the x sub-data) among the N sub-data correspond one-to-one with the Nx storage units among the N storage units, write the Nx sub-data into the memory of the Nx storage units accordingly. The reading module is further configured to read multiple second sub-data from multiple sub-data stored in the memory of multiple second storage units other than the first storage unit among the N storage units. The second writing module is further configured to write the first sub-data and the plurality of second sub-data in parallel to the first storage unit and the corresponding second storage unit based on the address correspondence.

13. An electronic device, comprising: processor; Memory, including one or more computer program modules; The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules are used to implement the address data writing method according to any one of claims 1-7 or the multiple set address data writing method according to claim 8 or 9.

14. A storage medium storing non-transitory computer-readable instructions, which, when executed by a computer, implement the method for writing address data according to any one of claims 1-7 or the method for writing multiple sets of address data according to claim 8 or 9.

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