Silicon carbide MOSFET device with integrated Schottky junction and manufacturing method

Abstract

The present application relates to the field of semiconductor device technology, and in particular to a silicon carbide MOSFET device with integrated Schottky junction and a manufacturing method, wherein the device comprises: an N-type silicon wafer; a groove located on the N-type silicon wafer, wherein a P+ injection region is provided on one side of the bottom of the groove, and an oxide layer and a deposited polysilicon layer are grown on the surface and sidewall of the groove; a split gate structure located above the oxide layer and the deposited polysilicon layer, wherein the split gate structure comprises an Active Gate and a Dummy Gate, and the two sides of the split gate structure comprise a P-Well region and an N-Source region; and a Contact region located above the P-Well region and the N-Source region. Thus, the problems in the related art that the electric field at the bottom of the groove of the trench-type power SiC MOSFET device is large, and it is easy to be broken down or injected into the interface state, or that the parasitic reverse diode is a bipolar device, and when working in reverse, there is a large diode reverse recovery current, resulting in large reverse losses, etc.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a silicon carbide MOSFET device with an integrated Schottky junction and a manufacturing method thereof. Background Art

[0002] SiC is mainly divided into planar type and trench type due to its excellent properties such as wide bandgap, high breakdown voltage, high critical breakdown electric field, high thermal conductivity, and high saturated electron drift velocity. Trench type power SiC MOSFET devices have lower on-resistance and greater current density due to the lack of JFET effect. They have the advantages of high integration, low on-resistance, small reverse capacitance, fast switching speed, and low switching loss. However, trench type power SiC MOSFET devices have the problem of large electric field at the bottom of the trench and easy breakdown or injection of interface states, which limits their long-term application reliability. Therefore, the mainstream products on the market are still planar trench.

[0003] In addition, the N-channel MOSFET device still parasitizes a body pin diode in its cell structure in addition to the MOS structure. Since the body diode adopts a pin structure, it will lead to a higher turn-on voltage drop and reverse recovery loss. In order to reduce the loss of this reverse diode, a common practice is to use a Schottky diode in anti-parallel with the MOSFET device to act as its freewheeling diode. However, this approach increases the cost and packaging area, which has obvious disadvantages. Summary of the invention

[0004] The present application provides a silicon carbide MOSFET device with an integrated Schottky junction and a manufacturing method to solve the problems of a silicon carbide MOSFET device with an integrated Schottky junction and a manufacturing method.

[0005] The first aspect of the present application provides a silicon carbide MOSFET device with an integrated Schottky junction, comprising: an N-type silicon wafer; a trench located on the N-type silicon wafer, wherein a P+ implantation region is provided on one side of the bottom of the trench, and an oxide layer and a deposited polysilicon layer are grown on the surface and sidewall of the trench; a split gate structure located above the oxide layer and the deposited polysilicon layer, wherein the split gate structure includes an Active Gate and a Dummy Gate, and both sides of the split gate structure include a P-Well region and an N-Source region; and a Contact region located above the P-Well region and the N-Source region. .

[0006] Preferably, a square-shaped Contact region is provided on the P-Well region and the N-Source region, wherein the P-Well region and the Contact region are block structures.

[0007] Preferably, the Contact region forms an ohmic contact with the P-Well region; and the Contact region forms a Schottky contact with the N-Source region.

[0008] Preferably, the P-Well region and the N-Source region are formed based on ion implantation, and the Contact region is formed by dry etching.

[0009] Preferably, one side gate of the split gate structure is an Active Gate, which is used for the switching operation of the device and the conduction of current, and the other side Dummy Gate and Source Contact are of equal potential, which are used to deplete the P-plus at the bottom of the trench during reverse withstand voltage, and deplete the adjacent trenches on both sides together to form a space charge region.

[0010] Preferably, the split gate structure and the trench are formed by dry etching, and the P+ implantation region is formed by ion implantation.

[0011] Preferably, the oxide layer and the deposited polysilicon layer are formed by thermal oxidation and deposition processes.

[0012] The second aspect of the present application provides a method for manufacturing a silicon carbide MOSFET device with an integrated Schottky junction, comprising the following steps: selecting an N-type silicon wafer with a preset resistivity; digging a groove on the N-type silicon wafer, and digging a P+ implantation region at one end of the bottom of the groove, wherein an oxide layer and a deposited polysilicon layer are grown on the surface and sidewalls of the groove; using dry etching to generate a split gate structure, wherein one side of the split gate structure is an Active Gate, which is used for the switching operation of the device and the conduction of the current, and the other side is a Dummy Gate and a Source Gate. The Contact equipotential is used to deplete the P-plus at the bottom of the groove during reverse withstand voltage, and deplete the adjacent grooves on both sides together to form a space charge region; define a strip-shaped P-Well area and an N-Source area, perform ion implantation on the P-Well layer and the N-Source layer through an ion implantation process, and form a block-shaped Contact connection through dry etching, the Contact and the P-Well area form an ohmic contact, and the Contact and the N-Plus area form a Schottky contact, so as to complete the manufacture of the silicon carbide MOSFET device with an integrated Schottky junction.

[0013] Preferably, the method of generating a split gate structure by dry etching includes: growing an oxide layer and depositing a polysilicon layer on an N-type silicon wafer as an etching mask; using photolithography technology to define a split gate pattern on the oxide layer; using dry etching technology to etch away the portion of the silicon wafer not covered by the oxide layer to form a split gate structure, removing the oxide layer, and completing the production of the split gate structure.

[0014] Preferably, the defining of the P-Well area and the N-Source area includes: identifying the position, size and state of the planned P-Well area and the N-Source area; generating a corresponding mask pattern according to the position, size and state of the P-Well area and the N-Source area; and transferring the mask pattern to the corresponding P-Well area and the N-Source area of ​​the N-type silicon wafer using a mask technology to define the P-Well area and the N-Source area.

[0015] Therefore, this application has at least the following beneficial effects:

[0016] The embodiment of the present application utilizes a split gate structure and P-plus injection at the bottom of the trench. During reverse withstand voltage, the adjacent trenches on both sides are depleted together to form a space charge region for protecting the gate oxide at the bottom of the trench, thereby achieving a high withstand voltage. The Schottky structure is integrated and the unipolar characteristics of the Schottky are utilized. When the device is turned off, the reverse recovery current of the diode can be effectively reduced, thereby reducing the operating loss of the device.

[0017] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1 A schematic diagram of the overall device structure provided according to an embodiment of the present application;

[0020] Figure 2 is a flow chart of a method for manufacturing a silicon carbide MOSFET device with an integrated Schottky junction according to an embodiment of the present application;

[0021] Figure 3 A schematic diagram of an N-type silicon wafer provided according to an embodiment of the present application;

[0022] Figure 4 A schematic diagram of a groove provided according to an embodiment of the present application;

[0023] Figure 5A schematic diagram of injecting a P+ region according to an embodiment of the present application;

[0024] Figure 6 A schematic diagram of an oxide layer and a deposited polysilicon layer provided according to an embodiment of the present application;

[0025] Figure 7 A schematic diagram of a split-gate structure provided according to an embodiment of the present application;

[0026] Figure 8 It is a schematic diagram of a P-Well region and an N-Source region provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0028] SiC trench MOSFET has lower on-resistance and higher current density due to the lack of JFET effect. However, trench power SiC MOSFET devices have problems such as large electric field at the bottom of the trench and easy breakdown or injection of interface states, which limits their long-term application reliability. In addition, the excessive reverse recovery current of the diode is also a problem that SiC MOSFET needs to be continuously optimized.

[0029] Therefore, the present application discloses a novel silicon carbide trench MOSFET structure with integrated Schottky junction, which can effectively protect the gate oxide at the bottom of the trench, so that the device can work under high withstand voltage conditions; the integrated Schottky diode can effectively reduce the diode reverse recovery current generated when the MOSFET is turned off, and reduce the loss of the device operation.

[0030] The following describes the integrated Schottky junction silicon carbide MOSFET device and manufacturing method of the present application embodiment with reference to the accompanying drawings. Specifically, Figure 1 A block diagram of a silicon carbide MOSFET device with an integrated Schottky junction provided in an embodiment of the present application.

[0031] like Figure 1 As shown, the silicon carbide MOSFET device with integrated Schottky junction includes: an N-type silicon wafer, a trench, a P+ implantation region, a split gate structure, a P-Well region, an N-Source region and a Contact region.

[0032] The trench is located on an N-type silicon wafer, wherein a P+ implantation region is provided on one side of the bottom of the trench, and an oxide layer and a deposited polysilicon layer are grown on the surface and sidewall of the trench; the split gate structure is located above the oxide layer and the deposited polysilicon layer, wherein the split gate structure includes an Active Gate and a Dummy Gate, and both sides of the split gate structure include a P-Well region and an N-Source region, and the Contact region is located above the P-Well region and the N-Source region.

[0033] It can be understood that the silicon carbide MOSFET device with integrated Schottky junction in the embodiment of the present application eliminates the JFET resistance and effectively reduces the specific on-resistance. In addition, the split gate structure has a gate on one side that is a channel gate for the switching operation of the device and the conduction of the current, and the gate on the other side is at the same potential as the Source Contact. During reverse withstand voltage, it is depleted together with the P-plus at the bottom of the trench, and the adjacent trenches on both sides are depleted together to form a space charge region for protecting the gate oxide at the bottom of the trench, playing a role in high withstand voltage; the bottom of the Contact forms an ohmic contact with the P-Well region for forward conduction of the device, and there is no P-Well region at the bottom of the Contact, and a Schottky contact is formed with the N-Source region. Due to the unipolar characteristics of the Schottky, when the device is turned off, the reverse recovery current of the diode can be effectively reduced, thereby reducing the working loss of the device.

[0034] In the embodiment of the present application, the P-Well region and the Contact region are block structures; the Contact region forms an ohmic contact with the P-Well region; and the Contact region forms a Schottky contact with the N-Source region.

[0035] It can be understood that the Contact region of the embodiment of the present application forms an ohmic contact with the P-Well region. Due to the unipolar characteristics of the Schottky diode, when the device is turned off, the reverse recovery current of the diode can be effectively reduced, thereby reducing the operating loss of the device. The Contact region forms a Schottky contact with the N-Source region for forward conduction of the device.

[0036] In the embodiment of the present application, the P-Well region and the N-Source region are formed based on ion implantation, and the Contact region is formed by dry etching.

[0037] It can be understood that in the embodiment of the present application, the P-Well region and the N-Source region are formed based on ion implantation, and the Contact region is formed by dry etching, which can improve the performance of the device, reduce the size of the device, and enhance the reliability of the device.

[0038] It should be noted that ion implantation is the process of implanting ions into semiconductor materials, and its main purpose is to change the electrical properties of semiconductor materials.

[0039] In the embodiment of the present application, one side of the split gate structure is the Active Gate, which is used for the switching operation of the device and the conduction of current. The other side, the Dummy Gate and the Source Contact, have the same potential and are used to deplete the P-plus at the bottom of the trench during reverse withstand voltage, and deplete the adjacent trenches on both sides together to form a space charge region.

[0040] It can be understood that one side of the split gate structure of the embodiment of the present application is an Active Gate for conducting the channel, and the other side is a Dummy Gate for connecting to the same potential as the bottom P+ to protect the bottom gate oxide during reverse depletion.

[0041] In the embodiment of the present application, the split gate structure and the trench are formed by dry etching, and the P+ implantation region is formed by ion implantation.

[0042] It can be understood that in the embodiment of the present application, the split gate structure and the trench are formed by dry etching, and the P+ implantation area is formed by ion implantation, which can improve the performance of the device, reduce the size of the device, and enhance the reliability of the device.

[0043] It should be noted that dry etching is used to etch specific patterns and structures on semiconductor materials.

[0044] In the embodiment of the present application, the oxide layer and the deposited polysilicon layer are formed by thermal oxidation and deposition processes.

[0045] It can be understood that the oxide layer and deposited polysilicon layer of the embodiment of the present application are formed by thermal oxidation and deposition processes. The oxide layer can be used as a passivation layer of the device to protect the surface of the device from the influence of the external environment, improve the reliability and stability of the device, and reduce the reverse leakage of the device; the deposited polysilicon layer is used as the gate electrode of the device for switching the device.

[0046] It should be noted that the thermal oxidation process is to expose the semiconductor material to a high-temperature oxygen environment so that an oxidation reaction occurs on its surface to form an oxide layer. The thermal oxidation process can form an oxide layer on the surface of semiconductor materials such as silicon, germanium, and gallium arsenide. The thickness and properties of the oxide layer can be adjusted by controlling the parameters of the thermal oxidation process. The advantages of the thermal oxidation process are simple process, low cost, and high quality of the oxide layer. The disadvantage is that the thickness and properties of the oxide layer are limited by the process parameters and are difficult to control accurately; the deposition process is to deposit one or more materials in the form of a thin film on the surface of the semiconductor material. The deposition process can form thin films of various materials, such as silicon oxide, silicon nitride, polysilicon, etc., on the surface of semiconductor materials such as silicon, germanium, and gallium arsenide. The advantage of the deposition process is that the thickness and properties of the film can be accurately controlled. The disadvantage is that the process is complex, the cost is high, and the quality of the film is greatly affected by the process parameters.

[0047] According to the silicon carbide MOSFET device with integrated Schottky junction proposed in the embodiment of the present application, a P+ injection region and a groove are provided on one side of the bottom of the groove to increase the channel density of the current, optimize the current path, and improve the current flow capacity of the device. In addition, in the split gate structure, one side of the gate is a channel gate, which is used for the switching operation of the device and the conduction of the current, and the other side of the gate and the Source Contact are of equal potential. During reverse withstand voltage, the P-plus at the bottom of the groove is depleted, and the adjacent grooves on both sides are depleted together to form a space charge region, which is used to protect the gate oxide at the bottom of the groove and play a role in high withstand voltage; the bottom of the Contact forms an ohmic contact with the P-Well region for forward conduction of the device, there is no P-Well region at the bottom of the Contact, and a Schottky contact is formed with the N-Source region. Due to the unipolar characteristics of the Schottky, when the device is turned off, the reverse recovery current of the diode can be effectively reduced, thereby reducing the working loss of the device.

[0048] Next, a method for manufacturing a silicon carbide MOSFET device with an integrated Schottky junction according to an embodiment of the present application is described with reference to the accompanying drawings.

[0049] like Figure 2 As shown, the method for manufacturing the silicon carbide MOSFET device with integrated Schottky junction comprises the following steps:

[0050] In step S101 , an N-type silicon wafer with a preset resistivity is selected.

[0051] Among them, the preset resistivity can be set according to actual needs without specific limitation.

[0052] In step S102, a trench is dug on an N-type silicon wafer, and a P+ implantation region is dug at one end of the bottom of the trench, wherein an oxide layer and a deposited polysilicon layer are grown on the surface and sidewalls of the trench.

[0053] It can be understood that in the embodiment of the present application, a groove is dug on an N-type silicon wafer, and a P+ injection region is dug at one end of the bottom of the groove. When the reverse withstand voltage is applied, the P-plus at the bottom of the groove is depleted, and the adjacent grooves on both sides are depleted together to form a space charge region, which is used to protect the gate oxide at the bottom of the groove and play a role in high withstand voltage.

[0054] In step S103, dry etching is used to generate a split gate structure, wherein one side of the split gate structure is an Active Gate for the switching operation of the device and the conduction of current, and the other side is a Dummy Gate and a Source Contact with equal potential, which are used to deplete the P-plus at the bottom of the trench during reverse withstand voltage, and deplete the adjacent trenches on both sides together to form a space charge region.

[0055] It can be understood that one side of the gate of the split gate structure in the embodiment of the present application is the Active Gate, which is used for the switching operation of the device and the conduction of current, and the other side Dummy Gate and Source Contact have equal potentials, which are used to deplete the P-plus at the bottom of the trench during reverse withstand voltage, and deplete the adjacent trenches on both sides together to form a space charge region, which is used to protect the gate oxide at the bottom of the trench and play a role in high withstand voltage.

[0056] In an embodiment of the present application, a split gate structure is generated by dry etching, including: growing an oxide layer and depositing a polysilicon layer on an N-type silicon wafer as an etching mask; using photolithography technology to define a split gate pattern on the oxide layer; using dry etching technology to etch away the portion of the silicon wafer not covered by the oxide layer to form a split gate structure, removing the oxide layer, and completing the production of the split gate structure.

[0057] It can be understood that the embodiments of the present application can grow an oxide layer and deposit a polysilicon layer on an N-type silicon wafer as an etching mask; use photolithography technology to define a split gate pattern on the oxide layer; use dry etching technology to etch away the portion of the silicon wafer not covered by the oxide layer to form a split gate structure, remove the oxide layer, complete the manufacture of the split gate structure, improve the performance of the device, and enhance the reliability of the device.

[0058] In step S104, strip-shaped P-Well regions and N-Source regions are defined, ion implantation is performed on the P-Well layer and the N-Source layer through an ion implantation process, and block-shaped Contact connections are formed by dry etching, and an ohmic contact is formed between the Contact and P-Well regions, and a Schottky contact is formed between the Contact and N-Plus regions, so as to complete the manufacture of a silicon carbide MOSFET device with an integrated Schottky junction.

[0059] It can be understood that in the embodiment of the present application, the P-Well region at the bottom of the Contact forms an ohmic contact for forward conduction of the device. There is no P-Well region at the bottom of the Contact, and a Schottky contact is formed with the N-Source region. Due to the unipolar characteristics of the Schottky, when the device is turned off, the reverse recovery current of the diode can be effectively reduced, thereby reducing the operating loss of the device.

[0060] In an embodiment of the present application, the position, size and state of the planned P-Well area and N-Source area are identified; a corresponding mask pattern is generated according to the position, size and state of the P-Well area and N-Source area; and the mask pattern is transferred to the corresponding P-Well area and N-Source area of ​​the N-type silicon wafer using a mask technology to define the P-Well area and N-Source area.

[0061] It can be understood that the embodiment of the present application generates a corresponding mask pattern according to the position, size and state of the P-Well area and the N-Source area; and uses mask technology to transfer the mask pattern to the corresponding P-Well area and N-Source area of ​​the N-type silicon wafer to define the P-Well area and the N-Source area, thereby improving the performance of the device and enhancing the reliability of the device.

[0062] It should be noted that the mask technology is to use a high-precision laser or electron beam system to engrave a mask pattern on a transparent quartz glass substrate, place the mask pattern on an N-type semiconductor substrate, and expose it through a photolithography system to transfer the mask pattern to the N-type semiconductor substrate.

[0063] The following is a specific embodiment to illustrate the manufacturing method of the silicon carbide MOSFET device with integrated Schottky junction of the present application, wherein the silicon carbide MOSFET device with integrated Schottky junction belongs to the design and manufacturing technology of SIC MOSFET, and the specific steps are as follows:

[0064] 1. First, select an N-type silicon wafer with a suitable resistivity ( Figure 3 );

[0065] 2. Dig trench on N- substrate silicon wafer ( Figure 4 );

[0066] 3. Inject P+ ( Figure 5 );

[0067] 4. Grow an oxide layer, deposit a Poly layer, and etch the Poly back to the Si surface ( Figure 6 );

[0068] 5. Use mask to define the Active and Dummy Gate patterns, and use dry etching to etch the Gate into a split gate structure. One side is the Active Gate, which is used for channel conduction, and the other side is the Dummy Gate, which is used to connect to the bottom P+ at the same potential to protect the bottom gate oxide during reverse depletion ( Figure 7 );

[0069] 6. Use mask to define strip-shaped P-Well and N-Source, and perform P-Well and N-Source injection ( Figure 8 );

[0070] 7. Use mask to define Contact as a block structure, dry etch out block Contact connection, form ohmic contact with P-Well, and form Schottky contact with N-Plus, and the device definition is completed ( Figure 1 ).

[0071] According to the manufacturing method of the silicon carbide MOSFET device with integrated Schottky junction proposed in the embodiment of the present application, the gate is made into a split gate structure by dry etching, one side of the gate is a channel gate, which is used for the switching operation of the device and the conduction of current, and the other side of the gate and the source contact have the same potential. During reverse withstand voltage, it is depleted together with the P-plus at the bottom of the trench, and the adjacent trenches on both sides are depleted together to form a space charge region, which effectively protects the gate oxide at the bottom of the trench and enables the device to operate under high withstand voltage conditions; the integrated Schottky diode can effectively reduce the diode reverse recovery current generated when the MOSFET is turned off, thereby reducing the loss of the device operation.

[0072] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0073] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0074] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0075] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one or a combination of multiple of the following technologies known in the art: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array, a field programmable gate array, etc.

[0076] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0077] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A silicon carbide MOSFET device with integrated Schottky junction, characterized in that: include: N-type silicon wafer; A groove located on the N-type silicon wafer, wherein a P+ implantation region is provided on one side of the bottom of the groove, and an oxide layer and a deposited polysilicon layer are grown on the surface and sidewalls of the groove; A split gate structure located above the oxide layer and the deposited polysilicon layer, wherein the split gate structure includes an Active Gate and a Dummy Gate, and both sides of the split gate structure include a P-Well region and an N-Source region, wherein the Dummy Gate and the Source Contact have the same potential and are used to deplete the P-plus at the bottom of the trench during reverse withstand voltage, and deplete the adjacent trenches on both sides together to form a space charge region; A contact region is located above the P-Well region and the N-Source region, wherein the contact region forms an ohmic contact with the P-Well region; and the contact region forms a Schottky contact with the N-Source region.

2. The silicon carbide MOSFET device with integrated Schottky junction according to claim 1, characterized in that: The P-Well region and the Contact region are block structures.

3. The silicon carbide MOSFET device with integrated Schottky junction according to claim 2, characterized in that: The P-Well region and the N-Source region are formed based on ion implantation, and the Contact region is formed by dry etching.

4. The silicon carbide MOSFET device with integrated Schottky junction according to claim 1, characterized in that: One side gate of the split gate structure is an Active Gate, which is used for the switching operation of the device and the conduction of current.

5. The silicon carbide MOSFET device with integrated Schottky junction according to claim 1, characterized in that: The split gate structure and the trench are formed by dry etching, and the P+ implantation region is formed by ion implantation.

6. The silicon carbide MOSFET device with integrated Schottky junction according to claim 1, characterized in that: The oxide layer and the deposited polysilicon layer are formed by thermal oxidation and deposition processes.

7. A method for manufacturing a silicon carbide MOSFET device with an integrated Schottky junction, characterized in that: The following steps are involved: Select an N-type silicon wafer with a preset resistivity; A trench is dug on the N-type silicon wafer, and a P+ implantation region is dug at one end of the bottom of the trench, wherein an oxide layer and a deposited polysilicon layer are grown on the surface and sidewall of the trench; A split gate structure is generated by dry etching, wherein one side of the split gate structure is an Active Gate for the switching operation of the device and the conduction of the current, and the other side is a Dummy Gate and a Source Contact with the same potential, which is used to deplete the P-plus at the bottom of the trench during reverse withstand voltage, and the adjacent trenches on both sides are depleted together to form a space charge region; A P-Well region and an N-Source region are defined, ions are implanted into the P-Well region and the N-Source region through an ion implantation process, and a block-shaped Contact connection is formed by dry etching, the Contact and the P-Well region form a Schottky contact, and the Contact and the N-Plus region form an ohmic contact, so as to complete the manufacture of the silicon carbide MOSFET device with an integrated Schottky junction.

8. The method for manufacturing a silicon carbide MOSFET device with integrated Schottky junction according to claim 7, characterized in that: The method of generating a split gate structure by dry etching includes: An oxide layer is grown on the N-type silicon wafer and a polysilicon layer is deposited as an etching mask; Using photolithography technology to define the split gate pattern on the oxide layer; Use dry etching technology to etch away the portion of the silicon wafer that is not covered by the oxide layer to form a split-gate structure, remove the oxide layer, and complete the production of the split-gate structure.

9. The method for manufacturing a silicon carbide MOSFET device with integrated Schottky junction according to claim 7, characterized in that: The definition of the P-Well region and the N-Source region includes: Identify the location, size and status of the planned P-Well area and N-Source area; generating a corresponding mask pattern according to the position, size and state of the P-Well region and the N-Source region; The mask pattern is transferred to the corresponding P-Well region and the N-Source region of the N-type silicon wafer by using a mask technology to define the P-Well region and the N-Source region.

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