Semiconductor device structure and preparation method thereof

Abstract

The invention provides a semiconductor device structure and a preparation method thereof. The semiconductor device structure comprises a first conductive type back surface layer, a trench gate and a deep trench field plate, wherein the first conductive type back surface layer is composed of a first conductive type buffer layer and a first conductive type follow current heavily doped region below the deep trench field plate; the trench gate penetrates through a second conductive type body region and extends into a first conductive type substrate layer; and the depth of the trench gate penetrating through the first conductive type heavily doped region is smaller than that of the deep trench field plate. The deep trench field plates in short circuit with the emitter electrode are arranged on the two sides of the trench gate, so that a large number of holes can be accumulated when the deep trench field plates are conducted, and the conduction voltage drop is reduced; meanwhile, the vertical electric field distribution is added into the deep trench field plate to optimize the compromise relation between the FRD breakdown voltage and the break-over voltage in the RC-IGBT, so that the working loss of the RC-IGBT in the follow current state is reduced; besides, carriers in a depletion layer can be rapidly extracted in a follow current state in cooperation with a deep trench field plate, so that the current released during reverse recovery is reduced, and the peak current of reverse recovery is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a semiconductor device structure and a preparation method thereof. Background Art

[0002] As an advanced power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device technology, IGBT (Insulated Gate Bipolar Transisitor) is widely used in the high voltage field.

[0003] like Figure 1 As shown in the figure, it is a device cross-sectional structure diagram of the IGBT device cell region including TGFS (Trench gate field stop, trench gate-long dielectric layer) in the prior art. The back side of the IGBT cell is formed by injection into a back side P-type heavily doped region (P+), and holes are injected into the N-type substrate (substrate) when the IGBT is turned on to perform conductivity modulation, thereby greatly reducing the on-state voltage drop; the back side of the IGBT cell is also provided with an N-type buffer layer (buffer) to rapidly reduce the electric field when the IGBT is reversely withstand voltage, so as to achieve low resistivity and high withstand voltage in the N-type substrate region.

[0004] However, this type of IGBT will repeatedly inject and extract holes during the switching process. Although these unbalanced carriers inject holes through conductivity modulation to reduce the resistivity of the N-type substrate when the IGBT is turned on, thereby reducing the on-state voltage drop; at the same time, when the IGBT is turned off, the unbalanced hole tail current will increase the loss, thereby increasing the turn-off loss. Therefore, the inverse correlation between the on-state voltage drop and the turn-off loss requires a trade off (balance) between the on-state voltage drop and the turn-off loss in the design of the IGBT, which limits the efficiency performance of the IGBT in the electronic power system.

[0005] In addition, in RC-IGBT (Reverse Conducting-IGBT), since FRD (Fast Recovery Diode) is integrated into the IGBT, the resistivity of the shared substrate not only affects the on-state voltage drop and turn-off loss of the IGBT, but also affects the BV (Breakdown Voltage) and VF (Forward Voltage) of the internally integrated FRD, thereby limiting the dual optimization of BV and VF of FRD in the RC-IGBT, resulting in a large working loss when it is in the freewheeling state; at the same time, the FRD in the RC-IGBT will form a spike current during reverse recovery, resulting in greater switching losses and poor reliability of the RC-IGBT, and is prone to generating large electromagnetic interference.

[0006] Therefore, there is an urgent need for a structure or method that can significantly improve the trade-off relationship between the on-state voltage drop and the turn-off loss of the IGBT in the RC-IGBT, the relationship between the FRD breakdown voltage and the on-state voltage drop, and reduce the reverse recovery peak current, so as to improve the device performance and reliability of the RC-IGBT.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0008] In view of the above shortcomings of the prior art, the object of the present invention is to provide a semiconductor device structure and a preparation method thereof, which are used to solve the problems in the prior art that the on-state voltage drop and breakdown voltage of the RC-IGBT are difficult to optimize simultaneously and the reverse recovery peak current is large.

[0009] To achieve the above object, the present invention provides a semiconductor device structure, the semiconductor device structure comprising: a collector, a second conductivity type heavily doped layer, a first conductivity type back layer, a first conductivity type substrate layer, a trench gate, a deep trench field plate, a second conductivity type body region, a first conductivity type heavily doped region, a gate, and an emitter;

[0010] The first conductive type back layer comprises a first conductive type buffer layer and a first conductive type freewheeling heavily doped region which are alternately distributed along the distribution direction of the trench gate and the deep trench field plate, and the first conductive type freewheeling heavily doped region is distributed at a corresponding position below the deep trench field plate;

[0011] The first conductive type substrate layer comprises a first surface and a second surface which are arranged opposite to each other, the first conductive type back surface layer, the second conductive type heavily doped layer and the collector are sequentially located on the second surface of the first conductive type substrate layer from top to bottom, and the second conductive type body region and the first conductive type heavily doped region are sequentially located on the first surface of the first conductive type substrate layer from bottom to top;

[0012] The trench gate and the deep trench field plate are both filling layers in the trench that penetrates the second conductive type body region and extends into the first conductive type substrate layer, the depth of the trench gate is less than the depth of the deep trench field plate, and the trench gate also penetrates the first conductive type heavily doped region;

[0013] The emitter is effectively electrically connected to the deep trench field plate, the second conductive type body region, and the second conductive type heavily doped layer, and the gate is effectively electrically connected to the trench gate.

[0014] Optionally, the depth of the deep trench field plate is greater than or equal to 20 microns.

[0015] Optionally, the depth of the deep trench field plate is 2-3 times the depth of the trench gate.

[0016] Optionally, the trench gate includes a gate oxide layer and a gate polysilicon, the gate oxide layer covers the inner wall of the trench where the trench gate is located, and the gate polysilicon fills the surface of the gate oxide layer in the trench where the trench gate is located; the deep trench field plate includes a field plate oxide layer and a field plate polysilicon, the field plate oxide layer covers the inner wall of the trench where the deep trench field plate is located, and the field plate polysilicon fills the surface of the field plate oxide layer in the trench where the deep trench field plate is located.

[0017] Optionally, the semiconductor device structure further includes a passivation layer and a protective layer, the passivation layer is located on all surfaces of the gate and the emitter that are not conductively led out, and the protective layer is located on the surface of the passivation layer.

[0018] Optionally, the semiconductor device structure further includes an interlayer dielectric layer; the interlayer dielectric layer is located on the exposed surface of the first conductive type heavily doped region between adjacent gates and / or emitters to insulate and isolate adjacent gates and / or emitters.

[0019] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.

[0020] The present invention also provides a method for preparing a semiconductor device structure, the method for preparing any one of the above-mentioned semiconductor device structures, the method comprising:

[0021] Providing a first conductive type substrate, the first conductive type substrate comprising a first surface and a second surface opposite to each other;

[0022] Disposing a first trench and a second trench on the first surface of the first conductive type substrate, wherein the depth of the second trench is greater than the depth of the first trench;

[0023] Disposing a trench gate in the first trench and a deep trench field plate in the second trench;

[0024] Doping is performed at a position on the first surface of the first conductive type substrate where the trench gate and the deep trench field plate are not provided, to obtain a second conductive type body region and a first conductive type heavily doped region, wherein the second conductive type body region and the first conductive type heavily doped region are sequentially located from bottom to top in a position close to the first surface of the first conductive type substrate;

[0025] A patterned trench is provided in the first conductive type heavily doped region and the second conductive type body region, wherein the patterned trench penetrates the first conductive type heavily doped region and extends into the second conductive type body region to expose the surfaces of the trench gate, the deep trench field plate and the second conductive type body region;

[0026] A patterned conductive layer is provided to cover the surface exposed by the patterned trench, the conductive layer electrically connected to the trench gate is a gate, and the conductive layer electrically connected to the deep trench field plate is an emitter;

[0027] The second surface of the first conductive type substrate is doped to obtain a first conductive type back layer and a second conductive type heavily doped layer, wherein the first conductive type back layer comprises a first conductive type buffer layer and a first conductive type freewheeling heavily doped region that are alternately distributed along the distribution direction of the trench gate and the deep trench field plate, and the first conductive type freewheeling heavily doped region is distributed at a corresponding position below the deep trench field plate; the first conductive type back layer and the second conductive type heavily doped layer are sequentially located from top to bottom in a position close to the second surface of the first conductive type substrate, and the first conductive type substrate between the first conductive type back layer and the second conductive type body region is a first conductive type substrate layer;

[0028] A collector electrode is disposed on the surface of the second conductive type heavily doped layer.

[0029] Optionally, the method of providing the first trench and the second trench on the first surface of the first conductive type substrate includes:

[0030] Disposing a hard mask layer on the first surface of the first conductive type substrate, wherein the hard mask layer comprises a silicon dioxide layer, a silicon nitride layer and a silicon dioxide layer in sequence from bottom to top;

[0031] Patterning the hard mask layer to expose the first surface of the first conductive type substrate for setting a preset position of the first trench;

[0032] Using the patterned hard mask layer as a mask, etching the first surface of the first conductive type substrate to obtain a first trench;

[0033] Patterning the hard mask layer again to simultaneously expose the first surface of the first conductive type substrate for setting the preset positions of the first trench and the second trench;

[0034] Using the patterned hard mask layer as a mask, etching the first surface of the first conductive type substrate to obtain a second trench; and further etching the first trench to obtain a second trench having a depth greater than a deep portion of the first trench;

[0035] The remaining hard mask layer is removed.

[0036] Optionally, the method of providing the trench gate and the deep trench field plate includes:

[0037] Thermally oxidizing the inner surfaces of the first trench and the second trench by furnace tube growth to obtain a gate oxide layer on the inner surface of the first trench and a field plate oxide layer on the inner surface of the second trench;

[0038] Filling the first trench and the second trench with polysilicon grown by a furnace tube, so that the surface of the gate oxide layer in the first trench is filled with gate polysilicon, and the surface of the field plate oxide layer in the second trench is filled with field plate polysilicon;

[0039] The first surface of the first conductive type substrate is planarized to expose the trench gate in the first trench and the deep trench field plate in the second trench.

[0040] As described above, the semiconductor device structure and the method for manufacturing the same of the present invention have the following beneficial effects:

[0041] The present invention arranges deep trench field plates short-circuited with the emitter on both sides of the trench gate, so that a large number of holes are accumulated in the deep trench field plates when the semiconductor device structure is turned on, thereby reducing the conduction voltage drop;

[0042] The present invention optimizes the compromise relationship between the FRD breakdown voltage and the on-voltage in the RC-IGBT by using the vertical electric field distribution added by the deep trench field plate, thereby reducing the working loss of the RC-IGBT in the freewheeling state;

[0043] The present invention cooperates with the deep trench field plate to enable the carriers in the depletion layer to be quickly extracted in the freewheeling state, thereby reducing the current released during reverse recovery and lowering the reverse recovery peak current. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic diagram of the structure of RC-IGBT in the prior art.

[0045] Figure 2 Shown is a schematic structural diagram of the semiconductor device structure in the present invention.

[0046] Figure 3 It is a schematic diagram of the structure presented by setting a hard mask layer in an optional example of step 2 of the method for preparing the semiconductor device structure of the present invention.

[0047] Figure 4 Shown is a schematic diagram of the structure presented by the patterned hard mask layer in an optional example of step 2 of the method for preparing the semiconductor device structure of the present invention.

[0048] Figure 5 It shows a schematic diagram of the structure of the first groove obtained in an optional example of step 2 of the method for preparing the semiconductor device structure of the present invention.

[0049] Figure 6 It is a schematic diagram of the structure presented by re-patterning the hard mask layer in an optional example of step 2 of the method for preparing the semiconductor device structure of the present invention.

[0050] Figure 7 It shows a schematic diagram of the structure of the first trench and the second trench obtained in an optional example of step 2 of the method for preparing the semiconductor device structure of the present invention.

[0051] Figure 8 It shows a schematic diagram of the structure presented by providing a trench gate and a deep trench field plate in step 3 of the method for preparing a semiconductor device structure of the present invention.

[0052] Fig. 9 It is a schematic diagram showing the structure presented by the second conductivity type body region and the first conductivity type heavily doped region obtained in step 4 of the method for preparing the semiconductor device structure of the present invention.

[0053] Fig.10 It is a schematic diagram showing the structure of providing an interlayer dielectric layer in an example of step 4 of the method for preparing a semiconductor device structure of the present invention.

[0054] Fig.11 It is a schematic diagram of the structure presented by setting a patterned groove in step 5 of the method for preparing the semiconductor device structure of the present invention.

[0055] Fig.12 It is a schematic diagram showing the structure of setting a conductive layer in an example of step 6 of the method for preparing the semiconductor device structure of the present invention.

[0056] Fig.13It is a schematic diagram showing the structure of the patterned conductive layer in step 6 of an example of the method for preparing the semiconductor device structure of the present invention.

[0057] Fig.14 It is a schematic diagram showing the structure of setting a passivation layer and a protective layer in an example of step 6 of the method for preparing a semiconductor device structure of the present invention.

[0058] Fig.15 It is a schematic diagram showing the structure of the first conductivity type back layer and the second conductivity type heavily doped layer obtained in step 7 of the method for preparing the semiconductor device structure of the present invention.

[0059] Fig.16 It is a schematic diagram showing the structure of setting the collector in step 8 of the method for preparing the semiconductor device structure of the present invention.

[0060] Description of Figure Numbers

[0061] 10. First conductivity type substrate; 11. First conductivity type substrate layer; 12. Second conductivity type body region; 13. First conductivity type heavily doped region; 14. First conductivity type back layer; 141. First conductivity type buffer layer; 142. First conductivity type freewheeling heavily doped region; 15. Second conductivity type heavily doped layer; 16. Interlayer dielectric layer; 17. Passivation layer; 18. Protective layer; 19. Patterned groove;

[0062] 20. Conductive layer; 21. Collector; 22. Emitter; 23. Gate;

[0063] 30. trench gate; 31. gate oxide layer; 32. gate polysilicon; 33. first trench;

[0064] 40. deep trench field plate; 41. field plate oxide layer; 42. field plate polysilicon; 43. second trench;

[0065] 50. Hard mask layer; 51. Silicon dioxide layer; 52. Silicon nitride layer. DETAILED DESCRIPTION

[0066] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0067] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0068] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0069] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0070] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0071] like Figure 1 As shown in the figure, in the RC-IGBT (Reverse Conducting-IGBT) that integrates IGBT (Insulated Gate Bipolar Transisitor) and FRD (Fast Recovery Diode) in the prior art, the inverse correlation between the on-state voltage drop and the turn-off loss of the IGBT part requires a trade-off (balance) between the on-state voltage drop and the turn-off loss in the design of the IGBT part, thereby limiting the efficiency performance of the IGBT in the electronic power system; and because the FRD is integrated in the IGBT, the resistivity of the shared substrate will also affect the BV (Breakdown) of the FRD. Voltage (breakdown voltage) and VF (Forward Voltage, conduction voltage drop), which limits the dual optimization of BV and VF of FRD in RC-IGBT, resulting in large working loss when it is in the freewheeling state; at the same time, FRD in RC-IGBT will form a peak current during reverse recovery, resulting in greater switching loss of RC-IGBT, poor reliability, and easy to generate large electromagnetic interference.

[0072] The present invention provides a semiconductor device structure, such as Figure 2 As shown, the semiconductor device structure includes: a collector 21, a second conductive type heavily doped layer 15, a first conductive type back layer 14, a first conductive type substrate layer 11, a trench gate 30, a deep trench field plate 40, a second conductive type body region 12, a first conductive type heavily doped region 13, a gate 23, and an emitter 22;

[0073] The first conductive type back layer 14 includes a first conductive type buffer layer 141 and a first conductive type freewheeling heavily doped region 142 which are alternately distributed along the distribution direction of the trench gate 30 and the deep trench field plate 40, and the first conductive type freewheeling heavily doped region 142 is distributed at a corresponding position below the deep trench field plate 40;

[0074] The first conductive type substrate layer 11 includes a first surface and a second surface that are oppositely arranged, the first conductive type back surface layer 14, the second conductive type heavily doped layer 15 and the collector electrode 21 are sequentially located on the second surface of the first conductive type substrate layer 11 from top to bottom, and the second conductive type body region 12 and the first conductive type heavily doped region 13 are sequentially located on the first surface of the first conductive type substrate layer 11 from bottom to top;

[0075] The trench gate 30 and the deep trench field plate 40 are both filling layers that penetrate the second conductive type body region 12 and extend into the trench of the first conductive type substrate layer 11. The depth of the trench gate 30 is less than the depth of the deep trench field plate 40. The trench gate 30 also penetrates the first conductive type heavily doped region 13.

[0076] The emitter 22 is effectively electrically connected to the deep trench field plate 40 , the second conductive type body region 12 , and the second conductive type heavily doped layer 15 , and the gate 23 is effectively electrically connected to the trench gate 30 .

[0077] The present invention arranges deep trench field plates 40 short-circuited with the emitter 22 on both sides of the trench gate 30 of the RC-IGBT, so that a large number of holes are accumulated in the deep trench field plates 40 when the semiconductor device structure is turned on, so that the conductivity modulation effect when the IGBT is partially turned on is stronger, and a higher carrier concentration can be formed near the emitter region, so that the resistivity of the first conductive type substrate layer 11 (drift region) is reduced, thereby reducing the turn-on voltage drop V CEAt the same time, the vertical electric field distribution added by the deep trench field plate 40 can make the electric field distribution in the RC-IGBT more uniform, so that the BV (breakdown voltage) of the FRD part can be increased under the condition of the same VF (on-state voltage drop) of the FRD (that is, the doping concentration of the first conductive type substrate layer 11 remains unchanged), so that the VF of the RC-IGBT can be reduced by using the first conductive type substrate layer 11 with a higher doping concentration while keeping the BV unchanged, thereby reducing the working state loss of the RC-IGBT when the RC-IGBT is in freewheeling in the circuit, thereby optimizing the compromise relationship between the FRD breakdown voltage and the on-state voltage in the RC-IGBT; in addition, the deep trench field plate 40 is used to enable the carriers stored in the depletion layer to be quickly extracted in the freewheeling state, thereby reducing the current released during reverse recovery and reducing the peak current of reverse recovery.

[0078] Specifically, the doping concentration of the first conductive type freewheeling heavily doped region 142 is greater than that of the first conductive type buffer layer 141 , so as to achieve a heavy doping effect of the first conductive type freewheeling heavily doped region 142 to satisfy its freewheeling function in the FRD.

[0079] In one embodiment, the depth of the deep trench field plate 40 is greater than or equal to 20 microns.

[0080] The present invention can further increase the number of holes accumulated in the deep trench field plate 40 when the IGBT portion in the RC-IGBT is turned on by setting the depth of the deep trench field plate 40 to be greater than or equal to 20 microns, thereby further reducing the resistivity of the drift region, thereby further reducing the on-state voltage drop of the IGBT portion and the working loss in the FRD freewheeling state; in addition, the deep trench field plate 40 with a depth greater than or equal to 20 microns can also further increase the speed at which carriers in the depletion layer are extracted in the freewheeling state, thereby further reducing the reverse recovery peak current; at the same time, as the depth of the deep trench field plate 40 is greater than or equal to 20 microns, the width of the deep trench field plate 40 will also be correspondingly expanded due to the process, thereby reducing the number of conductive channels formed per unit area of ​​the RC-IGBT and reducing the density of the conductive channels, thereby improving the working efficiency and thermal management efficiency of the RC-IGBT.

[0081] In one embodiment, the depth of the deep trench field plate 40 is 2-3 times the depth of the trench gate 30 .

[0082] The present invention sets the depth relationship between the deep trench field plate 40 and the trench gate 30 to ensure that the deep trench field plate 40 plays a role in the RC-IGBT while meeting the feasibility of the trench manufacturing process, which is conducive to promotion and application in actual production.

[0083] In one embodiment, the trench gate 30 includes a gate oxide layer 31 and a gate polysilicon 32, the gate oxide layer 31 covers the inner wall of the trench where the trench gate 30 is located, and the gate polysilicon 32 fills the surface of the gate oxide layer 31 in the trench where the trench gate 30 is located; the deep trench field plate 40 includes a field plate oxide layer 41 and a field plate polysilicon 42, the field plate oxide layer 41 covers the inner wall of the trench where the deep trench field plate 40 is located, and the field plate polysilicon 42 fills the surface of the field plate oxide layer 41 in the trench where the deep trench field plate 40 is located.

[0084] Specifically, the gate polysilicon 32 and the field plate polysilicon 42 may also be replaced by other gate materials, but polysilicon material is preferably used to ensure close contact with the underlying oxide layer to ensure device reliability.

[0085] Specifically, the depth of the deep trench field plate 40 mentioned in the present application mainly refers to the depth of the field plate polysilicon 42, and the depth of the trench gate 30 mentioned mainly refers to the depth of the gate polysilicon 32. Especially in the deep trench structure, since the gate oxide layer 31 and the field plate oxide layer 41 are usually a very thin film, they can be ignored compared with the thickness of the gate polysilicon 32 and the field plate polysilicon 42.

[0086] In one embodiment, the gate oxide layer 31 and the field plate oxide layer 41 both have a thickness of 1000 angstroms to 1500 angstroms.

[0087] In one embodiment, Figure 2 As shown, the semiconductor device structure further includes a passivation layer 17 and a protection layer 18 . The passivation layer 17 is located on all surfaces of the gate 23 and the emitter 22 that are not conductively led out, and the protection layer 18 is located on the surface of the passivation layer 17 .

[0088] The present invention protects the electrodes exposed on the surface of the semiconductor device structure by providing a passivation layer 17 and a protection layer 18, thereby reducing the risks of oxidation, damage or short circuit, and improving the product yield and reliability of the semiconductor device structure.

[0089] In one embodiment, Figure 2 As shown, the semiconductor device structure also includes an interlayer dielectric layer 16; the interlayer dielectric layer 16 is located on the exposed surface of the first conductive type heavily doped region 13 between adjacent gates 23 and / or emitters 22 to insulate and isolate adjacent gates 23 and / or emitters 22.

[0090] The present invention can further improve the insulation isolation between adjacent gate electrodes 23 and / or emitter electrodes 22 by providing an interlayer dielectric layer 16, thereby avoiding the problem of short circuit between electrodes and improving product yield.

[0091] Specifically, “between adjacent gates 23 and / or emitters 22 ” refers to the general term for three situations: “between adjacent gates 23 ”, “between adjacent emitters 22 ” or “between adjacent gates 23 and emitters 22 ”.

[0092] In one embodiment, the first conductivity type is N type, and the second conductivity type is P type.

[0093] The present invention adopts the N-type as the first conductive type, so as to achieve a lower resistivity and further reduce the conduction loss, while improving the switching speed of the RC-IGBT.

[0094] In one embodiment, the first conductivity type is P type, and the second conductivity type is N type.

[0095] The present invention also provides a method for preparing a semiconductor device structure, the method for preparing any one of the above-mentioned semiconductor device structures, the method comprising:

[0096] Step 1: providing a first conductive type substrate 10, wherein the first conductive type substrate 10 comprises a first surface and a second surface opposite to each other;

[0097] Step 2: Disposing a first trench 33 and a second trench 43 on the first surface of the first conductive type substrate 10 , wherein the depth of the second trench 43 is greater than the depth of the first trench 33 ;

[0098] Step 3: Disposing a trench gate 30 in the first trench 33 and a deep trench field plate 40 in the second trench 43;

[0099] Step 4: performing doping at a position on the first surface of the first conductive type substrate 10 where the trench gate 30 and the deep trench field plate 40 are not provided, to obtain a second conductive type body region 12 and a first conductive type heavily doped region 13, wherein the second conductive type body region 12 and the first conductive type heavily doped region 13 are sequentially located from bottom to top in a position close to the first surface of the first conductive type substrate 10;

[0100] Step 5: providing a patterned trench 19 in the first conductive type heavily doped region 13 and the second conductive type body region 12, wherein the patterned trench 19 penetrates the first conductive type heavily doped region 13 and extends into the second conductive type body region 12 to expose the surfaces of the trench gate 30, the deep trench field plate 40 and the second conductive type body region 12;

[0101] Step 6: a patterned conductive layer 20 is provided to cover the surface exposed by the patterned trench 19 , the conductive layer 20 electrically connected to the trench gate 30 is the gate 23 , and the conductive layer 20 electrically connected to the deep trench field plate 40 is the emitter 22 ;

[0102] Step 7: doping the second surface of the first conductive type substrate 10 to obtain a first conductive type back layer 14 and a second conductive type heavily doped layer 15, wherein the first conductive type back layer 14 includes a first conductive type buffer layer 141 and a first conductive type freewheeling heavily doped region 142 which are alternately distributed along the distribution direction of the trench gate 30 and the deep trench field plate 40, and the first conductive type freewheeling heavily doped region 142 is distributed at a corresponding position below the deep trench field plate 40; the first conductive type back layer 14 and the second conductive type heavily doped layer 15 are sequentially located from top to bottom in a position close to the second surface of the first conductive type substrate 10, and the first conductive type substrate 10 between the first conductive type back layer 14 and the second conductive type body region 12 is a first conductive type substrate layer 11;

[0103] Step 8: Disposing a collector electrode 21 on the surface of the second conductive type heavily doped layer 15 .

[0104] The method for preparing the semiconductor device structure of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the method for preparing the semiconductor device structure protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0105] First, step 1 is performed to provide a first conductive type substrate 10 , wherein the first conductive type substrate 10 includes a first surface and a second surface that are opposite to each other.

[0106] Then, step 2 is performed to form a first trench 33 and a second trench 43 on the first surface of the first conductive type substrate 10 , wherein the depth of the second trench 43 is greater than the depth of the first trench 33 .

[0107] In one embodiment, a method for providing the first trench 33 and the second trench 43 on the first surface of the first conductive type substrate 10 includes:

[0108] like Figure 3 As shown, a hard mask layer 50 is disposed on the first surface of the first conductive type substrate 10, and the hard mask layer 50 includes a silicon dioxide layer 51, a silicon nitride layer 52 and a silicon dioxide layer 51 in sequence from bottom to top;

[0109] like Figure 4As shown, the hard mask layer 50 is patterned to expose the first surface of the first conductive type substrate 10 for setting a preset position of the first trench 33;

[0110] like Figure 5 As shown, the first surface of the first conductive type substrate 10 is etched using the patterned hard mask layer 50 as a mask to obtain a first trench 33;

[0111] like Figure 6 As shown, the hard mask layer 50 is patterned again to simultaneously expose the first surface of the first conductive type substrate 10 for setting the preset positions of the first trench 33 and the second trench 43;

[0112] like Figure 7 As shown, the first surface of the first conductive type substrate 10 is etched using the patterned hard mask layer 50 as a mask to obtain a second trench 43; and the first trench 33 is further etched to obtain a second trench 43 having a depth greater than a deep portion of the first trench 33;

[0113] The remaining hard mask layer 50 is removed.

[0114] In one embodiment, the method for setting the hard mask layer 50 includes: first, epitaxially growing a thin silicon dioxide layer 51 of a certain thickness on the first surface of the first conductive type substrate 10, then depositing a silicon nitride layer 52 of a certain thickness on the silicon dioxide layer 51, and finally depositing another silicon dioxide layer 51 on the silicon nitride layer 52 to form a hard mask layer 50 composed of silicon dioxide-silicon nitride-silicon dioxide.

[0115] In one embodiment, the hard mask layer 50 may also use other suitable hard mask layers 50 , but preferably uses the hard mask layer 50 composed of silicon dioxide-silicon nitride-silicon dioxide in this solution.

[0116] In one embodiment, the method for patterning the hard mask layer 50 includes: setting a photoresist on the hard mask layer 50; exposing and developing the photoresist to obtain a patterned photoresist to reveal the area of ​​the hard mask layer 50 to be patterned; etching the patterned photoresist to reveal the hard mask layer 50; removing the remaining photoresist and cleaning.

[0117] In one embodiment, wet etching is used to remove the remaining hard mask layer 50 .

[0118] Next, proceed to step 3, such as Figure 8 As shown, a trench gate 30 is disposed in the first trench 33 , and a deep trench field plate 40 is disposed in the second trench 43 .

[0119] In one embodiment, the method of providing the trench gate 30 and the deep trench field plate 40 includes:

[0120] Thermally oxidizing the inner surfaces of the first trench 33 and the second trench 43 by furnace tube growth to obtain a gate oxide layer 31 on the inner surface of the first trench 33 and a field plate oxide layer 41 on the inner surface of the second trench 43;

[0121] Fill the first trench 33 and the second trench 43 with polysilicon grown by a furnace tube, so that the surface of the gate oxide layer 31 in the first trench 33 is filled with gate polysilicon 32, and the surface of the field plate oxide layer 41 in the second trench 43 is filled with field plate polysilicon 42;

[0122] The first surface of the first conductive type substrate 10 is planarized to expose the trench gate 30 in the first trench 33 and the deep trench field plate 40 in the second trench 43 .

[0123] In one embodiment, the method for planarizing the first surface of the first conductive type substrate 10 is: etching away excess polysilicon and oxide layer on the first surface of the first conductive type substrate layer 11 .

[0124] Then, proceed to step 4, such as Fig. 9 As shown, doping is performed at a position on the first surface of the first conductive type substrate 10 where the trench gate 30 and the deep trench field plate 40 are not set to obtain a second conductive type body region 12 and a first conductive type heavily doped region 13, and the second conductive type body region 12 and the first conductive type heavily doped region 13 are sequentially located from bottom to top in a position close to the first surface of the first conductive type substrate 10.

[0125] In one embodiment, a method for obtaining a second conductive type body region 12 and a first conductive type heavily doped region 13 includes: using photoresist exposure and development to define a position on the first surface of the first conductive type substrate 10 to set the second conductive type body region 12, injecting P-type impurities to form the second conductive type body region 12, and removing the remaining photoresist; using photoresist exposure and development to define a position on the first surface of the first conductive type substrate 10 to set the first conductive type heavily doped region 13, injecting N-type impurities to form the first conductive type heavily doped region 13, and removing the remaining photoresist; and placing the obtained product into a furnace tube for high-temperature well pushing to obtain the second conductive type body region 12 and the first conductive type heavily doped region 13 located in the first conductive type substrate 10 close to the first surface from bottom to top.

[0126] In one embodiment, Fig.10As shown, after setting the second conductive type body region 12 and the first conductive type heavily doped region 13, an interlayer dielectric layer 16 is set on their surfaces, and the interlayer dielectric layer 16 covers the exposed surfaces of the first conductive type heavily doped region 13, the trench gate 30 and the deep trench field plate 40.

[0127] In one embodiment, the method for providing the interlayer dielectric layer 16 includes: first forming a layer of silicon dioxide, and then depositing a certain thickness of borophosphate silicon glass to form the interlayer dielectric layer 16 .

[0128] Next, proceed to step 5, such as Fig.11 As shown, a patterned groove 19 is set in the first conductive type heavily doped region 13 and the second conductive type body region 12, and the patterned groove 19 passes through the first conductive type heavily doped region 13 and extends into the second conductive type body region 12 to expose the surfaces of the trench gate 30, the deep trench field plate 40 and the second conductive type body region 12.

[0129] In one embodiment, Fig.11 As shown, when the interlayer dielectric layer 16 is provided, when the patterned trench 19 is provided, the patterned trench 19 also penetrates the interlayer dielectric layer 16 .

[0130] Then, step 6 is performed to set a patterned conductive layer 20 to cover the surface exposed by the patterned trench 19 , the conductive layer 20 electrically connected to the trench gate 30 is the gate 23 , and the conductive layer 20 electrically connected to the deep trench field plate 40 is the emitter 22 .

[0131] In one embodiment, the method of providing the patterned conductive layer 20 includes: Fig.12 As shown, the surface of the patterned groove 19 and the exposed interlayer dielectric layer 16 is covered with a filling conductive layer 20; Fig.13 As shown, the covered and filled conductive layer 20 is patterned to obtain a gate electrode 23 electrically connected to the trench gate 30 and an emitter electrode 22 electrically connected to the deep trench field plate 40 .

[0132] In one embodiment, Fig.14 As shown, a passivation layer 17 and a protection layer 18 are sequentially disposed on the surface of the patterned conductive layer 20 where no conductive lead is performed.

[0133] In one embodiment, the method of providing the passivation layer 17 includes: depositing a layer of silicon nitride, exposing, developing and etching with a photoresist to obtain patterned silicon nitride as the passivation layer 17; and removing the remaining photoresist for cleaning.

[0134] In one embodiment, the method of setting the protective layer 18 includes: spin coating a layer of PI (Polyimide), exposing, developing and etching the photoresist to obtain a patterned PI, curing the PI to obtain the protective layer 18; and removing the remaining photoresist for cleaning.

[0135] Next, proceed to step 7, such as Fig.15 As shown, the second surface of the first conductive type substrate 10 is doped to obtain a first conductive type back layer 14 and a second conductive type heavily doped layer 15, the first conductive type back layer 14 includes a first conductive type buffer layer 141 and a first conductive type freewheeling heavily doped region 142 which are alternately distributed along the distribution direction of the trench gate 30 and the deep trench field plate 40, and the first conductive type freewheeling heavily doped region 142 is distributed at a corresponding position below the deep trench field plate 40; the first conductive type back layer 14 and the second conductive type heavily doped layer 15 are sequentially located from top to bottom in the first conductive type substrate 10 near the second surface, and the first conductive type substrate 10 between the first conductive type back layer 14 and the second conductive type body region 12 is a first conductive type substrate layer 11.

[0136] In one embodiment, before doping the second surface of the first conductive type substrate 10, the second surface of the first conductive type substrate 10 is thinned. Specifically, the thickness of the first conductive type substrate 10 after thinning is set according to the voltage requirement of the device.

[0137] In one embodiment, the thickness of the first conductive type substrate 10 after thinning is 60 micrometers to 100 micrometers.

[0138] In one embodiment, N-type impurities are injected into the second surface of the first conductive type substrate 10 by an ion implantation machine to obtain a first conductive type back layer 14 composed of the first conductive type buffer layer 141 and the first conductive type freewheeling heavily doped region 142 alternately distributed; P-type impurities are injected into the second surface of the first conductive type substrate 10 to obtain a second conductive type heavily doped layer 15.

[0139] Finally, proceed to step 8, such as Fig.16 As shown, a collector electrode 21 is disposed on the surface of the second conductive type heavily doped layer 15 .

[0140] In one embodiment, the method for providing the collector electrode 21 includes: depositing a layer of metal on the surface of the second conductive type heavily doped layer 15 , and then providing a metal alloy on the metal as a protective layer 18 of the collector electrode 21 .

[0141] In summary, the semiconductor device structure and preparation method thereof of the present invention can be achieved by arranging deep trench field plates short-circuited with the emitter on both sides of the trench gate, so that a large number of holes are accumulated in the deep trench field plates when the semiconductor device structure is turned on, thereby reducing the on-state voltage drop; at the same time, the vertical electric field distribution added by the deep trench field plates is used to optimize the compromise relationship between the FRD breakdown voltage and the on-state voltage in the RC-IGBT, thereby reducing the working loss of the RC-IGBT in the freewheeling state; in addition, the deep trench field plates are used to enable the carriers in the depletion layer to be quickly extracted in the freewheeling state, thereby reducing the current released during reverse recovery and reducing the peak current of reverse recovery.

[0142] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0143] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A semiconductor device structure, characterized in that: The semiconductor device structure comprises: a collector, a second conductive type heavily doped layer, a first conductive type back layer, a first conductive type substrate layer, a trench gate, a deep trench field plate, a second conductive type body region, a first conductive type heavily doped region, a gate, and an emitter; The first conductive type back layer comprises a first conductive type buffer layer and a first conductive type freewheeling heavily doped region which are alternately distributed along the distribution direction of the trench gate and the deep trench field plate, and the first conductive type freewheeling heavily doped region is distributed at a corresponding position below the deep trench field plate; The first conductive type substrate layer comprises a first surface and a second surface which are arranged opposite to each other, the first conductive type back surface layer, the second conductive type heavily doped layer and the collector are sequentially located on the second surface of the first conductive type substrate layer from top to bottom, and the second conductive type body region and the first conductive type heavily doped region are sequentially located on the first surface of the first conductive type substrate layer from bottom to top; The trench gate and the deep trench field plate are both filling layers in the trench that penetrates the second conductive type body region and extends into the first conductive type substrate layer, the depth of the trench gate is less than the depth of the deep trench field plate, and the trench gate also penetrates the first conductive type heavily doped region; The emitter is effectively electrically connected to the deep trench field plate, the second conductive type body region, and the second conductive type heavily doped layer, and the gate is effectively electrically connected to the trench gate.

2. The semiconductor device structure according to claim 1, characterized in that: The depth of the deep trench field plate is greater than or equal to 20 microns.

3. The semiconductor device structure according to claim 1, characterized in that: The depth of the deep trench field plate is 2-3 times the depth of the trench gate.

4. The semiconductor device structure according to claim 1, characterized in that: The trench gate includes a gate oxide layer and gate polysilicon, the gate oxide layer covers the inner wall of the trench where the trench gate is located, and the gate polysilicon fills the surface of the gate oxide layer in the trench where the trench gate is located; the deep trench field plate includes a field plate oxide layer and field plate polysilicon, the field plate oxide layer covers the inner wall of the trench where the deep trench field plate is located, and the field plate polysilicon fills the surface of the field plate oxide layer in the trench where the deep trench field plate is located.

5. The semiconductor device structure according to claim 1, characterized in that: The semiconductor device structure further includes a passivation layer and a protection layer. The passivation layer is located on all surfaces of the gate electrode and the emitter electrode that are not electrically conductively led out, and the protection layer is located on the surface of the passivation layer.

6. The semiconductor device structure according to claim 1, characterized in that: The semiconductor device structure also includes an interlayer dielectric layer; the interlayer dielectric layer is located on the exposed surface of the first conductive type heavily doped region between adjacent gates and / or emitters to insulate and isolate adjacent gates and / or emitters.

7. The semiconductor device structure according to claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

8. A method for preparing a semiconductor device structure, characterized in that: The preparation method is used to prepare the semiconductor device structure according to any one of claims 1 to 7, and the preparation method comprises: Providing a first conductive type substrate, the first conductive type substrate comprising a first surface and a second surface opposite to each other; Disposing a first trench and a second trench on the first surface of the first conductive type substrate, wherein the depth of the second trench is greater than the depth of the first trench; Disposing a trench gate in the first trench and a deep trench field plate in the second trench; Doping is performed at a position on the first surface of the first conductive type substrate where the trench gate and the deep trench field plate are not provided, to obtain a second conductive type body region and a first conductive type heavily doped region, wherein the second conductive type body region and the first conductive type heavily doped region are sequentially located from bottom to top in a position close to the first surface of the first conductive type substrate; A patterned trench is provided in the first conductive type heavily doped region and the second conductive type body region, wherein the patterned trench penetrates the first conductive type heavily doped region and extends into the second conductive type body region to expose the surfaces of the trench gate, the deep trench field plate and the second conductive type body region; A patterned conductive layer is provided to cover the surface exposed by the patterned trench, the conductive layer electrically connected to the trench gate is a gate, and the conductive layer electrically connected to the deep trench field plate is an emitter; The second surface of the first conductive type substrate is doped to obtain a first conductive type back layer and a second conductive type heavily doped layer, wherein the first conductive type back layer comprises a first conductive type buffer layer and a first conductive type freewheeling heavily doped region that are alternately distributed along the distribution direction of the trench gate and the deep trench field plate, and the first conductive type freewheeling heavily doped region is distributed at a corresponding position below the deep trench field plate; the first conductive type back layer and the second conductive type heavily doped layer are sequentially located from top to bottom in a position close to the second surface of the first conductive type substrate, and the first conductive type substrate between the first conductive type back layer and the second conductive type body region is a first conductive type substrate layer; A collector electrode is disposed on the surface of the second conductive type heavily doped layer.

9. The method for preparing a semiconductor device structure according to claim 8, characterized in that: The method of providing the first trench and the second trench on the first surface of the first conductive type substrate includes: Disposing a hard mask layer on the first surface of the first conductive type substrate, wherein the hard mask layer comprises a silicon dioxide layer, a silicon nitride layer and a silicon dioxide layer in sequence from bottom to top; Patterning the hard mask layer to expose the first surface of the first conductive type substrate for setting a preset position of the first trench; Using the patterned hard mask layer as a mask, etching the first surface of the first conductive type substrate to obtain a first trench; Patterning the hard mask layer again to simultaneously expose the first surface of the first conductive type substrate for setting the preset positions of the first trench and the second trench; Using the patterned hard mask layer as a mask, etching the first surface of the first conductive type substrate to obtain a second trench; and further etching the first trench to obtain a second trench having a depth greater than a deep portion of the first trench; The remaining hard mask layer is removed.

10. The method for preparing a semiconductor device structure according to claim 8, characterized in that: The method of providing the trench gate and the deep trench field plate comprises: Thermally oxidizing the inner surfaces of the first trench and the second trench by furnace tube growth to obtain a gate oxide layer on the inner surface of the first trench and a field plate oxide layer on the inner surface of the second trench; Filling the first trench and the second trench with polysilicon grown by a furnace tube, so that the surface of the gate oxide layer in the first trench is filled with gate polysilicon, and the surface of the field plate oxide layer in the second trench is filled with field plate polysilicon; The first surface of the first conductive type substrate is planarized to expose the trench gate in the first trench and the deep trench field plate in the second trench.

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