Metal oxide semiconductor field effect transistor and preparation method thereof

Abstract

The invention discloses a metal oxide semiconductor field effect transistor and a preparation method thereof. Each cell in the metal oxide semiconductor field effect transistor comprises a drain metal layer, a substrate, an epitaxial layer, a current expansion layer, a base region layer, an injection layer, a source metal region and a gate region, the drain metal layer, the substrate, the epitaxial layer, the current expansion layer, the base region layer and the injection layer are stacked in sequence; the upper part of the source electrode metal region covers the injection layer and the upper surface of the gate region, and the lower part of the source electrode metal region penetrates through the injection layer, the base region layer and the current expansion layer and extends to a buried layer region in the epitaxial layer; the side wall of the source metal region comprises a Schottky contact region and a gate region with the side wall as a longitudinal center line. According to the embodiment of the invention, the dynamic characteristics of the metal oxide semiconductor field effect transistor are improved while the conduction voltage drop and the reliability of the silicon carbide metal oxide semiconductor field effect transistor are ensured.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a metal oxide semiconductor field effect transistor and a preparation method thereof. Background Art

[0002] As a new generation of power semiconductor devices, silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) has many advantages, such as high voltage resistance, low on-resistance, high-speed switching and other characteristics, and has broad application prospects in the field of power electronics.

[0003] At present, the optimization design of SiC MOSFET mainly focuses on the following two directions:

[0004] Direction 1: Perform process or structural optimization design to improve the reliability of SiC MOSFET and reduce the forward conduction voltage drop of SiC MOSFET; Direction 2: Additional diodes are integrated in SiC MOSFET to reduce the conduction voltage drop of SiC MOSFET during reverse freewheeling.

[0005] However, while related technologies optimize SiC MOSFET to improve the reliability of SiC MOSFET and reduce the on-state voltage drop, SiC MOSFET still has problems such as high Miller capacitance and large switching loss, resulting in poor dynamic characteristics of the current SiC MOSFET. Summary of the invention

[0006] The purpose of the embodiments of the present application is to provide a metal oxide semiconductor field effect transistor and a method for preparing the same, which can solve the problem that the related technology cannot simultaneously optimize the on-state voltage drop, reliability and dynamic characteristics of a silicon carbide metal oxide semiconductor field effect transistor.

[0007] In a first aspect, an embodiment of the present application provides a metal oxide semiconductor field effect transistor, the metal oxide semiconductor field effect transistor comprising at least two cells, each of the cells comprising a drain metal layer, a substrate, an epitaxial layer, a current spreading layer, a base layer, an injection layer, a source metal region and a gate region;

[0008] Wherein, the drain metal layer, the substrate, the epitaxial layer, the current spreading layer, the base layer and the injection layer are stacked in sequence;

[0009] The upper part of the source metal region covers the upper surfaces of the injection layer and the gate region, and the lower part of the source metal region passes through the injection layer, the base layer and the current spreading layer along the longitudinal center line of the cell and extends to the buried layer region in the epitaxial layer; the longitudinal center line of the cell is the center line along the thickness direction of the cell;

[0010] The side wall of the source metal region includes a Schottky contact region and a gate region with the side wall as a longitudinal center line; the upper end of the Schottky contact region is connected to the bottom of the gate region, and the lower end of the Schottky contact region is connected to the top of the buried layer region.

[0011] Optionally, in the cell, the minimum distance between the side edge of the cell and the gate region is a first distance, the minimum distance between the side edge of the cell and the buried layer region is a second distance, and the minimum distance between the side edge of the cell and the Schottky contact region is a third distance;

[0012] The third distance is greater than the second distance, and the second distance is greater than the first distance.

[0013] Optionally, the width of the buried layer region is greater than or equal to the distance between Schottky contact regions in two side walls of the source metal region.

[0014] Optionally, the minimum distance between the lower end of the Schottky contact region and the bottom of the source metal region is a fourth distance, and the minimum distance between the bottom of the gate region and the bottom of the source metal region is a fifth distance; wherein the fifth distance is greater than the fourth distance.

[0015] Optionally, a first length of the Schottky contact region along a direction of the thickness of the cell is smaller than a first width of the gate region along a direction of the width of the cell, and the first length is greater than half of the first width.

[0016] Optionally, the distance between the upper surface of the injection layer and the lower surface of the current spreading layer is a sixth distance, and the distance between the upper surface of the injection layer and the bottom of the source metal region is a seventh distance; wherein the sixth distance is less than or equal to the seventh distance.

[0017] Optionally, the doping concentration of the buried layer region is greater than the doping concentration of the base layer.

[0018] Optionally, the doping concentration of the substrate is greater than the doping concentration of the current spreading layer, and the doping concentration of the current spreading layer is greater than the doping concentration of the epitaxial layer.

[0019] Optionally, the buried layer region wraps the entire bottom of the source metal region.

[0020] Optionally, the depth of the buried layer region is greater than 0 and less than the thickness of the epitaxial layer.

[0021] Optionally, the buried layer region includes a first buried layer region and a second buried layer region that are independent of each other, and the first buried layer region and the second buried layer region respectively wrap around different corner regions at the bottom of the source metal region.

[0022] Optionally, the gate region includes a gate filling portion and a dielectric layer wrapping the gate filling portion, and the dielectric layer is used to isolate the gate filling portion from the epitaxial layer, the current spreading layer, the base layer, the injection layer and the source metal region.

[0023] In a second aspect, an embodiment of the present application provides a method for preparing a metal oxide semiconductor field effect transistor, the method comprising:

[0024] A first intermediate member is prepared based on an original substrate; the first intermediate member comprises an original substrate and an epitaxial layer, a current spreading layer and an original base layer sequentially stacked on an upper surface of the original substrate; the epitaxial layer comprises a buried layer region; the first intermediate member comprises a source trench that penetrates the original base layer and the current spreading layer along a longitudinal center line of the first intermediate member and extends to the buried layer region in the epitaxial layer, and the longitudinal center line of the first intermediate member is a center line along a thickness direction of the first intermediate member;

[0025] A Schottky contact region connected to the top of the buried layer region is formed on the sidewall of the source trench, and a source metal is filled in the source trench having the Schottky contact region on the sidewall;

[0026] Using the side wall as a longitudinal center line, etching is performed on the side wall of the source trench filled with source metal to obtain a gate trench;

[0027] Preparing a first oxide layer on the inner wall of the gate trench, and filling polysilicon in the gate trench having the first oxide layer on the inner wall;

[0028] Performing a first ion implantation operation on the upper surface of the original base layer to obtain an implantation layer stacked on the upper surface of the base layer;

[0029] A second oxide layer is prepared on the upper surface of the gate trench filled with polysilicon to obtain a second intermediate member; the first oxide layer, the second oxide layer and the polysilicon in the gate trench constitute a gate region;

[0030] Preparing a source metal layer on the upper surface of the second intermediate member, wherein the source metal layer and the source metal in the source trench constitute a source metal region;

[0031] The lower surface of the original substrate is thinned to obtain a substrate, and a drain metal layer is prepared on the lower surface of the substrate to obtain a metal oxide semiconductor field effect transistor as described in any one of the above items; the metal oxide semiconductor field effect transistor includes at least two cells, and the cells include the drain metal layer, the substrate, the epitaxial layer, the current spreading layer, the base layer, the injection layer, the source metal region and the gate region.

[0032] Optionally, preparing the first intermediate piece based on the original substrate includes:

[0033] An epitaxial layer, a current spreading layer and an original base layer are sequentially formed on the upper surface of the original substrate to obtain a third intermediate member;

[0034] Etching the third intermediate member along the longitudinal center line of the third intermediate member to obtain a source trench penetrating the original base layer and the current spreading layer and extending into the epitaxial layer;

[0035] A second ion implantation operation is performed at the bottom of the source trench to form a buried layer region in the epitaxial layer in contact with the bottom of the source trench, thereby obtaining a first intermediate member.

[0036] Optionally, preparing the first intermediate piece based on the original substrate includes:

[0037] forming a first epitaxial layer on the upper surface of the original substrate;

[0038] Performing a third ion implantation operation in a target area on the upper surface of the first epitaxial layer to obtain a buried layer region;

[0039] forming a second epitaxial layer on the upper surface of the first epitaxial layer; the first epitaxial layer and the second epitaxial layer constitute an epitaxial layer stacked on the upper surface of the original substrate;

[0040] forming a current spreading layer and an original base layer in sequence on the upper surface of the second epitaxial layer to obtain a fourth intermediate member;

[0041] The fourth intermediate member is etched along the longitudinal center line of the fourth intermediate member to form a source trench penetrating the original base layer and the current spreading layer and extending to the buried layer region in the epitaxial layer, thereby obtaining a first intermediate member.

[0042] The metal oxide semiconductor field effect transistor provided in the embodiment of the present application comprises in each cell a drain metal layer, a substrate, an epitaxial layer, a current expansion layer, a base layer and an injection layer stacked in sequence, as well as a source metal region and a gate region; wherein the upper portion of the source metal region covers the upper surfaces of the injection layer and the gate region to form a source metal layer connected to the upper surface of the injection layer, the lower portion of the source metal region penetrates the injection layer, the base layer and the current expansion layer along the longitudinal center line of the cell and extends to the buried layer region in the epitaxial layer, the Schottky contact region and the epitaxial layer constitute a Schottky diode, the buried layer region and the epitaxial layer constitute a body diode, and the base layer and the current expansion layer constitute a body diode; when the metal oxide semiconductor field effect transistor is in a forward blocking state, the buried layer region connected to the source metal region can make the electric field of the drain metal layer The line is cut off, the electric field strength at the bottom of the gate area is reduced, and the reliability of the metal oxide semiconductor field effect tube is improved; when the metal oxide semiconductor field effect tube is in a reverse conduction state, since the conduction voltage drop of the Schottky diode is less than the conduction voltage drop of the body diode, the Schottky diode is turned on before the body diode, and the Schottky diode is in a unipolar mode when it is turned on, avoiding the bipolar degradation caused by the conduction of the body diode and reducing the conduction voltage drop of the metal oxide semiconductor field effect tube; further, the structure of the Schottky diode in the embodiment of the present application reduces the overlapping area of ​​the gate area and the drain metal layer, reduces the Miller capacitance of the metal oxide semiconductor field effect tube, thereby reducing the switching loss of the metal oxide semiconductor field effect tube and improving the dynamic characteristics of the metal oxide semiconductor field effect tube.

[0043] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 1 ;

[0045] Figure 2 It is a schematic diagram of the cross-sectional structure of a metal oxide semiconductor field effect transistor in a forward conduction state provided by an embodiment of the present application;

[0046] Figure 3 The cross-sectional structure of a metal oxide semiconductor field effect transistor in a forward blocking state provided in an embodiment of the present application is shown in FIG. Figure 1 ;

[0047] Figure 4 The cross-sectional structure of a metal oxide semiconductor field effect transistor in a forward blocking state provided in an embodiment of the present application is shown in FIG. Figure 2 ;

[0048] Figure 5The cross-sectional structure of a metal oxide semiconductor field effect transistor in a reverse conduction state provided in an embodiment of the present application is shown in FIG. Figure 1 ;

[0049] Figure 6 The cross-sectional structure of a metal oxide semiconductor field effect transistor in a reverse conduction state provided in an embodiment of the present application is shown in FIG. Figure 2 ;

[0050] Figure 7 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 2 ;

[0051] Figure 8 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 3 ;

[0052] Fig. 9 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 4 ;

[0053] Fig.10 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 5 ;

[0054] Fig.11 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 6 ;

[0055] Fig.12 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 7 ;

[0056] Fig.13 It is a flow chart of the steps of a method for preparing a metal oxide semiconductor field effect transistor provided in an embodiment of the present application;

[0057] Fig.14 This is a schematic diagram of a cross-sectional structure of a first middleware provided in an embodiment of the present application. Figure 1 ;

[0058] Fig.15 This is a schematic diagram of a cross-sectional structure of a first middleware provided in an embodiment of the present application. Figure 2 ;

[0059] Fig.16 This is a schematic diagram of a cross-sectional structure of a first middleware provided in an embodiment of the present application. Figure 3 ;

[0060] Fig.17This is a schematic diagram of a cross-sectional structure of a first middleware provided in an embodiment of the present application. Figure 4 ;

[0061] Fig.18 This is a schematic diagram of a cross-sectional structure of a first middleware provided in an embodiment of the present application. Figure 5 ;

[0062] Fig.19 This is a schematic diagram of a cross-sectional structure of a second middleware provided in an embodiment of the present application. Figure 1 ;

[0063] Fig. 20 This is a schematic diagram of a cross-sectional structure of a second middleware provided in an embodiment of the present application. Figure 2 ;

[0064] Fig.21 This is a schematic diagram of a cross-sectional structure of a second middleware provided in an embodiment of the present application. Figure 3 ;

[0065] Fig. 22 This is a schematic cross-sectional structure diagram of a third middleware provided in an embodiment of the present application. Figure 1 ;

[0066] Fig.23 This is a schematic cross-sectional structure diagram of a third middleware provided in an embodiment of the present application. Figure 2 ;

[0067] Fig.24 This is a schematic cross-sectional structure diagram of a fourth middleware provided in an embodiment of the present application. Figure 1 ;

[0068] Fig.25 This is a schematic cross-sectional structure diagram of a fourth middleware provided in an embodiment of the present application. Figure 2 ;

[0069] Fig.26 This is a schematic cross-sectional structure diagram of a fourth middleware provided in an embodiment of the present application. Figure 3 ;

[0070] Fig. 27 This is a schematic cross-sectional structure diagram of a fourth middleware provided in an embodiment of the present application. Figure 4 .

[0071] Description of reference numerals:

[0072] 10-drain metal layer; 20-substrate; 20'-original substrate; 30-epitaxial layer; 31-buried layer; 32-first epitaxial layer; 33-second epitaxial layer; 40-gate region; 41-dielectric layer; 411-first oxide layer; 412-second oxide layer; 42-gate filling portion; 50-current spreading layer; 60-base layer; 60'-original base layer; 70-injection layer; 71-P-type heavily doped ion injection layer; 72-N-type heavily doped ion injection layer; 80-source metal region; 90-Schottky contact region; 01-source trench; 02-gate trench. DETAILED DESCRIPTION

[0073] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0074] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0075] Product Examples

[0076] The silicon carbide diode provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0077] Reference Figure 1 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 1 It should be noted that the schematic diagram of the cross-sectional structure of the metal oxide semiconductor field effect tube is a schematic diagram of the cross-sectional structure along the thickness direction of the metal oxide semiconductor field effect tube; the metal oxide semiconductor field effect tube provided in the embodiment of the present application includes at least two cells, and after a voltage is applied to the metal oxide semiconductor field effect tube, each cell is in a parallel relationship. Figure 1 As shown, each cell in the metal oxide semiconductor field effect transistor includes a drain metal layer 10 , a substrate 20 , an epitaxial layer 30 , a current spreading layer 50 , a base layer 60 , an injection layer 70 , a source metal region 80 and a gate region 40 .

[0078] In the embodiment of the present application, the drain metal layer 10, the substrate 20, the epitaxial layer 30, the current spreading layer 50, the base layer 60 and the injection layer 70 are stacked in sequence.

[0079] The drain metal layer 10 can be any one of a titanium (Ti) layer, a titanium alloy layer, an aluminum (Al) layer and an aluminum alloy layer; the drain metal layer 10 serves as a back metal electrode layer connected to the substrate 20, providing good electrical contact for the metal oxide semiconductor field effect transistor, ensuring that current can smoothly pass through the metal oxide semiconductor field effect transistor.

[0080] The substrate 20 is an N-type heavily doped (N+) silicon carbide substrate, and the substrate 20 can be any one of a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate, and a 3C-SiC single crystal substrate. The substrate 20 serves as the underlying material of the entire metal oxide semiconductor field effect transistor, provides physical support for the metal oxide semiconductor field effect transistor, and ensures the structural integrity of the metal oxide semiconductor field effect transistor. In addition, the silicon carbide substrate has excellent thermal and electrical conductivity, so that the substrate 20 can effectively conduct away the heat generated inside the metal oxide semiconductor field effect transistor, while improving the uniformity of current distribution in the metal oxide semiconductor field effect transistor.

[0081] In some embodiments, the epitaxial layer 30 is an N-type lightly doped (N-) silicon carbide epitaxial layer, and the thickness of the epitaxial layer 30 is 6 μm to 20 μm.

[0082] The current spreading layer 50 (Current Spreading Layer, CSL) is an N-type lightly doped silicon carbide epitaxial layer, and the doping concentration of the current spreading layer 50 is greater than the doping concentration of the epitaxial layer 30 .

[0083] The base layer 60 is a P-type lightly doped (P-) silicon carbide epitaxial layer, and when the voltage of the gate region 40 is greater than the threshold voltage, a conductive channel is formed in the base layer 60. In some embodiments, the base layer 60 has a thickness of 0.5 μm to 3 μm.

[0084] It should be noted that the metal oxide semiconductor field effect transistor provided in the embodiment of the present application is an N-type MOS tube. In the cell, two P-type doped regions and an N-type doped region located between the two P-type doped regions can form a junction field effect transistor (JFET), such as Figure 1As shown, the base layer 60, the buried layer 31, the epitaxial layer 30 between the base layer 60 and the buried layer 31, and the current spreading layer 50 together constitute a junction field effect transistor; in the embodiment of the present application, the resistance of the junction field effect transistor can be adjusted by adjusting the thickness of the current spreading layer 50 to reduce the JFET effect of the metal oxide semiconductor field effect transistor.

[0085] In an embodiment of the present application, the injection layer 70 includes a P-type heavily doped ion injection layer 71 and an N-type heavily doped ion injection layer 72; one end of the N-type heavily doped ion injection layer 72 is connected to the gate region 40, and the other end of the N-type heavily doped ion injection layer 72 away from the gate region 40 is connected to the P-type heavily doped ion injection layer 71, and one end of the P-type heavily doped ion injection layer 71 away from the N-type heavily doped ion injection layer 72 extends to the side edge of the cell.

[0086] The P-type heavily doped ion implantation layer 71 is used to form an ohmic contact of the cell; and the N-type heavily doped ion implantation layer 72 is used to provide electrons.

[0087] In the embodiment of the present application, the upper portion of the source metal region 80 covers the upper surface of the injection layer 70 and the gate region 40 , and the lower portion of the source metal region 80 penetrates the injection layer 70 , the base layer 60 and the current spreading layer 50 along the longitudinal center line of the cell and extends to the buried layer region 31 in the epitaxial layer 30 .

[0088] The source metal region 80 may include at least one of copper (Cu), copper alloy, aluminum and aluminum alloy.

[0089] Specifically, the upper portion of the source metal region 80 covers the upper surface of the injection layer 70 and the gate region 40 to form a source metal layer connected to the upper surface of the injection layer 70, which is used to provide a low-impedance current channel for the metal oxide semiconductor field effect transistor, so that the current can flow smoothly from the metal oxide semiconductor field effect transistor into the external circuit.

[0090] The epitaxial layer 30 includes a buried region 31 in contact with the bottom of the source metal region 80 , so that the buried region 31 wraps the bottom of the source metal region 80 .

[0091] The longitudinal center line of the cell is the center line along the thickness direction of the cell; in the embodiment of the present application, the longitudinal center line of the source metal region 80 may coincide with the longitudinal center line of the cell, and the longitudinal center line of the source metal region 80 may not coincide with the longitudinal center line of the cell, and the embodiment of the present application does not make any specific limitation for comparison.

[0092] The buried region 31 is a P-type buried region (P Shielding Region, PSR). Specifically, the buried region 31 is a P-type heavily doped region.

[0093] Reference Figure 1 The buried region 31 and the epitaxial layer 30 constitute a first body diode D1 in the metal oxide semiconductor field effect transistor, and the base layer 60 and the current spreading layer 50 constitute a second body diode D2 in the metal oxide semiconductor field effect transistor.

[0094] In the embodiment of the present application, the side wall of the source metal region 80 includes a Schottky contact region 90 and a gate region 40 with the side wall as the longitudinal center line; wherein the upper end of the Schottky contact region 90 is connected to the bottom of the gate region 40, and the lower end of the Schottky contact region 90 is connected to the top of the buried layer region 31.

[0095] The gate region 40 penetrates the injection layer 70, the base layer 60 and the current spreading layer 50 and extends into the epitaxial layer 30, and the depth of the gate region 40 is less than the depth of the source metal region 80. The sum of the depth of the gate region 40 and the first length of the Schottky contact region 90 along the direction of the thickness of the cell is less than the depth of the source metal region 80.

[0096] Reference Figure 1 In the embodiment of the present application, the number of side walls of the source metal region 80 is 2, each side wall of the source metal region 80 includes a Schottky contact region 90 and a gate region 40 with the side wall as a longitudinal center line, the number of Schottky contact regions 90 is 2, and the number of gate regions 40 is also 2, forming a split gate structure in the silicon carbide metal oxide semiconductor field effect transistor.

[0097] The Schottky contact region 90 in the sidewall of the source metal region 80 and the epitaxial layer 30 form a Schottky Barrier Diode (SBD).

[0098] When the gate region 40 is grounded or negative voltage, the drain metal layer 10 is connected to a high level, and the source metal region 80 is grounded, that is, the metal oxide semiconductor field effect transistor is in a forward blocking state, the SBD is in a reverse bias state, and the buried layer region 31 connected to the SBD will not only suppress the reverse leakage of the SBD and prevent the Schottky junction from breaking down in advance, but also cut off the electric field line of the drain metal layer 10 at this location, reduce the electric field strength at the bottom of the gate region 40, and improve the reliability of the metal oxide semiconductor field effect transistor. When the gate region 40 is grounded or negative voltage, the drain metal layer 10 is connected to a low level, and the source metal region 80 is connected to a high level, that is, the metal oxide semiconductor field effect transistor is in a reverse conduction state, since the conduction voltage drop of the SBD is less than the conduction voltage drop of the body diode, when the metal oxide semiconductor field effect transistor is reversely conducted, the SBD will be conducted before the body diode, and the SBD is in a unipolar mode when it is conducted, avoiding the bipolar degradation caused by the conduction of the body diode, and reducing the conduction voltage drop of the metal oxide semiconductor field effect transistor. In terms of dynamic characteristics, the SBD structure in the embodiment of the present application effectively reduces the overlapping area between the gate region 40 and the drain metal layer 10, reduces the gate-drain capacitance (i.e., Miller capacitance) of the metal oxide semiconductor field effect transistor, and thereby reduces the switching loss of the metal oxide semiconductor field effect transistor, so that the metal oxide semiconductor field effect transistor has excellent dynamic characteristics and is more advantageous in high-frequency application environments.

[0099] The Schottky contact region 90 may include a Ti alloy or a nickel (Ni) alloy.

[0100] Reference Figure 2 , shows a schematic cross-sectional structure diagram of a metal oxide semiconductor field effect transistor provided by an embodiment of the present application in a forward conduction state; when the voltage of the gate region 40 is greater than the threshold voltage, the metal oxide semiconductor field effect transistor is in a forward conduction state, the conductive channel is turned on, and the electrons in the source metal region 80 pass through the conductive channel → current expansion layer 50 → epitaxial layer 30 from the source metal region 80 under the action of the electric field between the source metal region 80 and the drain metal layer 10, and finally flow to the drain metal layer 10. In this process, the Schottky junction of the SBD is in a small voltage reverse bias, and there is a partial depletion region in the heavily P-type doped buried layer 31, and there is also a partial depletion region at the first body diode and the second body diode; wherein, when forward conduction occurs, the voltage of the drain metal layer 10 is generally 15V to 30V, and the depletion regions at the buried layer 31, the first body diode, and the second body diode are relatively small.

[0101] Reference Figure 3 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor in a forward blocking state provided in an embodiment of the present application Figure 1When the MOSFET is in the forward blocking state, at the beginning of the withstand voltage, as the voltage of the drain metal layer 10 gradually increases from 0V to the breakdown voltage, the depletion region of the buried region 31, the depletion region of the first body diode, and the depletion region of the second body diode gradually increase. Figure 4 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor in a forward blocking state provided in an embodiment of the present application Figure 2 When the voltage of the drain metal layer 10 reaches the breakdown voltage, the depletion region of the buried layer 31 covers the entire epitaxial layer 30 , and the depletion region of the first body diode and the depletion region of the second body diode cover the entire current spreading layer 50 .

[0102] Reference Figure 5 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor in a reverse conduction state provided by an embodiment of the present application Figure 1 When the MOSFET is in the reverse conduction state and the voltage of the drain metal layer 10 is less than the conduction voltage drop of the first body diode and the second body diode, the conduction of the SBD will inhibit the conduction of the first body diode and the second body diode. At this time, only the electron current flows, which is a unipolar conduction mode. Figure 6 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor in a reverse conduction state provided by an embodiment of the present application Figure 2 ; When the metal oxide semiconductor field effect transistor is in the reverse conduction state and the voltage of the drain metal layer 10 is greater than the conduction voltage drop of the first body diode and the second body diode, the SBD, the first body diode and the second body diode are all turned on. At this time, the first body diode and the second body diode will inject holes into the epitaxial layer 30, which is a bipolar conduction mode. This conduction mode will cause bipolar degradation of the metal oxide semiconductor field effect transistor.

[0103] In the related technology, while the SiC MOSFET is optimized to improve the reliability and reduce the on-state voltage drop of the SiC MOSFET, the SiC MOSFET still has problems such as high Miller capacitance and large switching loss, resulting in poor dynamic characteristics of the current SiC MOSFET. There is a problem that the on-state voltage drop, reliability and dynamic characteristics of the silicon carbide metal oxide semiconductor field effect transistor cannot be optimized at the same time.

[0104] The metal oxide semiconductor field effect transistor provided in the embodiment of the present application comprises in each cell a drain metal layer 10, a substrate 20, an epitaxial layer 30, a current spreading layer 50, a base layer 60 and an injection layer 70 stacked in sequence, as well as a source metal region 80 and a gate region 40; wherein, the upper portion of the source metal region 80 covers the upper surfaces of the injection layer 70 and the gate region 40 to form a source metal layer connected to the upper surface of the injection layer 70, the lower portion of the source metal region 80 penetrates the injection layer 70, the base layer 60 and the current spreading layer 50 along the longitudinal center line of the cell and extends to the buried layer region 31 in the epitaxial layer 30, the Schottky contact region 90 and the epitaxial layer 30 form a Schottky diode, the buried layer region 31 and the epitaxial layer 30 form a body diode, and the base layer 60 and the current spreading layer 50 form a body diode; when the metal oxide semiconductor field effect transistor is in a forward blocking state, the source metal region 80 and the base layer 60 form a body diode. The buried layer region 31 connected to the region 80 can cut off the electric field line of the drain metal layer 10, reduce the electric field strength at the bottom of the gate region 40, and improve the reliability of the metal oxide semiconductor field effect tube; when the metal oxide semiconductor field effect tube is in the reverse conduction state, since the conduction voltage drop of the Schottky diode is less than the conduction voltage drop of the body diode, the Schottky diode is turned on before the body diode, and the Schottky diode is in a unipolar mode when it is turned on, avoiding the bipolar degradation caused by the conduction of the body diode, and reducing the conduction voltage drop of the metal oxide semiconductor field effect tube; further, the structure of the Schottky diode in the embodiment of the present application reduces the overlapping area of ​​the gate region 40 and the drain metal layer 10, reduces the Miller capacitance of the metal oxide semiconductor field effect tube, and then reduces the switching loss of the metal oxide semiconductor field effect tube, and improves the dynamic characteristics of the metal oxide semiconductor field effect tube. Therefore, the embodiment of the present application not only ensures the conduction voltage drop and reliability of the silicon carbide metal oxide semiconductor field effect tube, but also reduces the Miller capacitance and switching loss of the metal oxide semiconductor field effect tube, and improves the dynamic characteristics of the metal oxide semiconductor field effect tube.

[0105] Optionally, in some embodiments, referring to Figure 7 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 2 In the cell of the metal oxide semiconductor field effect transistor, the minimum distance between the side edge of the cell and the gate region 40 is a first distance W1, the minimum distance between the side edge of the cell and the buried region 31 is a second distance W2, and the minimum distance between the side edge of the cell and the Schottky contact region 90 is a third distance W3.

[0106] In the embodiment of the present application, the third distance W3 is greater than the second distance W2, and the second distance W2 is greater than the first distance W1.

[0107] Specifically, under the premise that the third distance W3 is greater than the second distance W2, the lateral width of the buried region 31 can be adjusted by adjusting the second distance W2. Adjusting the lateral width of the buried region 31 can adjust the current path when the SBD is turned on, thereby changing the degree of protection of the gate region 40 under the reverse withstand voltage state; wherein, the larger the lateral width of the buried region 31, the longer the current path when the SBD is turned on, and the greater the on-state voltage drop of the SBD, but the reliability of the metal oxide semiconductor field effect transistor is also improved accordingly; therefore, in the process of adjusting the lateral width of the buried region 31 by adjusting the second distance W2, the on-state voltage drop and reliability requirements of the metal oxide semiconductor field effect transistor can be compromised to reasonably determine the lateral width of the buried region 31, and the embodiments of the present application do not make specific limitations on this.

[0108] The lateral width of the buried layer region 31 refers to the dimension of the buried layer region 31 along the direction of the width of the cell.

[0109] In the embodiment of the present application, under the premise that the third distance W3 is greater than the first distance W1, the specific position of the SBD can be adjusted by adjusting the third distance W3.

[0110] Under the premise that the second distance W2 is greater than the first distance W1, the lateral width of the buried region 31 can be adjusted by adjusting the second distance W2 to adjust the current path when the SBD is turned on, thereby changing the degree of protection of the gate region 40 in the reverse withstand voltage state.

[0111] Optionally, in some embodiments, the width of the buried region 31 is greater than or equal to the distance between the Schottky contact regions 90 in two sidewalls of the source metal region 80 .

[0112] It can be understood that the distance between the Schottky contact regions 90 in the two side walls of the source metal region 80 refers to the distance between the Schottky contact regions 90 provided in the two side walls of the source metal region 80 in the cell in the direction of the width of the cell. The width of the buried region 31 is the lateral width of the buried region 31.

[0113] The cell of the metal oxide semiconductor field effect transistor provided in the embodiment of the present application can control the on-state voltage drop, reliability and specific position of the SBD of the metal oxide semiconductor field effect transistor by adjusting the third distance W3 and the second distance W2 of the cell, under the premise that the third distance W3 is greater than the second distance W2 and the second distance W2 is greater than the first distance W1, thereby improving the flexibility of the embodiment of the present application.

[0114] Optionally, in some embodiments, referring to Figure 8 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 3The minimum distance between the lower end of the Schottky contact region 90 and the bottom of the source metal region 80 is a fourth distance H1, and the minimum distance between the bottom of the gate region 40 and the bottom of the source metal region 80 is a fifth distance H2.

[0115] In the embodiment of the present application, the fifth distance H2 is greater than the fourth distance H1. Specifically, under the premise that the fifth distance H2 is greater than the fourth distance H1, the area of ​​the Schottky contact region 90 (that is, the area of ​​the SBD-Wall) can be adjusted by adjusting the fifth distance H2 and / or the fourth distance H1. By adjusting the area of ​​the Schottky contact region 90, the contact area between the Schottky contact region 90 and the epitaxial layer 30 can be adjusted, thereby adjusting the on-resistance and on-voltage drop of the SBD.

[0116] It can be understood that when the area of ​​the Schottky contact region 90 increases, the contact area between the Schottky contact region 90 and the epitaxial layer 30 increases, and the on-resistance of the SBD decreases; when the on-resistance of the SBD decreases, the forward conduction voltage drop of the SBD decreases, thereby reducing the conduction loss of the metal oxide semiconductor field effect transistor.

[0117] It should be noted that SBD-Wall refers to the Schottky contact region 90 located on the side wall of the source metal region 80 .

[0118] Optionally, in some embodiments, a first length of the Schottky contact region 90 along the thickness direction of the cell is smaller than a first width of the gate region 40 along the width direction of the cell, and the first length is greater than half of the first width.

[0119] In the metal oxide semiconductor field effect transistor provided in the embodiment of the present application, the fourth distance between the lower end of the Schottky contact region 90 and the bottom of the source metal region 80 is smaller than the fifth distance between the bottom of the gate region 40 and the bottom of the source metal region 80, and on the premise that the fourth distance is smaller than the fifth distance, the area of ​​the Schottky contact region 90 is adjusted by adjusting the fifth distance H2 and / or the fourth distance H1. By adjusting the area of ​​the Schottky contact region 90, the contact area between the Schottky contact region 90 and the epitaxial layer 30 is adjusted, thereby adjusting the on-resistance and on-voltage drop of the SBD, thereby improving the feasibility of the embodiment of the present application.

[0120] Optionally, in some embodiments, referring to Fig. 9 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 4 The distance between the upper surface of the injection layer 70 and the lower surface of the current spreading layer 50 is a sixth distance L1, and the distance between the upper surface of the injection layer 70 and the bottom of the source metal region 80 is a seventh distance L2.

[0121] In the embodiment of the present application, the sixth distance L1 is less than or equal to the seventh distance L2, which can reduce the resistance of the junction field effect transistor and further reduce the influence of the JFET effect on the performance of the metal oxide semiconductor field effect transistor.

[0122] Specifically, the embodiment of the present application adjusts the sixth distance L1 by adjusting the thickness of the current spreading layer 50; it can be understood that the base layer 60, the buried layer 31, the epitaxial layer 30 between the base layer 60 and the buried layer 31, and the current spreading layer 50 together constitute a junction field effect transistor; in the embodiment of the present application, the sixth distance L1 is adjusted by adjusting the thickness of the current spreading layer 50, so as to adjust the resistance of the junction field effect transistor and reduce the JFET effect of the metal oxide semiconductor field effect transistor.

[0123] It should be noted that, in the process of adjusting the sixth distance L1, the embodiment of the present application only adjusts the thickness of the current spreading layer 50; the thickness of the base layer 60 and the injection layer 70 are determined according to the process requirements of the metal oxide semiconductor field effect transistor, and in the process of adjusting the sixth distance L1, the thickness of the base layer 60 and the injection layer 70 remain unchanged.

[0124] In the metal oxide semiconductor field effect transistor provided in the embodiment of the present application, the sixth distance between the upper surface of the injection layer 70 and the lower surface of the current spreading layer 50 is less than or equal to the seventh distance between the upper surface of the injection layer 70 and the bottom of the source metal region 80, so as to ensure that the base layer 60, the buried layer region 31 and the epitaxial layer 30 and the current spreading layer 50 between the base layer 60 and the buried layer region 31 can jointly constitute a junction field effect transistor, and then the sixth distance L1 can be adjusted by adjusting the thickness of the current spreading layer 50 to achieve the adjustment of the resistance of the junction field effect transistor, so as to reduce the JFET effect of the metal oxide semiconductor field effect transistor and reduce the influence of the JFET effect on the performance of the metal oxide semiconductor field effect transistor.

[0125] Optionally, in some embodiments, the doping concentration of the buried region 31 is greater than the doping concentration of the base layer 60 .

[0126] The buried layer region 31 is a P-type heavily doped region, and the base layer 60 is a P-type lightly doped silicon carbide epitaxial layer.

[0127] Specifically, the doping concentration of the buried layer region 31 is 10 19 cm -3 , the doping concentration of the base layer 60 is 10 15 cm -3 Up to 10 18 cm -3 .

[0128] The doping concentration of the buried region 31 refers to the doping concentration of the impurity ions inside the buried region 31; in the embodiment of the present application, the buried region 31 is a P-type heavily doped region, and the doping concentration of the buried region 31 is the doping concentration of the aluminum element. Similarly, the doping concentration of the base layer 60 refers to the doping concentration of the impurity ions inside the base layer 60; in the embodiment of the present application, the base layer 60 is a P-type lightly doped region, and the doping concentration of the base layer 60 is the doping concentration of the aluminum element.

[0129] Optionally, in some embodiments, the doping concentration of the substrate 20 is greater than the doping concentration of the current spreading layer 50 , and the doping concentration of the current spreading layer 50 is greater than the doping concentration of the epitaxial layer 30 .

[0130] The substrate 20 is an N-type heavily doped silicon carbide substrate, the current spreading layer 50 is an N-type lightly doped silicon carbide epitaxial layer, and the epitaxial layer 30 is an N-type lightly doped silicon carbide epitaxial layer.

[0131] The doping concentration of the current spreading layer 50 is 10 15 cm -3 Up to 10 17 cm -3 , the doping concentration of the epitaxial layer 30 is 6×10 15 cm -3 Up to 6×10 16 cm -3 .

[0132] It should be noted that the doping concentration of the current spreading layer 50 refers to the doping concentration of the impurity ions inside the current spreading layer 50; in the embodiment of the present application, the current spreading layer 50 is an N-type lightly doped silicon carbide epitaxial layer, and the doping concentration of the current spreading layer 50 is the doping concentration of the nitrogen (Nitrogen, N) element. Similarly, the doping concentration of the epitaxial layer 30 refers to the doping concentration of the impurity ions inside the epitaxial layer 30; in the embodiment of the present application, the epitaxial layer 30 is an N-type lightly doped silicon carbide epitaxial layer, and the doping concentration of the epitaxial layer 30 is the doping concentration of the nitrogen element.

[0133] Optionally, in some embodiments, referring to Figure 1 , the buried layer region 31 wraps the entire bottom of the source metal region 80 .

[0134] The entire bottom of the source metal region 80 includes the bottom surface of the source metal region 80 and the corner regions connected to the left and right ends of the bottom surface. In the embodiment of the present application, the buried layer region 31 wraps the entire bottom of the source metal region 80 as a whole.

[0135] Optionally, in some embodiments, referring to Figure 1 , Fig.10 and Fig.11 ,in, Fig.10The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application is shown in FIG. Figure 5 , Fig.11 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application is shown in FIG. Figure 6 , the depth of the buried region 31 is greater than 0 and less than the thickness of the epitaxial layer 30 .

[0136] Specifically, Figure 1 , Fig.10 and Fig.11 As shown, the depth of the buried region 31 is greater than 0 and less than or equal to the distance between the bottom of the source metal region 80 and the lower surface of the epitaxial layer 30 .

[0137] Optionally, in some embodiments, referring to Fig.12 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 7 ;like Fig.12 As shown, the buried region 31 includes a first buried region 311 and a second buried region 312 which are independent of each other, and the first buried region 311 and the second buried region 312 respectively wrap around different corner regions at the bottom of the source metal region 80 .

[0138] It can be understood that in the embodiment of the present application, the first buried region 311 and the second buried region 312 in the buried region 31 respectively wrap different corner areas at the bottom of the source metal region 80, and the bottom surface between the first buried region 311 and the second buried region 312 is not wrapped by the buried region 31.

[0139] As an optional implementation, a Schottky contact region 90 may be provided on the bottom surface between the first buried region 311 and the second buried region 312 that is not wrapped by the buried region 31 , so that the Schottky contact region 90 there and the epitaxial layer 30 form a Schottky diode.

[0140] Optionally, in some embodiments, the gate region 40 includes a gate filling portion 42 and a dielectric layer 41 wrapping the gate filling portion 42; wherein the dielectric layer 41 is used to isolate the gate filling portion 42 from the epitaxial layer 30, the current spreading layer 50, the base layer 60, the injection layer 70, and the source metal region 80.

[0141] The gate filling portion 42 includes polysilicon; the dielectric layer 41 is an oxide layer, which plays a role of isolation and insulation.

[0142] In summary, the metal oxide semiconductor field effect transistor provided in the embodiment of the present application includes a drain metal layer 10, a substrate 20, an epitaxial layer 30, a current spreading layer 50, a base layer 60 and an injection layer 70, as well as a source metal region 80 and a gate region 40 stacked in sequence in each cell; wherein the upper part of the source metal region 80 covers the upper surface of the injection layer 70 and the gate region 40 to form a source metal layer connected to the upper surface of the injection layer 70, and the lower part of the source metal region 80 passes through the injection layer 70, the base layer 60 and the current spreading layer 50 along the longitudinal center line of the cell and extends to the buried layer 31 in the epitaxial layer 30, the Schottky contact region 90 and the epitaxial layer 30 form a Schottky diode, the buried layer 31 and the epitaxial layer 30 form a body diode, and the base layer 60 and the current spreading layer 50 form a body diode; when the metal oxide semiconductor field effect transistor is in a forward blocking state, the source The buried region 31 connected to the metal region 80 can cut off the electric field lines of the drain metal layer 10, reduce the electric field strength at the bottom of the gate region 40, and improve the reliability of the metal oxide semiconductor field effect transistor; when the metal oxide semiconductor field effect transistor is in a reverse conduction state, since the conduction voltage drop of the Schottky diode is less than the conduction voltage drop of the body diode, the Schottky diode is turned on before the body diode, and the Schottky diode is in a unipolar mode when it is turned on, avoiding the bipolar degradation caused by the conduction of the body diode and reducing the conduction voltage drop of the metal oxide semiconductor field effect transistor; further, the structure of the Schottky diode in the embodiment of the present application reduces the overlapping area of ​​the gate region 40 and the drain metal layer 10, reduces the Miller capacitance of the metal oxide semiconductor field effect transistor, thereby reducing the switching loss of the metal oxide semiconductor field effect transistor and improving the dynamic characteristics of the metal oxide semiconductor field effect transistor.

[0143] Method Embodiment

[0144] Reference Fig.13 , shows a flowchart of a method for preparing a metal oxide semiconductor field effect transistor provided in an embodiment of the present application, the method comprising steps S101 to S108:

[0145] Step S101 : preparing a first intermediate piece based on an original substrate.

[0146] Among them, refer to Fig.14 , showing a cross-sectional structure diagram of a first middleware provided in an embodiment of the present application Figure 1 ,like Fig.14 As shown, the first intermediate member includes an original substrate 20' and an epitaxial layer 30, a current spreading layer 50 and an original base layer 60' which are sequentially stacked on the upper surface of the original substrate 20'; the epitaxial layer 30 includes a buried region 31; the first intermediate member includes a source trench 01 which passes through the original base layer 60' and the current spreading layer 50 along the longitudinal center line of the first intermediate member and extends to the buried region 31 in the epitaxial layer 30.

[0147] The longitudinal center line of the first middle piece is a center line along the thickness direction of the first middle piece.

[0148] The original substrate 20 ′ is an N-type heavily doped silicon carbide substrate, and the thickness of the original substrate 20 ′ is 325 μm to 375 μm; the original substrate 20 ′ can be any one of a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate and a 3C-SiC single crystal substrate.

[0149] The epitaxial layer 30 is an N-type lightly doped silicon carbide epitaxial layer, and the thickness of the epitaxial layer 30 is 6 μm to 20 μm. The buried layer 31 is a P-type heavily doped region.

[0150] The current spreading layer 50 is an N-type lightly doped silicon carbide epitaxial layer, and the doping concentration of the current spreading layer 50 is greater than the doping concentration of the epitaxial layer 30 .

[0151] The original base layer 60 ′ is a P-type lightly doped silicon carbide epitaxial layer.

[0152] Step S102 , preparing a Schottky contact region connected to the top of the buried layer region on the sidewall of the source trench, and filling the source trench having the Schottky contact region on the sidewall with a source metal.

[0153] Specifically, after step S101, refer to Fig.15 , showing a cross-sectional structure diagram of a first middleware provided in an embodiment of the present application Figure 2 ,like Fig.15 As shown, first, Ti alloy or Ni alloy is deposited on the sidewall of the source trench 01 to obtain a Schottky contact region 90 connected to the top of the buried layer region 31; then, the source trench 01 with the Schottky contact region 90 on the sidewall is filled with a source metal by deposition or sputtering. The source metal may include at least one of copper, copper alloy, aluminum and aluminum alloy.

[0154] Step S103 , performing etching processing on the sidewall of the source trench filled with the source metal with the sidewall as the longitudinal center line to obtain a gate trench.

[0155] Specifically, refer to Fig.16 , showing a cross-sectional structure diagram of a first middleware provided in an embodiment of the present application Figure 3 ,like Fig.16 As shown, the gate trench 02 is etched on the original base layer 60', the current expansion layer 50 and the source metal filled in the source trench 01 by using ion etching technology with the side wall of the source trench 01 as the longitudinal center line, so as to obtain the gate trench 02 arranged on the side wall of the source trench 01. The gate trench 02 penetrates the original base layer 60', the current expansion layer 50 and extends to the epitaxial layer 30.

[0156] The depth of the gate trench 02 is less than that of the source trench 01 , and the sum of the depth of the gate trench 02 and the first length of the Schottky contact region 90 along the thickness direction of the cell is less than or equal to the depth of the source trench 01 .

[0157] Step S104, preparing a first oxide layer on the inner wall of the gate trench, and filling polysilicon in the gate trench having the first oxide layer on the inner wall.

[0158] Specifically, first, a sacrificial oxide layer of good quality is formed on the upper surface of the first intermediate member by using a dry oxygen thermal oxidation method, and the interface damage caused by ion implantation and ion etching is removed by etching the sacrificial oxide layer; then, after the sacrificial oxide layer is removed, Fig.17 , showing a cross-sectional structure diagram of a first middleware provided in an embodiment of the present application Figure 4 , a first oxide layer 411 is prepared on the inner wall of the gate trench 02 by combining dry oxygen thermal oxidation and deposition; finally, polysilicon is deposited in the gate trench 02 with the first oxide layer 411 on the inner wall by low pressure chemical vapor deposition (LPCVD) technology.

[0159] It should be noted that the polysilicon deposited in the gate trench 02 serves as the gate filling portion 42 in the gate region 40 in the embodiment of the present application; the first oxide layer 411 serves as a part of the dielectric layer 41 in the gate region 40 .

[0160] Step S105 , performing a first ion implantation operation on the upper surface of the original base layer to obtain an implantation layer stacked on the upper surface of the base layer.

[0161] The first ion implantation operation includes an Al element implantation operation and an N element implantation operation.

[0162] Specifically, refer to Fig.18 , showing a cross-sectional structure diagram of a first middleware provided in an embodiment of the present application Figure 5 , in conjunction with the mask Mask, an Al element is implanted to form a P-type heavily doped ion implantation layer 71 in the original base layer 60', and an N-type heavily doped ion implantation layer 72 is formed in the original base layer 60' through an N element implantation operation, thereby obtaining an implantation layer 70 including a P-type heavily doped ion implantation layer 71 and an N-type heavily doped ion implantation layer 72.

[0163] It should be noted that the upper part of the original base layer 60' is formed into an injection layer 70 through a first ion implantation operation, and the portion of the original base layer 60' outside the injection layer 70 is the base layer 60, and the injection layer 70 is stacked on the upper surface of the base layer 60; the thickness of the original base layer 60' is equal to the sum of the thicknesses of the injection layer 70 and the base layer 60.

[0164] Step S106 , preparing a second oxide layer on the upper surface of the gate trench filled with polysilicon to obtain a second intermediate member.

[0165] Specifically, refer to Fig.19 , showing a cross-sectional structure diagram of a second middleware provided in an embodiment of the present application Figure 1 First, an oxide layer is prepared on the upper surface of the first intermediate member; then, a portion of the oxide layer covering the implantation layer 70 is etched using a computed tomography (CT) etching technique to obtain a second oxide layer 412 covering the upper surface of the gate trench 02 filled with polysilicon.

[0166] In the embodiment of the present application, the first oxide layer 411 , the second oxide layer 412 and the polysilicon (gate filling portion 42 ) in the gate trench 02 constitute the gate region 40 .

[0167] Optionally, in some embodiments, due to the etching accuracy limitation of the CT etching technology, in the process of etching the portion of the oxide layer on the upper surface of the first intermediate member covering the injection layer 70, it may not be possible to accurately control the complete etching of the oxide layer covering the injection layer 70 while ensuring that the upper surface of the gate trench 02 is completely covered by the second oxide layer 412. In the case where the second oxide layer 412 covering the upper surface of the gate trench 02 is over-etched, a portion of the upper surface of the gate filling portion 42 is exposed, and after the source metal layer is subsequently prepared on the upper surface of the second intermediate member in step S107, the gate filling portion 42 will contact the source metal layer, so that the source metal region 80 and the gate region 40 are connected in parallel, resulting in defects in the metal oxide semiconductor field effect transistor obtained in step S108.

[0168] In practical application scenarios, in order to prevent the second oxide layer 412 from being over-etched, refer to Fig. 20 , showing a cross-sectional structure diagram of a second middleware provided in an embodiment of the present application Figure 2 , the second oxide layer 412 obtained after CT etching can cover the upper surface of the gate trench 02 while also covering a portion of the upper surface of the N-type heavily doped ion implantation layer 72 .

[0169] Step S107 , preparing a source metal layer on the upper surface of the second intermediate component, wherein the source metal layer and the source metal in the source trench constitute a source metal region.

[0170] Specifically, refer to Fig.21 , showing a cross-sectional structure diagram of a second middleware provided in an embodiment of the present application Figure 3 , preparing a source metal layer on the upper surface of the second intermediate member by sputtering; wherein the source metal layer may include at least one of copper, copper alloy, aluminum and aluminum alloy.

[0171] It should be noted that the source metal layer serves as the upper part of the source metal region 80 and covers the upper surface of the injection layer 70 and the gate region 40; the source metal filled in the source trench 01 in step S102 serves as the lower part of the source metal region 80, penetrates the injection layer 70, the base layer 60 and the current spreading layer 50 along the longitudinal center line of the cell and extends to the buried layer 31 in the epitaxial layer 30.

[0172] In the embodiment of the present application, after step S107, a passivation layer may be further prepared on the upper surface of the source metal layer to prevent chemical reactions of the source metal layer and improve the chemical stability of the device.

[0173] Step S108, thinning the lower surface of the original substrate to obtain a substrate, and preparing a drain metal layer on the lower surface of the substrate to obtain a metal oxide semiconductor field effect transistor.

[0174] Specifically, first, the lower surface of the original substrate 20' is thinned by at least one of mechanical grinding, chemical etching, and inductively coupled plasma etching (ICP) technology to reduce the thickness of the original substrate 20' to 100 μm to 180 μm, thereby obtaining the substrate 20; then, the drain metal layer 10 is formed on the lower surface of the substrate 20 by a sputtering process, referring to Figure 1 The drain metal layer 10 may be any one of a titanium layer, a titanium alloy layer, an aluminum layer and an aluminum alloy layer.

[0175] The metal oxide semiconductor field effect transistor includes at least two cells, and the cells include a drain metal layer 10 , a substrate 20 , an epitaxial layer 30 , a current spreading layer 50 , a base layer 60 , an injection layer 70 , a source metal region 80 and a gate region 40 .

[0176] It can be understood that the method for preparing a metal oxide semiconductor field effect transistor provided in the embodiment of the present application can be used to prepare the metal oxide semiconductor field effect transistor as described in any of the above items.

[0177] Optionally, in some embodiments, the step S101 of preparing the first intermediate piece based on the original substrate includes steps S1011 to S1013:

[0178] Step S1011, forming an epitaxial layer, a current spreading layer and an original base layer in sequence on the upper surface of the original substrate to obtain a third intermediate component.

[0179] Reference Fig. 22 , showing a cross-sectional structure diagram of a third middleware provided in an embodiment of the present application Figure 1 Specifically: first, the epitaxial layer 30 and the original current spreading layer are sequentially grown on the upper surface of the original substrate 20' by chemical vapor deposition; then, a third ion implantation operation is performed on the upper surface of the original current spreading layer to obtain the original base layer 60' stacked on the upper surface of the current spreading layer 50.

[0180] It can be understood that the upper part of the original current spreading layer forms the original base layer 60' through the third ion implantation operation, and the part of the original current spreading layer outside the original base layer 60' is the current spreading layer 50; the thickness of the original current spreading layer is equal to the sum of the thicknesses of the original base layer 60' and the current spreading layer 50.

[0181] Step S1012, etching the third intermediate member along the longitudinal center line of the third intermediate member to obtain a source trench penetrating the original base layer and the current spreading layer and extending into the epitaxial layer.

[0182] Specifically, refer to Fig.23 , showing a cross-sectional structure diagram of a third middleware provided in an embodiment of the present application Figure 2 The third intermediate member is etched along the longitudinal center line of the third intermediate member to obtain a source trench 01 penetrating the original base layer 60 ′ and the current spreading layer 50 and extending into the epitaxial layer 30 .

[0183] The longitudinal center line of the third middle piece is the center line along the thickness direction of the third middle piece.

[0184] Step S1013, performing a second ion implantation operation at the bottom of the source trench to form a buried layer region in the epitaxial layer in contact with the bottom of the source trench, thereby obtaining a first intermediate member.

[0185] Specifically, refer to Fig.14 , a second ion implantation operation is performed at the bottom of the source trench 01 to form a buried region 31 in the epitaxial layer 30 that contacts the bottom of the source trench 01 , thereby obtaining a first intermediate member.

[0186] In the process of preparing the first intermediate component of the method for preparing the metal oxide semiconductor field effect transistor provided in the embodiment of the present application, an epitaxial layer 30, a current expansion layer 50 and an original base layer 60' are first formed in sequence on the upper surface of the original substrate 20', and then a source trench 01 is prepared that penetrates the original base layer 60' and the current expansion layer 50 and extends to the epitaxial layer 30, and a second ion implantation operation is performed at the bottom of the source trench 01 to form a buried layer region 31 in the epitaxial layer 30 that contacts the bottom of the source trench 01, thereby obtaining the first intermediate component, thereby simplifying the steps of preparing the first intermediate component and improving the preparation efficiency of the metal oxide semiconductor field effect transistor.

[0187] Optionally, in some embodiments, the step S101 of preparing the first intermediate piece based on the original substrate includes steps S1014 to S1017:

[0188] Step S1014: forming a first epitaxial layer on the upper surface of the original substrate.

[0189] Specifically, the first epitaxial layer 32 is grown on the upper surface of the original substrate 20' by chemical vapor deposition. Fig.24 , showing a cross-sectional structure diagram of a fourth middleware provided in an embodiment of the present application Figure 1 .

[0190] Step S1015 , performing a third ion implantation operation in a target area on the upper surface of the first epitaxial layer to obtain a buried layer region.

[0191] Specifically, a third ion implantation operation is performed in the target area on the upper surface of the first epitaxial layer 32 to obtain a buried layer region 31. Fig.25 , showing a cross-sectional structure diagram of a fourth middleware provided in an embodiment of the present application Figure 2 .

[0192] The target region refers to the region where the buried region 31 needs to be formed. Specifically, when the buried region 31 wraps the entire bottom of the source metal region 80, the buried region 31 wraps the entire bottom of the source metal region 80 as a whole, and the target region is an area on the upper surface of the first epitaxial layer 32; when the buried region 31 includes a first buried region 311 and a second buried region 312 that are independent of each other, and the first buried region 311 and the second buried region 312 respectively wrap different corner areas of the bottom of the source metal region 80, the target region is two independent areas on the upper surface of the first epitaxial layer 32.

[0193] It should be noted that, when the target depth of the buried region 31 is greater than the single injection depth of the third ion implantation operation in the first epitaxial layer 32, the first epitaxial layer 32 includes at least two sub-epitaxial layers, wherein the thickness of the first sub-epitaxial layer stacked on the upper surface of the original substrate 20' is greater than or equal to the single injection depth of the third ion implantation operation in the first epitaxial layer 32, and the thickness of the second sub-epitaxial layer stacked on the upper surface of the first sub-epitaxial layer is less than or equal to the single injection depth of the third ion implantation operation in the first epitaxial layer 32, until the buried region 31 of the target depth is obtained.

[0194] It can be understood that in actual application scenarios, the cross-sectional view of the buried region 31 formed by the ion implantation operation in the cross-sectional structure is elliptical or nearly elliptical. When the target depth of the buried region 31 is greater than the single implantation depth of the third ion implantation operation in the first epitaxial layer 32, the cross-sectional view of the buried region 31 obtained by at least two third ion implantation operations is a "sugar-coated haws" shape formed by stacking at least two ellipses or nearly ellipses.

[0195] Step S1016: forming a second epitaxial layer on the upper surface of the first epitaxial layer.

[0196] Specifically, the second epitaxial layer 33 is grown on the upper surface of the first epitaxial layer 32 by chemical vapor deposition. Fig.26 , showing a cross-sectional structure diagram of a fourth middleware provided in an embodiment of the present application Figure 3 .

[0197] The first epitaxial layer 32 and the second epitaxial layer 33 together constitute an epitaxial layer 30 stacked on the upper surface of the original substrate 20 ′.

[0198] Step S1017: forming a current spreading layer and an original base layer in sequence on the upper surface of the second epitaxial layer to obtain a fourth intermediate component.

[0199] Specifically, the original current spreading layer is grown on the upper surface of the second epitaxial layer 33 by chemical vapor deposition; then, a third ion implantation operation is performed on the upper surface of the original current spreading layer to obtain an original base layer 60' stacked on the upper surface of the current spreading layer 50, referring to Fig. 27 , showing a cross-sectional structure diagram of a fourth middleware provided in an embodiment of the present application Figure 4 .

[0200] Step S1018, etching the fourth intermediate member along the longitudinal center line of the fourth intermediate member to form a source trench 01 penetrating the original base layer 60' and the current spreading layer and extending to the buried layer region 31 in the epitaxial layer 30, thereby obtaining a first intermediate member.

[0201] Specifically, refer to Fig.14 The fourth intermediate member is etched along its longitudinal center line to form a source trench 01 penetrating the original base layer 60' and the current spreading layer 50 and extending to the buried region 31 in the epitaxial layer 30, thereby obtaining a first intermediate member.

[0202] The longitudinal center line of the fourth middle piece is a center line along the thickness direction of the fourth middle piece.

[0203] In the process of preparing the first intermediate component of the method for preparing the metal oxide semiconductor field effect transistor provided in the embodiment of the present application, a buried region 31 is first prepared in the epitaxial layer 30, and then a source trench 01 is prepared that penetrates the original base layer 60' and the current expansion layer 50 and extends to the buried region 31 in the epitaxial layer 30 to obtain the first intermediate component, thereby improving the flexibility of preparing the metal oxide semiconductor field effect transistor.

[0204] As an optional implementation, after step S1017 and before step S1018, step S105 can be first performed to perform a first ion implantation operation on the upper surface of the original base layer 60' to obtain an implantation layer 70 stacked on the upper surface of the base layer 60, and then step S1018 can be continued to obtain a source trench 01 that penetrates the implantation layer 70, the base layer 60 and the current expansion layer 50 and extends to the buried layer region 31 in the epitaxial layer 30.

[0205] It is understandable that the method for preparing the metal oxide semiconductor field effect transistor provided in the embodiment of the present application can be used to prepare the metal oxide semiconductor field effect transistor as described in any of the above items, and can achieve the same technical effect. To avoid repetition, it will not be described here.

[0206] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0207] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A metal oxide semiconductor field effect transistor, characterized in that: The metal oxide semiconductor field effect transistor includes at least two cells, each of which includes a drain metal layer, a substrate, an epitaxial layer, a current spreading layer, a base layer, an injection layer, a source metal region and a gate region; Wherein, the drain metal layer, the substrate, the epitaxial layer, the current spreading layer, the base layer and the injection layer are stacked in sequence; The upper part of the source metal region covers the upper surfaces of the injection layer and the gate region, and the lower part of the source metal region passes through the injection layer, the base layer and the current spreading layer along the longitudinal center line of the cell and extends to the buried layer region in the epitaxial layer; the longitudinal center line of the cell is the center line along the thickness direction of the cell; The side wall of the source metal region includes a Schottky contact region and a gate region with the side wall as a longitudinal center line; the upper end of the Schottky contact region is connected to the bottom of the gate region, and the lower end of the Schottky contact region is connected to the top of the buried layer region.

2. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: In the cell, the minimum distance between the side edge of the cell and the gate region is a first distance, the minimum distance between the side edge of the cell and the buried layer region is a second distance, and the minimum distance between the side edge of the cell and the Schottky contact region is a third distance; The third distance is greater than the second distance, and the second distance is greater than the first distance.

3. The metal oxide semiconductor field effect transistor according to claim 2, characterized in that: The width of the buried layer region is greater than or equal to the distance between the Schottky contact regions in the two side walls of the source metal region.

4. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The minimum distance between the lower end of the Schottky contact region and the bottom of the source metal region is a fourth distance, and the minimum distance between the bottom of the gate region and the bottom of the source metal region is a fifth distance; wherein the fifth distance is greater than the fourth distance.

5. The metal oxide semiconductor field effect transistor according to claim 4, characterized in that: A first length of the Schottky contact region along a direction in which the thickness of the cell is located is smaller than a first width of the gate region along a direction in which the width of the cell is located, and the first length is greater than half of the first width.

6. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The distance between the upper surface of the injection layer and the lower surface of the current spreading layer is the sixth distance, and the distance between the upper surface of the injection layer and the bottom of the source metal region is the seventh distance; wherein the sixth distance is less than or equal to the seventh distance.

7. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The doping concentration of the buried layer region is greater than the doping concentration of the base layer.

8. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The doping concentration of the substrate is greater than the doping concentration of the current spreading layer, and the doping concentration of the current spreading layer is greater than the doping concentration of the epitaxial layer.

9. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The buried layer region wraps the entire bottom of the source metal region.

10. The metal oxide semiconductor field effect transistor according to claim 9, characterized in that: The depth of the buried layer region is greater than 0 and less than the thickness of the epitaxial layer.

11. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The buried layer region includes a first buried layer region and a second buried layer region which are independent of each other, and the first buried layer region and the second buried layer region respectively wrap different corner regions at the bottom of the source metal region.

12. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The gate region includes a gate filling portion and a dielectric layer wrapping the gate filling portion, and the dielectric layer is used to isolate the gate filling portion from the epitaxial layer, the current spreading layer, the base layer, the injection layer and the source metal region.

13. A method for preparing a metal oxide semiconductor field effect transistor, characterized in that: The method comprises: A first intermediate member is prepared based on an original substrate; the first intermediate member comprises an original substrate and an epitaxial layer, a current spreading layer and an original base layer sequentially stacked on an upper surface of the original substrate; the epitaxial layer comprises a buried layer region; the first intermediate member comprises a source trench that penetrates the original base layer and the current spreading layer along a longitudinal center line of the first intermediate member and extends to the buried layer region in the epitaxial layer, and the longitudinal center line of the first intermediate member is a center line along a thickness direction of the first intermediate member; A Schottky contact region connected to the top of the buried layer region is formed on the sidewall of the source trench, and a source metal is filled in the source trench having the Schottky contact region on the sidewall; Using the side wall as a longitudinal center line, etching is performed on the side wall of the source trench filled with source metal to obtain a gate trench; Preparing a first oxide layer on the inner wall of the gate trench, and filling polysilicon in the gate trench having the first oxide layer on the inner wall; Performing a first ion implantation operation on the upper surface of the original base layer to obtain an implantation layer stacked on the upper surface of the base layer; A second oxide layer is prepared on the upper surface of the gate trench filled with polysilicon to obtain a second intermediate member; the first oxide layer, the second oxide layer and the polysilicon in the gate trench constitute a gate region; Preparing a source metal layer on the upper surface of the second intermediate member, wherein the source metal layer and the source metal in the source trench constitute a source metal region; The lower surface of the original substrate is thinned to obtain a substrate, and a drain metal layer is prepared on the lower surface of the substrate to obtain the metal oxide semiconductor field effect transistor as described in any one of claims 1 to 12; the metal oxide semiconductor field effect transistor includes at least two cells, and the cells include the drain metal layer, the substrate, the epitaxial layer, the current spreading layer, the base layer, the injection layer, the source metal region and the gate region.

14. The method according to claim 13, characterized in that The step of preparing the first intermediate piece based on the original substrate comprises: An epitaxial layer, a current spreading layer and an original base layer are sequentially formed on the upper surface of the original substrate to obtain a third intermediate member; Etching the third intermediate member along the longitudinal center line of the third intermediate member to obtain a source trench penetrating the original base layer and the current spreading layer and extending into the epitaxial layer; A second ion implantation operation is performed at the bottom of the source trench to form a buried layer region in the epitaxial layer in contact with the bottom of the source trench, thereby obtaining a first intermediate member.

15. The method according to claim 13, characterized in that The step of preparing the first intermediate piece based on the original substrate comprises: forming a first epitaxial layer on the upper surface of the original substrate; Performing a third ion implantation operation in a target area on the upper surface of the first epitaxial layer to obtain a buried layer region; forming a second epitaxial layer on the upper surface of the first epitaxial layer; the first epitaxial layer and the second epitaxial layer constitute an epitaxial layer stacked on the upper surface of the original substrate; sequentially forming a current spreading layer and an original base layer on the upper surface of the second epitaxial layer to obtain a fourth intermediate member; The fourth intermediate member is etched along the longitudinal center line of the fourth intermediate member to form a source trench penetrating the original base layer and the current spreading layer and extending to the buried layer region in the epitaxial layer, thereby obtaining a first intermediate member.

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