Trench type power device with improved breakdown characteristics and preparation method thereof

Abstract

The present invention relates to a trench-type power device and a preparation method, in particular to a trench-type power device and a preparation method capable of improving breakdown characteristics. According to the technical solution provided by the present invention, a trench-type power device capable of improving breakdown characteristics, the trench-type power device comprises: a semiconductor substrate of a first conductivity type; an active region prepared in the central region of the semiconductor substrate, comprising a plurality of cells connected in parallel, wherein the cells in the active region adopt a trench structure, and the bottom of the trench of the cell trench is located below the second conductivity type base region across the active region; a first conductivity type carrier storage layer is arranged in the second conductivity type base region, and the first conductivity type carrier storage layer contacts the outer side wall of the corresponding cell trench. The present invention improves the breakdown characteristics of the power device, reduces the conduction loss of the power device, increases the switching speed, and effectively reduces the conduction voltage drop.

Description

Technical Field

[0001] The invention relates to a trench type power device and a preparation method thereof, in particular to a trench type power device capable of improving breakdown characteristics and a preparation method thereof. Background Art

[0002] As a new generation of power electronic devices, the insulated gate bipolar transistor (IGBT) combines the advantages of the field effect transistor (MOSFET) and the bipolar junction transistor (BJT). It has the advantages of MOSFET, such as easy driving, low input impedance, and fast switching speed, and the advantages of BJT, such as high on-state current density, low on-state voltage drop, low loss, and good stability. Therefore, it has developed into one of the core electronic components in modern power electronic circuits and is widely used in various fields such as transportation, communications, household appliances, and aerospace, greatly improving the performance of power electronic systems.

[0003] In the more than 30 years since the IGBT was introduced, how to reduce the switching loss of the IGBT and improve the trade-off relationship between the device's on-state voltage drop and turn-off loss has always been the focus of research. From the first generation of planar gate punch-through IGBT (PT-IGBT) to the sixth generation of field-stop trench IGBT (FST-IGBT), researchers have continuously improved the front and back structures of the IGBT to continuously improve the performance of the IGBT. However, for the sixth generation of FST-IGBT, its performance can still be further improved. On this basis, the seventh generation of trench charge storage IGBT (CST-IGBT) was invented.

[0004] Compared with FST-IGBT, for CST-IGBT, due to the introduction of an N-type charge storage layer under the P-type base region, the introduction of the N-type charge storage layer provides a hole barrier, which enhances the hole carrier concentration on the device surface, improves the distribution of carriers in the drift region of the device, enhances the conductivity modulation effect, reduces the forward conduction voltage drop of the device, and further optimizes the trade-off relationship between the on-state voltage drop and the turn-off loss of the device. However, the introduction of the carrier storage layer will reduce the depletion layer extension area in the drift region, and cannot effectively shield the high electric field near the gate oxide layer, causing the breakdown characteristics of the device to degrade.

[0005] In order to ensure that the breakdown characteristics of the IGBT device are not degraded, the depth of the trench should be made deeper. However, the deep trench gate will increase the gate capacitance of the device, especially the Miller capacitance (Cgc), and then increase the gate collector charge (Qgc), which will slow down the speed of the device when turning on and off, thereby increasing the switching loss of the device.

[0006] In addition, during the shutdown process of the IGBT device, it takes a certain amount of time to remove the charge stored in the drift region, which leads to serious tail current when the IGBT is turned off, greatly increasing the turn-off loss of the device. The turn-off loss can be reduced by reducing the lifetime of the carriers in the drift region, but at the same time it will be accompanied by an increase in the on-state voltage drop. Although the overall performance of the new generation of IGBTs has been improved, the on-state voltage drop is still likely to decrease further. How to optimize the reduction of the on-state voltage drop and improve the conduction loss is still a difficult problem that needs to be solved. Summary of the invention

[0007] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a trench power device and a preparation method that can improve the breakdown characteristics of the power device, reduce the conduction loss of the power device, increase the switching speed, and effectively reduce the conduction voltage drop.

[0008] According to the technical solution provided by the present invention, a trench power device capable of improving breakdown characteristics comprises:

[0009] A semiconductor substrate having a first conductivity type;

[0010] An active region, prepared in the central region of the semiconductor substrate, includes a plurality of cells connected in parallel, wherein the cells in the active region adopt a trench structure, and the bottom of the trench of the cell is located below the second conductive type base region that crosses the active region;

[0011] A first conductivity type carrier storage layer is disposed in the second conductivity type base region, and the first conductivity type carrier storage layer is in contact with an outer sidewall of a corresponding cell trench.

[0012] For any cellular groove, it includes a cellular main groove and cellular auxiliary groove units symmetrically distributed on both sides of the cellular main groove, wherein:

[0013] The cellular auxiliary groove unit includes at least one cellular auxiliary groove;

[0014] Filling a gate body in the cell column trench, wherein the gate body is insulated and isolated from the inner wall of the cell main trench by a main trench oxide layer covering the inner wall of the cell main trench;

[0015] Filling a source body in the cell auxiliary trench, wherein the source body is insulated and isolated from the inner wall of the cell auxiliary trench by an auxiliary trench oxide layer covering the inner wall of the cell auxiliary trench;

[0016] The gate body is electrically connected to the gate metal, and the source bodies in all the cell auxiliary trenches are electrically connected to the source metal;

[0017] The first conductive type carrier storage layer is at least distributed in the second conductive type base region between the cell main trench and the cell auxiliary trench adjacent to the cell main trench.

[0018] The first conductive type carrier storage layer is also distributed in the second conductive type base region between adjacent cell auxiliary trenches;

[0019] In the cross section of the trench power device, a first conductive type source region and a second conductive type source region are arranged on both sides of the cell main trench, wherein:

[0020] The first conductive type source region and the second conductive type source region are distributed in the second conductive type base region between the cell main trench and the cell auxiliary trench adjacent to the cell main trench, and the first conductive type source region contacts the outer side wall of the cell main trench and the outer side wall of the cell auxiliary trench adjacent to the cell main trench;

[0021] The second conductive type source region is located below the first conductive type source region, and the source metal is in ohmic contact with both the first conductive type source region and the second conductive type source region.

[0022] For the second conductive type base region between adjacent cell auxiliary trenches, the second conductive type base region is configured to be in a floating state, or the second conductive type base region is in ohmic contact with the source metal.

[0023] After the first conductive type carrier storage layer is disposed in the second conductive type base region, the second conductive type base region is divided into a second conductive type first sub-base region and a second conductive type second sub-base region, wherein:

[0024] In the cross section of the power semiconductor device, the depth of the second conductivity type first sub-base region is the same as the depth of the second conductivity type second sub-base region, and the depth of the first conductivity type carrier storage layer is less than the corresponding depths of the second conductivity type first sub-base region and the second conductivity type second sub-base region.

[0025] A first conductive type buried layer is disposed under the cell main trench and each cell auxiliary trench, wherein:

[0026] The first conductive type buried layer covers the bottom of the corresponding cell main trench or cell auxiliary trench.

[0027] A method for preparing a trench power device capable of improving breakdown characteristics is used to prepare the above trench power device, the method comprising:

[0028] A semiconductor substrate having a first conductivity type is provided, and a front cell process is performed on the front side of the semiconductor substrate, wherein:

[0029] When performing a front cell process on the front side of the semiconductor substrate, an active area is prepared in the central area of ​​the semiconductor substrate, wherein the active area includes a plurality of cells connected in parallel;

[0030] The cell in the active area adopts a groove structure, and the bottom of the cell groove is located below the second conductive type base region that crosses the active area;

[0031] A first conductivity type carrier storage layer is disposed in the second conductivity type base region, and the first conductivity type carrier storage layer is in contact with an outer sidewall of a corresponding cell trench.

[0032] When a front cell process is performed on the front side of the semiconductor substrate, the front cell process includes:

[0033] Performing trench etching on the front side of the semiconductor substrate to prepare a cellular trench in the semiconductor substrate, wherein any cellular trench includes a cellular main trench and cellular auxiliary trench units symmetrically distributed on both sides of the cellular main trench, and the cellular auxiliary trench unit includes at least one cellular auxiliary trench;

[0034] Performing a thermal oxidation process on the semiconductor substrate to obtain a main trench oxide layer covering the inner wall of the main trench of the cell and an auxiliary trench oxide layer covering the inner wall of the auxiliary trench of the cell;

[0035] Depositing electrode materials on the front side of the semiconductor substrate to obtain a gate body filled in the main trench of the cell and a source body filled in the auxiliary trench of the cell, wherein the gate body is insulated and isolated from the inner wall of the main trench of the cell where it is located by a main trench oxide layer covering the inner wall of the main trench of the cell, and the source body is insulated and isolated from the inner wall of the auxiliary trench of the cell where it is located by an auxiliary trench oxide layer covering the inner wall of the auxiliary trench of the cell;

[0036] Performing impurity ion implantation on the front surface of the semiconductor substrate to prepare a second conductive type base region that traverses the active region, a first conductive type carrier storage layer distributed in the second conductive type base region, and a first conductive type source region distributed on both sides of the cell main trench;

[0037] Metal deposition is performed on the front side of the semiconductor substrate to prepare source metal and gate metal, wherein the gate metal is electrically connected to the gate body, the source metal is electrically connected to all source bodies, and the source metal is also in ohmic contact with the first conductive type source region and at least the second conductive type base region where the first conductive type source region is located.

[0038] After the cell trench is prepared, first conductive type impurity ions are implanted above the front surface of the semiconductor substrate to prepare a first conductive type buried layer, wherein:

[0039] The first conductive type buried layer corresponds to the cell main trench and all the cell auxiliary trenches one by one, and the first conductive type buried layer covers the bottom of the corresponding cell main trench or cell auxiliary trench.

[0040] After the semiconductor substrate is subjected to a front cell process, a back process is performed on the back of the semiconductor substrate to form a back structure after the back process, wherein:

[0041] Based on the formed back surface structure and active area, the trench power device is a MOSFET type device or an IGBT type device.

[0042] The advantages of the present invention are as follows: the first conductive type carrier storage layer is located in the second conductive type base region, and the second conductive type base region is separated to form a second conductive type first sub-base region and a second conductive type second sub-base region. When the power device breaks down in the reverse direction, the first conductive type carrier storage layer is isolated by the second conductive type base region, thereby eliminating the influence of the first conductive type carrier storage layer on the breakdown characteristics of the power device. At the same time, the existence of the first conductive type carrier storage layer can increase the concentration of hole carriers, enhance the conductivity modulation effect, and reduce the on-state voltage drop.

[0043] The cell includes a cell main trench and several cell auxiliary trenches. The source body in the cell auxiliary trenches is electrically connected to the source metal. Based on the formed cell, the Miller capacitance Cgc and the gate collector charge Qgc can be effectively reduced, making the switching speed of the power device faster.

[0044] At the same time, part of the second conductive type base region can be configured in a floating state, and the second conductive type base region in a floating state can be used to effectively enhance the conductivity modulation and reduce the conduction voltage drop. By introducing the first conductive type buried layer at the bottom of the cell trench, the first conductive type buried layer can be used to block the hole carriers in the first conductive type drift region, enhance the conductivity modulation, and further reduce the conduction voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a schematic diagram of an embodiment of a trench power device of the present invention.

[0046] Figure 2 to Figure 8 For Figure 1 A cross-sectional view of a specific implementation process step of a trench type power device, wherein:

[0047] Figure 2 A cross-sectional view of an embodiment of preparing a cell main groove and a cell auxiliary groove unit in the present invention.

[0048] Figure 3 The figure is a cross-sectional view of an embodiment of the N-type buried layer prepared by the present invention.

[0049] Figure 4 The present invention is a cross-sectional view of an embodiment after the main trench oxide layer and the auxiliary trench oxide layer are prepared.

[0050] Figure 5A cross-sectional view of an embodiment of the present invention after a gate body and a source body are prepared.

[0051] Figure 6 It is a cross-sectional view of an embodiment after a P-type base region, an N-type carrier storage layer and an N+ source region are prepared in the present invention.

[0052] Figure 7 This is a cross-sectional view of an embodiment of the present invention after the source metal is prepared.

[0053] Figure 8 A cross-sectional view of an embodiment of a back structure prepared in the present invention.

[0054] Fig. 9 It is a schematic diagram of another embodiment of the trench power device of the present invention.

[0055] Explanation of the accompanying drawings: 1-collector metal, 2-P+ collector region, 3-N-type buffer layer, 4-N-type drift region, 5-N-type buried layer, 6-auxiliary trench first oxide layer, 7-auxiliary trench first source body, 8-cell third auxiliary trench, 9-P-type base region, 9-1-P-type first sub-base region, 9-2-P-type second sub-base region, 10-N-type carrier storage layer, 11-N+ source region, 12-P+ source region, 13-source metal, 14-insulating dielectric layer, 15-main trench oxide layer, 16-gate body, 17-cell main trench, 18-cell first auxiliary trench, 19-cell second auxiliary trench, 20-auxiliary trench second oxide layer, 21-auxiliary trench second source body, 22-auxiliary trench third source body, 23-auxiliary trench third oxide layer. DETAILED DESCRIPTION

[0056] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0057] In order to improve the breakdown characteristics of the power device and reduce the conduction loss of the power device, for a trench power device with improved breakdown characteristics, taking the first conductivity type as N as an example, in one embodiment of the present invention, the trench power device includes:

[0058] A semiconductor substrate having an N conductivity type;

[0059] An active region, prepared in the central region of the semiconductor substrate, includes a plurality of cells connected in parallel, wherein the cells in the active region adopt a trench structure, and the bottom of the trench of the cell is located below the P-type base region 9 that crosses the active region;

[0060] An N-type carrier storage layer 10 is disposed in the P-type base region 9 , and the N-type carrier storage layer 10 is in contact with the outer sidewall of the corresponding cell trench.

[0061] The semiconductor substrate may be made of commonly used materials such as silicon, etc. The material of the semiconductor substrate may be selected as required; the conductivity type of the semiconductor substrate is N-type. Persons skilled in the art will appreciate that when the first conductivity type is N-type, the second conductivity type is P-type.

[0062] Figure 1 , Figure 8 and Fig. 9 An embodiment of a semiconductor substrate is shown in FIG. 1 . In the figure, the semiconductor substrate includes an N-type drift region 4 and an N-type buffer layer 3. The N-type drift region 4 is supported on the N-type buffer layer 3, and the N-type drift region 4 is adjacent to the N-type buffer layer 3. Generally, the doping concentration of the N-type drift region 4 is lower than the doping concentration of the N-type buffer layer 3, and the depth of the N-type drift region 4 is greater than the depth of the N-type buffer layer 3. At this time, the surface corresponding to the N-type drift region 4 is used to form the front side of the semiconductor substrate, and the surface corresponding to the N-type buffer layer 3 is used to form the back side of the semiconductor substrate. The depth of the N-type drift region 4 specifically refers to the height in the direction from the N-type drift region 4 to the N-type buffer layer 3 in the figure. The depths mentioned below all have the same meaning. Please refer to the description here for details, and no further description will be given.

[0063] For power devices, an active area is generally included. The active area is used to form a functional area of ​​the power device. The active area is generally located in the central area of ​​the semiconductor substrate. A terminal protection area can generally be set in the outer circle of the active area. The specific positional relationship and function of the terminal protection area and the active area are consistent with the existing ones. The active area of ​​the power device generally includes a number of cells, and the cells in the active area are generally connected in parallel. In one embodiment of the present invention, the cell adopts a groove structure. When the cell adopts a groove form, it at least includes a cell groove; in addition, a P-type base region 9 is generally required to be set in the active area. The P-type base region 9 is distributed across the entire active area. When the P-type base region 9 and the cell groove are set in the active area at the same time, the bottom of the cell groove is located below the P-type base region 9, and the notch of the cell groove generally corresponds to the front side of the semiconductor substrate.

[0064] As can be seen from the above description, in order to provide a hole barrier, an N-type carrier storage layer 10 can generally be set in the active region. In the prior art, the N-type carrier storage layer 10 is generally located below the P-type base region 9, that is, the N-type carrier storage layer 10 here corresponds to the N-type charge storage layer mentioned in the background technology. In one embodiment of the present invention, the N-type carrier storage layer 10 is set in the P-type base region 9, and the N-type carrier storage layer 10 contacts the sidewall of the corresponding cell trench. At this time, the N-type carrier storage layer 10 can still provide a hole barrier.

[0065] In one embodiment of the present invention, after the N-type carrier storage layer 10 is disposed in the P-type base region 9, the P-type base region 9 is divided into a P-type first sub-base region 9-1 and a P-type second sub-base region 9-2, wherein:

[0066] In the cross section of the power semiconductor device, the depth of the P-type first sub-base region 9-1 is the same as the depth of the P-type second sub-base region 9-2, and the depth of the N-type carrier storage layer 10 is less than the corresponding depths of the P-type first sub-base region 9-1 and the P-type second sub-base region 9-2.

[0067] Figure 1 In the structure, the P-type first sub-base region 9-1, the N-type carrier storage layer 10 and the P-type second sub-base region 9-2 are arranged in sequence, and the N-type carrier storage layer 10 is adjacent to the P-type first sub-base region 9-1 and the P-type second sub-base region 9-2 respectively.

[0068] In a specific implementation, when the N-type carrier storage layer 10 is located in the P-type base region 9, when the power device is in reverse breakdown, the N-type carrier storage layer 10 is isolated by the P-type first sub-base region 9-1 and the P-type second sub-base region 9-2. At this time, the expansion of the depletion layer will not be reduced, and the influence of the N-type carrier storage layer 10 on the breakdown characteristics of the power device can be eliminated. At the same time, the presence of the N-type carrier storage layer 10 can increase the concentration of hole carriers, enhance the conductivity modulation effect, and reduce the conduction voltage drop. In addition, by using the P-type second sub-base region 9-2 below the N-type carrier storage layer 10, the Miller capacitance and the gate collector charge can be effectively reduced, so that the power device has a faster speed when turning on and off.

[0069] In one embodiment of the present invention, any cellular groove includes a cellular main groove 17 and cellular auxiliary groove units symmetrically distributed on both sides of the cellular main groove 17, wherein:

[0070] The cellular auxiliary groove unit includes at least one cellular auxiliary groove;

[0071] A gate body 16 is filled in the cell column trench 17 , and the gate body 16 is insulated and isolated from the inner wall of the cell main trench 17 by the main trench oxide layer 15 covering the inner wall of the cell main trench 17 ;

[0072] Filling a source body in the cell auxiliary trench, wherein the source body is insulated and isolated from the inner wall of the cell auxiliary trench by an auxiliary trench oxide layer covering the inner wall of the cell auxiliary trench;

[0073] The gate body 16 is electrically connected to the gate metal, and the source bodies in all the cell auxiliary trenches are electrically connected to the source metal 13;

[0074] The N-type carrier storage layer 10 is at least distributed in the P-type base region 9 between the cell main trench 17 and the cell auxiliary trench adjacent to the cell main trench 17 .

[0075] In order to further significantly reduce the gate-collector capacitance Cgc and the gate-collector charge Qgc and improve the switching speed, any cell groove generally refers to the cell main groove 17 and the cell auxiliary groove units symmetrically distributed on both sides of the cell main groove 17. Each cell auxiliary groove unit includes at least one cell auxiliary groove. For example, when the cell auxiliary groove unit includes one cell auxiliary groove, there is a cell auxiliary groove on each side of the cell main groove 17. At this time, the cell groove includes three grooves in total. When the cell auxiliary groove unit includes other numbers of cell auxiliary grooves, please refer to the description here.

[0076] Combine the following Figure 1 , Figure 8 and Fig. 9 The distribution of the cell trenches and the N-type carrier storage layer 10 will be described in detail. Figure 1 and Figure 8 In the embodiment, two cellular auxiliary grooves are arranged in the cellular auxiliary groove unit. At this time, two cellular grooves are distributed on both sides of the cellular main groove 17. In the figure, the two cellular auxiliary grooves include a cellular first auxiliary groove 18 and a cellular second auxiliary groove 19. The cellular first auxiliary groove 18 is adjacent to the cellular main groove 17, and the cellular second auxiliary groove 19 is located outside the cellular first auxiliary groove 18. Fig. 9 In the example, three cellular auxiliary grooves are set in the cellular auxiliary groove. Figure 1 as well as Figure 8 In comparison, it also includes a third cellular auxiliary groove 8, which is located outside the second cellular auxiliary groove 19. When the number of cellular auxiliary grooves in the cellular auxiliary groove unit is other numbers, please refer to the drawings and the above description.

[0077] Generally, the cell main groove 17 and the cell auxiliary groove are both in the shape of long strips, and the length direction of the cell main groove 17 is parallel to the length of the cell auxiliary groove. In order to form a cell, a gate body 16 is arranged in the cell main groove 17. The gate body 16 can be a conductive polysilicon or a metal gate. The material used for the gate body 16 can be selected as needed to meet the actual application requirements. The gate body 16 is insulated and isolated from the inner wall of the cell main groove 17 by the main groove oxide layer 15 in the cell main groove 17. The main groove oxide layer 15 is generally a silicon dioxide layer. The gate body 16 is generally electrically connected to the gate metal. The gate electrode of the power device can be formed by the electrical connection between the gate metal and the gate body 16. At this time, the corresponding power device is generally a MOSFET type device; of course, when the power device is an IGBT type device, the gate electrode of the power device can be formed.

[0078] In one embodiment of the present invention, the source body is filled in the auxiliary trench of the cell, and the source body is insulated and isolated from the inner wall of the auxiliary trench of the cell through the auxiliary trench oxide layer. The source body and the auxiliary trench oxide layer can refer to the description of the gate body 16 and the main trench oxide layer 15, which will not be repeated here. Different from the main trench 17 of the cell, the source body is electrically connected to the source metal 13. At this time, it is known to those skilled in the art that the use of the cell can further effectively reduce the Miller capacitance Cgc and the gate collector charge Qgc, making the switching speed of the power device faster.

[0079] In one embodiment of the present invention, the N-type carrier storage layer 10 is also distributed in the P-type base region 9 between adjacent cell auxiliary trenches;

[0080] In the cross section of the trench type power device, an N+ source region 11 and a P+ source region 12 are provided on both sides of the cell main trench 17, wherein:

[0081] The N+ source region 11 and the P+ source region 12 are distributed in the P-type base region 9 between the cell main trench 17 and the cell auxiliary trench adjacent to the cell main trench 17, and the N+ source region 11 contacts the outer side wall of the cell main trench 17 and the outer side wall of the cell auxiliary trench adjacent to the cell main trench 17;

[0082] The P+ source region 12 is located below the N+ source region 11 , and the source metal 13 is in ohmic contact with both the N+ source region 11 and the P+ source region 12 .

[0083] For the above-mentioned cell, the N-type carrier storage layer 10 can be distributed at least in the P-type base region 9 between the cell main trench 17 and the cell auxiliary trench adjacent to the cell main trench 17. From the above description, it can be seen that the N-type carrier storage layer 10 can be distributed at least in the P-type base region 9 between the cell main trench 17 and the cell first auxiliary trench 18. Figure 1 , Figure 8 and Fig. 9 FIG. 4 shows an embodiment in which an N-type carrier storage layer 10 is disposed in each P-type base region 9 . The distribution position of the N-type carrier storage layer 10 can be selected according to needs.

[0084] In order to form a conductive channel, an N+ source region 11 is also required. Figure 1 , Figure 8 and Fig. 9 In the figure, the N+ source region 11 is distributed on the outside of the cell main trench 17, that is, the N+ source region 11 is located in the P-type base region 9 between the cell main trench 17 and the cell first auxiliary trench 18, and the N+ source region 11 needs to contact the outer wall of the cell main trench 17 adjacent to the cell first auxiliary trench 18, and the side wall of the cell first auxiliary trench 18 adjacent to the cell main trench 17.

[0085] In addition, a P+ source region 12 may be provided in the P-type base region 9 where the N+ source region 11 is provided. The doping concentration of the P+ source region 12 is generally greater than the doping concentration of the P-type base region 9. The P+ source region 12 is located below the N+ source region 11 and contacts the N+ source region 11. The source metal 13 is in ohmic contact through the N+ source region 11 and the P+ source region 12. At this time, the source electrode of a MOSFET type device or the emitter of an IGBT type device may be configured based on the source metal 13.

[0086] In an embodiment of the present invention, the P-type base region 9 between adjacent cell auxiliary trenches is configured to be in a floating state, or the P-type base region 9 is in ohmic contact with the source metal 13 .

[0087] Figure 1 , Figure 8 and Fig. 9 In the embodiment, the P-type base region 10 between the first auxiliary trench 18 of the cell and the second auxiliary trench 19 of the cell is configured to be in a floating state. The floating state means that there is no contact hole above the P-type base region 9, and the source metal 13 is not in ohmic contact with the P-type base region 10. At this time, the P-type base region 9 in a floating state can be used to effectively enhance the conductivity modulation and reduce the conduction voltage drop of the power device. In addition, when the P-type base region 9 is in ohmic contact with the source metal 13, it can be in the form of the above-mentioned source metal 13 contacting through the P+ source region 12, or in the form of the source metal 13 directly in ohmic contact with the P-type base region 13 through the contact hole. The contact form can be selected according to actual needs. Figure 1 , Figure 8 and Fig. 9 2 and 3 show an embodiment in which a P+ source region 12 is disposed in a P-type base region 9 , and a source metal 13 is in contact with the P+ source region 12 , thereby achieving an ohmic contact with the P-type base region 9 .

[0088] In one embodiment of the present invention, an N-type buried layer 5 is disposed under the cell main trench 17 and each cell auxiliary trench, wherein:

[0089] The N-type buried layer 5 covers the bottom of the corresponding cell main trench 17 or the cell auxiliary trench.

[0090] Specifically, the N-type buried layer 5 is located in the N-type drift region 4, and the N-type buried layer 5 corresponds one-to-one to the cell main trench 17 and the cell auxiliary trenches, that is, an N-type buried layer 5 is arranged under the bottom of the cell main trench 17 and the bottom of each cell auxiliary trench, and the doping concentration of the N-type buried layer 5 is greater than the doping concentration of the N-type drift region 4. The N-type buried layer 5 can block part of the hole carriers in the N-type drift region 5, further enhance the conductivity modulation, and reduce the on-state voltage drop.

[0091] The above-mentioned trench power device can be prepared by the following process steps. Specifically, the preparation method includes:

[0092] A semiconductor substrate having an N conductive type is provided, and a front cell process is performed on the front side of the semiconductor substrate, wherein:

[0093] When performing a front cell process on the front side of the semiconductor substrate, an active area is prepared in the central area of ​​the semiconductor substrate, wherein the active area includes a plurality of cells connected in parallel;

[0094] The cell in the active area adopts a groove structure, and the bottom of the cell groove is located below the P-type base region 9 that crosses the active area;

[0095] An N-type carrier storage layer 10 is disposed in the P-type base region 9 , and the N-type carrier storage layer 10 is in contact with the outer sidewall of the corresponding cell trench.

[0096] The semiconductor substrate and the preparation of the active area can refer to the above description. Figure 2 to Figure 8 The specific process steps of the front cell process of the present invention are described.

[0097] In one embodiment of the present invention, when a front cellular process is performed on the front side of a semiconductor substrate, the front cellular process includes:

[0098] Performing trench etching on the front side of the semiconductor substrate to prepare a cellular trench in the semiconductor substrate, wherein any cellular trench includes a cellular main trench 17 and cellular auxiliary trench units symmetrically distributed on both sides of the cellular main trench, and the cellular auxiliary trench unit includes at least one cellular auxiliary trench;

[0099] Performing a thermal oxidation process on the semiconductor substrate to obtain a main trench oxide layer 15 covering the inner wall of the cell main trench 17 and an auxiliary trench oxide layer covering the inner wall of the cell auxiliary trench;

[0100] Electrode material is deposited on the front side of the semiconductor substrate to obtain a gate body 16 filled in the cell main trench 17 and a source body filled in the cell auxiliary trench, wherein the gate body 16 is insulated and isolated from the inner wall of the cell main trench 17 by the main trench oxide layer 15 covering the inner wall of the cell main trench 17, and the source body is insulated and isolated from the inner wall of the cell auxiliary trench by the auxiliary trench oxide layer covering the inner wall of the cell auxiliary trench;

[0101] Performing impurity ion implantation on the front surface of the semiconductor substrate to prepare a P-type base region 9 that traverses the active region, an N-type carrier storage layer 10 distributed in the P-type base region 9, and an N+ source region 11 distributed on both sides of the cell main trench 17;

[0102] Metal deposition is performed on the front side of the semiconductor substrate to prepare source metal 13 and gate metal, wherein the gate metal is electrically connected to the gate body 16, the source metal 13 is electrically connected to all source bodies, and the source metal 13 is also in ohmic contact with the N+ source region 11 and at least the P-type base region 9 where the N+ source region 11 is located.

[0103] Figure 2 The semiconductor substrate includes an N-type drift region 4. Groove etching is performed on the surface of the N-type drift region 4 to obtain a cell groove. The cell groove can refer to the above description. Figure 2 In the figure, the cell includes a cell main groove 17, a cell first auxiliary groove 18 distributed on both sides of the cell main groove 17, and a cell second auxiliary groove 19 distributed on both sides of the cell main groove 17. Generally, the cell main groove 17 and the cell auxiliary groove are obtained by the same groove etching process, and the depth of the cell main groove 17 and the groove depth of the cell auxiliary groove are consistent.

[0104] Figure 3 In the process, after the cell trench is prepared, N-type impurity ions are implanted above the front surface of the semiconductor substrate to prepare an N-type buried layer 5, wherein:

[0105] The N-type buried layer 5 corresponds to the cell main trench 17 and all the cell auxiliary trenches one by one, and the N-type buried layer 5 covers the bottom of the corresponding cell main trench 17 or cell auxiliary trench.

[0106] Specifically, the correspondence between the N-type buried layer 5 and the cell main trench 17 and the cell auxiliary trench can refer to the above description. The N-type buried layer 5 can be prepared by using existing processes, and the specific process is based on whether the required N-type buried layer 5 can be prepared.

[0107] Figure 4 In the figure, a common oxidation process in the technical field is used to prepare a main trench oxide layer 15 covering the inner wall of the cell main trench 17, and the main trench oxide layer 15 covers the sidewalls and bottom wall of the cell main trench 17. At the same time, an auxiliary trench oxide layer is prepared in the cell auxiliary trench. In the figure, the auxiliary trench first oxide layer 6 is formed on the inner wall of the cell first auxiliary trench 18, and the auxiliary trench second oxide layer 21 is formed on the inner wall of the cell second auxiliary trench 19.

[0108] Figure 5 In the process, electrode material deposition is performed to prepare the gate body 16 and the source body. The electrode material can be conductive polysilicon or metal, and the form of the electrode material can be selected as needed. In the figure, the source body formed in the first auxiliary trench 18 of the cell is the auxiliary trench first source body 7; the source body formed in the second auxiliary trench 19 of the cell is the auxiliary trench second source body 20. The gate body 16, the auxiliary trench first source body 7 and the auxiliary trench second source body 20 can refer to the above description.

[0109] After the gate body 16 and the source body are prepared, impurity ions are implanted above the front surface of the N-type drift region 4 to prepare a P-type base region 9, an N-type carrier storage layer 10 distributed in the P-type base region 9, and an N+ source region 11 distributed on both sides of the cell main trench 17; in addition, a P+ source region 12 can also be prepared in the corresponding P-type base region 9, such as Figure 6 In the specific process, P-type impurity ion implantation can be performed first to prepare a P-type base region 9, and then an N-type carrier storage layer 10 is formed by configuring an ion implantation process. The N-type carrier storage layer 10 is distributed in the P-type base region 9. The distribution of the N-type carrier storage layer 10 in the P-type base region 9 can refer to the above description.

[0110] After the N-type carrier storage layer 10 is prepared, P-type impurity ion implantation may be performed again to prepare the P+ source region 12, and thereafter, N-type impurity ion implantation may be performed to form the N+ source region 11. Of course, during the specific implementation, the specific ion implantation sequence, ion implantation conditions and process may be selected as required, so as to prepare the required P-type base region 9, N-type carrier storage layer 10, N+ source region 11 and P+ source region 12.

[0111] After the N+ source region 12 is prepared, an insulating dielectric layer is deposited on the front side of the N-type drift region 4 to prepare an insulating dielectric layer 14. The insulating dielectric layer 14 can be made of existing commonly used insulating dielectric materials. The insulating dielectric layer 14 covers the front side of the N-type drift region 4 and can shield the notch of the cell groove.

[0112] In order to meet the electrical connection of the source metal 13, it is necessary to etch the insulating dielectric layer 14 to obtain the source contact hole. The distribution position and depth of the source contact hole can be selected according to needs to meet the electrical connection requirements of the source metal 13.

[0113] After the source contact hole is prepared, metal deposition is performed, and the metal covers the insulating dielectric layer 14. The metal generally includes a source metal 13 and a gate metal, such as Figure 7 As shown, in the figure, the gate metal is not shown, and the connection and distribution between the gate metal and the gate body 16 can be consistent with the existing ones. The source metal 13 covers the insulating dielectric layer 14 and fills the source contact hole. The source metal 13 filled in the source contact hole can be used to achieve electrical connection between the source metal 13 and the source body, and the source metal 13 is also in ohmic contact with the N+ source region 11 and at least the P-type base region 9 where the N+ source region 11 is located. The specific electrical connection and ohmic contact can refer to the above description.

[0114] Figure 2 to Figure 7 Shows Figure 1In the embodiment of the embodiment, an embodiment of the front cell process of the power device is used. Fig. 9 In the embodiment of the present invention, the difference between the two is that when preparing the cell groove, a cell third auxiliary groove 8 is simultaneously formed on the outside of the cell second auxiliary groove 19. Thereafter, an N-type buried layer 5 is arranged at the bottom of the cell third auxiliary groove 8, and an auxiliary groove third oxide layer 23 and an auxiliary groove third source body 22 are arranged in the cell third auxiliary groove 8. The specific process can be referred to the above description, and will not be listed one by one here.

[0115] After the semiconductor substrate is subjected to a front cell process, a back process is performed on the back of the semiconductor substrate to form a back structure after the back process, wherein:

[0116] Based on the formed back surface structure and active area, the trench power device is a MOSFET type device or an IGBT type device.

[0117] For MOSFET devices and IGBT devices, both can use the same active area, but their back side structures are different. Figure 1 , Figure 8 and Fig. 9 An embodiment of the back side structure when the power device is an IGBT type device is shown in the figure. In the figure, the back side structure includes an N-type buffer layer 3, a P+ collector region 2 arranged on the N-type buffer layer 3, and a collector metal 1 arranged on the P+ collector region 2. The collector metal 1 is in ohmic contact with the P+ collector region 2. Based on the collector metal 1, a collector of the IGBT type device can be formed.

[0118] For MOSFET type devices, the P+ collector region 2 can be directly omitted. In this case, Figure 1 , Figure 8 and Fig. 9 The collector metal 1 is in ohmic contact with the N-type buffer layer 3. Of course, the back structure can also be in other forms, which can be selected according to the actual application requirements.

[0119] In summary, the N-type carrier storage layer 10 is located in the P-type base region 9, and the P-type base region 9 is separated into the P-type first sub-base region 9-1 and the P-type second sub-base region 9-2. When the power device is in reverse breakdown, the N-type carrier storage layer 10 is isolated by the P-type base region 9, eliminating the influence of the N-type carrier storage layer 10 on the breakdown characteristics of the power device; the P-type second sub-base region 9-2 under the N-type carrier storage layer 10 can effectively reduce the Miller capacitance and the gate collector charge, so that the power device can be turned on and off faster.

[0120] The cell includes a cell main trench 17 and several cell auxiliary trenches. The source body in the cell auxiliary trench is electrically connected to the source metal 13. Based on the formed cell, the Miller capacitance Cgc and the gate collector charge Qgc can be effectively reduced, making the switching speed of the power device faster.

[0121] At the same time, part of the P-type base region 9 can be configured in a floating state, and the P-type base region 9 in a floating state can be used to effectively enhance the conductivity modulation and reduce the conduction voltage drop. By introducing an N-type buried layer 5 at the bottom of the cell trench, the N-type buried layer 5 can be used to block the hole carriers in the N-type drift region 4, enhance the conductivity modulation, and further reduce the conduction voltage drop.

Claims

1. A trench power device having improved breakdown characteristics, characterized in that: The trench power device comprises: A semiconductor substrate of a first conductivity type, wherein the semiconductor substrate includes a first conductivity type drift region; An active region, prepared in the central region of the semiconductor substrate, includes a plurality of cells connected in parallel, wherein the cells in the active region adopt a trench structure, and the bottom of the cell trench is located below the second conductive type base region that crosses the active region; Disposing a first conductivity type carrier storage layer in the second conductivity type base region, wherein the first conductivity type carrier storage layer is in contact with an outer side wall of a corresponding cell trench; For any cellular groove, it includes a cellular main groove and cellular auxiliary groove units symmetrically distributed on both sides of the cellular main groove, wherein: The cellular auxiliary groove unit includes at least one cellular auxiliary groove; Filling a gate body in the cell main trench, wherein the gate body is insulated and isolated from the inner wall of the cell main trench by a main trench oxide layer covering the inner wall of the cell main trench; Filling a source body in the cell auxiliary trench, wherein the source body is insulated and isolated from the inner wall of the cell auxiliary trench by an auxiliary trench oxide layer covering the inner wall of the cell auxiliary trench; The gate body is electrically connected to the gate metal, and the source bodies in all the cell auxiliary trenches are electrically connected to the source metal; The first conductive type carrier storage layer is at least distributed in the second conductive type base region between the cell main trench and the cell auxiliary trench adjacent to the cell main trench; A first conductive type buried layer is arranged under the cell main trench and each cell auxiliary trench, the first conductive type buried layer covers the bottom of the corresponding cell main trench and cell auxiliary trench, and the doping concentration of the first conductive type buried layer is greater than the doping concentration of the first conductive type drift region.

2. The trench power device with improved breakdown characteristics according to claim 1, characterized in that: The first conductive type carrier storage layer is also distributed in the second conductive type base region between adjacent cell auxiliary trenches; In the cross section of the trench power device, a first conductive type source region and a second conductive type source region are arranged on both sides of the cell main trench, wherein: The first conductive type source region and the second conductive type source region are distributed in the second conductive type base region between the cell main trench and the cell auxiliary trench adjacent to the cell main trench, and the first conductive type source region contacts the outer side wall of the cell main trench and the outer side wall of the cell auxiliary trench adjacent to the cell main trench; The second conductive type source region is located below the first conductive type source region, and the source metal is in ohmic contact with both the first conductive type source region and the second conductive type source region.

3. The trench power device with improved breakdown characteristics according to claim 1, characterized in that: For the second conductive type base region between adjacent cell auxiliary trenches, the second conductive type base region is configured to be in a floating state, or the second conductive type base region is in ohmic contact with the source metal.

4. The trench power device with improved breakdown characteristics according to claim 2, characterized in that: After the first conductive type carrier storage layer is disposed in the second conductive type base region, the second conductive type base region is divided into a second conductive type first sub-base region and a second conductive type second sub-base region, wherein: In the cross section of the power device, the depth of the second conductivity type first subbase region is the same as the depth of the second conductivity type second subbase region, and the depth of the first conductivity type carrier storage layer is less than the corresponding depths of the second conductivity type first subbase region and the second conductivity type second subbase region.

5. A method for preparing a trench power device with improved breakdown characteristics, characterized in that: A method for preparing a trench power device according to any one of claims 1 to 4, the method comprising: A semiconductor substrate having a first conductivity type is provided, the semiconductor substrate comprising a first conductivity type drift region, and a front cell process is performed on the front surface of the semiconductor substrate, wherein: When performing a front cell process on the front side of the semiconductor substrate, an active area is prepared in the central area of ​​the semiconductor substrate, wherein the active area includes a plurality of cells connected in parallel; The cell in the active area adopts a groove structure, and the bottom of the cell groove is located below the second conductive type base region that crosses the active area; Disposing a first conductivity type carrier storage layer in the second conductivity type base region, wherein the first conductivity type carrier storage layer is in contact with an outer side wall of a corresponding cell trench; The front cell process comprises: Performing trench etching on the front side of the semiconductor substrate to prepare a cellular trench in the semiconductor substrate, wherein any cellular trench includes a cellular main trench and cellular auxiliary trench units symmetrically distributed on both sides of the cellular main trench, and the cellular auxiliary trench unit includes at least one cellular auxiliary trench; Performing a thermal oxidation process on the semiconductor substrate to obtain a main trench oxide layer covering the inner wall of the main trench of the cell and an auxiliary trench oxide layer covering the inner wall of the auxiliary trench of the cell; Depositing electrode materials on the front side of the semiconductor substrate to obtain a gate body filled in the main trench of the cell and a source body filled in the auxiliary trench of the cell, wherein the gate body is insulated and isolated from the inner wall of the main trench of the cell where it is located by a main trench oxide layer covering the inner wall of the main trench of the cell, and the source body is insulated and isolated from the inner wall of the auxiliary trench of the cell where it is located by an auxiliary trench oxide layer covering the inner wall of the auxiliary trench of the cell; Performing impurity ion implantation on the front surface of the semiconductor substrate to prepare a second conductive type base region that traverses the active region and a first conductive type carrier storage layer distributed in the second conductive type base region; Metal deposition is performed on the front surface of the semiconductor substrate to prepare source metal and gate metal, wherein the gate metal is electrically connected to the gate body, and the source metal is electrically connected to all source bodies; after the cell trench is prepared, first conductive type impurity ion implantation is performed above the front surface of the semiconductor substrate to prepare a first conductive type buried layer, wherein, The first conductive type buried layer corresponds one-to-one to the cell main trench and all the cell auxiliary trenches, and the first conductive type buried layer covers the bottom of the corresponding cell main trench and cell auxiliary trench, and the doping concentration of the first conductive type buried layer is greater than the doping concentration of the first conductive type drift region.

6. The method for preparing a trench power device capable of improving breakdown characteristics according to claim 5, characterized in that: Impurity ion implantation is performed above the front side of the semiconductor substrate to prepare a first conductive type source region distributed on both sides of the cell main trench; the source metal is also in ohmic contact with the first conductive type source region and at least with the second conductive type base region where the first conductive type source region is located.

7. The method for preparing a trench power device with improved breakdown characteristics according to claim 5, wherein: After the semiconductor substrate is subjected to a front cell process, a back process is performed on the back of the semiconductor substrate to form a back structure after the back process, wherein: Based on the formed back surface structure and active area, the trench power device is a MOSFET type device or an IGBT type device.

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