P-Ga2O3 / n-Ga2O3 pn junction diode and preparation method thereof

Abstract

The invention discloses a p-Ga2O3 / n-Ga2O3pn junction diode and a preparation method thereof, and solves the problems that gallium oxide p-type doping is difficult, and a heterojunction diode is large in leakage current and low in withstand voltage. The gallium oxide homogeneous pn junction structure comprises cathode metal, a substrate and an n-type Ga2O3 epitaxial layer from bottom to top, a p-type NiO layer is arranged above the n-type Ga2O3 epitaxial layer, a p-type Ga2O3 material layer is arranged between the n-type Ga2O3 epitaxial layer and the p-type NiO layer, and a gallium oxide homogeneous pn junction is formed. The preparation method comprises the steps of epitaxial wafer cleaning, p-type Ga2O3 material layer preparation, cathode metal preparation, photoetching, p-type NiO film deposition, photoetching and anode metal preparation. N / P ion implantation is carried out on the upper portion of the gallium oxide epitaxial layer, Ga atoms in Ga2O3 are separated out and react again through high-temperature annealing to form the effective p-type characteristic, meanwhile, the effective p-type characteristic is combined with the p-type characteristic of p-type nickel oxide, p-type doping of gallium oxide is achieved through a simple process, the gallium oxide homogeneous pn junction is obtained, reliability is high, leakage current is small, and the gallium oxide homogeneous pn junction is suitable for large-scale production. The preparation method is used for preparing the p-Ga2O3 / n-Ga2O3pn junction diode with high voltage resistance.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and mainly relates to power switching devices, specifically a p-Ga2O3 / n-Ga2O3 pn junction diode. It can be used to prepare a high-voltage, low-leakage current switching diode, which has high efficiency, wide bandgap characteristics and excellent thermal stability, and is suitable for preparing normally-off gallium oxide devices, which are widely used in high-power electronic devices, high-frequency switching devices and high-temperature working environments. Technical Background

[0002] Gallium oxide (Ga2O3) has five crystal forms, among which β-Ga2O3 has become the focus of research due to its excellent thermal stability and ultra-large bandgap (4.4-4.9eV). β-Ga2O3 has an extremely high breakdown field strength (about 8MV / cm), far exceeding Si, SiC and GaN, and has excellent Baliga quality factor and high-frequency Baliga figure of merit, which makes it show great potential in high-frequency, high-voltage and high-power applications. However, although the theoretical value of on-resistance of β-Ga2O3 is low, which is conducive to improving device efficiency, its p-type doping is relatively difficult, mainly due to the influence of n-type background carriers, the lack of effective shallow energy level acceptor impurities and the passivation of acceptor impurity ions. At present, n-type doping of gallium oxide is relatively mature, and Si and Sn are commonly used as doping elements, while there are few reports on the research and application of p-type doping. In the absence of p-type gallium oxide, n-type gallium oxide devices have some limitations in switching performance, especially in high-voltage applications, where the performance of the device is easily affected by heat and electric fields, resulting in loss and instability.

[0003] In order to solve the above problems, in the existing technology, some researchers have used more effective dopants, such as zinc (Zn), magnesium (Mg) or manganese (Mn). These materials are easier to increase the carrier concentration in gallium oxide to form p-type conductivity. However, the selection and concentration of dopants need to be precisely controlled, and the optimization process is complicated, which may increase the manufacturing cost and difficulty. In addition, some relevant researchers have adopted thin film growth technology, metal organic chemical vapor deposition (MOCVD) and pulsed laser deposition (PLD) and other technologies to achieve uniform doping on high-quality substrates, ensuring that the doping elements can be effectively integrated into the gallium oxide crystal structure, thereby improving conductivity. However, this solution usually requires complex equipment and precise control, is costly, and may have a long manufacturing cycle.

[0004] At present, existing technologies face challenges in solving the difficulty of p-type doping of gallium oxide, such as unstable dopant activity and difficulty in accurately controlling doping concentration. In addition, the interface trap concentration of heterojunction diodes made by doping other p-type semiconductors is usually around 10 12 to 10 14 cm-2 eV -1 The interface trap density is high, which affects the device performance and stability. The complex process conditions also increase the production cost. Summary of the invention

[0005] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose a p-Ga2O3 / n-Ga2O3pn junction diode with high device withstand voltage and small leakage current and a preparation method, thereby realizing p-type doping of gallium oxide.

[0006] The invention discloses a p-Ga2O3 / n-Ga2O3 pn junction diode, which is provided with cathode metal, substrate, n-type β-Ga2O3 epitaxial layer, a p-type NiO thin film layer above the n-type β-Ga2O3 epitaxial layer, and an anode metal layer deposited above the p-type NiO thin film layer from bottom to top. The invention is characterized in that: N / P ions are implanted on the entire upper surface of the n-type β-Ga2O3 epitaxial layer and high-temperature annealing is performed under nitrogen, a p-type Ga2O3 material layer is generated between the n-type β-Ga2O3 epitaxial layer and the p-type NiO thin film layer, a homogeneous gallium oxide pn junction is formed between the p-type Ga2O3 material layer and the n-type β-Ga2O3 epitaxial layer; and the whole diode constitutes a p-type gallium oxide-n-type gallium oxide pn junction diode with high withstand voltage and low leakage current.

[0007] The present invention is also a method for preparing a p-Ga2O3 / n-Ga2O3 pn junction diode, which is implemented on any one of the p-Ga2O3 / n-Ga2O3 pn junction diodes in claims 1-5, characterized in that a p-type Ga2O3 material layer with a thickness of 400-600nm is formed by N / P ion implantation and high temperature annealing between an n-type β-Ga2O3 epitaxial layer and a p-type NiO thin film layer, comprising the following steps:

[0008] 1) Cleaning the epitaxial wafer: Select the epitaxial wafer and clean it in acetone solution and isopropanol solution respectively, ultrasonically clean it for 5min-10min respectively, and then ultrasonically clean it in deionized water for 5min, and then blow dry it with nitrogen to obtain the cleaned epitaxial wafer. The epitaxial wafer is the assembly of the substrate and the n-type β-Ga2O3 epitaxial layer in the present invention. In practical applications, it is a purchased independent component;

[0009] 2) Preparing a p-type Ga2O3 material layer on the n-type Ga2O3 epitaxial layer: N / P ions are implanted on the cleaned n-type epitaxial wafer, and then high-temperature annealing is performed in a nitrogen environment, and finally a p-type Ga2O3 material layer is formed on the surface above the n-type epitaxial wafer, and a homogeneous gallium oxide pn junction is formed between the p-type Ga2O3 material layer and the n-type epitaxial wafer;

[0010] 3) Preparation of cathode metal: Ti / Au with a thickness of 60nm / 120nm is deposited as cathode metal at the bottom of the epitaxial layer by electron beam evaporation E-Beam system, and then annealed in nitrogen at 470°C for 1min to form a good ohmic contact;

[0011] 4) Photolithography to form a NiO thin film area: Spin-coat a photoresist on the formed p-type Ga2O3 material layer 4 and perform photolithography using a photolithography machine to form an area to be deposited with a p-type NiO thin film, and perform a debonding process in a debonding machine using a 200W oxygen environment for 5 minutes;

[0012] 5) Depositing a p-type NiO film: using inductively coupled plasma chemical vapor deposition ICP-CVD, a NiO film with a thickness of 70nm-150nm is deposited in the area where the p-type NiO is to be deposited on the p-type Ga2O3 material layer 4;

[0013] 6) Photolithography to form anode metal area: Photolithography is performed again on the deposited NiO thin film layer 5, and the stripping process is performed in a 200W oxygen environment in a stripping machine for 5 minutes to expose the area where the anode metal needs to be deposited on the NiO thin film layer 5;

[0014] 7) Preparation of anode metal: Ni / Au with a thickness of 60nm / 120nm is deposited in the anode metal area by electron beam evaporation E-Beam system, and then the wafer after metal deposition is placed in a stripping solution to form anode metal 6 after stripping. The stripping treatment is carried out in a 200W oxygen environment in a degumming machine for 5 minutes, followed by an organic cleaning to complete the preparation process of the entire p-Ga2O3 / n-Ga2O3 pn junction diode.

[0015] The present invention solves the problems of high production cost, unstable dopant activity and difficulty in accurately controlling doping concentration caused by complex manufacturing processes in the prior art. At the same time, the designed and prepared p-Ga2O3 / n-Ga2O3 pn junction diode realizes p-type doping of gallium oxide, and the homojunction also greatly reduces the interface trap concentration, further reduces the leakage current of the device, and improves the thermal stability and voltage resistance of the device. It also solves certain problems in the stability of n-type gallium oxide under high current, high temperature and high pressure, especially in terms of the current-voltage characteristics and reverse recovery characteristics of the device. By introducing p-type gallium oxide, the present invention can achieve more efficient current regulation and enhanced diode characteristics, and is suitable for applications such as power electronics and radio frequency amplifiers. P-type gallium oxide can also enhance the current control performance of gallium oxide-based devices and provide more stable operating characteristics. In particular, under extreme working conditions, p-type gallium oxide can maintain good thermal stability and electrical properties.

[0016] The present invention has the following advantages:

[0017] Improve the device breakdown voltage, reduce the device leakage current, and improve the thermal stability of the device: the present invention realizes p-type doping of gallium oxide through ion implantation and high-temperature annealing, and introduces p-type NiO into n-type gallium oxide, thereby enhancing the overall carrier concentration of the device and forming a gallium oxide homogeneous pn junction, which effectively improves the device breakdown voltage and reduces the leakage current, thereby improving the device's withstand voltage and thermal stability. The present invention has great engineering application value in high-voltage power electronic devices.

[0018] The preparation process is relatively simple, and the obtained homogeneous pn junction interface trap concentration is low: the present invention performs N / P ion implantation and high-temperature annealing on the surface of the n-type β-Ga2O3 epitaxial layer, so that Ga atoms in Ga2O3 precipitate and react to form p-type conditions, and combines with the p-type characteristics of NiO to obtain a gallium oxide homogeneous pn junction with a relatively simple process, which greatly reduces the interface traps at the pn junction interface.

[0019] The deposited nickel oxide film has good uniformity, higher density and faster deposition speed: when depositing the NiO film, the present invention applies the inductively coupled plasma chemical vapor deposition ICP-CVD process, which can form a large-area, high-uniformity and high-electron-density plasma under low temperature and low pressure conditions, thereby quickly depositing a high-quality nickel oxide film with good uniformity and high density. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the structure of the p-Ga2O3 / n-Ga2O3 pn junction diode of the present invention;

[0021] Figure 2 A schematic diagram of the process flow for preparing a p-Ga2O3 / n-Ga2O3 pn junction diode according to the present invention;

[0022] Figure 3 It is a flowchart of the method for preparing a p-Ga2O3 / n-Ga2O3 pn junction diode of the present invention. DETAILED DESCRIPTION

[0023] The present invention is described in detail below with reference to the accompanying drawings.

[0024] Embodiment 1:

[0025] In situations where high voltage and high current need to be controlled and converted, a gallium oxide homogeneous pn junction diode with high voltage resistance and good thermal conductivity is required as a core component to meet the needs of the above scenarios. However, p-type doping of gallium oxide is currently difficult to manufacture, and the prior art mostly uses other p-type semiconductors instead of p-type gallium oxide to manufacture heterojunction diodes. However, due to the high interface traps at the interface of the currently manufactured heterojunction diodes, the heterojunction diodes manufactured by the prior art have low voltage resistance and large leakage current, and the thermal conductivity of the heterojunction is not as good as that of the homojunction. At the same time, the manufacturing process of the prior art is also relatively complicated and the production cost is high. To this end, the present invention proposes a p-Ga2O3 / n-Ga2O3 pn junction diode machine and a preparation method thereof after research and experiments.

[0026] The technical idea of ​​the present invention is: by performing N / P ion implantation on the gallium oxide epitaxial layer, after high-temperature annealing in a nitrogen environment, Ga atoms in Ga2O3 will precipitate and react to form p-type conditions. Then, by depositing high-concentration NiO on the gallium oxide epitaxial layer, N and P ion implantation can introduce energy levels. The formation of this defect state can be combined with the p-type characteristics of NiO to enhance the overall carrier concentration, thereby realizing the production of p-type Ga2O3. The overall gallium oxide homogeneous pn junction is formed, which increases the heat resistance and pressure resistance of the device and reduces the leakage current.

[0027] The present invention is a p-Ga2O3 / n-Ga2O3 pn junction diode. The structure of the p-Ga2O3 / n-Ga2O3 pn junction diode of the present invention comprises from bottom to top: a cathode metal 1, a substrate 2, an n-type β-Ga2O3 epitaxial layer 3, a p-type NiO thin film layer 5 is arranged above the n-type β-Ga2O3 epitaxial layer 3, and an anode metal 6 is deposited above the p-type NiO thin film layer 5. The cathode metal 1 is one pin of the heterojunction diode, and the anode metal 6 is another pin of the heterojunction diode. Figure 1 , Figure 1 The present invention is a schematic diagram of the p-Ga2O3 / n-Ga2O3 pn junction diode structure. The present invention performs ion implantation of N / P ions above the surface of the n-type β-Ga2O3 epitaxial layer 3, and performs high-temperature annealing under nitrogen. After ion implantation and high-temperature annealing, a p-type Ga2O3 material layer 4 is formed between the n-type β-Ga2O3 epitaxial layer 3 and the p-type NiO thin film layer 5, and a homogeneous pn junction is formed between the p-type Ga2O3 material layer 4 and the n-type β-Ga2O3 epitaxial layer 3, thereby achieving p-type doping of gallium oxide, optimizing interface quality and reducing interface trap density.

[0028] The present invention is an overall technical solution. The present invention improves the thermal stability and performance of the device by forming a homogeneous pn junction of gallium oxide, and forms a p-Ga2O3 / n-Ga2O3 pn junction diode as a whole. The present invention forms a p-type Ga2O3 material layer 4 by performing ion implantation of N / P ions above the inside of the n-type β-Ga2O3 epitaxial layer 3 and performing high-temperature annealing under nitrogen, thereby achieving p-type doping of gallium oxide and improving the withstand voltage and reliability. In addition, the material layer 4 formed by the present invention and the annealing process make the preparation method of the present invention relatively simple, low in production cost, and have good development and application prospects.

[0029] Embodiment 2:

[0030] The p-Ga2O3 / n-Ga2O3 pn junction diode is the same as in Example 1, and a p-type Ga2O3 material layer 4 is formed between the n-type β-Ga2O3 epitaxial layer 3 and the p-type NiO thin film layer 5, and the thickness of the p-type Ga2O3 material layer 4 is 400-600nm. The p-type Ga2O3 material layer 4 formed by the present invention has a lower interface trap density at the interface of the pn junction diode formed by other p-type semiconductor materials, so that the withstand voltage and heat resistance of the gallium oxide diode are better. The present invention not only realizes the p-type doping of gallium oxide, but also studies and discusses its thickness. In the present invention, the thickness of the p-type Ga2O3 material layer 4 can generally be controlled at 400-600nm, and the specific thickness can be 400nm, 500nm, 600nm, etc., and the size of its thickness is specifically determined by the annealing temperature and time.

[0031] If the annealing temperature is set to 800°C and the annealing time is set to 30s, the thickness of the p-type Ga2O3 material layer 4 formed can reach 400nm. If the annealing temperature is set to 1000°C and the annealing time is set to 10s, the thickness of the p-type Ga2O3 material layer 4 formed can reach 500nm. If the annealing temperature is 1200°C and the annealing time is set to 5s, the thickness of the p-type Ga2O3 material layer 4 formed can reach 600nm.

[0032] Higher annealing temperatures can usually enhance the activation of dopants, increase carrier concentration, and thus improve p-type characteristics. However, too high a temperature may cause phase change or material damage to gallium oxide, reducing its electrical properties. Longer annealing times can promote the diffusion and uniform distribution of dopants in the gallium oxide lattice, improving the doping effect. However, too long a time may lead to excessive diffusion, reduce the effective carrier concentration, and affect the p-type characteristics. Therefore, it is actually necessary to determine the most suitable annealing temperature and time based on experiments so that the p-type doping of gallium oxide can achieve the optimal effect. According to research and experiments, when the thickness is 500nm, that is, the annealing temperature is set to 1000°C and the annealing time is set to 10s, the p-type doping of gallium oxide can achieve a comprehensive optimal effect.

[0033] Embodiment 3:

[0034] The p-Ga2O3 / n-Ga2O3 pn junction diode is the same as in Example 1-2. In the present invention, a high-concentration p-type nickel oxide thin film layer 5 is deposited on the n-type β-Ga2O3 epitaxial layer 3, and the thickness of the p-type NiO thin film layer 5 is 70-150nm. The high-concentration p-type nickel oxide thin film layer 5 deposited by the present invention can increase the doping concentration and enhance the p-type conductive properties of the material. The present invention not only proposes to construct a p-type NiO thin film layer 5, but also studies and explores its thickness. In the present invention, this thickness can be controlled at 70-150nm, and the specific thickness can be 70nm, 100nm, 150nm, etc. When a device with high interface quality and low defects is required, a p-type NiO thin film layer 5 with a thickness of 70nm can be used. When the device requires a high-power device and high-temperature resistant application, a p-type NiO thin film layer 5 with a thickness of 100nm can be used. When the device has a balanced demand for doping concentration and interface quality, a p-type NiO thin film layer 5 with a thickness of 150nm can be used. An appropriate p-type NiO thin film layer 5 may be selected to make the device suitable for different application scenarios.

[0035] Embodiment 4:

[0036] The p-Ga2O3 / n-Ga2O3 pn junction diode is the same as in Examples 1-3. In the present invention, the substrate 2 may be an n-type Ga2O3 substrate, a SiO2 substrate, or a sapphire insulating substrate, that is, any one of them may be selected. The design of the substrate in the present invention is not just a single material. According to the application requirements of power devices in high frequency, high voltage or high power, three substrate materials are mainly selected, and the corresponding substrate materials can be selected according to different requirements. When the device is required to work in a higher voltage working environment, the substrate of the gallium oxide homogeneous pn diode can adopt an n-type Ga2O3 substrate with a thickness of 300um; when the device is used for high frequency applications, the substrate of the gallium oxide homogeneous pn diode can adopt a sapphire substrate with a thickness of 300um; when the device works in high power and high temperature application scenarios, the substrate of the gallium oxide homogeneous pn diode can adopt a SiO2 substrate with a thickness of 200um. The use of different substrate materials can make the application scenarios of the device more extensive.

[0037] Embodiment 5:

[0038] The p-Ga2O3 / n-Ga2O3 pn junction diode is the same as in Examples 1-4, and the cathode metal 1 of the present invention is a double-layer metal structure, wherein the lower layer is Au with a thickness of 120nm and the upper layer is Ti with a thickness of 60nm. If the device needs to work in high current and high power applications, the cathode metal 1 can adopt a double-layer metal structure with a lower layer thickness of 200nm Au and an upper layer thickness of 100nm Ti. If the gallium oxide homogeneous pn junction diode device is required to achieve lower on-resistance and lower parasitic capacitance, the cathode metal 1 adopts a double-layer metal structure with a lower layer thickness of 120nm Au and an upper layer thickness of 60nm Ti. The cathode metal of the present invention adopts a double-layer metal structure, and different metal layers can optimize the contact characteristics with the semiconductor, reduce contact resistance, and improve current transmission efficiency. The design of this double-layer metal structure can significantly improve the electrical performance, thermal performance and reliability of the device, is suitable for high-power and high-temperature application scenarios, and provides a new solution for the development of the next generation of high-efficiency electronic devices.

[0039] Embodiment 6:

[0040] The p-Ga2O3 / n-Ga2O3 pn junction diode is the same as in Examples 1-5, and the anode metal 6 of the present invention is a double-layer metal structure, wherein the lower layer is Ni with a thickness of 60nm and the upper layer is Au with a thickness of 120nm. In high current and high power applications, the anode metal 6 of the device can adopt a double-layer structure of Ni with a lower layer of 100nm and Au with an upper layer of 200nm. This design helps to enhance electrical conductivity and thermal management. If lower on-resistance and parasitic capacitance need to be achieved, the anode metal 6 can adopt a double-layer structure of Ni with a lower layer of 60nm and Au with an upper layer of 120nm. This is the preferred value obtained by the present invention, and the different thicknesses of the double-layer metal can actually be adjusted according to demand. Through this double-layer metal structure, different metal layers can optimize the contact characteristics with the semiconductor, significantly reduce the contact resistance, and improve the current transmission efficiency. This design significantly improves the electrical performance, thermal performance and reliability of the device, and is very suitable for high power and high temperature application scenarios. In addition, the double-layer metal structure exhibits better stability and oxidation resistance in a high temperature environment, thereby extending the service life of the device.

[0041] Embodiment 7:

[0042] The present invention also provides a method for preparing a p-Ga2O3 / n-Ga2O3 pn junction diode, which is to achieve the preparation of the above diode, see Figure 3 , Figure 3 The flowchart of the method for preparing a p-Ga2O3 / n-Ga2O3 pn junction diode of the present invention is as follows. The present invention performs ion implantation of N / P ions on the upper part of the n-type β-Ga2O3 epitaxial layer 3 and performs high temperature annealing under nitrogen to form a p-type Ga2O3 material layer 4 between the n-type β-Ga2O3 epitaxial layer 3 and the p-type NiO thin film layer 5. A homogeneous pn junction is formed between the p-type Ga2O3 material layer 4 and the n-type β-Ga2O3 epitaxial layer 3. Figure 2 , Figure 2 The schematic diagram of the process flow for preparing a p-Ga2O3 / n-Ga2O3 pn junction diode according to the present invention includes the following steps:

[0043] 1) Cleaning the epitaxial wafer: The present invention selects three substrates as epitaxial wafers for heterojunction diode applications. This example uses gallium oxide epitaxial wafers as examples. Gallium oxide epitaxial wafer 3 is selected and ultrasonically cleaned in acetone solution and isopropanol solution for 5 min to 10 min, then ultrasonically cleaned in deionized water for 5 min, and then dried with nitrogen. After drying, the cleaned gallium oxide epitaxial wafer is obtained. Figure 2 (a) Figure 2(a) is a cleaned epitaxial wafer. The epitaxial wafer is a combination of the substrate 2 and the n-type β-Ga2O3 epitaxial layer 3 in the present invention. In practical applications, it can be a purchased complete product. Organic pollutants, particles and metal ions on the surface of the epitaxial wafer are removed by cleaning. The clean surface helps to form a high-quality interface, reduce interface defects and trap density, and thus improve device performance.

[0044] 2) Preparing a p-type Ga2O3 material layer 4 on the n-type gallium oxide epitaxial layer: N / P ions are implanted on the cleaned n-type epitaxial wafer 3 to form a doping concentration of 5e19cm -3 , a highly doped region with a depth of 40nm-60nm, such as Figure 2 (b) Figure 2 (b) shows the process of N / P ion implantation. Then, in the N2 environment, the furnace annealing temperature is set to 800-1200°C, and high-temperature annealing is performed for 5s-20s. Finally, a p-type Ga2O3 material layer 4 with a thickness of 400nm-600nm is formed on the upper surface of the n-type epitaxial wafer 3, and a pn junction is formed between the p-type Ga2O3 material layer 4 and the n-type epitaxial wafer 3, as shown in FIG. Figure 2 (c) Figure 2 (c) shows a homogeneous pn junction of gallium oxide. The p-type Ga2O3 material layer 4 formed by the present invention realizes p-type doping of gallium oxide, and the interface trap density at the interface can be greatly reduced compared with the heterogeneous pn junction, thereby increasing the withstand voltage and heat resistance of the device.

[0045] 3) Preparation of cathode metal 1: The present invention deposits Ti / Au with a thickness of 60nm / 120nm as cathode metal 1 at the bottom of the epitaxial layer by electron beam evaporation E-Beam system, because the cathode metal is the pin for external contact, and then annealing in nitrogen at 470°C for 1min to form a good ohmic contact, such as Figure 2 (d) Figure 2 (d) shows the cathode metal that forms a good ohmic contact. The good ohmic contact of the present invention can provide low and stable resistance, reduce energy loss in current transmission, and improve the conductivity of the device.

[0046] 4) Photolithography to form NiO thin film area: Spin-coat photoresist on the formed p-type Ga2O3 material layer 4, then place the designed photolithography mask, and use a photolithography machine to perform photolithography to form an area to be deposited with p-type NiO thin film, such as Figure 2 (e) Figure 2(e) shows the area to be deposited with p-type NiO film formed by photoresist. The photoresist is removed in a 200W oxygen environment for 5 minutes in a photoresist stripping machine to remove the residual photoresist that has not been fully developed after photolithography. The clean surface after photoresist stripping ensures the smooth progress of subsequent deposition and other processing steps, improves the accuracy of depositing p-type NiO film, and the quality and reliability of the entire manufacturing process.

[0047] 5) Deposition of p-type NiO thin film: see Figure 2 (f) Figure 2 (f) shows the application of inductively coupled plasma chemical vapor deposition ICP-CVD to deposit a NiO film 5 with a thickness of 70nm-150nm on the area where p-type NiO is to be deposited on the p-type Ga2O3 material layer 4. The deposited nickel oxide film can more easily activate the activity of the dopant, enhance the p-type conductivity of the material, and promote the realization of p-type doping of gallium oxide.

[0048] 6) Photolithography to form anode metal area: Photolithography is performed again on the deposited NiO film layer 5, and the stripping process is performed in a 200W oxygen environment in a stripping machine for 5 minutes to expose the area where the anode metal needs to be deposited on the NiO film layer 5, see Figure 2 (g) Figure 2 (g) shows the photoresist-formed anode metal area to be deposited.

[0049] 7) Preparation of anode metal: Ni / Au with a thickness of 60nm / 120nm is deposited on the anode metal area by electron beam evaporation E-Beam system, and then the wafer after metal deposition is placed in a stripping solution, and anode metal 6 is formed after stripping. The stripping treatment is carried out in a 200W oxygen environment in a stripping machine for 5 minutes, and then an organic cleaning is performed, such as Figure 2 (h), Figure 2 (h) shows the gallium oxide homogeneous pn diode of the present invention. The good ohmic contact of the present invention can provide low and stable resistance, reduce energy loss in current transmission, improve the conductivity of the device, and complete the preparation process of the entire p-Ga2O3 / n-Ga2O3 pn junction diode.

[0050] After the N / P ion implantation, the present invention controls different annealing temperatures and annealing times during the high temperature annealing process, thereby generating p-type Ga2O3 material layers 4 of different thicknesses. This annealing time and temperature are very important, as they allow Ga atoms in Ga2O3 to precipitate and react to form p-type doping of gallium oxide, thereby achieving p-type doping of gallium oxide. The p-type Ga2O3 material layer 4 is formed by a relatively simple process to complete the p-type doping of gallium oxide. The preparation method of the present invention is relatively simple, and the process parameters are relatively easy to control, the production cost is low, and the yield is relatively high.

[0051] Embodiment 8:

[0052] The method for preparing a p-Ga2O3 / n-Ga2O3 pn junction diode according to claim 6 is characterized in that the thickness of the p-type Ga2O3 material layer in step 2) is specifically controlled by the following process conditions:

[0053] The doping concentration is 5e19cm by N / P ion implantation on the n-type epitaxial wafer. -3 , a highly doped region with a depth of 40nm-60nm, and then in a N2 environment, the annealing temperature in the furnace is set to 800-1200℃, and a high-temperature annealing is performed for 5s-20s, and finally a p-type Ga2O3 material layer with a thickness of 400nm-600nm is formed on the surface above the n-type epitaxial wafer.

[0054] The present invention forms p-type gallium oxide on the surface of n-type gallium oxide by ion implantation, and has many advantages such as precise doping control, lower process temperature, simple process, lower cost and reduced interface defects. This makes the technology particularly suitable for applications with high performance requirements for pn junctions or other surface electronic devices, such as high-power devices, radio frequency components, and electronic equipment in high-temperature environments.

[0055] Embodiment 9:

[0056] The p-Ga2O3 / n-Ga2O3 pn junction diode method according to claim 6, wherein in step 5, it is characterized in that the present invention uses low temperature deposition equipment ICP-CVD to deposit p-type NiO film, and the process conditions are as follows:

[0057] Reaction chamber pressure: 10mTorr;

[0058] Ionization voltage: 1.8-4.5KV;

[0059] Plasma ionization electrode: Ni;

[0060] Reaction chamber gases: O2, N2, Ar.

[0061] The present invention adopts low-temperature deposition equipment ICP-CVD to deposit p-type NiO film. Low-temperature deposition reduces thermal damage to substrate and other device materials. The plasma density and energy during the deposition process are controllable, which helps to obtain a uniform and dense film and improve the overall performance of the device.

[0062] The present invention uses an inductively coupled plasma chemical vapor deposition (ICP-CVD) process when depositing a NiO film, and can form a large-area, high-uniformity and high-electron-density plasma under low temperature and low pressure conditions, thereby quickly depositing a high-quality nickel oxide film with good uniformity and high density.

[0063] The p-Ga2O3 / n-Ga2O3 pn junction diode and preparation method of the present invention, wherein the gallium oxide homojunction diode structure can reduce the pn junction interface traps, improve the voltage resistance and thermal reliability of the device. At the same time, the process conditions of the preparation method are relatively simple and easy to control, and the process production cost is relatively low, and has good development and application prospects.

[0064] Embodiment 10:

[0065] The structure and preparation process of the p-Ga2O3 / n-Ga2O3 pn junction diode of the present invention are further described in detail below with reference to the accompanying drawings.

[0066] Reference Figure 1 The p-Ga2O3 / n-Ga2O3 pn junction diode of the present invention comprises: a cathode metal 1, a substrate 2, an n-type β-Ga2O3 epitaxial layer 3, a p-type Ga2O3 material layer 4, a p-type NiO layer 5, and an anode metal 6. Among them, the cathode metal 1 is located at the bottom of the device, and it uses Ti / Au with a thickness of 60nm / 120nm; the substrate 2 is located on the cathode metal 1, and it uses any one of a Ga2O3 substrate, a SiO2 substrate and a sapphire insulating substrate; the n-type β-Ga2O3 epitaxial layer 3 is on the substrate 2; the p-type NiO layer 5 is deposited above the n-type β-Ga2O3 epitaxial layer 3; the anode metal 6 is located at the upper part of the p-type NiO layer 5, and it uses Ni / Au with a thickness of 60nm / 120nm; the p-type Ga2O3 material layer 4 is located between the n-type β-Ga2O3 epitaxial layer 3 and the p-type NiO layer 5, and the material layer 4 and the n-type β-Ga2O3 epitaxial layer 3 constitute a gallium oxide homogeneous pn junction to form a normally-off gallium oxide device with a high withstand voltage.

[0067] Reference Figure 2 The present invention provides the following three more detailed implementation instructions for preparing p-Ga2O3 / n-Ga2O3 pn junction diodes:

[0068] 1. The present invention manufactures a p-Ga2O3 / n-Ga2O3 pn junction diode having an insulating substrate of 300um-thick gallium oxide, an n-type β-Ga2O3 film of 100um thickness and a p-type NiO film of 70nm thickness.

[0069] Cleaning epitaxial wafer: Figure 2 As shown in (a), a gallium oxide homoepitaxial wafer is selected and placed in acetone solution, isopropanol solution, and deionized water in turn for ultrasonic cleaning for 5 minutes each, and then blown dry with nitrogen.

[0070] N / P ion implantation and high temperature annealing to form a p-type Ga2O3 material layer: N / P ion implantation is performed on the cleaned n-type gallium oxide epitaxial wafer to form a doping concentration of 5e19cm-3 , a highly doped region with a depth of 40nm, such as Figure 2 (b);

[0071] Then, in a N2 environment, the furnace annealing temperature is set to 800°C, and high-temperature annealing is performed for 20 seconds. Finally, a p-type Ga2O3 material layer with a thickness of 400nm is formed on the upper surface of the n-type epitaxial wafer. Figure 2 (c).

[0072] Make cathode ohmic contact electrode: Figure 2 As shown in (d), at the bottom of the device substrate, Ti / Au with a thickness of 60nm / 120nm is deposited in the cathode area by an electron beam evaporation E-Beam system; then the device is placed in an annealing furnace, and the annealing temperature in the furnace is set to 480℃ in a N2 environment, and the annealing time is 1min to form a good ohmic contact.

[0073] Photolithography forms the area where the p-type NiO film is to be deposited: Figure 2 As shown in (e), photolithography is performed on the surface of the sample where the p-type Ga2O3 material layer is formed. A layer of photoresist is first applied, and then a series of specific photolithography processes such as alignment, exposure, development, and pattern detection are used to form the area where the p-type NiO film is to be deposited.

[0074] Deposition of p-type NiO film: Using inductively coupled plasma chemical vapor deposition ICP-CVD, a NiO film with a thickness of 70 nm is deposited in the area where p-type NiO is to be deposited on the p-type Ga2O3 material layer, such as Figure 2 (f).

[0075] Making a metal anode: Perform another photolithography on the deposited NiO layer to expose the area where the anode metal needs to be deposited on the NiO layer, such as Figure 2 (g);

[0076] Then, the device is deposited with Ni / Au with a thickness of 60nm / 120nm in the anode metal area through an electron beam evaporation E-Beam system, and the wafer after metal deposition is placed in a stripping solution to form an anode after stripping. Figure 2 (h); Use 200W oxygen environment to remove the glue in the degumming machine for 5 minutes, and then perform organic cleaning to complete the preparation process of the entire device.

[0077] 2. The present invention manufactures a p-Ga2O3 / n-Ga2O3 pn junction diode in which the insulating substrate is sapphire with a thickness of 300um, the n-type β-Ga2O3 film with a thickness of 200um and the p-type NiO film with a thickness of 100nm.

[0078] Cleaning the substrate:

[0079] 1.1) Transferring a 200um thick n-Ga2O3 film to a 300um thick sapphire insulating substrate;

[0080] 1.2) After the transfer, the sample was placed in acetone solution and isopropanol solution for ultrasonic cleaning for 8 minutes each, then rinsed with a large amount of deionized water and dried with nitrogen. Figure 2 (a) shown.

[0081] Preparation of p-type Ga2O3 material layer is:

[0082] 2.1) N / P ion implantation is performed on the cleaned n-type gallium oxide epitaxial wafer to form a doping concentration of 5e19cm -3 , a highly doped region with a depth of 50nm, such as Figure 2 (b);

[0083] 2.2) Then, in a N2 environment, the furnace annealing temperature is set to 1000°C, and high-temperature annealing is performed for 10 seconds. Finally, a p-type Ga2O3 material layer with a thickness of 500 nm is formed on the upper surface of the n-type epitaxial wafer. Figure 2 (c).

[0084] Make cathode ohmic contact electrode:

[0085] At the bottom of the device substrate, Ti / Au with a thickness of 60nm / 120nm is deposited in the cathode area by an electron beam evaporation E-Beam system; then the device is placed in an annealing furnace, and the annealing temperature in the furnace is set to 480℃ in a N2 environment, and the annealing time is 1min to form a good ohmic contact, such as Figure 2 (d).

[0086] Photolithography forms the area where p-type NiO film is to be deposited:

[0087] Photolithography is performed on the surface of the sample where the p-type Ga2O3 material layer is formed. A layer of photoresist is first applied, and then a series of specific photolithography processes such as alignment, exposure, development, and pattern detection are used to form the area where the p-type NiO film is to be deposited. Figure 2 (e).

[0088] Deposition of p-type NiO thin film:

[0089] A NiO film with a thickness of 100 nm is deposited on the p-type Ga2O3 material layer in the region where the p-type NiO is to be deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD). Figure 2 (f).

[0090] Making a metal anode:

[0091] 6.1) Perform another photolithography on the deposited NiO layer to expose the area where the anode metal needs to be deposited on the NiO layer, such as Figure 2 (g);

[0092] 6.2) Then, the device is subjected to an electron beam evaporation E-Beam system to deposit Ni / Au with a thickness of 60nm / 120nm in the anode metal region, and the wafer after metal deposition is placed in a stripping solution to form an anode after stripping. Figure 2 (h); Use 200W oxygen environment to remove the glue in the degumming machine for 5 minutes, and then perform organic cleaning to complete the preparation process of the entire device.

[0093] 3. The present invention manufactures a p-Ga2O3 / n-Ga2O3 pn junction diode having an insulating substrate of SiO2 with a thickness of 200 um, an n-type β-Ga2O3 film with a thickness of 200 um and a p-type NiO film with a thickness of 150 nm.

[0094] Cleaning samples:

[0095] First, a 200um thick n-Ga2O3 film was transferred onto a 300um thick SiO2 insulating substrate;

[0096] Then, the transferred sample was ultrasonically cleaned in acetone solution, isopropanol solution, and deionized water for 5 min each, and then dried with nitrogen. Figure 2 (a).

[0097] N / P ion implantation and high temperature annealing to form a p-type Ga2O3 material layer:

[0098] First, N / P ion implantation was performed on the cleaned n-type gallium oxide epitaxial wafer to form a doping concentration of 5e19cm -3 , a highly doped region with a depth of 60nm, such as Figure 2 (b);

[0099] Then, in a N2 environment, the furnace annealing temperature is set to 1200°C, and high-temperature annealing is performed for 5 seconds. Finally, a p-type Ga2O3 material layer with a thickness of 600nm is formed on the upper surface of the n-type epitaxial wafer. Figure 2 (c).

[0100] Make cathode ohmic contact electrode:

[0101] At the bottom of the device substrate, Ti / Au with a thickness of 60nm / 120nm is deposited in the cathode area by an electron beam evaporation E-Beam system; then the device is placed in an annealing furnace, and the annealing temperature in the furnace is set to 480℃ in a N2 environment, and the annealing time is 1min to form a good ohmic contact, such as Figure 2 (d).

[0102] Photolithography forms the area where p-type NiO film is to be deposited:

[0103] Photolithography is performed on the surface of the sample where the p-type Ga2O3 material layer is formed. A layer of photoresist is first applied, and then a series of specific photolithography processes such as alignment, exposure, development, and pattern detection are used to form the area where the p-type NiO film is to be deposited. Figure 2 (e).

[0104] Deposition of p-type NiO thin film:

[0105] A NiO film with a thickness of 150 nm is deposited on the p-type Ga2O3 material layer in the region where the p-type NiO is to be deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD). Figure 2 (f).

[0106] Making a metal anode:

[0107] First, photolithography is performed again on the deposited NiO layer to expose the area where the anode metal needs to be deposited on the NiO layer, such as Figure 2 (g);

[0108] Then, the device is deposited with Ni / Au with a thickness of 60nm / 120nm in the anode metal area through an electron beam evaporation E-Beam system, and the wafer after metal deposition is placed in a stripping solution to form an anode after stripping. Figure 2 (h); Use 200W oxygen environment to remove the glue in the degumming machine for 5 minutes, and then perform organic cleaning to complete the preparation process of the entire device.

[0109] In summary, the present invention provides a p-Ga2O3 / n-Ga2O3 pn junction diode and a preparation method thereof, which mainly solves the problem of difficulty in p-type doping of gallium oxide due to unstable dopant activity and difficulty in accurately controlling doping concentration, and also solves the problem of high production cost and difficulty in controlling the time and temperature of annealing process due to complex manufacturing process in the prior art. The gallium oxide homogeneous pn junction diode structure of the present invention includes from bottom to top: cathode metal, substrate, n-type Ga2O3 epitaxial layer, p-type NiO layer is arranged above the n-type Ga2O3 epitaxial layer, wherein a p-type Ga2O3 material layer is arranged between the n-type Ga2O3 epitaxial layer and the p-type NiO layer, and the layer and the n-type Ga2O3 epitaxial layer constitute a gallium oxide homogeneous pn junction, and the whole constitutes a p-Ga2O3 / n-Ga2O3 homogeneous pn junction diode.

[0110] The preparation method of the gallium oxide homogeneous pn junction diode of the present invention comprises the following steps: cleaning the epitaxial wafer, preparing a p-type Ga2O3 material layer, preparing a cathode metal, photolithographically forming a NiO film area, depositing a p-type NiO film, photolithographically forming an anode metal area, and preparing an anode metal.

[0111] The innovation of the gallium oxide homogeneous pn junction diode structure of the present invention is that a p-type Ga2O3 material layer is prepared on the n-type Ga2O3 epitaxial layer, and the p-type Ga2O3 material layer realizes p-type doping of gallium oxide, and the interface trap concentration at the homogeneous pn junction interface is lower, thereby increasing the voltage resistance and heat resistance of the gallium oxide diode.

[0112] The innovation of the preparation method of the p-Ga2O3 / n-Ga2O3 pn junction diode of the present invention lies in that when preparing the p-type Ga2O3 material layer, N / P ion implantation and high-temperature annealing are performed on the surface of the n-type β-Ga2O3 epitaxial layer to cause Ga atoms in the layer to precipitate and react to form p-type conditions, and a homogeneous pn junction of gallium oxide is obtained by a relatively simple process, which reduces the interface traps at the pn junction interface, thereby improving the reliability and withstand voltage of the device and reducing the leakage current. The method can be used to prepare a high-withstand voltage p-Ga2O3 / n-Ga2O3 pn junction diode.

[0113] The above are only embodiments of the present invention, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. Obviously, for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention, but these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A p-Ga2O3 / n-Ga2O3 pn junction diode, comprising, from bottom to top: a cathode metal, a substrate, an n-type β-Ga2O3 epitaxial layer, a p-type NiO thin film layer disposed above the n-type β-Ga2O3 epitaxial layer, and an anode metal layer deposited above the p-type NiO thin film layer, characterized in that: By performing ion implantation of N / P ions on the entire upper surface of the n-type β-Ga2O3 epitaxial layer and performing high-temperature annealing under nitrogen, a p-type Ga2O3 material layer is generated between the n-type β-Ga2O3 epitaxial layer and the p-type NiO thin film layer, and a homogeneous gallium oxide pn junction is formed between the p-type Ga2O3 material layer and the n-type β-Ga2O3 epitaxial layer; the whole constitutes a p-type gallium oxide-n-type gallium oxide pn junction diode with high withstand voltage and low leakage current.

2. The p-Ga2O3 / n-Ga2O3 pn junction diode according to claim 1, characterized in that: The thickness of the p-type Ga2O3 material layer formed between the n-type β-Ga2O3 epitaxial layer and the p-type NiO thin film layer is 400nm-600nm.

3. The p-Ga2O3 / n-Ga2O3 pn junction diode according to claim 1, characterized in that: The substrate may be an n-type Ga2O3 substrate, a SiO2 substrate, or a sapphire insulating substrate.

4. The p-Ga2O3 / n-Ga2O3 pn junction diode according to claim 1, characterized in that: The cathode metal is a double-layer metal structure, wherein the lower layer is Au with a thickness of 120 nm, and the upper layer is Ti with a thickness of 60 nm.

5. The p-Ga2O3 / n-Ga2O3 pn junction diode according to claim 1, characterized in that: The anode metal is a double-layer metal structure, wherein the lower layer is Ni with a thickness of 60 nm, and the upper layer is Au with a thickness of 120 nm.

6. A method for preparing a p-Ga2O3 / n-Ga2O3 pn junction diode, implemented on any one of the p-Ga2O3 / n-Ga2O3 pn junction diodes in claims 1-5, characterized in that: A p-type Ga2O3 material layer with a thickness of 400-600nm is formed between the n-type β-Ga2O3 epitaxial layer and the p-type NiO thin film layer by N / P ion implantation and high temperature annealing, including the following steps: 1) Cleaning the epitaxial wafer: Select the epitaxial wafer and clean it in acetone solution and isopropanol solution respectively, ultrasonically clean it for 5min-10min respectively, and then ultrasonically clean it in deionized water for 5min, and then blow dry it with nitrogen to obtain the cleaned epitaxial wafer. The epitaxial wafer is the assembly of the substrate and the n-type β-Ga2O3 epitaxial layer in the present invention. In practical applications, it is a purchased independent component; 2) Preparing a p-type Ga2O3 material layer on the n-type Ga2O3 epitaxial layer: N / P ions are implanted on the cleaned n-type epitaxial wafer, and then high-temperature annealing is performed in a nitrogen environment, and finally a p-type Ga2O3 material layer is formed on the surface above the n-type epitaxial wafer, and a homogeneous gallium oxide pn junction is formed between the p-type Ga2O3 material layer and the n-type epitaxial wafer; 3) Preparation of cathode metal: Ti / Au with a thickness of 60nm / 120nm is deposited as cathode metal at the bottom of the epitaxial layer by electron beam evaporation E-Beam system, and then annealed in nitrogen at 470°C for 1min to form a good ohmic contact; 4) Photolithography to form a NiO thin film area: Spin-coat a photoresist on the formed p-type Ga2O3 material layer 4 and perform photolithography using a photolithography machine to form an area to be deposited with a p-type NiO thin film, and perform a debonding process in a debonding machine using a 200W oxygen environment for 5 minutes; 5) Depositing a p-type NiO film: using inductively coupled plasma chemical vapor deposition ICP-CVD, a NiO film with a thickness of 70nm-120nm is deposited in the area where the p-type NiO is to be deposited on the p-type Ga2O3 material layer 4; 6) Photolithography to form anode metal area: Photolithography is performed again on the deposited NiO thin film layer 5, and the stripping process is performed in a 200W oxygen environment in a stripping machine for 5 minutes to expose the area where the anode metal needs to be deposited on the NiO thin film layer 5; 7) Preparation of anode metal: Ni / Au with a thickness of 60nm / 120nm is deposited in the anode metal area by electron beam evaporation E-Beam system, and then the wafer after metal deposition is placed in a stripping solution to form anode metal 6 after stripping. The stripping treatment is carried out in a 200W oxygen environment in a degumming machine for 5 minutes, followed by an organic cleaning to complete the preparation process of the entire p-Ga2O3 / n-Ga2O3 pn junction diode.

7. The method for preparing a p-Ga2O3 / n-Ga2O3 pn junction diode according to claim 6, characterized in that: The thickness of the p-type Ga2O3 material layer described in step 2) is specifically controlled by the following process conditions: The doping concentration is 5e19cm by N / P ion implantation on the n-type epitaxial wafer. -3 , a highly doped region with a depth of 40nm-60nm, and then in a N2 environment, the annealing temperature in the furnace is set to 800-1200℃, and a high-temperature annealing is performed for 5s-20s, and finally a p-type Ga2O3 material layer with a thickness of 400nm-600nm is formed on the surface above the n-type epitaxial wafer.

8. The method for preparing a p-Ga2O3 / n-Ga2O3 pn junction diode according to claim 6, characterized in that: The p-type NiO film deposited in step 5) is specifically deposited by using a low temperature deposition device ICP-CVD to deposit the p-type NiO film, and the process conditions are as follows: Reaction chamber pressure: 10mTorr; Ionization voltage: 1.8-4.5KV; Plasma ionization electrode: Ni; Reaction chamber gases: O2, N2, Ar.

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