Field-effect transistor devices, their fabrication methods and power devices

Abstract

This invention provides a field-effect transistor (FET), its fabrication method, and a power device thereof. The FET includes a substrate, a functional body, a gate dielectric, and a gate. The functional body includes a drift epitaxial region, a channel region, a source region, a first shielding region, and a second shielding region. Multiple gate trenches with their openings located on the surface away from the substrate are formed within the functional body. Each gate trench contains a gate and a gate dielectric. The channel region contacts the gate dielectric in one of the gate trenches and has a channel. The first shielding region is located between the channel region and another gate trench, and it contacts the gate dielectric in the other gate trench. The second shielding region is located below the gate trench and is connected to the first shielding region. The first and second shielding regions can significantly reduce the on-resistance of the device and increase its breakdown voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a field-effect transistor device, its fabrication method, and a power device thereof. Background Technology

[0002] Silicon carbide (SiC) is a wide-bandgap semiconductor material with advantages such as high breakdown electric field strength, good thermal stability, and high carrier saturation drift velocity, making it advantageous for applications in high-voltage and high-current devices. Power semiconductor devices made using wide-bandgap semiconductor materials are commonly used in high-voltage, high-current, and high-temperature operating environments, and are gradually replacing traditional silicon (Si) materials in the field of power electronics.

[0003] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used semiconductor power devices. MOSFETs have either a lateral or vertical structure. In a lateral MOSFET, the electrodes (source and drain) are located on the same surface of the device. In a vertical MOSFET, the electrodes are located on opposite surfaces of the device. Vertical MOSFETs have lower on-resistance because they lack a junction field-effect transistor (JFET).

[0004] Traditional trench MOSFET devices typically have a drift epitaxial region, a base region, and a source region in their epitaxial layer. The doping type of the base region differs from that of the drift epitaxial region and the source region. Under a suitable gate bias, a conductive channel connecting the drift epitaxial region and the source region is formed in the base region. For example... Figure 1 The illustrated trench MOSFET device includes a substrate 110, a drift epitaxial region 120 disposed on the substrate 110, a base region 130 disposed on the drift epitaxial region 120, a source region 140 disposed on the base region 130, and a gate trench 150 extending through the source region 140, the base region 130, and into the drift epitaxial region 120. A gate dielectric 151 and a gate 152 are disposed in the gate trench 150. A source electrode 160 is electrically connected to the source region 140, and a gate insulating layer 153 is disposed on the gate 152, separating the gate 152 and the source electrode 160. A drain electrode 170 is also electrically connected to the surface of the substrate 110 away from the drift epitaxial region 120. The operation of this device can be described as follows: when the device is in a blocking state, there are almost no electrons in the base region 130, and electrons cannot flow from the source region 140 to the drift epitaxial region 120. Typically, the drift epitaxial region 120 and source region 140 are n-type doped while the base region 130 is p-type doped, so there are no electrons in the channel during blocking. When a voltage greater than the threshold is applied to the gate 132, a layer with a high electron concentration is formed in the base region 130 near the interface of the gate dielectric 151, called the inversion channel, at which point the source region 140 and the drift epitaxial region 120 can be connected.

[0005] However, the main problem with the aforementioned trench MOSFET device with an inverting channel is the high interface state density between the base region 130 and the gate dielectric 151, resulting in a high on-resistance. Simultaneously, the bottom of the gate dielectric 151 is subjected to a very high electric field and can break down, leading to a low breakdown voltage achievable by the device. Summary of the Invention

[0006] Therefore, it is necessary to provide a field-effect transistor device that reduces the on-resistance of the device while protecting the gate dielectric.

[0007] According to one embodiment of the present invention, a field-effect transistor device includes a substrate, a functional body, a gate dielectric, and a gate.

[0008] The functional body includes a drift epitaxial region, a channel region, a source region, a first shielding region, and a second shielding region. The drift epitaxial region is stacked on the substrate, and the channel region and the source region are stacked sequentially on the surface of the drift epitaxial region away from the substrate. The substrate, the drift epitaxial region, the channel region, and the source region have a first conductivity type, and the first shielding region and the second shielding region have a second conductivity type opposite to the first conductivity type.

[0009] The functional body includes multiple gate trenches with the openings located on the side surface away from the substrate. Each gate trench contains the gate and the gate dielectric. The first shielding region, the source region, and the channel region are located between adjacent gate trenches. The channel region contacts the gate dielectric in one of the gate trenches and has a channel. The first shielding region is located between the channel region and another gate trench and contacts the gate dielectric. The second shielding region is located below the gate trench and is connected to the first shielding region.

[0010] In one embodiment, the sidewalls of each of the gate trenches along the arrangement direction of the plurality of gate trenches include opposing first sidewalls and second sidewalls, the first shielding region being located in the first sidewall, and the source region and the channel region being located in the second sidewall.

[0011] In one embodiment, the first sidewall is formed by the first shielding area.

[0012] In one embodiment, the second sidewall is formed by the source region and the channel region.

[0013] In one embodiment, a drift layer, a current spreading layer, and a current limiting layer are sequentially stacked in the integral formed by the drift epitaxial region and the channel region. The interface between the drift layer and the current spreading layer is located below the bottom of the gate trench, and the interface between the current spreading layer and the current limiting layer is flush with or above the bottom of the gate trench. The doping concentration of the current limiting layer is lower than that of the drift layer.

[0014] In one embodiment, the doping concentration of the current spreading layer is higher than that of the drift layer.

[0015] In one embodiment, the spacing between adjacent gate trenches is ≤1 μm.

[0016] In one embodiment, the spacing between adjacent gate trenches is 0.3 μm to 1 μm.

[0017] In one embodiment, the substrate of the functional body is silicon carbide.

[0018] In one embodiment, the thickness of the substrate is 100 μm to 500 μm, and / or

[0019] The thickness of the drift epitaxial region is 5 μm to 100 μm.

[0020] Correspondingly, a method for fabricating a field-effect transistor device in any of the above embodiments includes the following steps: epitaxially growing a functional body including the drift epitaxial region, the channel region, and the source region on the substrate; etching the functional body to form a gate trench, the gate trench penetrating the source region and extending to the bottom of the channel region; performing ion implantation on the sidewalls and bottom wall of the gate trench to form the first shielding region and the second shielding region; and forming the gate dielectric and the gate.

[0021] In one embodiment, during ion implantation into the sidewalls and bottomwalls of the gate trench, an inclined ion implantation method is used to simultaneously form the first shielding region and the second shielding region.

[0022] Furthermore, a power device includes a first external electrode, a second external electrode, and a field-effect transistor device according to any of the above embodiments, wherein the first external electrode is electrically connected to the source of the field-effect transistor device, and the second external electrode is electrically connected to the drain of the field-effect transistor.

[0023] The field-effect transistor device of the present invention has the following beneficial effects.

[0024] The channel region is in contact with the gate dielectric of one of the gate trenches, and a conductive channel can be formed at the interface near the gate dielectric in the channel region. Under the combined action of the gate and the first shielding region located on both sides of the channel, the carriers in the channel between adjacent gate trenches can be exhausted without a gate bias voltage, closing the channel and thus turning off the device. When the voltage applied to the gate is above the threshold voltage, carriers accumulate at the interface between the gate dielectric and the channel region, forming a conductive accumulation channel, thus turning on the device. This makes the field-effect transistor a normally closed device, and the distance between the gate trenches can be flexibly adjusted within a large range while ensuring the device is normally closed. Compared to devices with inverting channels, this device can significantly reduce the on-resistance because it lacks a base region. Simultaneously, the first and second shielding regions can shield the high electric field at the bottom of the gate dielectric, improving the breakdown voltage of the device. The connected first and second shielding regions can be formed simultaneously, effectively simplifying the fabrication process. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the cross-sectional structure of a trench MOSFET device;

[0026] Figure 2 This is a schematic diagram of the cross-sectional structure of a field-effect transistor device according to the present invention;

[0027] Figure 3 for Figure 2 A schematic diagram of a cross-sectional structure of a specific example of a field-effect transistor device. Detailed Implementation

[0028] To facilitate understanding of the present invention, a more comprehensive description is provided below. Preferred embodiments of the invention are shown herein. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. The term “more” as used herein includes two or more items. The term “above a certain number” as used herein should be understood as a number and a range greater than a certain number.

[0030] like Figure 1A major problem with the trench MOSFET device shown is the high interface state density between the base region 130 and the gate dielectric 131, resulting in a large on-resistance. To overcome this problem of high on-resistance in the trench MOSFET device, this invention proposes a field-effect transistor device that does not use a p-type base region as a channel.

[0031] According to an embodiment of the present invention, a field-effect transistor device includes a substrate, a functional body, a gate dielectric, and a gate; the functional body includes a drift epitaxial region, a channel region, a source region, a first shielding region, and a second shielding region corresponding to the first shielding region; the drift epitaxial region is stacked on the substrate, and the channel region and the source region are sequentially stacked on the surface of the drift epitaxial region away from the substrate; the substrate, the drift epitaxial region, the channel region, and the source region have a first conductivity type, and the first shielding region and the second shielding region have a second conductivity type opposite to the first conductivity type.

[0032] The functional body includes multiple gate trenches with the openings located on the side surface away from the substrate. Each gate trench contains the gate and the gate dielectric. The first shielding region, the source region, and the channel region are located between adjacent gate trenches. The channel region contacts the gate dielectric in one of the gate trenches and has a channel. The first shielding region is located between the channel region and another gate trench and contacts the gate dielectric in the other gate trench. The second shielding region is located below the gate trench and is connected to the first shielding region.

[0033] While some techniques propose channel depletion by utilizing the work function difference between the gate and channel regions, achieving depletion typically requires a spacing of less than 0.2 μm between adjacent gate trenches, which is difficult to achieve with current process conditions. Other techniques propose placing heavily doped base regions embedded from the source region between adjacent gate trenches to deplete the channel; however, the limited ion implantation depth in actual fabrication makes the process difficult and often hinders effective channel depletion.

[0034] It is understood that the channel region is in contact with the gate dielectric of one of the gate trenches, and a channel can be formed in the channel region near the gate dielectric. The first and second shielding regions, having a second conductivity type, can be formed simultaneously via ion implantation. The first shielding regions located on both sides of the channel and the gate work together to deplete the carriers in the channel region between adjacent gate trenches without applying a gate bias voltage, thereby turning off the channel and the device, making the field-effect transistor device a normally closed device. Specifically, this field-effect transistor device has a channel of the first conductivity type, and the carriers in the channel are mainly depleted by the first shielding region and the gate, thereby turning off the device. The introduced first shielding region allows the distance between the gate trenches to be flexibly adjusted within a large range. When the voltage applied to the gate is above the threshold voltage, carriers accumulate in the channel, forming a conductive accumulation channel, thereby turning on the device. Compared to devices with inverting channels, this device can significantly reduce the on-resistance of the device because it lacks a base region. Therefore, this field-effect transistor device is a normally closed device with an accumulation channel. Meanwhile, the first and second shielding regions can shield the high electric field at the bottom of the gate dielectric, thereby improving the breakdown voltage of the device.

[0035] Understandably, the gate can be a semiconductor of the second conductivity type, such as polysilicon of the second conductivity type.

[0036] Please refer to Figure 2 The diagram shown is a cross-sectional view of a field-effect transistor (FET) device 200, representing a specific implementation of the aforementioned FET device. The FET device 200 includes a substrate 210 and a functional body. The functional body includes a drift epitaxial region 221, a channel region 222, a source region 230, multiple first shielding regions 241, and multiple second shielding regions 242. The substrate 210, drift epitaxial region 221, channel region 222, and source region 230 have a first conductivity type, while the first shielding regions 241 and second shielding regions 242 have a second conductivity type opposite to the first conductivity type. The drift epitaxial region 221 is stacked on the substrate 210, the channel region 222 is stacked on the drift epitaxial region 221, and the source region 230 is stacked on the channel region 222. The functional body has multiple gate trenches with openings located on the surface away from the substrate 210, and each gate trench contains a gate 252 and a gate dielectric 251. The first shielding region 241, the source region 230, and the channel region 222 are disposed between adjacent gate trenches, with the channel region 222 contacting one of the gate trenches (e.g., Figure 2 The gate dielectric 251 in the gate trench (left side) has a channel in the channel region 222, which is formed close to the gate dielectric 251. Further, the bottom of the channel region 222 is flush with the bottom of the gate trench. The first shielding region 241 is located between the channel region 222 and another gate trench (e.g., the left side). Figure 2The first shielding region 241 is located between the gate trenches on the right side of the gate trench, and the first shielding region 241 contacts the gate dielectric 251 in another gate trench. The second shielding region 242 is located below the gate trench and is connected to the first shielding region 241.

[0037] The gate dielectric 251 is disposed in conjunction with the trench wall of the gate trench to insulate the gate 252 from the trench wall. The field-effect transistor device 200 also includes a source 260 electrically connected to the source region 230, a gate insulating layer 253 insulating the source 260 from the gate 252, and a drain 270 electrically connected to the substrate 210.

[0038] Doping intrinsic semiconductors yields doped semiconductors. Based on the different doping atoms, doped semiconductors can be classified into N-type and P-type semiconductors. In N-type semiconductors, the electron concentration is much higher than the hole concentration, therefore, electron conduction is predominant. In P-type semiconductors, the hole concentration is much higher than the electron concentration, therefore, hole conduction is predominant. It can be understood that a semiconductor has a first conductivity type, corresponding to a first doping type; a semiconductor has a second conductivity type, corresponding to a second doping type. In the above embodiments, the first conductivity type can be selected from electron conduction, and the second conductivity type can be selected from hole conduction; correspondingly, the region with the first conductivity type is N-type doped, and the region with the second conductivity type is P-type doped.

[0039] In one specific example, such as Figure 2 The substrate 210 may be a silicon carbide semiconductor substrate. The substrate 210 may be N-type doped, and the N-type doped impurity atoms may include, for example, nitrogen or phosphorus. The substrate 210 may have a resistivity of 0.02 ± 0.01 Ω·cm.

[0040] The substrate 210 can have any suitable thickness; in one specific example, the thickness of the substrate 210 is 100 μm to 500 μm. Further, the thickness of the substrate 210 can be selected from 200 μm to 400 μm.

[0041] In one specific example, the functional entity can be fabricated on substrate 210 via epitaxial growth. Specifically, a silicon carbide drift epitaxial region 221 can be epitaxially grown on silicon carbide substrate 210. In one specific example, the thickness of the drift epitaxial region 221 can be selected from 5 μm to 100 μm. Further, the thickness of the drift epitaxial region 221 is selected from 10 μm to 80 μm.

[0042] In one specific example, the doping concentration of the drift epitaxial region 221 is lower than that of the substrate 210. Specifically, the drift epitaxial region 221 may have, for example, a doping concentration of 1 × 10⁻⁶. 15~1×10 18 / cm 3 The doping concentration between [variable values]. The doping concentration of channel region 222 can also be, for example, 1 × 10 [units]. 15 ~1×10 18 / cm 3 The doping concentration between them.

[0043] In one specific example, source region 230 may have, for example, 1×10 18 ~1×10 21 / cm 3 The doping concentration between the two. Specifically, the source region 230 can be formed at the top end of the drift epitaxial region 221 via ion implantation.

[0044] In one specific example, along the arrangement direction of the plurality of gate trenches, the gate trenches have opposing first and second sidewalls, a first shielding region 241 is located in the first sidewall, and the source region 230 and the channel region 222 are disposed in the second sidewall. For example Figure 2 As shown, the left sidewall of the gate trench is the first sidewall, and the right sidewall of the gate trench is the second sidewall.

[0045] In one specific example, the second shielding region 242 contacts a portion of the gate dielectric 251 at the bottom of the gate trench, while another portion of the gate dielectric 251 at the bottom of the gate trench also contacts the drift epitaxial region 221.

[0046] In one specific example, adjacent gate trenches are spaced apart by a first sidewall of one gate trench and a second sidewall of another gate trench. Further, the first sidewall is formed by a first shielding region, and the second sidewall is formed by a source region 230 and a channel region 222.

[0047] In one specific example, the first shielding region 241 may have, for example, 1×10 17 ~1×10 19 / cm 3 The doping concentration between them.

[0048] In one specific example, the second shielding region 242 may have, for example, 1×10 17 ~1×10 19 / cm 3 The doping concentrations are between [specific values]. Furthermore, the doping concentrations of the first shielding region 241 and the second shielding region 242 are the same.

[0049] In this first field-effect transistor device 200, when no gate bias is applied, the carriers in the channel region 222 between adjacent gate trenches are depleted, thereby turning off the channel and the device, making the field-effect transistor device a normally closed device. Carrier depletion refers to the depletion of mobile carriers in the channel next to the gate dielectric 251, resulting in the closing of the conductive channel and the device being off. When the voltage applied to the gate 252 exceeds the threshold voltage, an accumulation-type conductive channel dominated by majority carriers is formed at the interface between the gate dielectric 251 and the channel region 222, causing the device to turn on.

[0050] The channel region 222 between adjacent gate trenches is depleted through the first shielding region 241 and the gate 252. To ensure the depletion of the channel region 222, in one specific example, the distance between adjacent gate trenches should not be too large, otherwise there may be cases where depletion is not achieved. For example, the spacing between adjacent gate trenches is ≤1μm. Further, considering the process accuracy issues in the actual fabrication process, the spacing between adjacent gate trenches can be set to be larger, for example, between 0.3μm and 1μm. Optionally, the spacing between adjacent gate trenches is 0.3μm, 0.5μm, 0.7μm, 0.9μm, or 1μm.

[0051] Furthermore, corresponding to the distance limitation between adjacent gate trenches, the width of the first shielding region 241 should not be too large, otherwise it will still lead to the formation of an inversion channel in conventional technology. In some specific examples, the width of the first shielding region 241 can be set to ≤0.5μm, optionally, the width of the first shielding region 241 can be set to ≤0.3μm, and further, the width of the first shielding region 241 can be set to ≤0.1μm.

[0052] In one specific example, although the depth of the second shielding region 242 can be selected from other doping depths, considering the synchronicity with the actual fabrication process of the first shielding region 241, the depth of the second shielding region 242 can be ≤1μm. Further, the depth of the second shielding region 242 can be ≤0.5μm.

[0053] The first shielding region 241 and the second shielding region 242, having a second conductivity type, can be formed simultaneously via ion implantation. The first shielding region 241 depletes the charge carriers in the channel region 222 between adjacent gate trenches, making the field-effect transistor a normally closed device and allowing for flexible adjustment of the distance between the gate trenches over a wide range. When the voltage applied to the gate 252 exceeds the threshold voltage, charge carriers accumulate at the interface of the channel region 222 near the gate dielectric 251, forming an accumulation channel. Compared to an inverting channel, this significantly reduces the on-resistance of the device due to the absence of a base region. Simultaneously, the first shielding region 241 and the second shielding region 242 shield the high electric field at the bottom of the gate dielectric 251, improving the breakdown voltage of the device.

[0054] Figure 3 It shows Figure 2 A further preferred structural schematic diagram of the field-effect transistor device 200. This field-effect transistor device... Figure 2 Based on the structure shown, Figure 2 The overall structure consisting of the drift epitaxial region 221 and the channel region 222 has been further designed. Specifically, the overall structure consisting of the drift epitaxial region 221 and the channel region 222 includes a drift layer 2201, a current spreading layer 2202, and a current limiting layer 2203 stacked sequentially. The interface between the drift layer 2201 and the current spreading layer 2202 is located below the gate trench, and the interface between the current spreading layer 2202 and the current limiting layer 2203 is flush with the bottom of the gate trench or located above the bottom of the gate trench. Figure 3 The diagram shows the interface between the current spreading layer 2202 and the current confinement layer 2203 being flush with the bottom of the gate trench. In this case, the current confinement layer 2203 can be understood as the channel region 222. The doping concentration of the current confinement layer 2203 is lower than that of the drift layer 2201. The lower the doping concentration of the current confinement layer 2203, the larger the spacing between the gate trenches can be, resulting in lower leakage current in the blocked state.

[0055] In one specific example, the doping concentration of the current spreading layer 2202 is higher than that of the drift layer 2201. In this case, the current spreading layer 2202 can be used to reduce the on-resistance of the device.

[0056] Specifically, the current spreading layer 2202 may have, for example, 2×10 15 ~1×10 18 / cm 3 The doping concentration between [variable values]. The current confinement layer 2203 can have, for example, a doping concentration of 1 × 10 [units]. 15 ~9×10 17 / cm 3 The doping concentration between these values. Drift layer 2201 can have, for example, a doping concentration of 1 × 10⁻⁶.15 ~9×10 17 / cm 3 The doping concentration between them.

[0057] Another embodiment of the present invention provides a method for fabricating a field-effect transistor device, comprising the following steps: epitaxially growing a functional body comprising a drift epitaxial region, a channel region and a source region on a substrate; etching the functional body to form a gate trench, the gate trench penetrating the source region and extending to the bottom of the channel region; and performing ion implantation into the sidewalls and bottomwalls of the gate trench to form a first shielding region and a second shielding region.

[0058] In the epitaxial growth of the functional host, the drift epitaxial region, channel region and source region can be formed by controlling the specific doping amount.

[0059] In the process of etching the functional body to form gate trenches, a mask template can be used to shield the area in order to prepare multiple phase-spaced gate trenches.

[0060] In one specific example, during ion implantation into the sidewalls and bottomwalls of the gate trench, a tilted ion implantation method is used to simultaneously form a first shielding region and a second shielding region. It is understood that the first and second shielding regions having a second conductivity type can be obtained by controlling the type of implanted ions. The width of the first shielding region and the thickness of the second shielding region can be controlled by controlling the ion implantation dose. Further, during tilted ion implantation, the tilt angle of the ion implantation relative to the gate trench sidewall can be 2° to 30°. Further, the tilt angle of the ion implantation relative to the gate trench sidewall can be 5° to 10°.

[0061] Another embodiment of the present invention provides a power device including a first external electrode, a second external electrode, and a field-effect transistor device according to any of the above embodiments, wherein the first external electrode is electrically connected to the source of the field-effect transistor device, and the second external electrode is electrically connected to the drain of the field-effect transistor.

[0062] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A field-effect transistor device, characterized in that, Includes substrate, functional body, gate dielectric and gate; The functional unit includes a drift epitaxial region, a channel region, a source region, a first shielding region, and a second shielding region. The drift epitaxial region is stacked on the substrate, and the channel region and the source region are stacked sequentially on the surface of the drift epitaxial region away from the substrate. The substrate, the drift epitaxial region, the channel region, and the source region have a first conductivity type, and the first shielding region and the second shielding region have a second conductivity type opposite to the first conductivity type. The functional body is provided with a plurality of gate trenches with the slots located on the side surface away from the substrate. Each gate trench contains the gate and the gate dielectric. A first shielding region, a source region, and a channel region are disposed between adjacent gate trenches. The channel region contacts the gate dielectric in one of the gate trenches and has a channel. The first shielding region is located between the channel region and another gate trench and contacts the gate dielectric in the other gate trench. The second shielding region is located below the gate trench and is connected to the first shielding region. Along the arrangement direction of the plurality of gate trenches, the sidewalls of each gate trench include opposing first sidewalls and second sidewalls. The first sidewall is formed by the first shielding region, and the second sidewall is formed by the source region and the channel region. The width of the first shielding region is ≤0.5μm, and the depth of the second shielding region is ≤1μm. The entirety comprising the drift epitaxial region and the channel region includes a drift layer, a current spreading layer, and a current limiting layer stacked sequentially. The interface between the drift layer and the current spreading layer is located below the gate trench, and the interface between the current spreading layer and the current limiting layer is flush with or above the bottom of the gate trench. The doping concentration of the current limiting layer is lower than that of the drift layer, and the doping concentration of the current spreading layer is higher than that of the drift layer.

2. The field-effect transistor device according to claim 1, characterized in that, The spacing between adjacent gate trenches is ≤1μm.

3. The field-effect transistor device according to claim 1, characterized in that, The spacing between adjacent gate trenches is 0.3 μm to 1 μm.

4. The field-effect transistor device according to any one of claims 1 and 3, characterized in that, The substrate of the functional body is silicon carbide.

5. The field-effect transistor device according to any one of claims 1 and 3, characterized in that, The thickness of the substrate is 100μm~500μm, and / or The thickness of the drift epitaxial region is 5μm to 100μm.

6. A method for fabricating a field-effect transistor device according to any one of claims 1 to 5, characterized in that, Includes the following steps: A functional entity comprising the drift epitaxial region, the channel region, and the source region is epitaxially grown on the substrate; The functional body is etched to form a gate trench, which penetrates the source region and extends to the bottom of the channel region; Ion implantation is performed on the sidewalls and bottom wall of the gate trench to form the first shielding region and the second shielding region; The gate dielectric and the gate are formed.

7. The method for fabricating a field-effect transistor device according to claim 6, characterized in that, During the ion implantation process into the sidewalls and bottomwalls of the gate trench, an inclined ion implantation method is used to simultaneously form the first shielding region and the second shielding region.

8. A power device, characterized in that, It includes a first external electrode, a second external electrode, and a field-effect transistor device according to any one of claims 1 to 5, wherein the first external electrode is electrically connected to the source of the field-effect transistor device, and the second external electrode is electrically connected to the drain of the field-effect transistor.

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