Semiconductor device and manufacturing method thereof

By incorporating a III-V compound barrier layer and insulating structure in HEMT devices, the parasitic coupling problem of high-voltage metal traces to the gate is solved, improving the device's reliability and withstand voltage capability, and simplifying the manufacturing process.

CN122373402APending Publication Date: 2026-07-10SILERGY SEMICON TECH (HANGZHOU) CO LTD
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Patent Information

Application Number
CN202610611527.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-05-06
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

In the prior art, the parasitic coupling effect of high voltage metal traces to the gate seriously affects the reliability of HEMT devices, resulting in a high risk of gate voltage overshoot.

Method used

A barrier layer made of group III-V compounds is deposited on the gate structure. The band gap is wider than that of the channel layer. It is formed by a one-step deposition process, covering the gate structure and part of the barrier layer. Combined with the design of the insulating structure and transition region, the concentration of two-dimensional electron gas is controlled to enhance the dielectric and breakdown voltage.

Benefits of technology

It effectively suppresses the parasitic coupling effect of the high-voltage metal trace above the gate to the gate, reduces the risk of gate voltage overshoot, improves the reliability and withstand voltage of the device, and simplifies the manufacturing process and reduces costs.

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Abstract

The embodiment of the invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; a channel layer, wherein the channel layer is located on the substrate; the barrier layer is located on the channel layer, and two-dimensional electron gas is generated on the interface of the channel layer and the barrier layer; the gate structure is positioned on the barrier layer; the insulating structure wraps the gate structure and covers the upper surface of a part, adjacent to the gate structure, of the barrier layer; the barrier layer comprises a first part wrapping the insulation structure and a second part at least partially covering the exposed upper surface of the barrier layer, and the source electrode structure and the drain electrode structure are located on the two sides of the grid electrode structure.
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