Integrated circuit

Abstract

The utility model relates to an integrated circuit. The integrated circuit mainly comprises a first groove and a second groove which are formed in the front face of a substrate and are in an annular shape, and the first groove and the second groove are filled with insulating materials. The first drift layer is implanted in the position, located on the inner side of the first groove, of the front face of the substrate, and the second drift layer is implanted in the position, located between the first groove and the second groove, of the front face of the substrate. The integrated circuit further comprises a connecting ring of the second conduction type implanted in the first drift layer and internally wound on the inner side of the top of the first groove, and a first emitter region and a contact region implanted in the first drift layer and located on the inner side of the connecting ring. The integrated circuit further comprises a doped ring of the first conductivity type implanted in the second drift layer and internally wound on the inner side of the second trench, and a second emitter region implanted in the second drift layer and externally wound on the outer side of the first trench. The first buried region and the second buried region are arranged alternately with each other and are arranged in the first drift layer and below the tie ring.

Description

Technical Field

[0001] The utility model mainly relates to the technical field of expansion docks, and more specifically, to a technical solution for preventing current backflow in aspects such as universal serial bus expansion docks and corresponding integrated circuits. Background Art

[0002] There are many disadvantages in the traditional hot-swap design of docking stations. Docking stations such as USB docking stations or hubs can cause potential damage to related electronic devices or hardware inserted into the docking stations: if devices are frequently hot-plugged from the USB docking station, there is a high probability that the hot-plug interface and devices of the docking station will be damaged. This is because the sudden power-on or power-off operation of plugging and unplugging devices in the docking station is a kind of jump voltage. Since the power supply terminal voltages of two or more devices plugged into the docking station are not always the same, but in most cases they are not the same. When any two devices are plugged into the docking station, the difference in their power supply terminal voltages will form a backflow current and be injected into the docking station and the one with the lower power supply terminal voltage, and at the same time, a jump transient voltage will be formed, and both the docking station and the device will be damaged. This is a serious problem that needs to be solved urgently. Utility Model Content

[0003] The present application relates to an integrated circuit, characterized in that it comprises:

[0004] A first and a second groove are formed in a ring shape and are opened on the front surface of a substrate, the first groove is located inside the second groove, the substrate is of a first conductivity type, and the first and the second grooves are filled with an insulating material;

[0005] A first drift layer implanted on the front side of the substrate and located inside the first trench, and a second drift layer implanted on the front side of the substrate and located between the first trench and the second trench, wherein both the first and second drift layers are of the second conductivity type;

[0006] A second conductive type connecting ring implanted in the first drift layer and wound inside the top of the first trench, a first emitter region and a contact region implanted in the first drift layer and located inside the connecting ring, the first emitter region being of the first conductive type and the contact region being of the second conductive type;

[0007] A doped ring of the first conductivity type implanted in the second drift layer and wound around the inner side of the second trench, and a second emitter region implanted in the second drift layer and wound around the outer side of the first trench, wherein the second emitter region is of the second conductivity type;

[0008] A plurality of first buried regions and a plurality of second buried regions are arranged in the first drift layer and below the connecting ring. The alternating first buried regions and second buried regions are both arranged in strips. The first buried regions are of the first conductivity type and the second buried regions are of the second conductivity type.

[0009] In the integrated circuit, the first emitter region and the contact region are both defined as a first signal terminal, and the second emitter region and the doped ring are both defined as a second signal terminal;

[0010] A transient voltage is input from the first signal terminal, and the integrated circuit absorbs the power impact of the transient voltage and outputs a discharge current for discharging the transient voltage from the second signal terminal.

[0011] In the above-mentioned integrated circuit, a plurality of diodes perpendicular to the substrate are formed between the plurality of first buried regions and the connecting rings respectively. When any diode is reversely broken down under the impact of the transient voltage, the breakdown current flowing through the any diode flows toward the substrate, forming a discharge path of the discharge current based on the transistor of the first emitter region, the first drift layer, and the substrate and the transistor based on the connecting ring, the substrate, and the second emitter region.

[0012] In the above-mentioned integrated circuit, multiple diodes perpendicular to the substrate are formed between the multiple first buried regions and the connecting rings respectively; the doping concentrations of the multiple first buried regions are set to be equal, so that the breakdown voltages of the multiple diodes when they are reversely broken down are all set to be the same, and the multiple diodes are synchronously not reversely broken down or synchronously reversely broken down.

[0013] In the above integrated circuit, multiple first buried regions respectively form multiple diodes perpendicular to the substrate between the connecting rings; the doping concentrations of the multiple first buried regions are different, so that the breakdown voltages of the multiple diodes when they are reversely broken down are set to be different, and the greater the transient voltage, the greater the number of the diodes that are reversely broken down.

[0014] In the above integrated circuit, the doping concentration of the second drift layer is lower than the doping concentration of the first drift layer.

[0015] The above integrated circuit also includes a dielectric layer covering the front side of the substrate and an annular upper electrode plate and a lower electrode plate wrapped in the dielectric layer;

[0016] The outer edge of the lower electrode plate is disposed above the insulator in the first groove, the inner edge of the lower electrode plate is disposed above the connecting ring, and the lower electrode plate is in contact with the connecting ring and is electrically connected thereto;

[0017] The upper electrode plate is spaced apart from the lower electrode plate and at least a partial area of ​​the upper electrode plate overlaps with the lower electrode plate below, and the upper electrode plate is electrically connected to the doping ring and the second emission region;

[0018] A capacitor is formed by an upper plate, a lower plate, and a portion of a dielectric layer located between the upper plate and the lower plate.

[0019] The above integrated circuit has a plurality of metal pads disposed on the surface of the dielectric layer, at least one of the metal pads being electrically connected to the first emitter region and the contact region through an interconnection structure penetrating the dielectric layer at the center of each of the upper plate and the lower plate;

[0020] And at least another metal pad is electrically connected to the doped ring, the second emitter region, and the upper plate through an interconnection structure penetrating the dielectric layer above the second drift region.

[0021] In the above-mentioned integrated circuit, multiple first buried regions respectively form multiple diodes perpendicular to the substrate between the connecting rings; when the capacitor is charged, the first and second buried regions are reverse biased with respect to each other, and if any diode is in a reverse breakdown state, the reverse breakdown state of any diode is interrupted by the reverse bias caused by the capacitor voltage.

[0022] The above-mentioned integrated circuit also includes an annular extended electrode plate and a buffer ring implanted on the front side of the substrate and wrapped around the outside of the second groove; the outer edge of the extended electrode plate is arranged above the buffer ring, and the inner edge of the extended electrode plate is arranged above the insulator in the second groove, and the extended electrode plate is in contact with the buffer ring and electrically connected thereto; when the capacitor is charged, the voltage drop of the extended electrode plate electrically connected to the lower electrode plate causes the buffer ring to be exhausted, and the buffer ring is of the second conductivity type.

[0023] The present application also relates to a method for preventing current backflow in an expansion dock, characterized in that an integrated circuit is used to suppress the backflow current induced by the voltage difference at the power supply terminal between the first and second devices inserted into the expansion dock;

[0024] The integrated circuit comprises:

[0025] A first and a second groove are formed in a ring shape and are opened on the front surface of a substrate, the first groove is located inside the second groove, the substrate is of a first conductivity type, and the first and the second grooves are filled with an insulating material;

[0026] A first drift layer implanted on the front side of the substrate and located inside the first trench, and a second drift layer implanted on the front side of the substrate and located between the first trench and the second trench, wherein both the first and second drift layers are of the second conductivity type;

[0027] A second conductive type connecting ring implanted in the first drift layer and wound inside the top of the first trench, a first emitter region and a contact region implanted in the first drift layer and located inside the connecting ring, the first emitter region being of the first conductive type and the contact region being of the second conductive type;

[0028] A doped ring of the first conductivity type implanted in the second drift layer and wound around the inner side of the second trench, and a second emitter region implanted in the second drift layer and wound around the outer side of the first trench;

[0029] A plurality of first buried regions and a plurality of second buried regions arranged in the first drift layer and located below the connecting ring, the alternating first buried regions and second buried regions are both arranged in strips, the first buried regions are of the first conductivity type and the second buried regions are of the second conductivity type;

[0030] The method comprises: configuring a first signal terminal at a first emitter region and a contact region; configuring a second signal terminal at a second emitter region and a doped ring; coupling the respective power terminal voltages of the first device and the second device to the first signal terminal, and when the first and second devices generate a pulse transient voltage jump due to the difference in their respective power terminal voltages at the moment of being inserted into the expansion dock, forming a conductive path between the first and second signal terminals of the integrated circuit to absorb the backflow current; utilizing the integrated circuit to absorb the power impact of the transient voltage, and outputting a discharge current of the integrated circuit to discharge the transient voltage from the second signal terminal.

[0031] In the above method, the first emitter region and the contact region are both defined as the first signal terminal, and the second emitter region and the doped ring are both defined as the second signal terminal (the first emitter region and the contact region are both short-circuited and regarded as the first signal terminal, and the second emitter region and the doped ring are both short-circuited and regarded as the second signal terminal);

[0032] A transient voltage is input from the first signal terminal, and the integrated circuit absorbs the power impact of the transient voltage and outputs a discharge current for discharging the transient voltage from the second signal terminal.

[0033] In the above method, a plurality of diodes perpendicular to the substrate are formed between the plurality of the first buried regions and the connecting rings respectively. When any diode is reversely broken down under the impact of the transient voltage, the breakdown current flowing through the any diode flows toward the substrate, forming a discharge path of the transistor based on the first emitter region, the first drift layer, and the substrate, and a discharge path of the transistor based on the connecting ring, the substrate, and the second emitter region for the discharge current.

[0034] In the above method, a plurality of diodes perpendicular to the substrate are formed between the plurality of first buried regions and the connecting rings respectively; the doping concentrations of the plurality of first buried regions are set to be equal, so that the breakdown voltages of the plurality of diodes when reversely broken down are all set to be the same, and the plurality of diodes are not reversely broken down synchronously or are reversely broken down synchronously; or the doping concentrations of the plurality of first buried regions are all different, so that the breakdown voltages of the plurality of diodes when reversely broken down are all set to be different, and the greater the transient voltage, the greater the number of the diodes that are reversely broken down.

[0035] In the above method, the doping concentration of the second drift layer is lower than the doping concentration of the first drift layer.

[0036] The above method further includes a dielectric layer covering the front surface of the substrate and an annular upper electrode plate and a lower electrode plate wrapped in the dielectric layer;

[0037] The outer edge of the lower electrode plate is disposed above the insulator in the first groove, the inner edge of the lower electrode plate is disposed above the connecting ring, and the lower electrode plate is in contact with the connecting ring and is electrically connected thereto;

[0038] The upper electrode plate is spaced apart from the lower electrode plate and at least a partial area of ​​the upper electrode plate overlaps with the lower electrode plate below, and the upper electrode plate is electrically connected to the doping ring and the second emission region;

[0039] A capacitor is formed by an upper plate, a lower plate, and a portion of a dielectric layer located between the upper plate and the lower plate.

[0040] In the above method, a plurality of metal pads are arranged on the surface of the dielectric layer, and at least one metal pad is electrically connected to the first emitter region and the contact region through an interconnection structure penetrating the dielectric layer at the center of the upper plate and the lower plate;

[0041] At least one other metal pad is electrically connected to the doped ring, the second emitter region, and the upper plate through an interconnection structure penetrating the dielectric layer above the second drift region.

[0042] In the above method, a plurality of diodes perpendicular to the substrate are formed between the plurality of first buried regions and the connecting rings;

[0043] When the capacitor is charged, the first and second buried regions are reverse biased with respect to each other, and if any diode is in a reverse breakdown state, the reverse breakdown state of the diode is interrupted by the reverse bias caused by the capacitor voltage.

[0044] The above method further includes an annular extension plate and a buffer ring implanted on the front surface of the substrate and wrapped around the outside of the second groove;

[0045] The outer edge of the extended plate is disposed above the buffer ring, the inner edge of the extended plate is disposed above the insulator in the second groove, the extended plate is in contact with and electrically connected to the buffer ring, and the buffer ring is of the second conductivity type;

[0046] When the capacitor is charged, the voltage drop across the extended plate connected to the lower plate completely depletes the buffer ring.

[0047] One of the advantages of the present application. For a docking station that is often exposed to hot plugging, two or more devices are often inserted into the docking station simultaneously or successively. When any two devices are inserted into the docking station, the voltage difference between their power terminals will form a backflow current and be injected into the one with the lower power terminal voltage and the docking station. At this time, the jump transient voltage formed at the power terminal can be released by the integrated circuit. The integrated circuit forms a conductive path to absorb the backflow current, the integrated circuit absorbs the power impact of the transient voltage, and provides a discharge path for discharging the transient voltage. When facing the backflow current and the transient voltage accompanying it, the docking station triggers the integrated circuit to generate a discharge path to release or remove the aforementioned negative transient quantities.

[0048] The second advantage of the present application. The diodes that trigger the integrated circuit to turn on and form a discharge path have a physical structure of multiple diodes perpendicular to the substrate. As an excitation module for the integrated circuit to turn on, multiple diodes are only broken down and diverted during the excitation stage, forming a current flowing to the substrate, and exciting the transistor to turn on. After the transistor is excited and turned on, the diodes are allowed not to bear the large current for implementing the discharge task, and the diode excitation function is maintained. When the docking station continues to insert other devices, the conduction excitation function of the diodes can still be re-enabled. The excitation function of the diode and the excitation exit mechanism ensure that the docking station can continuously insert an unlimited number of devices. If the diode lacks an exit mechanism, it will be damaged under the impact of the hot plug backflow current with a large single power of the docking station, and the subsequent power impact of the docking station plugging and unplugging again will not be able to continue to excite the integrated circuit to turn on and enable the discharge function. When the diode is reversely broken down, it corresponds to the excited state that starts the integrated circuit to turn on, and the reverse breakdown state of the diode is interrupted by the reverse bias caused by the capacitor voltage, which corresponds to the exit mechanism of the diode after excitation. In addition, the solution of the present application that the greater the transient voltage caused by the hot plug event, the more diodes are reversely broken down, which just fits the advantage of the greater the power impact and the greater the discharge current.

[0049] The third advantage of the present application. The semiconductor structure deployed in the integrated circuit or integrated circuit advocates the reasonable dispersion of the electric field strength at the edge of the main node in the integrated circuit. The semiconductor layout of the integrated circuit actually plays the role of widening the main junction depletion region outward, reducing the electric field concentration intensity in the integrated circuit and ultimately increasing the breakdown voltage of the integrated circuit when facing the continuous hot plugging event of the expansion dock, that is, improving the level of resistance to power shocks. At the same time, it solves the current mismatch between a group of bipolar transistors and the concerns about the current difference of the mismatched current flowing into the diode of the excitation module that turns on the integrated circuit. Current mismatch is a negative phenomenon in which the current difference between a group of bipolar transistors is too large, squeezing the current difference into the diode as the excitation module, so that the diode passively accepts the current shock. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to make the above purposes, features and advantages more understandable, the following text will explain the specific implementation methods in detail in conjunction with the drawings. After reading the following description and referring to the following drawings, the features and advantages of the present application will become apparent.

[0051] Figure 1 A diagram showing the internal structure of a semiconductor in a vertical cross section of an integrated circuit.

[0052] Figure 2 An example of a semiconductor structure is shown in cross-section from the top of an integrated circuit.

[0053] Figure 3 An example of a cross-section of the top of an integrated circuit with the tie ring removed is shown.

[0054] Figure 4 An embodiment of a capacitor integrated into a vertical cross section of an integrated circuit is shown.

[0055] Figure 5 An embodiment of a bottom plate of a capacitor integrated into an integrated circuit is shown.

[0056] Figure 6 An embodiment of a top plate of a capacitor integrated into an integrated circuit is shown.

[0057] Figure 7 Shown is the extended plate and buffer ring in a vertical cross-section of an integrated circuit.

[0058] Figure 8 A cross-section of the top of an integrated circuit showing the extended and upper plates. DETAILED DESCRIPTION

[0059] The technical solutions disclosed in the present application are clearly and completely described below in conjunction with various specific embodiments. However, the described embodiments are only embodiments used for narrative explanation in the present application rather than all embodiments. Based on these embodiments, technicians in this field should realize that any solution obtained without creative work falls within the scope of protection of the present application.

[0060] See also Figure 1, showing an integrated circuit applied to a docking station. The docking station here can also be replaced by a hub, that is, the integrated circuit can also be applied to the hub. The docking station or hub can expand some restricted or limited resources of the original device. Usually, the docking station or hub can be used to expand the storage function, network function or connection function of the original device. A single docking station or hub allows multiple storage devices such as mechanical hard disks, flash hard disks or small-size memory cards to be mounted. A single docking station or hub allows multiple different-screen displays to be connected to the same main display device at the same time. A single docking station or hub allows a display, mouse, keyboard, storage device and network cable to be connected to a computer. A single docking station or hub integrates multiple functions such as data transmission, audio and video transmission, power charging, external screen, external mobile storage, etc. And so on. USB-Hub universal serial port related docking stations are a common and commonly used type of docking stations. The following is an explanation of the docking station.

[0061] See also Figure 1 In many cases of docking stations, the power supply voltages of two or more devices plugged into the docking station are not always the same, but in most cases they are not the same. The industry uses Vbus to mark the power supply voltage of the docking station and the plugged-in devices, or ports such as the power supply terminal. The Vbus of each device is different.

[0062] See also Figure 1 , assuming that the voltage of the power supply terminal (i.e., Vbus port) of the first device is V1. Even in the case of distinguishing between master and slave nodes, it can be assumed that the first device is a master device, characterized by having a downstream port. In the case of not distinguishing between master and slave nodes, the first device is still applicable to the scheme of this article. The downstream port (Downstream Facing Port) is one of the most important features of the master device or master node. The downstream port of the master device or master node (Host) provides Vbus power supply or can also provide data output. The typical device is a power adapter, which always only provides power supply. For example, the power supply terminal of the first device can be directly electrically connected or indirectly coupled to the connection wire_1 (connected to Vbus) shown in the figure.

[0063] See also Figure 1, assuming that the voltage of the power supply end (i.e., Vbus port) of the second device is V2. Similarly, in the case of distinguishing between master and slave nodes, it can also be assumed that the second device is a slave device, characterized by having an upstream port. In the case of not distinguishing between master and slave nodes, the second device is still applicable to the solution of this article. The upstream port (Upstream Facing Port) is also one of the most important features of a slave device or a slave node. The upstream port of a slave device or a slave node (Device) draws power from Vbus or can also provide data output. Typical devices are U disks, mobile disks and other storage devices for data storage. Obviously, they are always read data and draw power from Vbus but do not provide Vbus power supply, such as TF memory cards. For example, the power supply end of the second device can be directly electrically connected or indirectly coupled to the connection wire_1 (connected to Vbus) shown in the figure.

[0064] See also Figure 1 , assuming that the first device uses a dual-role port (Dual Role Port), the first device can be used as both a master device and a slave device. A computer is one of the typical dual-role port devices. Currently, many types of computers can be used as both a host that provides external power and a device to be charged (with a built-in rechargeable battery). For example, if a mobile phone is used as a host, it can provide power to other devices or read data from a USB flash drive. The mobile phone can also be used as a slave device to be charged and read data. Assuming that the second device uses a dual-role port (Dual Role Port), the second device can be used as both a master device and a slave device. Mobile power supplies are typical applications of dual-role ports. The discharge and charging of mobile power supplies can be achieved through a USB port (such as Type-C), which can be used for both discharge and charging.

[0065] See also Figure 1, the first device or the second device mentioned above are just some examples. The multiple ports of the docking station or hub can be plugged with more devices such as the third device or the fourth device or even the fifth device. The main disadvantages of hot-plugging of traditional docking stations are: the voltages of the power supply terminals of the two or more devices inserted, such as V1 and V2, are not equal in most cases. When the first device and the second device are inserted into the docking station at the same time or successively, the power supply terminal Vbus port of the first device and the power supply terminal Vbus port of the second device need to be connected. The so-called one supplies power while the other takes power is the main manifestation of Vbus port connection; in view of the inequality between V1 and V2, the plugging and unplugging of devices is equivalent to a sudden power-on or power-off operation at the power supply terminal port. The voltage of the device with a larger power supply terminal voltage will be transiently pulled down, and the voltage of the device with a smaller power supply terminal voltage will be transiently pulled up. The sudden power-on or power-off operation of plugging and unplugging devices in the docking station causes a jump voltage at the Vbus port. The high voltage level of the device with a larger power supply voltage relative to the low voltage level of the device with a smaller power supply voltage will also generate a transient current at the Vbus port of the device with a larger voltage flowing from the device with a larger voltage to the device with a smaller voltage. That is, the difference between their power supply voltages V1 and V2 will form a backflow current and inject it into the docking station and the one with a lower power supply voltage, such as its Vbus port. At the same time, it will also form a jump transient voltage, and both the docking station and the hot-swappable device will be damaged. Note that in addition to the phenomenon of backflow current during the hot-swap stage, the device also has this phenomenon during the operating stage of the device. For example, if the workload rate of one end of the first device or the second device increases sharply, its power supply voltage will often be lowered, and the power supply voltage of other devices with a lighter workload will be relatively high, thereby generating a light or heavy backflow current. The current of the device with a lighter workload at the other end will flow back to the end with a heavier workload, which may burn this end. The first device or the second device has both high-voltage devices and low-voltage devices, or there are also non-powered devices.

[0066] See also Figure 1 In an optional embodiment, the first device (or the first device is a first expansion device compatible with the docking station, such as a USB expansion device) and the second device (or the second device is a second expansion device compatible with the docking station, such as a USB expansion device) can connect their respective Vbus ports to the connection wire_1. Computers or storage servers or hard disks, mobile hard disks, handheld devices, mobile phones, tablet computers, industrial computers, monitoring machines or switches, and the various devices mentioned above are all expansion devices compatible with the docking station.

[0067] See also Figure 1In an optional embodiment, the components and operating modes of each functional module of the illustrated integrated circuit (which may be referred to as an integrated circuit structure, an integrated circuit or an integrated circuit chip, an integrated chip, an integrated circuit device, a semiconductor device, etc.) will be explained step by step below.

[0068] See also Figure 1 In an optional embodiment, the integrated circuit has a first groove 50 and a second groove 55 which are opened on the front side of a substrate P-sub and are in the form of a ring. The first groove 50 is located inside the second groove 55. The substrate shown in the figure is of the first conductivity type, such as the P conductivity type. The first groove 50 and the second groove 55 are filled with insulating materials, and the insulating materials can be, for example, oxides, silicon nitride, or silicate glass. Since the grooves involve electric field regulation, in fact, the insulating materials filled inside them are preferably dielectrics such as benzocyclobutene. The bulk resistivity, critical electric field strength, and relative dielectric constant of such materials are suitable for regulating the electric field distribution in the first groove 50 and the second groove 55. The first groove and the second groove can also be respectively referred to as inner grooves and outer grooves in the context.

[0069] See also Figure 1 , the first groove 50 and the second groove 55 can be etched using the same mask. For example, a mask with inner and outer groove patterns is used to etch the substrate P-sub, the inner groove pattern exposes the substrate at the position of the first groove 50 and the outer groove pattern exposes the substrate at the position of the second groove 55, and the substrate P-sub is etched based on the mask, the first groove 50 is etched at the substrate exposed by the inner groove pattern, and the second groove 55 is etched at the substrate exposed by the outer groove pattern. The so-called inner groove pattern is, for example, an opening or window pattern made on a mask. The biggest advantage of the first groove 50 and the second groove 55 being prepared simultaneously is that the process is simple, the cost is saved, and there is no need for too many masks.

[0070] See also Figure 1, the first groove 50 and the second groove 55 can also be formed by etching in steps. For example, the substrate P-sub is etched using a first mask with an inner groove pattern, and the first groove 50 is formed after the substrate at the position where the inner groove pattern exposes the first groove 50 is etched. The etching implementation environment at this time is recorded as the inner groove etching condition. For another example, the substrate P-sub is etched using a second mask with an outer groove pattern, and the second groove 55 is formed after the substrate at the position where the outer groove pattern exposes the second groove 55 is etched. The etching implementation environment at this time is recorded as the outer groove etching condition. The inner groove etching condition and the outer groove etching condition can be set to be inconsistent. If the etching parameters such as etching gas, etching time, and etching rate are set to be different, the depth and width of the first groove 50 and the second groove 55 can be different. Due to the differences in the electric field distribution inside the integrated circuit, grooves of different depths are required in some occasions to adjust the field strength. For another example, if the groove depth is not configured, it may not provide a reasonable current path for the transistor. The biggest advantage of asynchronously preparing the first trench 50 and the second trench 55 is that the depth and width of the inner and outer trenches can be flexibly controlled without hindering each other. For example, the relatively deep outer trench can balance the leakage current and electric field distribution around the integrated circuit; the inner trench with flexibly controllable depth and width can adjust the electric field distribution of the main junction of the integrated circuit and provide a more reasonable lateral current path for the transistor.

[0071] See also Figure 1 The first trench 50 and the second trench 55, which are originally hollow, are first filled with insulating material and then the insulating material is etched back, and only some residual insulating material filled in the trenches is retained, and other insulating materials covering the positions of the substrate P-sub front surface and other positions outside the trenches need to be cleaned up. The deposition methods of the insulating material include chemical vapor deposition and physical vapor deposition.

[0072] See also Figure 2 In an optional embodiment, the context and the accompanying drawings take a ring with a rectangular cross section as an example to illustrate the first groove 50 and the second groove 55, which can be combined with Figure 8 In fact, the first groove 50 and the second groove 55 can also be designed into a circular ring or an elliptical ring, or even a polygonal ring structure, such as a pentagonal ring frame structure, a hexagonal ring frame structure, a honeycomb ring frame, etc. The quadrilateral ring frame structure shown in the figure is only an option.

[0073] See also Figure 1In an optional embodiment, the integrated circuit has a first drift layer 10 implanted on the front side of the substrate P-sbu and located inside the first trench 50, and the integrated circuit has a second drift layer 20 implanted on the front side of the substrate P-sbu and located between the first trench 50 and the second trench 55. In an optional embodiment, it is preferably designed that both the first drift layer 10 and the second drift layer 20 are of the second conductivity type, such as the N conductivity type.

[0074] See also Figure 1 In an optional embodiment, the integrated circuit has a second conductive type connection ring 11 implanted in the first drift layer 10 and wound inside the top of the first trench 50. The position of the connection ring 11 wound inside the top of the first trench can be referred to. Figure 1 The annular structure (ring) of the connecting ring 11 can be referred to Figure 2 The connecting ring 11 is, for example, of N conductivity type, but has a higher concentration than the first drift layer 10 .

[0075] See also Figure 1 In an optional embodiment, the integrated circuit has a first emitter region 13 and a contact region 12 implanted in the first drift layer 10 and located inside the aforementioned connecting ring 11. The first emitter region 13 and the contact region 12 can be arranged in a strip or stripe shape or a rectangular or square shape. The vertical cross-sectional view of the contours and positional relationship of the first emitter region 13 and the contact region 12 can be referred to. Figure 1 As shown, the morphology of the first emitter region 13 and the contact region 12 can refer to the top view of the integrated circuit, that is, the reference Figure 2 As shown. The first emitter region 13 is of the first conductivity type, such as P type, and preferably heavily doped with a concentration greater than that of the substrate. The contact region 12 is of the second conductivity type, such as N type. The doping concentration of the contact region 12 is preferably higher than that of the connecting ring 11, but both are higher than that of the first drift layer 10. The implantation depth of the first emitter region, the contact region, the connecting ring, etc. is shallower than the implantation depth of the first drift layer 10.

[0076] See also Figure 1 The doping regions on the front side of the substrate P-sub (the first drift layer, the second drift layer, the connecting ring, the first emitter region or the contact region, the doping ring, the second emitter region, the first buried region, the second buried region, etc.) are based on the front side process of the wafer and the doping depth of these doping regions is the depth seen from the front side of the substrate P-sub, or the depth of ion implantation from the front side. The preparation of the substrate P-sub and the integrated circuit is compatible with the current wafer process.

[0077] See also Figure 1In an optional embodiment, the integrated circuit has a doping ring 22 of the first conductivity type, such as the P conductivity type, implanted in the second drift layer 20 and wound inside the second trench 55. The position of the doping ring 22 wound inside the second trench can be referred to as Figure 1 As shown. The doping ring 22 is not just wrapped around the inner side of the top of the second trench but extends downward from the second drift layer 20 to the substrate P-sub. For example, the doping ring 22 extends from the front or upper surface of the second drift layer 20 to the substrate P-sub region below the second drift layer 20. The implantation profile of the doping ring 22 and the vertical cross-sectional view of its positional relationship can be referred to. Figure 1 The doping ring 22 extends downward from the second drift layer 20 to the substrate or to the substrate region below the second drift layer. The ring structure of the doping ring 22 can be referred to as Figure 2 The integrated circuit is shown in top plan view. The doped ring 22 is, for example, of P conductivity type, but with a higher concentration than that of the substrate.

[0078] See also Figure 1 In an optional embodiment, the integrated circuit has a second emitter region 24 implanted in the second drift layer 20 and surrounding the outside of the first trench 50. The second emitter region 24 is, for example, of the second conductivity type of the N-doped type and its doping concentration is much higher than the doping concentration of the second drift layer 20. The position of the second emitter region 24 surrounding the top of the first trench can be referred to Figure 1 The ring structure of the second emitting area 24 is shown in Figure 2 The implantation depth of the second emitter region 24 is much shallower than that of the doped ring 22.

[0079] See also Figure 2 , is the front side of the integrated circuit viewed from the top. Figure 1 , is to show the profile of the integrated circuit from the vertical section of the integrated circuit. From the comparison and combination of the top view and the cross-sectional view, we can deeply understand the deployment details and phase position relationship of each functional module inside the integrated circuit. It is worth noting that because the inner and outer grooves are used, it is equivalent to isolating the first drift layer on the inside and the second drift layer on the outside. The original transistor current path and related parameters such as the electric field distribution line inside the integrated circuit are greatly modulated. Some doping area contours mentioned in the context are arranged into a so-called ring structure (ring), which is a balance to the aforementioned modulation to a large extent. For example, moving the transistor current path downward as a whole will significantly increase the lateral resistance on the path. If the doping area contour is a ring (ring), many parallel radial current paths can be formed. The parallel paths can attenuate the parasitic lateral resistance and compensate for the negative effects of modulation.

[0080] See also Figure 2Based on the perspective of the top view of the integrated circuit, it can be seen that the main functional modules of the transistor, that is, the doping areas of each ring structure, are closed ring frames. Figure 1 It is possible to observe a plurality of first buried regions 14 and a plurality of second buried regions 15 arranged in the first drift layer 10 and located below the tie ring, but Figure 2 The top view of the connecting ring blocks the first buried areas 14 and the second buried areas 15 below it, so it is necessary to use Figure 3 To explain.

[0081] See also Figure 3 , the front side of the integrated circuit is also viewed from the top of the integrated circuit, but the connecting ring is deliberately removed from the figure to expose a plurality of first buried regions 14 arranged in the first drift layer 10 but below the connecting ring 11 and a plurality of second buried regions 15 below the connecting ring. In an optional example, the first buried region 14 is of the first conductivity type such as the P conductivity type and the second buried region 15 is of the second conductivity type such as the N conductivity type. In an alternative example, the first buried region 14 is of the second conductivity type such as the N conductivity type and the second buried region 15 is of the first conductivity type such as the P conductivity type.

[0082] See also Figure 3 The first buried regions 14 and the second buried regions 15 are arranged alternately. In other words, the first buried regions 14 and the second buried regions 15 are arranged alternately. The alternating first buried regions 14 and the second buried regions 15 are arranged in strips.

[0083] See also Figure 3 , a first buried region 14 of the first conductivity type, such as a p region, and a second buried region 15 of the second conductivity type, such as an n region, are alternately implanted below the connecting ring, and the p region and the n region are arranged alternately. The local area of ​​multiple p regions and multiple n regions below the connecting ring is represented by the alternating area shown in the figure. The alternating area represents: for example, the local area of ​​the first drift layer 10 located below the connecting ring is implanted with P dopants and N dopants in turn and forms an alternating layout of p regions and n regions. It can be considered that an n region is inserted between any two adjacent p regions, and a p region is inserted between any two adjacent n regions, that is, the first buried region 14 (p region) and the second buried region 15 (n region) are alternately implanted in the local area. In the optional option, the first buried region and the second buried region reach the connecting ring 11 upward at the local area, and the first buried region and the second buried region reach the substrate position below the first drift layer 10 downward at the local area. The first buried region and the second buried region are configured to extend from the connecting ring 11 to the substrate position below the first drift layer 10, for example. Combination Figure 1 shown.

[0084] See also Figure 3, the first buried region 14 of the second conductivity type, such as the n region, and the second buried region 15 of the first conductivity type, such as the p region, are alternately implanted below the connecting ring, and the n region and the p region are arranged alternately. The local area of ​​multiple n regions and multiple p regions below the connecting ring is represented by the alternating area shown in the figure. The alternating area represents: for example, the local area of ​​the first drift layer 10 located below the connecting ring is implanted with N dopants and P dopants in turn and forms an alternating layout of n regions and p regions. It can be considered that a p region is inserted between any two adjacent n regions, and an n region is inserted between any two adjacent p regions, that is, the first buried region 14 (n region) and the second buried region 15 (p region) are alternately implanted in the local area. In the optional option, the first buried region and the second buried region reach the connecting ring 11 upward at the local area, and the first buried region and the second buried region reach the substrate position below the first drift layer 10 downward at the local area. The first buried region and the second buried region are configured to extend from the connecting ring 11 to the substrate position below the first drift layer 10, for example. Figure 1 shown.

[0085] See also Figure 3 If the first buried region 14 and the first drift layer 10 have the same doping type or conductivity type, then it can be directly a part or sub-region of the first drift layer 10. In this case, the first buried region 14 does not need to be implanted with dopants separately, and only the second buried region 15 is formed and the first buried region 14 is reserved. Figure 1 The reserved first buried region, for example, the gap between two adjacent second buried regions 15 is regarded as a first buried region 14 .

[0086] See also Figure 3 If the second buried region 15 and the first drift layer 10 have the same doping type or conductivity type, then it can be directly a part or sub-region of the first drift layer 10. In this case, the second buried region 15 does not need to be implanted with dopants separately, and it is sufficient to form the first buried region 14 and reserve the second buried region 15. Figure 1 The reserved second buried region is such that the gap between two adjacent first buried regions 14 is regarded as a second buried region 15 .

[0087] See also Figure 3 , if the first buried region 14 and the first drift layer 10 have the same doping type or conductivity type, it is no longer a part or sub-region of the first drift layer 10. At this time, the first buried region 14 needs to be implanted with dopants separately and the second buried region 15 and the first buried region 14 need to be implanted separately. Figure 1 In this case, the first buried region and the first drift layer have different doping concentrations or different dopants, and the first buried region 14 needs to be re-implanted.

[0088] See also Figure 3If the second buried region 15 has the same doping type or conductivity type as the first drift layer 10, it is no longer a part or sub-region of the first drift layer 10. In this case, the second buried region 15 needs to be implanted with dopants separately and the first buried region 14 and the second buried region 15 need to be implanted separately. Figure 1 In this case, the second buried region and the first drift layer have different doping concentrations or different dopants, and the second buried region 15 needs to be re-implanted.

[0089] See also Figure 1 In an optional embodiment, the above description states that, for example, the power supply terminal of the first device can be directly electrically connected or indirectly coupled to the wire_1 (connected to Vbus) shown in the figure, and the power supply terminal of the second device can be directly electrically connected or indirectly coupled to the wire_1 (connected to Vbus) shown in the figure. The specific form of the wire_1 includes, for example, a metal wire or any conductive wire or conductive strip or metal conductive tape or probe or metal spring or bonding wire and other conductive materials.

[0090] See also Figure 1 , the voltage of the power end (i.e., Vbus port) of the first device is assumed to be V1. And the voltage of the power end (i.e., Vbus port) of the second device is assumed to be V2. In an optional embodiment, the connection wire_1 is electrically connected to the first emission area 13 and the contact area 12 as shown in the figure. In view of the vast majority of scenarios where V1 and V2 are not equal, the difference in their power end voltages will form a backflow current and be injected into the docking station and the one with a lower power end voltage. Obviously, the backflow current will also flow into the position of the connection wire_1. The voltage difference between the two devices generates current, which is a common phenomenon when any devices are interconnected, especially when high-voltage devices and low-voltage devices are coupled. The electrostatic ESD generated when any two devices are coupled will also generate an injection current and transient voltage at the position of the connection wire_1.

[0091] See also Figure 1 The first emitter region 13 and the contact region 12 are both defined as the first signal terminal, and the second emitter region 24 and the doped ring 22 are both defined as the second signal terminal as shown in the figure. The following will introduce the discharge path and the conduction path of the backflow current or transient voltage / transient current generated between the first signal terminal and the second signal terminal.

[0092] See also Figure 1, the first emission area 13 and the contact area 12 can be electrically connected by a wire, a conductive strip, a metal conductive strip, a probe, a metal shrapnel, or a bonding wire, etc. (such as using wire_1). The form of the connection wire_1 includes a wire, a conductive strip, a metal conductive strip, a probe, a metal shrapnel, or a bonding wire, etc., and the connection wire_1 is regarded as the first signal terminal. According to the foregoing, it is necessary to couple the power supply terminal voltage V1-V2 of the first device and the second device to the first signal terminal. The example shown in the figure is an embodiment in which the first emission area and the contact area are defined as the first signal terminal.

[0093] See also Figure 1 , the second emitter region 24 and the doped ring 22 can be electrically connected by a wire, a conductive strip, a metal conductive strip, a probe, a metal shrapnel, or a bonding wire, etc. (such as using wire_2). The connection wire_2 is in the form of a wire, a conductive strip, a metal conductive strip, a probe, a metal shrapnel, or a bonding wire, etc., and the connection wire_2 is regarded as the second signal terminal. In this example, the second signal terminal can be connected to a reference voltage such as a reference ground GND, a negative voltage, a low-level voltage, etc. The illustrated example is an embodiment in which the second emitter region and the doped ring are defined as the second signal terminal. The low-level voltage can be zero voltage or slightly higher than zero voltage or slightly lower than zero voltage, which is usually much lower than the power supply terminal voltage V1-V2.

[0094] See also Figure 1 , the transient voltage is input from the first signal terminal. For example, in a typical case, when the first device and the second device are inserted into the docking station, a pulse-type (most common single pulse signal) transient voltage jump occurs due to the voltage difference between the power terminals of the first device and the second device. The transient voltage occurs at the Vbus of the docking station, the power terminal of the first device such as the Vbus port, and the power terminal of the second device such as the Vbus port. The Vbus of the docking station usually allows power to be supplied to some electronic components on the docking station's own circuit board. Electrostatic discharge refers to the sudden discharge phenomenon caused by the accumulation of charge on an object. Electrostatic discharge may occur when the first device and the second device are in different charge states or one of the devices carries too much charge. This discharge can generate extremely high voltage and instantaneous current and is sufficient to damage sensitive electronic components or devices. The first signal terminal at the connection wire_1 can resist static electricity. The integrated circuit absorbs the power impact of the transient voltage and discharges the discharge current of the transient voltage from the second signal terminal such as GND output.

[0095] See also Figure 3 It is known that: the plurality of first buried regions and the plurality of second buried regions 14-15 arranged in the first drift layer 10 and located below the connecting ring 11 constitute a p region and an n region, and the first buried regions 14 and the second buried regions 15 are alternately arranged in strips. For example, the first buried region 14 is of P type and the second buried region 15 is of N type.

[0096] See also Figure 4 In an optional embodiment, multiple first buried regions respectively form multiple diodes perpendicular to the substrate with the connecting rings: a diode D2 perpendicular to the substrate P-sub is formed between the first buried regions 14a and 14c and the connecting ring 11 as shown in the figure, and a diode D1 perpendicular to the substrate P-sub is formed between the first buried regions 14b and 14d and the connecting ring 11 as shown in the figure. Figure 7 A finite number of diodes such as diodes D1-D2 are shown. If Figure 4 The use is not limited to the first buried areas 14a, 14b, 14c, 14d, etc. shown in the figure. Figure 7 The diodes between the first buried region and the connecting ring in the figure are far more than the limited number of diodes D1-D2 shown in the figure, but there are more.

[0097] See also Figure 7 In an optional embodiment, when any diode, such as diode D1, is reversely broken down under the impact of the aforementioned transient voltage, the junction (PN-junction) of diode D1 reaches the reverse breakdown voltage. In this case, the breakdown current flowing through any diode, such as D1, flows to the substrate P-sub. Figure 1 If the transient voltage does not reach the reverse breakdown voltage of any diode such as D1, it does not reverse breakdown.

[0098] See also Figure 7 In an optional embodiment, when any diode, such as diode D2, is reversely broken down under the impact of the aforementioned transient voltage, the junction (PN-junction) of diode D2 reaches the reverse breakdown voltage. In this case, the breakdown current flowing through any diode, such as D2, flows to the substrate P-sub. Figure 1 If the transient voltage does not reach the reverse breakdown voltage of any diode such as D2, it does not reverse breakdown.

[0099] See also Figure 7 In an optional embodiment, when any diode such as D1 or D2 is reversely broken down under the impact of the aforementioned transient voltage, the breakdown current flowing through any diode such as D1 or D2 flows to the substrate. As mentioned above, the transient voltage can be input from the first signal terminal. At this time, the integrated circuit absorbs the power impact of the transient voltage and outputs the discharge current of the transient voltage from the second signal terminal. Because the breakdown current of the diode such as D1 or D2 flows to the substrate, a discharge path or a conductive path is formed based on the first emitter region, the first drift layer, and the PNP of the substrate and the transistor NPN based on the connecting ring, the substrate, and the second emitter region. In fact, the PNP and NPN are turned on.

[0100] See also Figure 1 In an optional embodiment, when the breakdown current of a diode such as D1 or D2 flows to the substrate, a voltage drop will be formed on the parasitic resistance of the substrate P-sub and the doped ring 22. The mechanism is that the breakdown current flowing to the substrate will bear a certain degree of voltage because it flows through the parasitic resistance of the substrate P-sub and the doped ring 22. The above-mentioned integrated circuit has an NPN bipolar transistor based on the connecting ring 11, the substrate P-sub, and the second emitter region 24, and the so-called voltage drop formed on the parasitic resistance is equivalent to the voltage drop applied between the base and the emitter of the NPN bipolar transistor. The voltage drop condition applied by the base will cause the NPN bipolar transistor to be triggered to turn on and be regarded as a discharge path or a conduction path. Thereby, a discharge path from the first signal terminal (wire_1) to the second signal terminal (wire_2) is formed for guiding the discharge current.

[0101] See also Figure 1 In an optional embodiment, the breakdown current of the diode such as D1 or D2 flows to the substrate. At this time, the NPN transistor of the connecting ring 11, the substrate P-sub, and the second emitter region 24 in the integrated circuit is turned on, and a flow current is formed between the contact area 12 inside the first drift layer 10 in the integrated circuit and the connecting ring 11. It is noted that the flow current will flow through the resistance between the contact area 12 and the connecting ring 11, and the resistance includes the resistance of the area where the first drift layer 10 is located. And the flow current will form a voltage drop between the contact area 12 and the first drift layer 10 when it flows through the resistance. The above-mentioned integrated circuit has a PNP transistor based on the first emitter region 13, the first drift layer 10, and the substrate P-sub. The above-mentioned voltage drop is equivalent to the voltage drop applied between the emitter and the base of the PNP bipolar transistor. The condition of the base voltage drop will cause the PNP bipolar transistor to be triggered to turn on and be regarded as another coexisting discharge path or another coexisting conductive path. Thereby, another discharge path from the first signal terminal (wire_1) to the second signal terminal (wire_2) for guiding the discharge current is formed.

[0102] See also Figure 1 , the transient voltage is input from the first signal terminal (wire_1), the integrated circuit absorbs the power impact of the transient voltage and outputs the discharge current of the transient voltage from the second signal terminal (wire_2). Multiple first buried regions respectively form multiple diodes such as D1-D2 and the like perpendicular to the substrate between the connecting rings. When any diode is reversely broken down under the impact of the transient voltage, the breakdown current flowing through any diode such as D1-D2 flows to the substrate, forming the discharge path of the discharge current based on the first emitter region, the first drift layer, the PNP of the substrate and the transistor NPN based on the connecting ring, the substrate and the second emitter region.

[0103] See also Figure 4, multiple first buried regions (such as 14a-14c, etc.) respectively form multiple diodes such as D1-D2, etc. perpendicular to the substrate between the connecting ring 11. The doping concentrations of multiple first buried regions (such as 14a-14c, etc.) are set to be equal, that is, the first buried regions 14a-14c have the same breakdown configuration, so that the breakdown voltages of multiple diodes D1-D2 when they are reversely broken down are all set to be the same. In this case of equal breakdown, multiple diodes D1-D2 are synchronously not reversely broken down or synchronously reversely broken down. It can be understood that: under the impact of transient voltage, multiple diodes D1-D2, etc. either reversely break down at the same time (synchronous breakdown) or do not reversely break down at the same time (synchronous non-breakdown). Synchronous non-breakdown means that the energy of transient voltage or backflow current is small and insufficient to cause the integrated circuit to form a discharge path. Synchronous breakdown means that the energy of transient voltage or backflow current is large and the synchronous path of diodes (such as D1-D2, etc.) that are all turned on at this time provides a large breakdown current flowing to the substrate P-sub, forming a discharge path for large current to flow at one time.

[0104] See also Figure 4 , multiple first buried regions (such as 14a-14c, etc.) respectively form multiple diodes such as D1-D2, etc. perpendicular to the substrate between the connecting ring 11. The doping concentrations of the multiple first buried regions (such as 14a-14c, etc.) are set to be unequal, that is, the first buried regions 14a-14c have different breakdown arrangements, so that the breakdown voltages of the multiple diodes D1-D2 when they are reversely broken down are set to be different. In this unequal breakdown situation, the more diodes D1-D2 are broken down when the transient voltage is greater. It can be understood that: when the multiple diodes D1-D2, etc. are impacted by the transient voltage, the greater the transient voltage, the more diodes are reversely broken down. For example, when the voltage of the transient voltage is low or the energy is small, only the diode D1 may be reversely broken down. For example, when the voltage level of the transient voltage is high or the energy is large, more diodes D1-D2 may be broken down. This example provides a step-type current discharge path: unstable transient voltages are usually high-frequency transients and continuously change dynamically. For example, if several devices with different power supply voltages are continuously inserted into the docking station instead of only the first device and the second device, the transient voltage will naturally change in a follow-up manner. In the case of a small transient voltage value, a small number of diodes D1 are reversely broken down (the discharge current has a low-level discharge path), and in the case of a large transient voltage value, a large number of diodes D1-D2 are broken down (the discharge current has a high-level discharge path). If the transient voltage is larger, the integrated circuit provides a discharge path with a larger current.

[0105] See also Figure 1, the main junction in the integrated circuit is mainly between the first drift layer 10 and the substrate P-sub. The shape of the depletion layer of the main junction shrinks and narrows near the inner groove. The distribution of the electric field lines is not balanced. The field strength of the main junction is higher near the inner groove than other places. The excessively strong electric field will cause breakdown such as avalanche to occur early at the narrowing point. In an optional embodiment, the doping concentration of the second drift layer 20 is designed to be lower than the doping concentration of the first drift layer 10. The depletion layer between the first drift layer 10 and the substrate can partially slow down the narrowing shape of the main junction depletion layer. The main junction depletion layer will expand outward along the first drift layer at the first drift layer. For example, when a reverse voltage such as a transient voltage is applied to the main junction and as the transient voltage increases, the depletion layer of the main junction expands outward and extends to the first drift layer 10. The first drift layer 10 then attenuates the maximum electric field distribution near the main junction, greatly improving the withstand voltage level of the integrated circuit. It should be noted that the depletion layer width is negatively correlated with the doping concentration: that is, when the doping concentration increases, the depletion layer width decreases, and when the doping concentration decreases, the depletion layer width increases. An increase in doping concentration will result in a decrease in the depletion layer width and an increase in the capacitance of the PN junction.

[0106] See also Figure 4 The integrated circuit also includes a dielectric layer ox covering the front side of the substrate P-sub, and the integrated circuit also includes an upper electrode plate 32a and a lower electrode plate 31 in a ring shape and enclosed in the dielectric layer ox. Figure 5 The ring structure or ring frame structure of the lower plate is shown. Figure 6 The ring structure or ring frame structure of the upper plate is shown.

[0107] See also Figure 4 The outer edge of the lower electrode plate 31 is disposed above the insulator in the first groove 50. The lower electrode plate is a ring frame structure and includes an inner edge and an outer edge. The inner edge of the lower electrode plate 31 is disposed above the connecting ring 11. As shown in the figure, the lower electrode plate 31 is designed to contact the connecting ring 11 (such as ohmic contact) and is electrically connected to the connecting ring 11.

[0108] See also Figure 4 The upper plate 32a is spaced apart from the lower plate 31, and at least a partial area of ​​the upper plate 32a overlaps with the lower plate 31 below it. The upper plate 32a is electrically connected to the doped ring 22 and the second emitter region 24. For example, the upper plate is connected to the doped ring 22 and the second emitter region 24 through some metal interconnection structures.

[0109] See also Figure 4The upper plate 32a, the lower plate 31, and the dielectric layer ox located between the upper plate 32a and the lower plate 31 form a capacitor, which belongs to a MIM (Metal-Insulator-Metal) capacitor. The upper plate 32a is the plate of the capacitor and the lower plate 31 is the plate of the capacitor. The dielectric layer ox between the upper plate 32a and the lower plate 31 is the medium of the capacitor that hinders the movement of charges. The dielectric layer ox is generally an insulator.

[0110] See also Figure 4 In an optional embodiment, the lower electrode 31 is prepared, for example, by depositing a thin first metal layer on the front side of the substrate, and then patterning and etching the first metal layer to retain only the portion of the first metal layer that is intentionally reserved after the etching process, i.e., the lower electrode 31. The substrate of the lower electrode 31, i.e., the substrate of the first metal layer, can be made of a metal material such as copper or aluminum, or a copper-aluminum alloy. The first metal layer can also first deposit a titanium lining layer and then cover the titanium with other metal materials. The conductor material selection of the first metal layer is diverse. When preparing the lower electrode 31 from the aforementioned first metal layer, it is necessary to pay attention to the positional relationship of the reserved lower electrode 31, such as Figure 5 shown.

[0111] See also Figure 5 The outer edge 31T of the lower plate 31 is configured to shrink inward relative to the outer sidewall 50b of the first groove 50 to prevent the outer edge 31T of the lower plate 31 from touching the second drift layer 20. The shrinkage of the outer edge 31T relative to the outer sidewall 50b of the first groove means that the outer edge 31T shrinks toward the lower plate 31 itself or shrinks back and can be observed from the top view in the figure.

[0112] See also Figure 5 , the inner edge 31R of the lower plate 31 is configured to shrink inward relative to the inner ring edge 11a of the coupling ring 11, so as to prevent the inner edge 31R of the lower plate 31 from touching the first drift layer 10. For example, it is substantially possible to prevent the inner edge 31R of the lower plate from touching the portion of the first drift layer 10 located inside the coupling ring 11. The shrinkage of the inner edge 31R relative to the inner ring edge 11a of the coupling ring means that the inner edge 31R shrinks toward the lower plate 31 itself or shrinks back and can be observed from the top view in the figure.

[0113] See also Figure 5The inner edge 31R of the lower plate 31 shrinks inwards, which means that the inner edge 31R shrinks (i.e. shrinks back) to the lower plate itself; the outer edge 31T shrinks inwards, which means that the outer edge 31T shrinks (i.e. shrinks back) to the lower plate itself. Therefore, the outer edge 31T of the lower plate 31 is on the inner side of the outer side wall of the first groove 50, and the inner ring edge 11a of the connecting ring 11 is on the inner side of the inner edge 31R of the lower plate 31.

[0114] See also Figure 5 The lower plate 31 is also a ring, and the hollow area at the center of the lower plate 31 substantially overlaps the first emitting area 13 and the contact area 12. That is, the hollow area at the center of the lower plate 31 can be aligned with the first emitting area 13 and the contact area 12.

[0115] See also Figure 5 In summary, the outer edge of the lower electrode plate is retracted relative to the outer side wall of the first groove to prevent the outer edge of the lower electrode plate from touching the second drift layer. The inner edge of the lower electrode plate is retracted relative to the inner ring edge of the connecting ring to prevent the inner edge of the lower electrode plate from touching the first drift layer. The outer edge of the lower electrode plate is on the inner side of the outer side wall of the first groove. The inner ring edge of the connecting ring is on the inner side of the inner edge of the lower electrode plate.

[0116] See also Figure 4 In an optional embodiment, after preparing the lower electrode plate 31, an insulating lower dielectric layer may be deposited on the front side of the substrate, and then the lower dielectric layer may be ground or etched back, so the lower dielectric layer at this stage will cover the lower electrode plate 31 inside. The lower dielectric layer may be prepared using insulating films such as silicon oxide, silicon nitride, borophosphosilicate glass, or non-doped silicate glass. The lower dielectric layer is a component of the dielectric layer ox.

[0117] See also Figure 4 In an optional embodiment, the upper electrode 32a is prepared by, for example, depositing a thin second metal layer on the lower dielectric layer, and then patterning and etching the second metal layer, leaving only the portion of the second metal layer that is intentionally reserved after the etching process, namely, the upper electrode 32a. The substrate of the upper electrode 32a, that is, the substrate of the second metal layer, can be made of a metal material such as copper or aluminum, or a copper-aluminum alloy. The second metal layer can also first deposit a titanium lining layer and then cover the titanium with other metal materials. The conductor material selection of the second metal layer is diverse. When preparing the upper electrode 32a from the aforementioned second metal layer, it is necessary to pay attention to the positional relationship of the reserved upper electrode 32a, such as Figure 6 shown.

[0118] See also Figure 6The upper plate 32a is also a ring, and the hollow area at the center of the upper plate 32a substantially overlaps the first emitting area 13 and the contact area 12. That is, the hollow area at the center of the upper plate 32a can be aligned with the first emitting area 13 and the contact area 12.

[0119] See also Figure 4 , the upper electrode plate 32a and the lower electrode plate 31 are substantially parallel to each other. The upper electrode plate 32a is spaced apart from the lower electrode plate 31 and at least a partial area of ​​the upper electrode plate 32a overlaps with the lower electrode plate 31. For example, the upper electrode plate 32a is spaced apart from the lower electrode plate 31 and at least a partial area of ​​the upper electrode plate 32a overlaps with the lower electrode plate 31 through the dielectric layer ox.

[0120] See also Figure 4 In an optional embodiment, after preparing the upper electrode 32a, an insulating upper dielectric layer can be deposited on the lower dielectric layer, and then the upper dielectric layer is ground or etched back, so the upper dielectric layer at this stage will cover the upper electrode 32a inside. The upper dielectric layer can be prepared using insulating films such as silicon oxide, silicon nitride, borophosphosilicate glass or undoped silicate glass. The upper dielectric layer is a component of the dielectric layer ox. At this time, the upper dielectric layer and the lower dielectric layer are fused into a whole, and they together constitute the dielectric layer ox, see Figure 4 and Figure 7 .

[0121] See also Figure 4, the first emitter region 13 and the contact region 12 can be electrically connected by a wire, a conductive strip, a metal conductive strip, a probe, a metal spring, or a bonding wire (interconnection structure 38 is used in this example). In this example, the interconnection structure 38 is, for example, a metal material filled inside a through hole (via) that passes through the dielectric layer ox. The metal material typically contains tungsten or copper or aluminum or a copper-aluminum alloy; or a lining layer such as titanium or titanium nitride is first sputtered or deposited on the side wall of the through hole, and then the metal material is filled in the through hole with the lining layer. As shown in the figure, the interconnection structure 38 passes through the dielectric layer ox and ohmically contacts the first emitter region 13 and the contact region 12 respectively. As shown in the figure, the example of the related through hole of the built-in interconnection structure 38 advocates forming a through hole at the position of the dielectric layer ox aligned with both the first emission area 13 and the contact area 12, and this through hole is defined as a common or shared through hole, and the metal material filled in this common or shared through hole will ohmically contact both the first emission area 13 and the contact area 12, that is, the interconnection structure 38 can ohmically contact both the first emission area 13 and the contact area 12 in this common or shared through hole. In other examples, it is necessary to form a sub-through hole that can be aligned with the first emission area 13 in the dielectric layer ox, and another sub-through hole that is aligned with the contact area 12 in the dielectric layer ox, and thereby prepare two sub-through holes that coexist at the same time. Then, when the metal material is filled in these two sub-through holes, two interconnection structures will be formed, and one of them contacts the first emission area 13, and the other contacts the contact area 12 accordingly. The two interconnection structures can be set to be connected to each other. The interconnection structure 38 replaces wire_1 and is regarded as a first signal terminal. Figure 6 The interconnection structure 38 is shown from the perspective of a top view. For example, in this embodiment, an interconnection structure 38 is provided that penetrates the dielectric layer at the center of the upper plate 32a and the lower plate 31, and the interconnection structure 38 is electrically connected to the first emitter region 13 and the contact region 12. In this embodiment, it is noted that a through hole for arranging the interconnection structure 38 is provided at the position of the dielectric layer ox above the first drift region 10.

[0122] See also Figure 4, the second emitter region 24 and the doped ring 22 can be electrically connected by a wire, a conductive strip, a metal conductive strip, a probe, a metal spring, or a bonding wire (interconnection structure 32b is used in this example). In this example, the interconnection structure 32b is a metal material filled inside a through hole (via) that passes through the dielectric layer ox. The metal material typically contains tungsten, copper, aluminum, or a copper-aluminum alloy; or a liner layer such as titanium or titanium nitride is first sputtered or deposited on the side wall of the through hole, and then the metal material is filled in the through hole with the liner layer. As shown in the figure, the interconnection structure 32b passes through the dielectric layer ox and ohmically contacts the second emitter region 24 and the doped ring 22 respectively. As shown in the figure, the example of the related through hole of the built-in interconnection structure 32b advocates forming a through hole at the position of the dielectric layer ox aligned with both the second emission region 24 and the doped ring 22, and this through hole is defined as a common or shared through hole, and the metal material filled in this common or shared through hole will ohmically contact both the second emission region 24 and the doped ring 22, that is, the interconnection structure 32b can ohmically contact both the second emission region 24 and the doped ring 22 in this common or shared through hole. In other examples, it is necessary to form a type of sub-through hole that can be aligned with the second emission region 24 in the dielectric layer ox, and another type of sub-through hole that is aligned with the doped ring 22 in the dielectric layer ox, and thereby prepare two types of sub-through holes that coexist at the same time. Then, when the metal material is filled in these two types of sub-through holes, two interconnection structures will be formed, and one of them contacts the second emission region 24, and the other contacts the doped ring 22 accordingly. The two types of interconnection structures can be set to be connected to each other. The interconnection structure 32b replaces wire_2 and can be regarded as the second signal terminal. Figure 6 The interconnection structure 32b is shown from the perspective of the top view. For example, in this embodiment, an interconnection structure 32b is provided that penetrates the dielectric layer at the outer sides of the upper plate 32a and the lower plate 31, and the interconnection structure 32b is electrically connected to the second emitter region 24 and the doping ring 22. In this embodiment, it is noted that a through hole for arranging the interconnection structure 32b is provided at the position of the dielectric layer ox above the second drift region 20. Such a through hole passes through the upper plate 32a or is close to the edge of the upper plate 32a during the preparation stage. Then, the metal material is filled in the through hole to prepare the interconnection structure 32b, so that the interconnection structure 32b in the through hole can be electrically connected to the upper plate 32a.

[0123] See also Figure 7The above text records the preparation of the dielectric layer ox and the preparation of some interconnect structures 38, 32b. As shown in the figure, in this example, a third metal layer can be further sputtered or deposited on the dielectric layer ox. For example, a third metal layer is generated on the dielectric layer by physical vapor deposition. Thereafter, the third metal layer is subjected to patterned etching treatment, and only the portion of the third metal layer that is specially reserved after the etching treatment, namely, the metal pads IO1 and IO2, is retained. The substrate of the pad, namely, the substrate of the third metal layer, can use a metal material such as copper or aluminum, or a copper-aluminum alloy. The third metal layer can also first deposit a titanium lining layer and then cover other metal materials on the titanium. The conductor material selection of the third metal layer is diverse. When the metal pads IO1 and IO2 are prepared from the aforementioned third metal layer, it is necessary to pay attention to the positional relationship of the reserved metal pads IO1-IO2.

[0124] See also Figure 7 , as mentioned above, the matters to be noted when the third metal layer is subjected to patterned etching and the metal pads are reserved are: the metal pad IO1 is aligned with the interconnection structure 38, and the metal pad IO2 is aligned with the interconnection structure 32b. That is, some reserved parts (used as IO1) retained by the etching of the third metal layer need to overlap with the interconnection structure 38, and other reserved parts (used as IO2) retained by the etching of the third metal layer need to overlap with the interconnection structure 32b. Then the result of the preparation is that the metal pad IO1 overlaps with the interconnection structure 38 below it and they are electrically connected to each other. At the same time, the result of the preparation makes the metal pad IO2 overlap with the interconnection structure 32b below it and they are electrically connected to each other. The other non-reserved parts of the third metal layer can be directly etched and removed. The metal pads IO1 and IO2 can be regarded as the first signal end and the second signal end mentioned above, respectively. The upper plate 32a of the capacitor is electrically connected to the metal pad IO2, but the lower plate of the capacitor is not directly electrically connected to any metal pad.

[0125] See also Figure 7 In an optional embodiment, a plurality of metal pads IO1, IO2, etc. are arranged on the surface or upper surface or top of the dielectric layer ox, and the metal pad IO1 is electrically connected to the first emission region 13 and the contact region 12 through an interconnection structure 38 of the dielectric layer ox penetrating the center of the upper plate 32a and the lower plate 31.

[0126] See also Figure 7 In an optional embodiment, a plurality of metal pads IO1, IO2, etc. are arranged on the surface, upper surface or top of the dielectric layer ox, and the metal pad IO2 is electrically connected to the doped ring 22, the second emitter region 24, and the upper plate 32a through an interconnection structure 32b that passes through the dielectric layer ox above the second drift region 20.

[0127] See also Figure 7In an optional embodiment, the capacitor with the lower plate 31 and the upper plate 32a has multiple charging paths and different types of charging sources are intertwined: for example, when the transient voltage triggers the PNP and NPN to turn on, part of the discharge current charges the capacitor, and the reverse current (such as entering from IO1) charges the capacitor. In addition, it is known that the previous text records that multiple first buried areas 14 form multiple diodes D1-D2 between the connecting ring 11. Note that when the capacitor is charged, the first buried area 14 and the second buried area 15 are reversely biased against each other. For example, the charging voltage of the capacitor is reversely applied between the first buried area 14 and the second buried area 15, then they are reversely biased against each other. In addition, it is known that the previous text records that when any diode (such as D1 or D2) is reversely broken down under the impact of the transient voltage, the breakdown current flowing through any diode flows to the substrate P-sub. At this time, any diode is in a reverse breakdown state, and the reverse breakdown state of any diode is interrupted by the aforementioned reverse bias caused by the capacitor voltage.

[0128] See also Figure 7 , assuming that any diode such as D1 is reversely broken down under the impact of transient voltage, the breakdown current flowing through any diode such as D1 flows to the substrate P-sub. At this time, the diode such as D1 is in a reverse breakdown state, but the reverse breakdown state of any diode such as D1 is interrupted by the aforementioned reverse bias caused by the capacitor voltage. In the integrated circuit, the voltage of the capacitor causes the first buried area 14 and the second buried area 15 to be reverse biased to each other and form a depletion layer between them, and even the voltage of the capacitor causes the first buried area 14 and the second buried area 15 to deplete each other and terminate the conduction of the diode D1. At this time, there is no longer any breakdown current flowing from the diode D1 to the substrate P-sub. Combined with Figure 4 . It is worth noting that the breakdown current flowing to the substrate is sufficient to guide PNP and NPN to turn on through the drainage effect of diode D1, and the conduction of PNP and NPN is not affected after the breakdown current flowing from diode D1 to the substrate is interrupted or stopped. It can be seen that the capacitor voltage is used to stop the current channel flowing from any diode D1 in the reverse breakdown state to the substrate P-sub. Any diode D1 is only reversely broken down and drained at the stage of forming the breakdown current flowing to the substrate P-sub, but after completing the drainage task, the current channel of any diode such as D1 itself is stopped. To protect the diode D1 from being damaged. The voltage of the capacitor is a low-frequency signal with a relatively stable ripple relative to the transient voltage.

[0129] See also Figure 7, assuming that any diode such as D2 is reversely broken down under the impact of transient voltage, the breakdown current flowing through any diode such as D2 flows to the substrate P-sub. At this time, the diode such as D2 is in a reverse breakdown state, but the reverse breakdown state of any diode such as D2 is interrupted by the aforementioned reverse bias caused by the capacitor voltage. In the integrated circuit, the voltage of the capacitor causes the first buried area 14 and the second buried area 15 to be reverse biased to each other and form a depletion layer between them, and even the voltage of the capacitor causes the first buried area 14 and the second buried area 15 to deplete each other and terminate the conduction of the diode D2. At this time, there is no longer any breakdown current flowing from the diode D2 to the substrate P-sub. Combined with Figure 4 It is worth noting that the breakdown current flowing to the substrate is sufficient to guide the PNP and NPN to turn on through the diversion effect of the diode D2, and the conduction of the PNP and NPN is not affected after the breakdown current flowing to the substrate from the diode D2 is interrupted or stopped. It can be seen that the capacitor voltage is used to stop the current channel flowing to the substrate P-sub from any diode D2 in the reverse breakdown state. The any diode D2 is only reversely broken down and diverted at the stage of forming the breakdown current flowing to the substrate P-sub, but after completing the diversion task, the current channel of any diode such as D2 itself is stopped. To protect the diode D2 from being damaged.

[0130] See also Figure 7 In an optional embodiment: a plurality of first buried regions respectively form a plurality of diodes perpendicular to the substrate with the connecting ring; when the capacitor is charged, the first and second buried regions are reverse biased with respect to each other, and if any diode is in or enters a reverse breakdown state, the reverse breakdown state of the any diode is interrupted by the reverse bias caused by the capacitor voltage. And in an optional embodiment: the capacitor voltage is used to terminate the current channel of the any diode in the reverse breakdown state flowing to the substrate, and the any diode is reversely broken down and diverted only at the stage of forming a breakdown current flowing to the substrate, and after completing the diversion task, the current channel of the any diode itself is terminated by the capacitor voltage.

[0131] See also Figure 7, triggering the integrated circuit to conduct and form the diodes D1-D2 of the discharge path, their circuit structure is a plurality of diodes perpendicular to the substrate. As the excitation module of the integrated circuit conduction, the plurality of diodes are only broken down in the excitation stage to conduct current, forming a current flowing to the substrate and stimulating the PNP / NPN to conduct. After the transistor is excited and turned on, the diodes are allowed not to bear the large current of the discharge task, and the diode excitation function is maintained. When the expansion dock continues to insert other devices, the conduction excitation function of the diodes D1-D2 can still be re-enabled. The excitation function of the diode and the excitation exit mechanism ensure that the expansion dock can continuously insert an unlimited number of devices. If the diode lacks an exit mechanism, it will be damaged under the impact of the single hot plug backflow current with a large power of the expansion dock, and the subsequent power impact of the expansion dock plugging and unplugging again will not be able to continue to stimulate the integrated circuit to conduct and enable the discharge function. When the diode is reversely broken down, it corresponds to the excited state that starts the integrated circuit to conduct, and the reverse breakdown state of the diode is interrupted by the reverse bias caused by the capacitor voltage, which corresponds to the exit mechanism of the diode after excitation. In addition, the solution of the present application that the greater the transient voltage caused by the hot plug event, the more diodes are reversely broken down, which just fits the advantage of the greater the power impact and the greater the discharge current.

[0132] See also Figure 7 In an optional embodiment: a plurality of first buried regions respectively form a plurality of diodes perpendicular to the substrate with the connecting ring; when the capacitor is charged, the first and second buried regions are reverse biased with respect to each other, and if any diode is in or enters a reverse breakdown state, the reverse breakdown state of the any diode is interrupted by the reverse bias caused by the capacitor voltage. And in an optional embodiment: the capacitor voltage is used to terminate the current channel of the any diode in the reverse breakdown state flowing to the substrate, thereby preventing the current difference between a pair of transistors (PNP / NPN), i.e., the differential current, from being transferred to the any diode, and preventing the differential current caused by the current mismatch between the pair of transistors (PNP / NPN) from flowing to the any diode and damaging the any diode.

[0133] See also Figure 7 It is worth noting that two transistors can be combined into a dual current discharge path, which has the advantage of being able to offset transient high power more quickly, but there is also a current mismatch problem between this group of transistors. The most typical external concern of the current mismatch problem is that the current difference between the two transistors is too large, and the difference current between the two transistors is forced to be transferred to the diodes D1-D2 connected in series and parallel with the two transistors. Figure 4This article can effectively suppress the excessive overcurrent phenomenon, that is, the differential current that damages the diodes D1-D2, and ensure that they are not damaged. If the diodes lack a protection mechanism, they will be damaged in the accidental current mismatch event of the continuous power shock of the docking station. Then, the power shock of the subsequent docking station plugging and unplugging will not continue to stimulate the integrated circuit to turn on and enable the discharge function.

[0134] See also Figure 7 The integrated circuit includes an extended plate 31P with a ring structure, and the integrated circuit includes a buffer ring 40 implanted on the front side of the substrate and wrapped around the outside of the second groove 55. The positional relationship and contour of the buffer ring 40 wrapped around the outside of the second groove can be referred to Figure 7 The annular structure (ring) of the buffer ring 40 can be referred to Figure 7 The schematic diagram of the integrated circuit structure is shown in FIG. The buffer ring 40 is of the second conductivity type, such as the N conductivity type. The local area of ​​the extended plate 31P substantially overlaps with the buffer ring 40, which is also a ring frame. Figure 8 shown.

[0135] See also Figure 7 The outer edge of the extended plate 31P is disposed above the buffer ring 40, and the inner edge of the extended plate 31P is disposed above the insulator in the second groove 55. The extended plate 31P contacts the buffer ring 40 and is electrically connected to the buffer ring 40 as shown in the figure. Figure 8 When the capacitor with the lower plate 31 and the upper plate 32a is charged, the voltage drop of the extended plate 31P electrically connected to the lower plate 31 causes the buffer ring 40 to be exhausted.

[0136] See also Figure 7 , the outer edge of the extended plate 31P is extended or stretched outward relative to the outer side wall 55b of the second groove 55, so that the outer edge of the extended plate 31P contacts and touches the buffer ring 40. The outer edge of the extended plate is extended outward, which means that the outer edge is extended or stretched outward from the extended plate. As shown in the figure, the outer edge of the extended plate 31P is outside the outer side wall 55b of the second groove 55. Figure 8 shown.

[0137] See also Figure 7, the inner edge of the extended plate 31P is contracted or retracted toward itself relative to the inner sidewall 55a of the second groove 55 to prevent the inner edge of the extended plate 31P from contacting the second drift layer 20. For example, the retraction or retraction can prevent the extended plate 31P from contacting the doping ring 22 of the second drift layer 20. The inner edge of the extended plate contracts inwardly means that the inner edge contracts or retracts toward the extended plate itself. As shown in the figure, the inner edge of the extended plate 31P is on the inner side of the outer sidewall 55b of the second groove 55, and the inner sidewall 55a of the second groove 55 is on the inner side of the inner edge of the extended plate 31P, that is, the inner edge of the extended plate 31P is on the outer side of the inner sidewall 55a of the second groove 55.

[0138] See also Figure 8 , the extended plate 31P and the lower plate 31 can be electrically connected by wires, or conductive strips, metal conductive strips, or probes, or metal springs, or bonding wires (such as using the interconnection plate 44). In an optional embodiment: for example, an interconnection structure 31C can be prepared to align with and electrically connect to the lower plate 31, and an interconnection structure 31D can also be prepared to align with and electrically connect to the extended plate 31P, and the interconnection plate 44 is electrically connected to the interconnection structure 31C and the interconnection structure 31D, thereby achieving electrical connection between the extended plate 31P and the lower plate 31. In an alternative embodiment where the interconnection structure is not used: for example, the interconnection structures 31C and 31D are no longer prepared, and the interconnection plate 44 is prepared together with the extended plate 31P and the lower plate 31. For example, they are all parts specially reserved for the patterned etching process of the first metal layer. At this time, the three of them are naturally electrically connected together, and they are actually different segments of the same metal layer. In order to avoid short circuit, an insulating isolation layer can be formed between the interconnection plate 44 and the second drift layer 20 to avoid short circuit between the interconnection plate 44 and the second drift layer 20 below it. For example, the insulating material in the first trench 50 and the second trench 55 is formed by first filling and then etching back, so when etching back the insulating material deposited on the substrate surface, a part of the deposited insulating material can be reserved above the second drift layer 20, and this part of the reserved insulating material can be regarded as an insulating isolation layer formed between the interconnection plate 44 and the second drift layer 20. A single interconnection plate 44 is shown in the figure, and a plurality of interconnection plates 44 can actually be prepared.

[0139] See also Figure 7, regarding the method for preventing backflow of current in the expansion dock, the integrated circuit described above is used to suppress the backflow current induced by the power terminal voltage difference between the first device and the second device inserted into the expansion dock (for example, the power terminal voltage difference between V1 and V2 mentioned above). The integrated circuit will not be described separately. The method for preventing backflow of current includes configuring a first signal terminal such as wire_1 or IO1 at the first emission area 13 and the contact area 12, and the method includes configuring a second signal terminal such as wire_2 or IO2 at the second emission area 24 and the doping ring 22. It is necessary to couple the power terminal voltages of the first device and the second device, such as V1 and V2, to the first signal terminal, and the coupling mode includes a direct connection mode, a resistance connection mode, or an indirect connection mode through a capacitor, etc. When the first device and the second device are inserted into the expansion dock, a pulse transient voltage jump is generated due to the power terminal voltage difference between the first device and the second device, such as V1 and V2, respectively, a conductive path or a discharge path is formed between the first signal terminal and the second signal terminal of the integrated circuit to absorb the backflow current. For example, a conduction path or a discharge path is formed between wire_1 (or IO1) and wire_2 (or IO2) to absorb the backflow current. The conduction path of PNP / NPN can be regarded as a discharge path. Thus, the integrated circuit is used to absorb the power impact of the transient voltage, and the discharge current of the integrated circuit that discharges the transient voltage is output from the second signal terminal wire_2 (or IO2). In this way, the backflow current induced by the voltage difference between the power supply terminals of the first device and the second device inserted into the docking station is suppressed. There are many ways to suppress the backflow current in the integrated circuit: on the one hand, the integrated circuit absorbs the backflow current to charge the capacitor, and on the other hand, the conduction path of PNP / NPN can release the backflow current.

[0140] See also Figure 7 In an optional embodiment: the integrated circuit includes an annular extended plate, including a buffer ring implanted on the front side of the substrate and wrapped around the outside of the second groove; the outer edge of the extended plate is arranged above the buffer ring, the inner edge of the extended plate is arranged above the insulator in the second groove, the extended plate contacts and is electrically connected to the buffer ring, and the buffer ring is of the second conductivity type; when the capacitor is charged, the voltage drop of the extended plate electrically connected to the lower plate causes the buffer ring to be completely exhausted. And in an optional embodiment: the buffer ring is exhausted by the voltage drop of the capacitor voltage, avoiding the accumulation of an electric field strength that reaches an avalanche condition between the first drift layer and the substrate, and preventing the depletion layer between the first drift layer and the substrate from expanding to penetrate the second drift layer and cut off the discharge path. For example, the conductive path or discharge path (PNP / NPN) formed between the first signal terminal and the second signal terminal of the integrated circuit is prevented from being cut off, and the partial penetration or complete penetration of the second drift layer will cause the current of the PNP / NPN transistor to be reduced or even completely cut off.

[0141] See also Figure 7 The advantage at this time is reflected in the semiconductor structure deployed in the integrated circuit, which is designed to reasonably disperse the electric field strength at the edge of the main node in the integrated circuit. For example, based on the buffer ring 40, the semiconductor layout of the integrated circuit actually plays a role in widening the main junction depletion region outward, reducing the electric field concentration intensity in the integrated circuit and ultimately improving the breakdown voltage of the integrated circuit when facing the continuous hot plugging event of the expansion dock, that is, improving the resistance level.

[0142] See also Figure 7 In an optional embodiment, a Cartesian coordinate system with abscissa Ele and ordinate Dep indicates that the extended plate 31P and the buffer ring 40 are not used: the abscissa Ele is the electric field strength and the ordinate Dep is the depth. It is found that the highest value of the electric field strength inside the integrated circuit device appears in the dielectric or insulator at the corner of the top of the first trench 50 on the main junction side (represented by the node position N1), and it is found that the highest value of the electric field strength in the silicon-based material or semiconductor material inside the integrated circuit device appears at the corner between the side wall and the bottom of the first trench 50 near the main junction side (at this time, the highest electric field strength in the silicon base is represented by a different node position N2). When a reverse bias is applied, the aforementioned field strength of the main junction between the first drift layer and the substrate will be higher than other places. An overly strong or narrowed electric field at a certain place will cause device breakdown or avalanche. A more negative impact is that the second drift layer 20 is even penetrated to cut off the discharge path or conduction path of the PNP / NPN. The present application designs that the extended plate 31P contacts and is electrically connected to the buffer ring 40. When the capacitor is charged, the voltage drop (i.e., the capacitor voltage) of the extended plate 31P electrically connected to the lower plate 31 causes the buffer ring 40 to be completely exhausted. At this time, in a preferred embodiment: the buffer ring 40 is exhausted because it carries or shares the voltage drop of the capacitor voltage. The capacitor voltage is no longer just reverse biased against the main junction. The receiving function of the buffer ring 40 can prevent the electric field strength between the first drift layer 10 and the substrate P-sub from accumulating to reach avalanche breakdown. Due to the buffering of the depletion layer between the buffer ring 40 and the substrate P-sub, the electric field line profile of the second drift 20 previously affected by the narrowing of the main junction or the excessive accumulation of the field strength is adjusted. The buffering effect can effectively prevent the depletion layer between the first drift layer 10 and the substrate P-sub from expanding to penetrate the second drift layer 20, thereby effectively avoiding the interruption of the discharge path or conduction path of the PNP / NPN.

[0143] See also Figure 8 , and based on Figure 7The advantages of this application include that the integrated circuit forms a conductive path to absorb the backflow current, the integrated circuit absorbs the power impact of the transient voltage, and provides a discharge path for discharging the transient voltage. After the transistor is excited and turned on, the diode is allowed to not bear the large current that implements the discharge task, keeping its function intact. The electric field strength at the edge of the main node in the integrated circuit is reasonably dispersed, and the semiconductor layout of the integrated circuit actually plays the role of widening the main junction depletion region outward, reducing the electric field concentration intensity in the integrated circuit and ultimately increasing the breakdown voltage of the integrated circuit when facing the continuous hot plug event of the expansion dock, that is, improving the resistance level against power impact.

[0144] The above description and drawings provide typical embodiments of specific structures of specific embodiments. The above application proposes existing preferred embodiments, but these contents are not intended to be limiting. For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the attached claims should be regarded as covering all changes and modifications to the true intention and scope of the present application. Any and all equivalent scopes and contents within the scope of the claims should be considered to still be within the intention and scope of the present application.

Claims

1. An integrated circuit, characterized in that: include: A first and a second groove are formed in a ring shape and are opened on the front surface of a substrate, the first groove is located inside the second groove, the substrate is of a first conductivity type, and the first and the second grooves are filled with an insulating material; A first drift layer implanted on the front side of the substrate and located inside the first trench, and a second drift layer implanted on the front side of the substrate and located between the first trench and the second trench, wherein both the first and second drift layers are of the second conductivity type; A second conductive type connecting ring implanted in the first drift layer and wound inside the top of the first trench, a first emitter region and a contact region implanted in the first drift layer and located inside the connecting ring, the first emitter region being of the first conductive type and the contact region being of the second conductive type; A doped ring of the first conductivity type implanted in the second drift layer and wound around the inner side of the second trench, and a second emitter region implanted in the second drift layer and wound around the outer side of the first trench, wherein the second emitter region is of the second conductivity type; A plurality of first buried regions and a plurality of second buried regions are arranged in the first drift layer and below the connecting ring. The alternating first buried regions and second buried regions are both arranged in strips. The first buried regions are of the first conductivity type and the second buried regions are of the second conductivity type.

2. The integrated circuit according to claim 1, characterized in that: The first emitter region and the contact region are both defined as a first signal terminal, and the second emitter region and the doped ring are both defined as a second signal terminal; A transient voltage is input from the first signal terminal, and the integrated circuit absorbs the power impact of the transient voltage and outputs a discharge current for discharging the transient voltage from the second signal terminal.

3. The integrated circuit according to claim 2, characterized in that: A plurality of diodes perpendicular to the substrate are formed between the plurality of first buried regions and the connecting rings respectively. When any diode is reversely broken down under the impact of the transient voltage, the breakdown current flowing through the any diode flows toward the substrate, forming a discharge path of the transistor based on the first emitter region, the first drift layer, and the substrate, and a discharge path of the transistor based on the connecting ring, the substrate, and the second emitter region for the discharge current.

4. The integrated circuit according to claim 2, characterized in that: A plurality of first buried regions and the connecting rings respectively form a plurality of diodes perpendicular to the substrate; The doping concentrations of the plurality of first buried regions are set equal, so that the breakdown voltages of the plurality of diodes when reversely broken down are all set to be the same, wherein the plurality of diodes are not reversely broken down synchronously or are reversely broken down synchronously; or The doping concentrations of the plurality of first buried regions are all different, so that the breakdown voltages of the plurality of diodes when they are reversely broken down are all set to be different, wherein the greater the transient voltage is, the greater the number of the diodes that are reversely broken down is.

5. The integrated circuit according to claim 1, characterized in that: It also includes a dielectric layer covering the front side of the substrate and an annular upper electrode plate and a lower electrode plate wrapped in the dielectric layer; The outer edge of the lower electrode plate is disposed above the insulator in the first groove, the inner edge of the lower electrode plate is disposed above the connecting ring, and the lower electrode plate is in contact with the connecting ring and is electrically connected thereto; The upper electrode plate is spaced apart from the lower electrode plate and at least a partial area of ​​the upper electrode plate overlaps with the lower electrode plate below, and the upper electrode plate is electrically connected to the doping ring and the second emission region; A capacitor is formed by an upper plate, a lower plate, and a portion of a dielectric layer located between the upper plate and the lower plate.

6. The integrated circuit according to claim 5, characterized in that: A plurality of metal pads are arranged on the surface of the dielectric layer, and at least one of the metal pads is electrically connected to the first emitter region and the contact region through an interconnection structure penetrating the dielectric layer at the center of the upper electrode plate and the lower electrode plate; as well as At least one other metal pad is electrically connected to the doped ring, the second emitter region, and the upper plate through an interconnection structure penetrating the dielectric layer above the second drift region.

7. The integrated circuit according to claim 5, characterized in that: A plurality of first buried regions and the connecting rings respectively form a plurality of diodes perpendicular to the substrate; When the capacitor is charged, the first and second buried regions are reverse biased with respect to each other, and if any diode is in a reverse breakdown state, the reverse breakdown state of the diode is interrupted by the reverse bias caused by the capacitor voltage.

8. The integrated circuit according to claim 5, characterized in that: It also includes an annular extended plate and a buffer ring implanted on the front side of the substrate and wrapped around the outside of the second groove; The outer edge of the extended plate is disposed above the buffer ring, the inner edge of the extended plate is disposed above the insulator in the second groove, the extended plate is in contact with and electrically connected to the buffer ring, and the buffer ring is of the second conductivity type; When the capacitor is charged, the voltage drop across the extended plate electrically connected to the lower plate causes the buffer ring to be completely depleted.

9. The integrated circuit according to claim 1, characterized in that: The first conductivity type is a P conductivity type and the second conductivity type is an N conductivity type.

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