Back contact battery and manufacturing method thereof, photovoltaic module

Abstract

The present invention discloses a back contact battery and a manufacturing method thereof, and a photovoltaic module, which relate to the field of photovoltaic technology, so as to form a minority carrier inversion layer at the edge portion of the first surface through a majority carrier passivation layer, and reduce the carrier recombination at the edge portion of the first surface by setting a majority carrier passivation layer with a larger thickness in a non-electrode collection area. The back contact battery includes a semiconductor substrate, a first doped semiconductor part, a second doped semiconductor part, and a majority carrier passivation layer. The first surface includes a non-electrode collection area located at the edge, and an electrode collection area located inside the non-electrode collection area. The electrode collection area includes a minority carrier area and a majority carrier area alternately spaced along a first direction. Along the first direction, the minority carrier area located at the most edge is closer to the non-electrode collection area than the majority carrier area located at the most edge. The first doped semiconductor part is arranged in the majority carrier area. The second doped semiconductor part is arranged in the minority carrier area. The majority carrier passivation layer is arranged in the non-electrode collection area. The thickness of the majority carrier passivation layer is greater than the thickness of the second doped semiconductor part.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a back contact cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] A solar cell is a device that can convert sunlight into electrical energy. Specifically, when the solar cell is in operation, sunlight shines on the semiconductor pn junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field of the pn junction, photogenerated holes flow to the p region, and photogenerated electrons flow to the n region. When the circuit is connected, current can be generated. Among them, a solar cell in which both the positive electrode and the negative electrode are on the back of the cell is a back-contact cell. Compared with a double-sided contact solar cell, the front of the back-contact cell is not blocked by a metal electrode, so that the light-facing side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, and is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0003] However, in the existing back contact battery, the minority carrier collection efficiency at the edge portion located on the backlight side is low, which is not conducive to improving the working efficiency of the back contact battery. Summary of the invention

[0004] The object of the present invention is to provide a back-contact cell and a method for manufacturing the same, as well as a photovoltaic module, so as to form a minority carrier inversion layer on the inner side of a semiconductor substrate at the edge portion of a first surface through a majority carrier passivation layer. Under the action of the electric field generated by the majority carrier passivation layer, the minority carrier inversion layer repels photogenerated minority carriers, so that the minority carriers on the inner side of the semiconductor substrate at the edge portion of the first surface are accelerated to be transmitted to the adjacent second doped semiconductor portion, which is beneficial to improving the collection efficiency of the second doped semiconductor portion for the minority carriers generated near the edge portion of the first surface, and by arranging a thicker majority carrier passivation layer in the non-electrode collection area to further reduce the carrier recombination at the edge portion of the first surface, the working efficiency of the back-contact cell is improved.

[0005] In order to achieve the above-mentioned objectives, in a first aspect, the present invention provides a back-contact battery, which includes: a semiconductor substrate, a first doped semiconductor portion, a second doped semiconductor portion, and a majority carrier passivation layer. The semiconductor substrate has a first surface and a second surface opposite to each other. The first surface includes a non-electrode collection area located at the edge, and an electrode collection area located inside the non-electrode collection area. The electrode collection area includes a minority carrier area and a majority carrier area alternately spaced along a first direction. Along the first direction, the minority carrier area located at the edge is closer to the non-electrode collection area than the majority carrier area located at the edge. The first doped semiconductor portion is arranged in the majority carrier area. The second doped semiconductor portion is arranged in the minority carrier area. The conductivity type of the second doped semiconductor portion is opposite to that of the first doped semiconductor portion. The majority carrier passivation layer is arranged in the non-electrode collection area. The thickness of the majority carrier passivation layer is greater than the thickness of the second doped semiconductor portion.

[0006] In the case of adopting the above technical solution, in the back contact battery provided by the present invention, the first surface of the semiconductor substrate includes a non-electrode collection area located at the edge, and an electrode collection area located inside the non-electrode collection area. The above-mentioned non-electrode collection area refers to: the majority carrier passivation layer and other structures with conductive properties arranged on the non-electrode collection area are not electrically connected to the conductive electrode, electrode mesh or welding strip and other interconnection structures, which can ensure that the majority carriers gathered inside the majority carrier passivation layer generate an electric field and form a minority carrier inversion layer on the inner side of the semiconductor substrate at the edge part, and the above-mentioned electrode collection area refers to: the first doped semiconductor part and the second doped semiconductor part and other structures with conductive properties arranged on the electrode collection area need to be electrically connected to the conductive electrode, electrode mesh or welding strip and other interconnection structures to lead out the majority carriers (which can be referred to as majority carriers) or minority carriers (which can be referred to as minority carriers) collected by themselves, which is conducive to the formation of photocurrent. It can be understood that the structure provided on the above-mentioned non-electrode collection area and the structure provided on the electrode collection area are electrically insulated to prevent the structure provided on the non-electrode collection area from being electrically connected to the above-mentioned conductive electrode, electrode mesh or welding strip and other interconnection structures through the structure provided on the electrode collection area. In addition, the above-mentioned electrical connection method does not include electrical connection achieved through the semiconductor substrate. In the above case, the area located at the edge of the first surface is the non-electrode collection area. Such a setting can prevent the second doped semiconductor part provided in the minority carrier area adjacent to the non-electrode collection area from being electrically connected to the side of the semiconductor substrate of the opposite conductivity type through the majority carrier passivation layer provided in the non-electrode collection area due to the existence of factors such as winding plating, that is, to prevent edge overlap short circuit, so that the back contact battery has higher electrical reliability.

[0007] Secondly, along the first direction, the minority carrier region located at the outermost edge is closer to the non-electrode collection region than the majority carrier region located at the outermost edge. At this time, along the first direction, the film layers adjacent to the outer non-electrode collection region are all second doped semiconductor parts. Since the second doped semiconductor part is arranged in the minority carrier region, the second doped semiconductor part is the emitter of the back contact battery. Based on this, when along the first direction, the film layers adjacent to the outer non-electrode collection region are all second doped semiconductor parts, the area proportion of the emitter within the range close to the non-electrode collection region on the first surface can be increased, so that the transmission distance of the minority carriers located at the edge of the semiconductor substrate to the emitter becomes shorter, which is beneficial to improve the collection efficiency of the emitter region for the minority carriers at the edge of the semiconductor substrate and suppress the recombination of carriers at the edge of the semiconductor substrate. Furthermore, the conductivity type of the majority carrier passivation layer arranged in the non-electrode collection area is opposite to the conductivity type of the second doped semiconductor part arranged in the minority carrier area. At the same time, the majority carrier passivation layer is not electrically connected to the above-mentioned conductive electrode and other interconnection structures. Therefore, the majority carriers in the majority carrier passivation layer can be enriched on the inner side of the semiconductor substrate within the non-electrode collection area to form a minority carrier inversion layer. At this time, the minority carriers located at the edge portion of the semiconductor substrate are repelled by the minority carrier inversion layer, so that the minority carriers on the inner side of the semiconductor substrate at the edge portion of the first surface are accelerated to be transmitted to the adjacent second doped semiconductor part, making it easier to be collected by the second doped semiconductor part adjacent to the non-electrode collection area and timely exported, thereby further improving the collection efficiency of the emitter region for the minority carriers at the edge portion of the semiconductor substrate and improving the working efficiency of the back contact battery. In addition, the field passivation effects of the majority-substrate passivation layer and the second doped semiconductor portion on the semiconductor substrate are respectively proportional to their own thicknesses. Therefore, when the thickness of the majority-substrate passivation layer arranged in the non-electrode collection area is greater than the thickness of the second doped semiconductor portion, the majority-substrate passivation layer has a higher field passivation effect on the non-electrode collection area, reducing the number of defects in the non-electrode collection area located at the edge of the first surface, and further improving the working efficiency of the back contact battery.

[0008] As a possible implementation solution, along the first direction, the width of the non-electrode collecting region is smaller than the width of the minority carrier region.

[0009] When the above technical solution is adopted, as mentioned above, structures such as the majority carrier passivation layer and having conductive characteristics arranged on the non-electrode collection area are not electrically connected to interconnection structures such as conductive electrodes, electrode meshes or welding strips. At this time, the majority carriers collected by structures such as the majority carrier passivation layer and having conductive characteristics arranged on the non-electrode collection area cannot be extracted, affecting the collection efficiency of majority carriers of the back contact battery. Based on this, when the width of the non-electrode collection area is smaller than the width of the minority carrier area along the first direction, it is beneficial to reduce the proportion of the non-electrode collection area on one side of the first surface from which the majority carriers cannot be extracted, so that the proportion of the electrode collection area co-located on the first surface with the non-electrode area collection is relatively large, thereby improving the collection efficiency of minority carriers and majority carriers of the back contact battery, and further improving the working efficiency of the back contact battery.

[0010] As a possible implementation scheme, along the first direction, the width of the non-electrode collecting area is less than 1000 μm. The preferred range of the width of the non-electrode collecting area is 100 μm to 250 μm. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect that along the first direction, the width of the non-electrode collecting area is less than the width of the minority carrier area described above, and will not be repeated here.

[0011] As a possible implementation scheme, in the first surface, the non-electrode collecting area is further arranged outside the electrode collecting area along a second direction. The second direction is different from the first direction.

[0012] When the above technical solution is adopted, the majority carrier passivation layer can also be arranged outside the electrode collection area along the second direction, which is beneficial to improve the collection efficiency of minority carriers of the edge of the emitter region along the second direction to the edge of the semiconductor substrate, and further inhibit the recombination of carriers at the edge of the semiconductor substrate. In addition, because the majority carrier passivation layer has a higher field passivation effect on the non-electrode collection area, when the non-electrode collection area is also arranged outside the electrode collection area along the second direction, it can also improve the passivation effect of the edge portion of the first surface along the second direction, reduce the number of defects in the non-electrode collection area located at the edge of the first surface, and further improve the working efficiency of the back contact battery.

[0013] As a possible implementation solution, the second direction is perpendicular to the first direction.

[0014] When the above technical solution is adopted, in the actual application process, the shape of the first surface of the semiconductor substrate is usually a rectangle or a rectangle with a chamfer. Based on this, when the above second direction is perpendicular to the first direction, it is beneficial to make the distribution of the minority carrier region and the majority carrier region more matched with the shape of the first surface of the semiconductor substrate, and then it is beneficial to further improve the first doped semiconductor part arranged in the minority carrier region and the second doped semiconductor part arranged in the majority carrier region. The efficiency has a higher carrier collection efficiency, and it can also reduce the difficulty of interconnecting different back contact batteries. In addition, when the second direction is perpendicular to the first direction, it is beneficial to make the non-electrode collection area just completely located at each part of the edge of the first surface, increase the proportion of the non-electrode collection area in the edge part of the first surface, further reduce the number of defects in the non-electrode collection area located at the edge of the first surface, and further improve the working efficiency of the back contact battery.

[0015] As a possible implementation scheme, the width of the non-electrode collection area along the second direction is less than or equal to the width of the non-electrode collection area along the first direction. In this case, while ensuring that the non-electrode collection area at the edge of the first surface along the second direction corresponds to a lower carrier recombination rate under the field passivation effect of the majority carrier passivation layer, the proportion of the non-electrode collection area along the second direction that cannot derive the majority carriers is reduced, so that the proportion of the electrode collection area co-located on the first surface with the non-electrode area collection is relatively large, thereby improving the collection efficiency of minority carriers and majority carriers of the back contact battery, and further improving the working efficiency of the back contact battery. In addition, the risk of interconnection structures such as solder strips interconnecting different back contact batteries being short-circuited through the multi-carrier passivation layer due to the non-electrode collection area also being arranged outside the electrode collection area along the second direction can also be reduced, ensuring that the back contact battery has a high electrical reliability.

[0016] As a possible implementation, the multi-sub passivation layer includes a third doped semiconductor portion disposed on the non-electrode collection region, the third doped semiconductor portion has the same conductivity type as the first doped semiconductor portion, and the material of the third doped semiconductor portion is the same as that of the first doped semiconductor portion.

[0017] In the case of adopting the above technical solution, the above third doped semiconductor part has the same conductivity type as the first doped semiconductor part, which can achieve the enrichment of majority carriers in the majority carrier passivation layer, which is conducive to the formation of a minority carrier inversion layer in the non-electrode collection area, and ensures that the second doped semiconductor part adjacent to the non-electrode collection area has a higher minority carrier collection efficiency. In addition, when the third doped semiconductor part has the same conductivity type as the first doped semiconductor part, and the material of the third doped semiconductor part is the same as the material of the first doped semiconductor part, the third doped semiconductor part and the first doped semiconductor part can be formed simultaneously based on the same material and through the same operation steps, which can not only ensure that the etching amount when forming the first doped semiconductor part is reduced and the manufacturing efficiency of the back contact battery is improved, but also prevent the etchant when additionally forming one of the third doped semiconductor part and the first doped semiconductor part from affecting the other, ensuring that the first doped semiconductor part has a higher carrier collection efficiency, and the third doped semiconductor part has a higher passivation effect on the non-electrode collection area, further improving the working performance of the back contact battery.

[0018] As a possible implementation scheme, the above-mentioned back contact cell further includes a hydrogen-containing passivation layer. The hydrogen-containing passivation layer is arranged on the side of the majority passivation layer away from the semiconductor substrate.

[0019] When adopting the above technical solution, the presence of the hydrogen-containing passivation layer can not only further passivate the non-electrode collection area, thereby further reducing the carrier recombination rate in the non-electrode collection area, but also prevent the etchant performing the patterning process from affecting the majority-carrier passivation layer located underneath it when manufacturing the second doped semiconductor part or electrode and other structures, thereby ensuring that the majority-carrier passivation layer has a higher passivation effect on the non-electrode collection area and the enrichment effect of the majority-carrier passivation layer on the majority carriers, thereby further improving the working performance of the back contact battery.

[0020] As a possible implementation scheme, in the first surface, the area located between the majority sub-region and the minority sub-region along the first direction is the spacing region. The first doped semiconductor part is also arranged on the spacing region. The second doped semiconductor part also extends to cover the top of the part of the first doped semiconductor part corresponding to the spacing region. In the spacing region, the second doped semiconductor part and the first doped semiconductor part are arranged at intervals along the thickness direction of the semiconductor substrate. In this case, the first doped semiconductor part and the second doped semiconductor part have a larger area ratio on one side of the first surface, which can reduce the etching amount when the first doped semiconductor material (used to manufacture the first doped semiconductor part) and the second doped semiconductor material (used to manufacture the second doped semiconductor part) arranged in the whole layer are selectively etched, thereby improving the manufacturing efficiency of the back contact battery.

[0021] As a possible implementation scheme, when the back contact battery further includes a hydrogen-containing passivation layer, at least part of the hydrogen-containing passivation layer is integrally continuous with the second doped semiconductor portion. In this case, it is possible to ensure that the etching amount when the second doped semiconductor material disposed in the entire layer is further reduced when being selectively etched, thereby improving the manufacturing efficiency of the back contact battery, and it is also beneficial to prevent the etchant from damaging the corresponding passivation structure (such as the multi-sub passivation layer, etc.) located at the edge and side of the semiconductor substrate in order to remove the portion of the second doped semiconductor material corresponding to the non-electrode collection area, thereby ensuring that the edge and side of the semiconductor substrate have a good passivation effect.

[0022] As a possible implementation solution, the surface of the non-electrode collecting area is a polished surface.

[0023] When the above technical solution is adopted, in the actual manufacturing process, the deposited film thickness of the multi-carrier passivation layer is inversely proportional to the specific surface area of ​​the non-electrode collection area where it is located, and the passivation effect of the multi-carrier passivation layer on the non-electrode collection area is proportional to its own deposition thickness. Based on this, compared with the velvet surface, when the surface of the non-electrode collection area is a polished surface, the surface of the non-electrode collection area is relatively flat, which is conducive to increasing the deposited film thickness of the multi-carrier passivation layer on the non-electrode collection area, and then it is conducive to improving the passivation effect of the multi-carrier passivation layer on the non-electrode collection area. In addition, compared with the velvet surface, the polished surface has fewer defect recombination centers, which can further reduce the carrier recombination rate at the edge of the first surface.

[0024] As a possible implementation solution, the surface of the minority carrier region is a suede surface.

[0025] When the above technical solution is adopted, the second doped semiconductor part is arranged in the minority carrier area. The surface of the minority carrier area is a velvet surface with a large specific surface area. At this time, compared with the polished surface, the deposited film thickness of the second doped semiconductor part on the velvet surface is relatively small, ensuring that the thickness of the majority carrier passivation layer arranged in the non-electrode collection area can be greater than the thickness of the second doped semiconductor part arranged in the minority carrier area, ensuring that the non-electrode collection area has a higher passivation effect. In addition, the velvet surface has a large specific surface area, which is conducive to making the side of the second doped semiconductor part formed on the minority carrier area away from the semiconductor substrate also have a large specific surface area, which is conducive to increasing the contact area between the second doped semiconductor part and the corresponding conductive electrode, and improving the contact performance between the two.

[0026] As a possible implementation scheme, the multi-sub passivation layer includes a doped polysilicon layer. In this case, in the actual application process, compared with the doped amorphous silicon layer, the thickness of the doped polysilicon layer is larger, so when the multi-sub passivation layer includes a doped polysilicon layer, it is beneficial to make the multi-sub passivation layer have a larger thickness, further improving the passivation effect of the multi-sub passivation layer on the non-electrode collection area.

[0027] As a possible implementation, the second doped semiconductor portion includes at least one of a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer. In this case, compared with the doped polycrystalline silicon layer, the thickness of the doped amorphous silicon layer is relatively small, so when the second doped semiconductor portion includes a doped amorphous silicon layer, the difficulty of manufacturing a multi-sub passivation layer having a thickness greater than that of the second doped semiconductor portion can be reduced, which is conducive to improving the yield of the back contact battery.

[0028] As a possible implementation scheme, the conductivity type of the majority-sub passivation layer is N-type, and the conductivity type of the second doped semiconductor portion is P-type.

[0029] As a possible implementation solution, the above-mentioned back contact battery further includes a first interface passivation layer, and the first interface passivation layer is arranged between the semiconductor substrate and the first doped semiconductor part.

[0030] When the above technical solution is adopted, the passivation contact structure composed of the first interface passivation layer and the first doped semiconductor part has an excellent interface passivation effect, and can realize the selective collection of carriers, at least reduce the carrier recombination rate of the multi-sub-region of the first surface, and further improve the photoelectric conversion efficiency of the back contact battery.

[0031] As a possible implementation solution, the above-mentioned back contact battery further includes a second interface passivation layer, and the second interface passivation layer is at least arranged between the semiconductor substrate and the second doped semiconductor part.

[0032] When the above technical solution is adopted, the passivation contact structure composed of the second interface passivation layer and the second doped semiconductor portion located on the second region can realize the selective collection of carriers and reduce the carrier recombination rate of the minority carrier region of the first surface.

[0033] As a possible implementation scheme, when the back contact cell further includes a first interface passivation layer and a second interface passivation layer, the first interface passivation layer and the first doped semiconductor portion constitute a first passivation contact structure, and the second interface passivation layer and the second doped semiconductor portion constitute a second passivation contact structure. The first passivation contact structure and the second passivation contact structure have different passivation contact types; and / or the first passivation contact structure is a tunneling passivation contact structure; and / or the second passivation contact structure is a heterogeneous contact structure.

[0034] In the case of adopting the above technical solution, when the passivation contact types of the first passivation contact structure and the second passivation contact structure are different, the passivation contact types of the first passivation contact structure and the second passivation contact structure can be respectively adjusted according to the requirements of different actual application scenarios, so as to improve the applicability of the back contact battery provided by the present invention in different application scenarios. For example: in the actual manufacturing process, after forming the first passivation contact structure in the multi-sub-region and forming the second passivation contact structure set in the whole layer, it is usually necessary to use a laser processing process to pattern the mask material set in the whole layer to form a mask layer for selectively etching the second passivation contact structure. In order to process all parts of the mask material corresponding to the multi-sub-region, the heat of the laser radiation will be conducted to the first passivation contact structure. Because the heat of the laser is high, when the first passivation contact structure has a high thermal stability, the influence of the heat of the laser radiation on the first passivation contact structure can be reduced, and even the heat of the laser radiation will not affect the first passivation contact structure, thereby improving the yield of the back contact battery. The portion of the second passivation contact structure corresponding to the majority-carrier region needs to be removed, and the laser processing process has a high precision. Therefore, the portion of the second passivation contact structure corresponding to the minority-carrier region will not be affected by heat, or the thermal impact will be small. At this time, the manufacturing process has lower requirements on the thermal stability of the second passivation contact structure, and the thermal stability of the second passivation contact structure can be set to be lower than the thermal stability of the first passivation contact structure.

[0035] In addition, when the first passivation contact structure is a tunneling passivation contact structure, since amorphous silicon materials are easy to form polycrystalline silicon or single crystal silicon at high temperatures, and the chemical properties of tunneling passivation materials and polycrystalline silicon at high temperatures are relatively stable, compared with heterogeneous contact structures, tunneling passivation contact structures are less sensitive to high-temperature laser thermal damage, and can reduce the impact on the passivation effect during the laser processing process, further increasing the process window and reducing the process difficulty. Secondly, when the multi-sub passivation layer and the first doped semiconductor portion are formed simultaneously, the multi-sub passivation layer and the first interface passivation layer can be better coated in the non-electrode collection area, or even on the side of the semiconductor substrate, which can further reduce the number of defects in the edge portion of the first surface. In addition, the heterogeneous contact structure has a passivation effect that is superior to the tunneling passivation contact structure. Therefore, when the second passivation contact structure is a heterogeneous contact structure, the carrier recombination rate at the interface between the semiconductor substrate and the second interface passivation layer can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the back contact battery.

[0036] In a second aspect, the present invention provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.

[0037] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0038] In a third aspect, the present invention provides a method for manufacturing a back-contact battery, the method for manufacturing a back-contact battery comprising: first, providing a semiconductor substrate, the semiconductor substrate having a first surface and a second surface relative to each other. The first surface includes a non-electrode collection area located at the edge, and an electrode collection area located on the inner side of the non-electrode collection area. The electrode collection area includes a minority carrier area and a majority carrier area alternately spaced along a first direction. Along the first direction, the minority carrier area located at the outermost edge is closer to the non-electrode collection area than the majority carrier area located at the outermost edge. Next, a first doped semiconductor portion arranged in the majority carrier area is formed. Next, a second doped semiconductor portion arranged in the minority carrier area is formed. The conductivity type of the second doped semiconductor portion is opposite to that of the first doped semiconductor portion. Next, a majority carrier passivation layer is formed and arranged in the non-electrode collection area. The thickness of the majority carrier passivation layer is greater than the thickness of the second doped semiconductor portion.

[0039] As a possible implementation scheme, the first doped semiconductor portion and the majority passivation layer are formed simultaneously.

[0040] As a possible implementation scheme, in the first surface, the area located between the majority carrier region and the minority carrier region along the first direction is the spacing region. After providing a semiconductor substrate, the manufacturing method of the back contact battery also includes: forming a whole layer of a first doped semiconductor material arranged on the first surface. Next, the portion of the first doped semiconductor material corresponding to the minority carrier region is selectively removed, so that the portion of the first doped semiconductor material remaining in the majority carrier region and the spacing region forms a first doped semiconductor portion, and the portion of the first doped semiconductor material remaining in the non-electrode collection region forms a majority carrier passivation layer. Next, a whole layer of a second doped semiconductor material is formed on the minority carrier region, the first doped semiconductor portion and the majority carrier passivation layer. Next, the portion of the second doped semiconductor material corresponding to the majority carrier region is selectively removed, so that the portion of the second doped semiconductor material remaining in the minority carrier region and the spacing region forms a second doped semiconductor portion, and the portion of the second doped semiconductor material remaining in the non-electrode collection region forms at least a portion of the hydrogen-containing passivation layer.

[0041] The beneficial effects of the third aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0043] Figure 1 A longitudinal cross-sectional view of a first structure of a back contact battery provided in an embodiment of the present invention Figure 1 ;

[0044] Figure 2 Schematic diagram of the distribution of the non-electrode collecting area and the electrode collecting area on the first surface of the back contact battery provided in an embodiment of the present invention Figure 1 ;

[0045] Figure 3 Schematic diagram of the distribution of the non-electrode collecting area and the electrode collecting area on the first surface of the back contact battery provided in an embodiment of the present invention Figure 2 ;

[0046] Figure 4 A longitudinal cross-sectional view of a first structure of a back contact battery provided in an embodiment of the present invention Figure 2 ;

[0047] Figure 5 A longitudinal cross-sectional view of a first structure of a back contact battery provided in an embodiment of the present invention Figure 3 ;

[0048] Figure 6 A longitudinal cross-sectional view of a first structure of a back contact battery provided in an embodiment of the present invention Figure 4 ;

[0049] Figure 7 A longitudinal cross-sectional view of a first structure of a back contact battery provided in an embodiment of the present invention Figure 5 ;

[0050] Figure 8 A longitudinal cross-sectional view of a first structure of a back contact battery provided in an embodiment of the present invention Figure 6 ;

[0051] Fig. 9 A longitudinal cross-sectional view of a first structure of a back contact battery provided in an embodiment of the present invention Figure 7 ;

[0052] Fig.10 A longitudinal cross-sectional view of a first structure of a back contact battery provided in an embodiment of the present invention Figure 8 ;

[0053] Fig.11 A longitudinal cross-sectional view of a first structure of a back contact battery provided in an embodiment of the present invention Figure 9 ;

[0054] Fig.12 A longitudinal cross-sectional view of a first structure of a back contact battery provided in an embodiment of the present invention Figure 10 .

[0055] Figure numerals: 11 is a semiconductor substrate, 12 is a non-electrode collecting region, 13 is an electrode collecting region, 14 is a minority carrier region, 15 is a majority carrier region, 16 is a spacer region, 17 is a first doped semiconductor portion, 18 is a second doped semiconductor portion, 19 is a majority carrier passivation layer, 20 is a hydrogen-containing passivation layer, 21 is a first interface passivation layer, 22 is a second interface passivation layer, 23 is an insulating layer, 24 is a transparent conductive layer, 25 is an insulating groove, 26 is a first electrode, and 27 is a second electrode. DETAILED DESCRIPTION

[0056] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0057] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in actual applications due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0058] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0059] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0060] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0061] A solar cell is a device that can convert sunlight into electrical energy. Specifically, when the solar cell is in operation, sunlight shines on the semiconductor pn junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field of the pn junction, photogenerated holes flow to the p region, and photogenerated electrons flow to the n region. When the circuit is connected, current can be generated. Among them, a solar cell in which both the positive electrode and the negative electrode are on the back of the cell is a back-contact cell. Compared with a double-sided contact solar cell, the front of the back-contact cell is not blocked by a metal electrode, so that the light-facing side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, and is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0062] However, in the existing back contact battery, the minority carrier collection efficiency at the edge portion located on the backlight side is low, which is not conducive to improving the working efficiency of the back contact battery.

[0063] Specifically, the above-mentioned back contact battery generally includes a semiconductor substrate, a first doped semiconductor portion and a second doped semiconductor portion. Wherein, along the direction parallel to the backlight surface of the semiconductor substrate, the first doped semiconductor portion and the second doped semiconductor portion are both formed on a partial area of ​​the backlight surface of the semiconductor substrate. The first doped semiconductor portion can be alternately spaced with the second doped semiconductor portion, or the second doped semiconductor portion can extend to cover the portion of the first doped semiconductor portion away from the semiconductor substrate. Wherein, the first doped semiconductor portion and the second doped semiconductor portion have opposite conductivity types to collect and extract electrons and holes respectively, which is conducive to the formation of photocurrent. When the second doped semiconductor portion extends to cover the portion of the first doped semiconductor portion away from the semiconductor substrate, the stacked first doped semiconductor portion and the second doped semiconductor portion are spaced to suppress leakage.

[0064] In the above case, in the actual manufacturing process, when the first doped semiconductor part and the second doped semiconductor part are formed on the side of the backlight surface, the formation quality and uniformity of the first doped semiconductor part and the second doped semiconductor part in the edge area are not as good as the formation quality and uniformity of the first doped semiconductor part and the second doped semiconductor part in the middle area due to the different flow rates and flow rates of the deposition gas and / or doping gas in the middle area and the edge area, which leads to the passivation effect of the back contact battery in the edge area being worse than that in the middle area, and the recombination rate of electrons and holes in the edge area of ​​the back contact battery is higher. In addition, in the existing back contact battery, as described above, when manufacturing the above-mentioned first doped semiconductor part and the second doped semiconductor part, the first doped semiconductor part and the second doped semiconductor part are generally distributed alternately and spaced on the side of the backlight surface, and even in the edge area of ​​the first surface, the first doped semiconductor part and the second doped semiconductor part are electrically connected to the corresponding electrodes to lead out the collected carriers. However, such a setting, on the one hand, is prone to edge leakage problems, and on the other hand, it will lead to low collection efficiency of minority carriers in the edge area, which is not conducive to improving the working efficiency of the back contact battery.

[0065] In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a back contact battery. Figure 1 As shown, the back contact cell provided by the embodiment of the present invention includes: a semiconductor substrate 11, a first doped semiconductor portion 17, a second doped semiconductor portion 18 and a majority carrier passivation layer 19. The semiconductor substrate 11 has a first surface and a second surface opposite to each other. The first surface includes a non-electrode collection area 12 located at the edge, and an electrode collection area 13 located inside the non-electrode collection area 12. The electrode collection area 13 includes a minority carrier area 14 and a majority carrier area 15 alternately distributed along a first direction. Along the first direction, the minority carrier area 14 located at the edge is closer to the non-electrode collection area 12 than the majority carrier area 15 located at the edge. The first doped semiconductor portion 17 is arranged in the majority carrier area 15. The second doped semiconductor portion 18 is arranged in the minority carrier area 14. The conductivity type of the second doped semiconductor portion 18 is opposite to that of the first doped semiconductor portion 17. The majority carrier passivation layer 19 is arranged in the non-electrode collection area 12. The thickness of the majority carrier passivation layer 19 is greater than the thickness of the second doped semiconductor portion 18.

[0066] When the above technical solution is adopted, Figure 1As shown, in the back contact cell provided by the embodiment of the present invention, the first surface of the semiconductor substrate 11 includes a non-electrode collection area 12 located at the edge, and an electrode collection area 13 located inside the non-electrode collection area 12. The above-mentioned non-electrode collection area 12 refers to: the majority carrier passivation layer 19 and other structures with conductive properties arranged on the non-electrode collection area 12 are not electrically connected to the conductive electrode, electrode mesh or welding strip and other interconnection structures, which can ensure that the majority carriers gathered inside the majority carrier passivation layer 19 generate an electric field and form a minority carrier inversion layer on the inner side of the edge portion of the semiconductor substrate 11, and the above-mentioned electrode collection area 13 refers to: the first doped semiconductor part 17 and the second doped semiconductor part 18 and other structures with conductive properties arranged on the electrode collection area 13 need to be electrically connected to the conductive electrode, electrode mesh or welding strip and other interconnection structures to lead out the majority carriers (majority carriers for short) or minority carriers (majority carriers for short) collected by themselves, which is conducive to the formation of photocurrent. It can be understood that the structure provided on the non-electrode collection area 12 is electrically insulated from the structure provided on the electrode collection area 13 to prevent the structure provided on the non-electrode collection area 12 from being electrically connected to the conductive electrode (such as the first electrode 26 and the second electrode 27 in the figure), the electrode mesh or the interconnection structure such as the welding strip through the structure provided on the electrode collection area 13. In addition, the above-mentioned electrical connection method does not include the electrical connection achieved through the semiconductor substrate 11. In the above case, the area at the edge of the first surface is the non-electrode collection area 12. Such a setting can prevent the second doped semiconductor part 18 provided in the minority carrier area 14 adjacent to the non-electrode collection area 12 from being electrically connected to the side of the semiconductor substrate 11 of the opposite conductivity type through the majority carrier passivation layer 19 provided in the non-electrode collection area 12 due to the existence of factors such as winding plating, that is, to prevent edge overlap short circuit, so that the back contact battery has higher electrical reliability. Secondly, along the first direction, the minority carrier region 14 located at the outermost edge is closer to the non-electrode collection region 12 than the majority carrier region 15 located at the outermost edge. At this time, along the first direction, the film layers adjacent to the outer non-electrode collection region 12 are all second doped semiconductor parts 18. Since the second doped semiconductor part 18 is arranged in the minority carrier region 14, the second doped semiconductor part 18 is the emitter of the back contact battery. Based on this, when along the first direction, the film layers adjacent to the outer non-electrode collection region 12 are all second doped semiconductor parts 18, the area proportion of the emitter within the range close to the non-electrode collection region 12 on the first surface can be increased, so that the transmission distance of the minority carriers located at the edge of the semiconductor substrate 11 to the emitter becomes shorter, which is beneficial to improve the collection efficiency of the emitter for the minority carriers at the edge of the semiconductor substrate 11 and suppress the recombination of carriers at the edge of the semiconductor substrate 11.Furthermore, the conductivity type of the majority carrier passivation layer 19 arranged in the non-electrode collection area 12 is opposite to the conductivity type of the second doped semiconductor portion 18 arranged in the minority carrier area 14. At the same time, the majority carrier passivation layer 19 is not electrically connected to the above-mentioned conductive electrode and other interconnection structures. Therefore, the majority carriers in the majority carrier passivation layer 19 can be enriched on the inner side of the semiconductor substrate 11 within the non-electrode collection area 12 to form a minority carrier inversion layer. At this time, the minority carriers located at the edge portion of the semiconductor substrate 11 are repelled by the minority carrier inversion layer, so that the minority carriers on the inner side of the semiconductor substrate 11 at the edge portion of the first surface are accelerated to be transmitted to the adjacent second doped semiconductor portion, making it easier for them to be collected by the second doped semiconductor portion 18 adjacent to the non-electrode collection area 12 and exported in time, thereby further improving the collection efficiency of the emitter region for the minority carriers at the edge portion of the semiconductor substrate 11 and improving the working efficiency of the back contact battery. In addition, the field passivation effects of the majority-substrate passivation layer 19 and the second doped semiconductor portion 18 on the semiconductor substrate 11 are respectively proportional to their own thicknesses. Therefore, when the thickness of the majority-substrate passivation layer 19 arranged in the non-electrode collection area 12 is greater than the thickness of the second doped semiconductor portion 18, the majority-substrate passivation layer 19 has a higher field passivation effect on the non-electrode collection area 12, thereby reducing the number of defects in the non-electrode collection area 12 located at the edge of the first surface, and further improving the working efficiency of the back contact battery.

[0067] In actual application, the embodiment of the present invention does not specifically limit the material and conductivity type of the semiconductor substrate. For example, the semiconductor substrate may be a silicon substrate. Alternatively, the semiconductor substrate may be a substrate made of any semiconductor material such as a germanium silicon substrate, a germanium substrate, or a gallium arsenide substrate. In addition, the semiconductor substrate may be an N-type semiconductor substrate or a P-type semiconductor substrate.

[0068] Secondly, the semiconductor substrate includes a first surface and a second surface relative to each other, the first surface of the semiconductor substrate corresponds to the backlight surface of the back-contact battery, and the second surface of the semiconductor substrate corresponds to the light-facing surface of the back-contact battery. Among them, the first surface includes a non-electrode collection area located at the edge, and an electrode collection area located inside the non-electrode collection area. Specifically, the distribution of the non-electrode collection area on the first surface can be determined based on the distribution of the multi-sub passivation layer formed on one side of the first surface and not electrically connected to the interconnection structure such as the conductive electrode. As for the distribution of the electrode collection area on the first surface, after determining the distribution of the non-electrode collection area on the first surface, the area on the first surface located inside the non-electrode collection area is the electrode collection area. Secondly, as Figure 2As shown, in the first surface, the non-electrode collecting area 12 can be arranged only along the first direction on the outside of the electrode collecting area 13; at this time, the electrode collecting area 13 can be continuously distributed from one side edge of the first surface along the extension direction of the non-electrode collecting area 12 to the other side edge, and there is no need to selectively etch the first doped semiconductor part and the second doped semiconductor part on both side edges of the first surface along the extension direction of the non-electrode collecting area 12 during the manufacturing process. While reducing the etching amount and improving the manufacturing efficiency of the back contact battery, it can also increase the proportion of the electrode collecting area 13 in the first surface, and further improve the collection efficiency of the first doped semiconductor part and the second doped semiconductor part for carriers. The above-mentioned first direction can be any direction parallel to the first surface. Preferably, when the shape of the first surface of the semiconductor substrate is a rectangle or a rectangle with a chamfer, the first direction can be parallel to the extension direction of any side length of the non-cambered side of the rectangle.

[0069] Or, if Figure 3 As shown, in the first surface, the non-electrode collection area 12 is also arranged outside the electrode collection area 13 along the second direction. The second direction is different from the first direction. In this case, the majority carrier passivation layer can also be arranged outside the electrode collection area 13 along the second direction, which is beneficial to improve the collection efficiency of minority carriers of the edge of the emitter region along the second direction to the edge of the semiconductor substrate, and further inhibit the recombination of carriers at the edge of the semiconductor substrate. In addition, because the majority carrier passivation layer has a higher field passivation effect on the non-electrode collection area 12, when the non-electrode collection area 12 is also arranged outside the electrode collection area 13 along the second direction, it can also improve the passivation effect of the edge portion along the second direction in the first surface, reduce the number of defects in the non-electrode collection area 12 located at the edge of the first surface, and further improve the working efficiency of the back contact battery. Wherein, the above-mentioned second direction can be any direction parallel to the first surface and different from the first direction.

[0070] Preferably, the second direction can be perpendicular to the first direction. In this case, in actual application, the shape of the first surface of the semiconductor substrate is usually a rectangle or a rectangle with a chamfer. Based on this, when the second direction is perpendicular to the first direction, it is beneficial to make the distribution of the minority carrier region and the majority carrier region more match the shape of the first surface of the semiconductor substrate, and then it is beneficial to further improve the first doped semiconductor part and the second doped semiconductor part respectively arranged in the minority carrier region and the majority carrier region. The efficiency has a higher carrier collection efficiency, and the difficulty of interconnecting different back contact batteries can also be reduced. In addition, when the second direction is perpendicular to the first direction, it is beneficial to make the non-electrode collection area just completely located at each part of the edge of the first surface, increase the proportion of the non-electrode collection area in the edge part of the first surface, further reduce the number of defects in the non-electrode collection area located at the edge of the first surface, and further improve the working efficiency of the back contact battery.

[0071] As for the width of the above-mentioned non-electrode collection area along the first direction, and the width of the non-electrode collection area along the second direction when the non-electrode collection area is also arranged outside the electrode collection area along the second direction, as mentioned above, the structures such as the multi-sub passivation layer arranged on the non-electrode collection area and having conductive characteristics are not electrically connected to the conductive electrode, electrode mesh or welding strip and other interconnection structures. At this time, the majority carriers collected by the structures such as the multi-sub passivation layer arranged on the non-electrode collection area and having conductive characteristics cannot be extracted, affecting the collection efficiency of the majority carriers of the back contact battery. However, the multi-sub passivation layer arranged in the non-electrode collection area can help improve the collection efficiency of the minority carriers of the second doped semiconductor part of the non-electrode collection area, and has a higher passivation effect on the edge of the first surface. Based on this, the width of the non-electrode collection area along the first direction and along the second direction can be determined according to the requirements for the passivation effect of the edge portion of the first surface of the back contact battery in the actual application scenario, and the requirements for the collection efficiency of the carriers of the edge portion of the first surface, and no specific limitation is made here.

[0072] Exemplarily, along the first direction, the width of the non-electrode collection area can be less than or equal to the width of the minority carrier area. When the width of the non-electrode collection area along the first direction is less than the width of the minority carrier area, it is helpful to reduce the proportion of the non-electrode collection area on the side of the first surface from which the majority carriers cannot be derived, so that the proportion of the electrode collection area co-located on the first surface with the non-electrode area collection is relatively large, thereby improving the collection efficiency of minority carriers and majority carriers of the back contact battery, and further improving the working efficiency of the back contact battery. As for the specific width of the non-electrode collection area along the first direction, it can be determined according to the specifications of the back contact battery.

[0073] Exemplarily, along the first direction, the width of the non-electrode collecting region may be less than 1000 μm. For example, the width of the non-electrode collecting region may be 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 600 μm, 800 μm or 1000 μm. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect that the width of the non-electrode collecting region is less than the width of the minority carrier region along the first direction described above, which will not be repeated here.

[0074] Exemplarily, the width of the non-electrode collection area along the second direction may be less than or equal to the width of the non-electrode collection area along the first direction. In this case, while ensuring that the non-electrode collection area at the edge of the first surface along the second direction corresponds to a lower carrier recombination rate under the field passivation effect of the majority carrier passivation layer, the proportion of the non-electrode collection area along the second direction that cannot derive the majority carriers is reduced, so that the proportion of the electrode collection area co-located on the first surface with the non-electrode area collection is relatively large, thereby improving the collection efficiency of minority carriers and majority carriers of the back contact battery, and further improving the working efficiency of the back contact battery. In addition, the risk of interconnection structures such as solder strips interconnecting different back contact batteries being short-circuited through the multi-carrier passivation layer due to the non-electrode collection area also being arranged outside the electrode collection area along the second direction can also be reduced, thereby ensuring that the back contact battery has a higher electrical reliability.

[0075] As for the electrode collection area included in the above-mentioned first surface, the electrode collection area includes a minority carrier area and a majority carrier area that are alternately spaced and distributed along the first direction. Among them, it is defined that in the first surface, the area located between the majority carrier area and the minority carrier area along the first direction is a spacing area. The distribution of the above-mentioned minority carrier area, the majority carrier area and the spacing area on the first surface can be determined according to the distribution of the first doped semiconductor part and the second doped semiconductor part formed on one side of the first surface. Specifically, because the first doped semiconductor part for collecting and deriving the majority carriers included in the back contact battery is at least arranged in the majority carrier area, the distribution range of the majority carrier area on the first surface can be determined according to the distribution requirements of at least part of the first doped semiconductor part in the actual application scenario. Because the second doped semiconductor part for collecting and deriving the minority carriers included in the back contact battery is at least arranged in the minority carrier area, the distribution range of the minority carrier area on the first surface can be determined according to the distribution requirements of at least part of the second doped semiconductor part in the actual application scenario. Secondly, after the range of the minority carrier area and the majority carrier area is determined, the distribution range of the spacing area between the minority carrier area and the majority carrier area in the electrode collection area on the first surface is also determined.

[0076] It can be understood that the minority carrier region corresponds to the emitter region of the back contact battery, and the majority carrier region corresponds to the back field region of the back contact battery; one of the minority carrier region and the majority carrier region corresponds to the P region, and the other corresponds to the N region. The spacer region can correspond to the PN overlap region or the PN spacer region.

[0077] As for the regional shapes of the minority carrier region and the majority carrier region, they can be set according to actual needs and are not specifically limited here. For example, the minority carrier region and the majority carrier region can be arranged alternately in strips or in interdigitated shapes.

[0078] In terms of surface morphology, the second surface of the semiconductor substrate can be a polished surface or a velvet surface. Preferably, the second surface is a velvet surface to improve the light trapping effect of the second surface and improve the utilization rate of light by the semiconductor substrate.

[0079] Secondly, if Figure 4 As shown, the surface of the non-electrode collection area 12 included in the first surface can be a polished surface. In this case, in the actual manufacturing process, the deposited film thickness of the majority-carrier passivation layer 19 is inversely proportional to the specific surface area of ​​the non-electrode collection area 12 where it is located, and the passivation effect of the majority-carrier passivation layer 19 on the non-electrode collection area 12 is proportional to its own deposition thickness. Based on this, compared with the velvet surface, when the surface of the non-electrode collection area 12 is a polished surface, the surface of the non-electrode collection area 12 is relatively flat, which is conducive to increasing the deposited film thickness of the majority-carrier passivation layer 19 on the non-electrode collection area 12, and further conducive to improving the passivation effect of the majority-carrier passivation layer 19 on the non-electrode collection area 12. In addition, compared with the velvet surface, the polished surface has fewer defect recombination centers, which can further reduce the carrier recombination rate at the edge of the first surface.

[0080] For example, Figure 4 As shown, the surface of the minority carrier region 14 can be a velvet surface. In this case, the second doped semiconductor portion 18 is arranged in the minority carrier region 14. And the surface of the minority carrier region 14 is a velvet surface with a large specific surface area. At this time, compared with the polished surface, the deposited film thickness of the second doped semiconductor portion 18 on the velvet surface is relatively small, ensuring that the thickness of the majority carrier passivation layer 19 arranged in the non-electrode collection area 12 can be greater than the thickness of the second doped semiconductor portion 18 arranged in the minority carrier region 14, ensuring that the non-electrode collection area 12 has a higher passivation effect. In addition, the velvet surface has a larger specific surface area, which is beneficial for the second doped semiconductor portion 18 formed on the minority carrier region 14 to have a larger specific surface area on the side away from the semiconductor substrate 11, which is beneficial for increasing the contact area between the second doped semiconductor portion 18 and the corresponding conductive electrode, and improving the contact performance between the two.

[0081] Of course, the above-mentioned non-electrode collecting area and minority carrier area may also have the same surface morphology, and the sizes of the texture structures arranged on the surfaces of the non-electrode collecting area and minority carrier area are different, so that the surface roughness of the non-electrode collecting area is smaller than the surface roughness of the minority carrier area. For example: the non-electrode collecting area and the minority carrier area may both be polished surfaces or both be velvet surfaces, etc. When both surfaces are velvet surfaces, the size of the texture structure on the non-electrode collecting area is smaller than the size of the texture structure in the minority carrier area. Alternatively, the above-mentioned non-electrode collecting area and minority carrier area may also have other different surface morphologies in addition to polished surfaces or velvet surfaces. Alternatively, the non-electrode collecting area and the minority carrier area may also have the same surface morphology and the size of the texture structure is also the same. At this time, a thicker majority carrier passivation layer and a thinner second doped semiconductor portion may be obtained by adjusting the deposition parameters separately.

[0082] For the above-mentioned first doped semiconductor part and the second doped semiconductor part, from the aspect of conductivity type, the embodiment of the present invention does not specifically limit the conductivity type of the first doped semiconductor part and the second doped semiconductor part, as long as the first doped semiconductor part corresponds to the minority carrier region, and the second doped semiconductor part corresponds to the majority carrier region. Specifically, the conductivity type of the first doped semiconductor part can be N-type, in which case the conductivity type of the second doped semiconductor part is P-type; or the conductivity type of the first doped semiconductor part can also be P-type, in which case the conductivity type of the second doped semiconductor part is N-type.

[0083] In terms of the formation position, Figure 1 and Figure 4 As shown, the first doped semiconductor portion 17 can be arranged only in the majority-carrier region 15, and the second doped semiconductor portion 18 can be arranged only in the minority-carrier region 14. At this time, the first doped semiconductor portion 17 and the second doped semiconductor portion 18 can be isolated by the above-mentioned spacer region 16 to suppress leakage. At this time, a spacer region 16 can also be arranged between the non-electrode collection region 12 and the electrode collection region 13 to separate the conductive structure such as the majority-carrier passivation layer 19 arranged in the non-electrode collection region 12 from the first doped semiconductor portion 17 and the second doped semiconductor portion 18 arranged in the electrode collection region 13 to prevent short circuit.

[0084] Or, if Figure 5 As shown, the first doped semiconductor portion 17 is not only arranged in the majority-subregion 15, but also arranged in the spacer region 16. In addition, the second doped semiconductor portion 18 is not only arranged in the minority-subregion 14, but also extends to cover the portion of the first doped semiconductor portion 17 corresponding to the spacer region 16. In the spacer region 16, the second doped semiconductor portion 18 and the first doped semiconductor portion 17 are spaced apart along the thickness direction of the semiconductor substrate 11 to suppress leakage and further improve the working performance of the back contact battery. In this case, the first doped semiconductor portion 17 and the second doped semiconductor portion 18 have a larger area occupancy on one side of the first surface, which can reduce the etching amount when the first doped semiconductor material (used to manufacture the first doped semiconductor portion 17) and the second doped semiconductor material (used to manufacture the second doped semiconductor portion 18) are selectively etched to improve the manufacturing efficiency of the back contact battery.

[0085] The back contact cell may include a spacer layer. Based on this, in the spacer region, the second doped semiconductor portion and the first doped semiconductor portion may be separated by the spacer layer along the thickness direction of the semiconductor substrate. Specifically, Figure 6 As shown, the spacer layer (such as the insulating layer 23 in the figure) can be disposed only along the thickness direction of the semiconductor substrate 11 between the first doped semiconductor portion 17 and the second doped semiconductor portion 18 corresponding to the spacer region 16; or Figure 7As shown, the spacer layer can be arranged between the first doped semiconductor part 17 and the second doped semiconductor part 18 corresponding to the spacer region 16 along the thickness direction of the semiconductor substrate 11 and the direction parallel to the first surface. Secondly, the spacer layer can only include the portion of the second interface passivation layer 22 extending to the first doped semiconductor part 17 and the second doped semiconductor part 18 described below; or the spacer layer can only include the insulating layer 23, which can be a mask layer formed before the first doped semiconductor material (used to manufacture the first doped semiconductor part 17) is selectively etched in the actual manufacturing process and used as an etching protection, or the insulating layer 23 can also be an insulating layer 23 formed separately on the portion of the spacer region 16 corresponding to the first doped semiconductor part 17 after the first doped semiconductor part 17 is formed in the actual manufacturing process. Alternatively, the above-mentioned spacer layer can simultaneously include the portion of the second interface passivation layer 22 extending to the first doped semiconductor part 17 and the second doped semiconductor part 18, and the above-mentioned insulating layer 23.

[0086] In addition, the material of the first doped semiconductor part and / or the second doped semiconductor part may include any semiconductor material such as silicon, silicon germanium, germanium or gallium arsenide. In terms of the arrangement of the material, the crystal phase of the first doped semiconductor part and / or the second doped semiconductor part may be amorphous, microcrystalline, nanocrystalline, single crystal or polycrystalline, etc. Among them, the materials of the first doped semiconductor part and the second doped semiconductor part may be the same or different. For example: the materials of the first doped semiconductor part and the second doped semiconductor part may both be doped polycrystalline silicon. For another example: the materials of the first doped semiconductor part and the second doped semiconductor part may both include at least one of doped amorphous silicon, doped microcrystalline silicon and doped nanocrystalline silicon. For another example: the material of the first doped semiconductor part may be doped polycrystalline silicon, and the material of the second doped semiconductor part may include at least one of doped amorphous silicon, doped microcrystalline silicon and doped nanocrystalline silicon.

[0087] Preferably, the first doped semiconductor portion may include a doped polysilicon layer. In this case, in actual application, compared with the doped amorphous silicon layer, the thickness of the doped polysilicon layer is larger, and the multi-sub passivation layer can be formed integrally with the first doped semiconductor portion of the same conductivity type as itself. Therefore, when the first doped semiconductor portion includes a doped polysilicon layer, and the first doped semiconductor portion and the multi-sub passivation layer are formed integrally, it is beneficial to make the multi-sub passivation layer have a larger thickness, further improving the passivation effect of the multi-sub passivation layer on the non-electrode collection area. Of course, the first doped semiconductor portion may also include other semiconductor materials, and the first doped semiconductor portion may also be formed non-integrally with the multi-sub passivation layer.

[0088] Preferably, the second doped semiconductor portion includes at least one of a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer. In this case, compared with the doped polycrystalline silicon layer, the thickness of the doped amorphous silicon layer is relatively small, so when the second doped semiconductor portion includes a doped amorphous silicon layer, the difficulty of manufacturing a multi-sub passivation layer having a thickness greater than that of the second doped semiconductor portion can be reduced, which is conducive to improving the yield of the back contact battery.

[0089] Secondly, if Figure 6 and Figure 7 As shown, the first doped semiconductor portion 17 may be directly disposed at least on the multi-sub-region 15. Figure 8 As shown, the above-mentioned back contact battery can also include a first interface passivation layer 21. The first interface passivation layer 21 is arranged between the semiconductor substrate 11 and the first doped semiconductor part 17. In this case, the passivation contact structure composed of the first interface passivation layer 21 and the first doped semiconductor part 17 has an excellent interface passivation effect, and can realize the selective collection of carriers, reduce the carrier recombination rate of the minority carrier region 14 on the first surface of the semiconductor substrate 11, and further improve the photoelectric conversion efficiency of the back contact battery. The material and thickness of the first interface passivation layer 21 can be set according to the material of the first doped semiconductor part 17 and actual needs, and are not specifically limited here. For example: when the material of the first doped semiconductor part is doped polycrystalline silicon, the first interface passivation layer is a tunneling passivation layer. For another example: when the material of the first doped semiconductor part includes at least one of doped amorphous silicon, doped microcrystalline silicon and doped nanocrystalline silicon, the first interface passivation layer is an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer or a mixed layer of the above three.

[0090] As for the second doped semiconductor portion, Figure 7 As shown, the second doped semiconductor portion 18 may be directly disposed at least in the minority carrier region 14. Fig. 9As shown, the above-mentioned back contact battery may also include a second interface passivation layer 22, which is at least arranged between the semiconductor substrate 11 and the second doped semiconductor part 18. Specifically, when the second doped semiconductor part 18 is only arranged in the minority carrier region 14, the second interface passivation layer 22 is only arranged between the semiconductor substrate 11 and the second doped semiconductor part 18. When the second doped semiconductor part 18 also extends to cover the part of the first doped semiconductor part 17 corresponding to the spacer region 16, the second interface passivation layer 22 also extends between the second doped semiconductor part 18 and the first doped semiconductor part 17. In this case, the passivation contact structure composed of the second interface passivation layer 22 and the part of the second doped semiconductor part 18 located on the second region can realize the selective collection of carriers and reduce the carrier recombination rate of the minority carrier region 14 of the first surface. The material and thickness of the second interface passivation layer 22 can be set according to the material of the second doped semiconductor part 18 and actual needs, and are not specifically limited here. For example: when the material of the second doped semiconductor part is doped polysilicon, the second interface passivation layer is a tunneling passivation layer. For another example, when the material of the second doped semiconductor portion includes doped amorphous silicon, doped microcrystalline silicon and doped nanocrystalline silicon, the second interface passivation layer is an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon or a mixture of the three.

[0091] In addition, when the back contact cell includes a first interface passivation layer and a second interface passivation layer, the first interface passivation layer and the first doped semiconductor portion constitute a first passivation contact structure, and the second interface passivation layer and the second doped semiconductor portion constitute a second passivation contact structure.

[0092] Among them, the passivation contact types of the first passivation contact structure and the second passivation contact structure can be the same. For example: the first passivation contact structure and the second passivation contact structure are both tunneling passivation contact structures or heterogeneous contact structures. Alternatively, the passivation contact types of the first passivation contact structure and the second passivation contact structure can also be different. For example: one of the first passivation contact structure and the second passivation contact structure is a tunneling passivation contact structure, and the other is a heterogeneous contact structure. In this case, when the passivation contact types of the first passivation contact structure and the second passivation contact structure are different, the passivation contact types of the first passivation contact structure and the second passivation contact structure can be adjusted respectively according to different actual application scenario requirements to improve the applicability of the back contact battery provided by the embodiment of the present invention in different application scenarios.

[0093] For example: in the actual manufacturing process, after forming the first passivation contact structure in the multi-sub-region and forming the second passivation contact structure set in the whole layer, it is usually necessary to use a laser processing process to pattern the mask material set in the whole layer to form a mask layer for selectively etching the second passivation contact structure. In order to process all parts of the mask material corresponding to the multi-sub-region, the heat of the processing laser radiation will be conducted to the first passivation contact structure. Because the heat of the laser is high, when the first passivation contact structure has a high thermal stability, the influence of the heat of the laser radiation on the first passivation contact structure can be reduced, and even the heat of the laser radiation will not affect the first passivation contact structure, thereby improving the yield of the back contact battery. The part of the second passivation contact structure corresponding to the multi-sub-region needs to be removed, and the precision of the laser processing process is high, so the part of the second passivation contact structure corresponding to the minority sub-region will not be affected by heat, or the heat affected is small. At this time, the manufacturing process has a low requirement for the thermal stability of the second passivation contact structure, and the thermal stability of the second passivation contact structure can be set to be lower than the thermal stability of the first passivation contact structure.

[0094] For another example: in the actual manufacturing process, a thermal oxidation process can be used to form the tunneling passivation layer included in the tunneling passivation contact structure. At this time, compared with the passivation layer of intrinsic semiconductor materials such as intrinsic amorphous silicon formed by a low-temperature process, the tunneling passivation layer has better coverage. Based on this, the first passivation contact structure can be set as a tunneling passivation contact structure. After the first passivation contact structure is formed, the side of the semiconductor substrate can also be coated with at least part of the first passivation contact structure, thereby reducing the number of defects on the side of the semiconductor substrate and further improving the working performance of the back contact battery. Secondly, when the multi-sub passivation layer and the first doped semiconductor portion are formed simultaneously, the multi-sub passivation layer and the first interface passivation layer can be better coated in the non-electrode collection area, or even the side of the semiconductor substrate, which can further reduce the number of defects in the edge portion of the first surface. In addition, when the first passivation contact structure is a tunnel passivation contact structure, since amorphous silicon materials are easy to form polycrystalline silicon or single crystal silicon at high temperatures, and the chemical properties of tunnel passivation materials and polycrystalline silicon at high temperatures are relatively stable, compared with heterogeneous contact structures, tunnel passivation contact structures are less sensitive to high-temperature laser thermal damage, and can reduce the impact on the passivation effect during the laser processing process, further increasing the process window and reducing the process difficulty. In addition, the heterogeneous contact structure has a passivation effect that is superior to the tunnel passivation contact structure, so when the second passivation contact structure is a heterogeneous contact structure, the carrier recombination rate at the interface between the semiconductor substrate and the second interface passivation layer can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the back contact battery.

[0095] As for the majority carrier passivation layer, from the perspective of the film layer structure, the majority carrier passivation layer may include a third doped semiconductor portion disposed on the non-electrode collection region, and the third doped semiconductor portion has the same conductivity type as the first doped semiconductor portion. In this case, the third doped semiconductor portion has the same conductivity type as the first doped semiconductor portion, which can achieve the enrichment of majority carriers in the majority carrier passivation layer, facilitate the formation of a minority carrier inversion layer in the non-electrode collection region, and ensure that the second doped semiconductor portion adjacent to the non-electrode collection region has a higher minority carrier collection efficiency.

[0096] In terms of the film layer structure, the multi-sub passivation layer can be a single-layer structure, in which case the third doped semiconductor portion can only include a single-layer doped semiconductor layer disposed on the non-electrode collection region. Alternatively, the multi-sub passivation layer can be a stacked structure, in which case the third doped semiconductor portion can include multiple doped semiconductor layers stacked on the non-electrode collection region along the thickness direction of the semiconductor substrate; in this case, the doping concentrations of the dopants in different doped semiconductor layers can be the same or different.

[0097] From the material aspect, the embodiment of the present invention does not specifically limit the material of the majority passivation layer, which can be determined according to actual needs and the actual manufacturing process, as long as the thickness of the majority passivation layer is greater than the thickness of the second doped semiconductor portion.

[0098] Specifically, when the multi-sub passivation layer includes the third doped semiconductor part, the material of the third doped semiconductor part can be the same as that of the first doped semiconductor part. In this case, the third doped semiconductor part has the same conductivity type as that of the first doped semiconductor part, and the material of the third doped semiconductor part is also the same as that of the first doped semiconductor part. At this time, the third doped semiconductor part and the first doped semiconductor part can be formed simultaneously based on the same material and through the same operation steps, which can not only reduce the etching amount when forming the first doped semiconductor part and improve the manufacturing efficiency of the back contact battery, but also prevent the etchant from affecting the other when additionally forming one of the third doped semiconductor part and the first doped semiconductor part, ensuring that the first doped semiconductor part has a higher carrier collection efficiency, and the third doped semiconductor part has a higher passivation effect on the non-electrode collection area, further improving the working performance of the back contact battery.

[0099] Of course, the material of the third doped semiconductor part included in the majority passivation layer may also be different from the material of the first doped semiconductor part. In this case, the third doped semiconductor part and the first doped semiconductor part can be formed in different operation steps and based on different materials to improve the applicability of the back contact battery provided by the embodiment of the present invention in different application scenarios.

[0100] In the actual manufacturing process, the multi-sub passivation layer can be formed integrally with the first doped semiconductor part, that is, the multi-sub passivation layer and the first doped semiconductor part are formed simultaneously based on the same material and through the same operation steps; at this time, when the back contact battery also includes a first interface passivation layer, the first interface passivation layer can also be arranged between the part of the semiconductor substrate corresponding to the non-electrode collection area and the multi-sub passivation layer, so as to further passivate the non-electrode collection area and reduce the number of defects in the non-electrode collection area. In addition, the multi-sub passivation layer can also be formed non-integrally with the first doped semiconductor part, in which case a multi-sub passivation layer of corresponding material and corresponding thickness can be separately arranged according to actual needs.

[0101] Exemplarily, the multi-sub passivation layer may include a doped polysilicon layer. In this case, in actual application, compared with the doped amorphous silicon layer, the thickness of the doped polysilicon layer is larger, so when the multi-sub passivation layer includes a doped polysilicon layer, it is beneficial to make the multi-sub passivation layer have a larger thickness, further improving the passivation effect of the multi-sub passivation layer on the non-electrode collection area.

[0102] The specific conductivity type of the majority carrier passivation layer can be determined according to the conductivity type of the semiconductor substrate and the material of the majority carrier passivation layer, as long as the majority carrier passivation layer can form a minority carrier inversion layer.

[0103] Exemplarily, the conductivity type of the multi-sub passivation layer may be N-type, and the conductivity type of the second doped semiconductor portion may be P-type. In this case, as described above, the multi-sub passivation layer preferably includes a doped polysilicon layer, and the second doped semiconductor portion preferably includes a doped amorphous silicon layer. Moreover, compared with the P-type doped polysilicon layer, the P-type doped amorphous silicon layer has better contact performance with the conductive material, which is beneficial to reduce the transmission loss between the P-type doped semiconductor portion and the conductive material in the back contact battery, and further improve the workability of the back contact battery.

[0104] As a possible implementation, Fig. 9 It is shown that the above-mentioned back contact battery can also include a hydrogen-containing passivation layer 20. The hydrogen-containing passivation layer 20 is arranged on the side of the majority passivation layer 19 away from the semiconductor substrate 11. In this case, the presence of the hydrogen-containing passivation layer 20 can not only further passivate the non-electrode collection area 12, thereby further reducing the carrier recombination rate of the non-electrode collection area 12, but also prevent the etchant performing the patterning process from affecting the majority passivation layer 19 located below itself when manufacturing the second doped semiconductor part 18 or the electrode and other structures, thereby ensuring that the majority passivation layer 19 has a higher passivation effect on the non-electrode collection area 12, and ensuring that the majority passivation layer 19 has an enrichment effect on the majority carriers, thereby further improving the working performance of the back contact battery.

[0105] The embodiment of the present invention does not specifically limit the material of the hydrogen-containing passivation layer, as long as the non-electrode collection area can be further passivated by hydrogen ions. For example, the hydrogen-containing passivation layer may include at least one of a silicon nitride layer, a hydrogen-containing intrinsic amorphous silicon layer, a hydrogen-containing silicon oxide layer, and a hydrogen-containing aluminum oxide layer. For another example, the hydrogen-containing passivation layer may include a doped semiconductor layer having a conductivity type opposite to that of the multi-sub passivation layer.

[0106] Specifically, in the case where the hydrogen-containing passivation layer includes a doped semiconductor layer of opposite conductivity type to the multi-sub passivation layer, when the first doped semiconductor portion is also arranged in the spacer region, and the second doped semiconductor portion also extends to cover the portion of the first doped semiconductor portion corresponding to the spacer region, at least a portion of the hydrogen-containing passivation layer can be continuous with the second doped semiconductor portion. In this case, the amount of etching when the second doped semiconductor material disposed in the entire layer is selectively etched can be further reduced, and the manufacturing efficiency of the back contact battery can be further improved. It is also beneficial to prevent the etchant from damaging the corresponding passivation structure (such as the multi-sub passivation layer, etc.) located at the edge and side of the semiconductor substrate in order to remove the portion of the second doped semiconductor material corresponding to the non-electrode collection area, thereby ensuring that the edge and side of the semiconductor substrate have a good passivation effect.

[0107] Of course, in the case where the hydrogen-containing passivation layer includes a doped semiconductor layer having a conductivity type opposite to that of the majority sub-passivation layer, the hydrogen-containing passivation layer may be manufactured separately from the second doped semiconductor portion.

[0108] In addition, if Fig. 9 As shown, in the case where the hydrogen-containing passivation layer 20 includes an impurity-doped semiconductor layer of opposite conductivity type to the multi-sub passivation layer 19, when at least a portion of the hydrogen-containing passivation layer 20 is integrally continuous with the second impurity-doped semiconductor portion 18, and the back-contact battery also includes a second interface passivation layer 22, the hydrogen-containing passivation layer 20 may also include a portion of the second interface passivation layer 22 corresponding to the non-electrode collection area 12.

[0109] like Fig. 9 and Fig.10 As shown, the hydrogen-containing passivation layer 20 may be disposed only on a portion of the multi-sub passivation layer 19 away from the semiconductor substrate 11, or may be disposed on the entire region of the multi-sub passivation layer 19 away from the semiconductor substrate 11. The formation range of the hydrogen-containing passivation layer 20 on the multi-sub passivation layer 19 may be set according to actual needs and is not specifically limited here.

[0110] As a possible implementation, Fig.11 and Fig.12As shown, in the case where the first doped semiconductor portion 17 is also arranged in the spacer region 16, and the second doped semiconductor portion 18 also extends to cover the portion of the first doped semiconductor portion 17 corresponding to the spacer region 16, the above-mentioned back contact cell may further include a transparent conductive layer 24. The transparent conductive layer 24 covers the first doped semiconductor portion 17, the second doped semiconductor portion 18 and the majority carrier passivation layer 19. In addition, an insulating groove 25 is arranged in the transparent conductive layer 24, and the insulating groove 25 is used to electrically insulate the majority carrier passivation layer 19 from the second doped semiconductor portion 18 of the minority carrier region 14 and the first doped semiconductor portion 17 of the majority carrier region 15, respectively, and to electrically insulate the second doped semiconductor portion 18 of the minority carrier region 14 from the first doped semiconductor portion 17 of the majority carrier region 15.

[0111] As for the specific location of the insulating groove, it can be set according to actual needs, as long as it can be used in the back contact battery provided in the embodiment of the present invention.

[0112] In a second aspect, an embodiment of the present invention provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.

[0113] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0114] In a third aspect, an embodiment of the present invention provides a method for manufacturing a back-contact battery. Specifically, the method for manufacturing a back-contact battery includes the following steps:

[0115] First, a semiconductor substrate is provided, wherein the semiconductor substrate has a first surface and a second surface relative to each other. The first surface includes a non-electrode collecting region located at the edge, and an electrode collecting region located inside the non-electrode collecting region. The electrode collecting region includes a minority carrier region and a majority carrier region alternately spaced along a first direction. Along the first direction, the minority carrier region located at the outermost edge is closer to the non-electrode collecting region than the majority carrier region located at the outermost edge. Next, a first doped semiconductor portion arranged in the majority carrier region is formed. Next, a second doped semiconductor portion arranged in the minority carrier region is formed. The conductivity type of the second doped semiconductor portion is opposite to that of the first doped semiconductor portion. Next, a majority carrier passivation layer is formed and arranged in the non-electrode collecting region. The thickness of the majority carrier passivation layer is greater than the thickness of the second doped semiconductor portion.

[0116] Specifically, the material and conductivity type of the semiconductor substrate, and the specific distribution of the non-electrode area and the electrode collection area in the first surface can be referred to in the previous text, and will not be repeated here. In addition, the embodiment of the present invention does not specifically limit the formation order of the above-mentioned first doped semiconductor part and the second doped semiconductor part. The "second doped semiconductor part is opposite to the conductivity type of the first doped semiconductor part" in the above-mentioned "form a second doped semiconductor part arranged in the minority carrier area. The conductivity type of the second doped semiconductor part is opposite to that of the first doped semiconductor part" is only a limitation on the conductivity type of the first doped semiconductor part and the second doped semiconductor part, and does not specifically limit the formation order of the two. In the actual manufacturing process, the first doped semiconductor part arranged in the majority carrier area may be formed first, and then the second doped semiconductor part arranged in the minority carrier area may be formed; or the second doped semiconductor part arranged in the minority carrier area may be formed first, and then the second doped semiconductor part arranged in the majority carrier area may be formed.

[0117] The process of forming the first doped semiconductor portion and the second doped semiconductor portion is described below by taking the first doped semiconductor portion being formed first and then the second doped semiconductor portion being formed as an example:

[0118] The first type: when the first doped semiconductor part is only arranged in the majority-carrier region, and the second doped semiconductor part is only arranged in the minority-carrier region, a process such as chemical vapor deposition can be used to form a first intrinsic semiconductor layer arranged in an entire layer. Next, the first intrinsic semiconductor layer can be doped by diffusion or ion implantation, so that the first intrinsic semiconductor layer forms a first doped semiconductor part. Next, a mask layer is formed on the side of the first doped semiconductor part away from the semiconductor substrate. Wherein, when the material of the first doped semiconductor part includes silicon and the first doped semiconductor part is formed by a diffusion process, a doped silicon glass layer is formed on the side of the first doped semiconductor part away from the semiconductor substrate while the first doped semiconductor part is formed. Based on this, when the mask layer is the above-mentioned doped silicon glass layer, it is not necessary to form an additional mask layer. When the mask layer does not include the above-mentioned doped silicon glass layer, a deposition process is required to form an additional mask layer on the side of the first doped semiconductor part away from the semiconductor substrate. At this time, the material of the mask layer can be silicon nitride or silicon oxynitride. Then, an etching process such as laser etching can be used to remove at least the portion of the mask layer corresponding to the spacer and minority carrier regions. Among them, when the majority carrier passivation layer is not formed integrally with the first doped semiconductor part, it is also necessary to remove the portion of the mask layer corresponding to the non-electrode collection area. When the majority carrier passivation layer is formed integrally with the first doped semiconductor part, it is only necessary to remove the portion of the mask layer corresponding to the spacer area and the minority carrier area. Next, under the protection of the mask layer, an etching process such as wet etching can be used to remove the portion of the first doped semiconductor part not covered by the mask layer. Next, a deposition process can be used to form a second intrinsic semiconductor layer with a whole layer arrangement on the first doped semiconductor part, the spacer area, the minority carrier area and the non-electrode collection area. Then, the second intrinsic semiconductor layer can be doped by a process such as diffusion or ion implantation to form a second doped semiconductor part in the second intrinsic semiconductor layer. Then, a mask layer can be formed on the second doped semiconductor part in the manner described above, and the mask layer covers the portion of the second doped semiconductor part corresponding to the minority carrier area. Then, under the protection of the mask layer, the portion of the second doped semiconductor part not covered by the mask layer is removed.

[0119] The second type: when the first doped semiconductor part is also arranged in the spacer area, and the second doped semiconductor part also extends to cover the part of the first doped semiconductor part corresponding to the spacer area, a process such as chemical vapor deposition can be used to form a first intrinsic semiconductor layer arranged in an entire layer. Next, the first intrinsic semiconductor layer can be doped by diffusion or ion implantation, so that the first intrinsic semiconductor layer forms a first doped semiconductor part. Next, a mask layer is formed on the side of the first doped semiconductor part away from the semiconductor substrate. The formation process of the mask layer can refer to the above text and will not be repeated here. Then, an etching process such as laser etching can be used to remove at least the part of the mask layer corresponding to the minority carrier area. Among them, when the majority carrier passivation layer is not formed integrally with the first doped semiconductor part, it is also necessary to remove the part of the mask layer corresponding to the non-electrode collection area. When the majority carrier passivation layer is formed integrally with the first doped semiconductor part, only the part of the mask layer corresponding to the minority carrier area needs to be removed. Next, under the protection of the mask layer, an etching process such as wet etching can be used to remove the part of the first doped semiconductor part not covered by the mask layer. Next, a deposition process can be used to form a second intrinsic semiconductor layer arranged in an entire layer on the first doped semiconductor part, the minority carrier area and the non-electrode collection area. Then, the second intrinsic semiconductor layer can be doped by diffusion or ion implantation to form the second intrinsic semiconductor layer into a second doped semiconductor part. Then, a mask layer can be formed on the second doped semiconductor part in the manner described above, and the mask layer at least covers the portion of the second doped semiconductor part corresponding to the spacer area and the minority carrier area. Wherein, when the back contact battery also includes a hydrogen-containing passivation layer formed integrally with the second doped semiconductor part, the mask layer also needs to cover the portion of the second doped semiconductor part corresponding to the non-electrode collection area. When the back contact battery does not include a hydrogen-containing passivation layer, or the hydrogen-containing passivation layer is not formed integrally with the second doped semiconductor part, the mask layer only needs to cover the portion of the second doped semiconductor part corresponding to the spacer area and the minority carrier area. Then, under the protection of the mask layer, the portion of the second doped semiconductor part not covered by the mask layer is removed.

[0120] From the above content, it can be seen that the above-mentioned first doped semiconductor part can be formed simultaneously with the majority passivation layer, so as to improve the manufacturing efficiency of the back contact battery while reducing the damage of the etchant to the non-electrode collection area and reducing the number of defects in the non-electrode collection area.

[0121] Of course, the multi-child passivation layer can also be formed non-simultaneously with the first doped semiconductor portion. In this case, the embodiment of the present invention does not specifically limit the formation order of the multi-child passivation layer. The multi-child passivation layer can be formed after the first doped semiconductor portion and the second doped semiconductor portion are formed, or before the first doped semiconductor portion and the second doped semiconductor portion are formed, or after manufacturing one of the first doped semiconductor portion and the second doped semiconductor portion and before manufacturing the other. Specifically, a whole layer of multi-child passivation material can be formed, and then, under the protection of the mask layer, the multi-child passivation material is selectively etched, leaving only the portion of the multi-child passivation material corresponding to the non-electrode collection area.

[0122] Exemplarily, after providing a semiconductor substrate, the manufacturing method of the above-mentioned back contact battery may include the steps of: forming a first doped semiconductor material disposed on the first surface in an entire layer. Next, selectively removing the portion of the first doped semiconductor material corresponding to the minority carrier region, so that the portion of the first doped semiconductor material remaining in the majority carrier region and the spacer region forms a first doped semiconductor portion, and the portion of the first doped semiconductor material remaining in the non-electrode collection region forms a majority carrier passivation layer. Next, forming a second doped semiconductor material disposed in an entire layer on the minority carrier region, the first doped semiconductor portion and the majority carrier passivation layer. Next, selectively removing the portion of the second doped semiconductor material corresponding to the majority carrier region, so that the portion of the second doped semiconductor material remaining in the minority carrier region and the spacer region forms a second doped semiconductor portion, and the portion of the second doped semiconductor material remaining in the non-electrode collection region forms at least a portion of a hydrogen-containing passivation layer. In this case, the majority carrier passivation layer and the first doped semiconductor portion are both formed integrally based on the first doped semiconductor material. At least a portion of the hydrogen-containing passivation layer and the second doped semiconductor portion are both formed integrally based on the second doped semiconductor material, so as to improve manufacturing efficiency while reducing the damage of the etchant to the non-electrode collection region and reducing the number of defects in the non-electrode collection region. In addition, the specific manufacturing process in this case can refer to the corresponding manufacturing process in the second case described above, and will not be repeated here.

[0123] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0124] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0125] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to each other; the first surface includes a non-electrode collecting area located at an edge, and an electrode collecting area located inside the non-electrode collecting area; the electrode collecting area includes a minority carrier area and a majority carrier area alternately spaced along a first direction; along the first direction, the minority carrier areas located at the most edges on both sides are closer to the non-electrode collecting area than the majority carrier areas located at the most edges, and the minority carrier areas located at the most edges on both sides are adjacent to the non-electrode collecting area; A first doped semiconductor portion is disposed in the plurality of sub-regions; A second doped semiconductor portion is disposed in the minority carrier region; the conductivity type of the second doped semiconductor portion is opposite to that of the first doped semiconductor portion; and a multi-sub passivation layer, which is arranged in the non-electrode collection area; the thickness of the multi-sub passivation layer is greater than the thickness of the second doped semiconductor part, and the multi-sub passivation layer has the same conductivity type as the first doped semiconductor part; the multi-sub passivation layer includes a third doped semiconductor part arranged on the non-electrode collection area.

2. The back contact cell according to claim 1, characterized in that: Along the first direction, the width of the non-electrode collecting region is smaller than the width of the minority carrier region; And / or, along the first direction, the width of the non-electrode collecting area is less than 1000 μm.

3. The back contact cell according to claim 1, characterized in that: In the first surface, the non-electrode collecting area is further arranged outside the electrode collecting area along a second direction; the second direction is different from the first direction.

4. The back contact cell according to claim 3, wherein the second direction is perpendicular to the first direction; And / or, the width of the non-electrode collecting area along the second direction is less than or equal to the width of the non-electrode collecting area along the first direction.

5. The back contact cell according to claim 1, characterized in that: The material of the third doped semiconductor portion is the same as that of the first doped semiconductor portion.

6. The back contact cell according to claim 1, characterized in that: The back contact cell further comprises a hydrogen-containing passivation layer; the hydrogen-containing passivation layer is arranged on a side of the multi-sub passivation layer away from the semiconductor substrate.

7. The back contact battery according to any one of claims 1 to 6, characterized in that: In the first surface, a region between the majority subregion and the minority subregion along the first direction is a spacing region; The first doped semiconductor portion is also disposed on the spacer region; The second doped semiconductor portion further extends to cover the portion of the first doped semiconductor portion corresponding to the spacing region; in the spacing region, the second doped semiconductor portion and the first doped semiconductor portion are spaced apart from each other along the thickness direction of the semiconductor substrate.

8. The back contact cell according to claim 6, characterized in that: In the case where the back contact cell further comprises the hydrogen-containing passivation layer, at least a portion of the hydrogen-containing passivation layer is integrally continuous with the second doped semiconductor portion.

9. The back contact battery according to any one of claims 1 to 6, characterized in that: The surface of the non-electrode collection area is a polished surface; And / or, the surface of the minority carrier region is suede.

10. The back contact battery according to any one of claims 1 to 6, characterized in that: The multi-sub passivation layer includes a doped polysilicon layer; and / or, the second doped semiconductor portion includes at least one of a doped amorphous silicon layer, a doped microcrystalline silicon layer and a doped nanocrystalline silicon layer; And / or, the conductivity type of the majority-sub passivation layer is N-type, and the conductivity type of the second doped semiconductor portion is P-type.

11. The back contact battery according to any one of claims 1 to 6, characterized in that: The back contact cell further comprises a first interface passivation layer, wherein the first interface passivation layer is disposed between the semiconductor substrate and the first doped semiconductor portion; And / or, the back contact cell further includes a second interface passivation layer, and the second interface passivation layer is at least arranged between the semiconductor substrate and the second doped semiconductor portion.

12. The back contact cell according to claim 11, characterized in that: In the case where the back contact cell further includes the first interface passivation layer and the second interface passivation layer, the first interface passivation layer and the first doped semiconductor portion constitute a first passivation contact structure, and the second interface passivation layer and the second doped semiconductor portion constitute a second passivation contact structure; The first passivation contact structure and the second passivation contact structure have different passivation contact types; and / or the first passivation contact structure is a tunneling passivation contact structure; and / or the second passivation contact structure is a heterogeneous contact structure.

13. A photovoltaic module, characterized in that: Comprising a back contact battery as claimed in any one of claims 1 to 12.

14. A method for manufacturing a back contact battery, characterized in that: include: A semiconductor substrate is provided, wherein the semiconductor substrate has a first surface and a second surface opposite to each other; the first surface includes a non-electrode collecting region located at an edge, and an electrode collecting region located inside the non-electrode collecting region; the electrode collecting region includes a minority carrier region and a majority carrier region alternately spaced along a first direction; along the first direction, the minority carrier region located at the most edges on both sides is closer to the non-electrode collecting region than the majority carrier region located at the most edges, and the minority carrier region located at the most edges on both sides is adjacent to the non-electrode collecting region; forming a first doped semiconductor portion disposed in the plurality of sub-regions; forming a second doped semiconductor portion disposed in the minority carrier region; the second doped semiconductor portion has a conductivity type opposite to that of the first doped semiconductor portion; A multi-sub passivation layer is formed and arranged in the non-electrode collection area; the thickness of the multi-sub passivation layer is greater than the thickness of the second doped semiconductor part, and the multi-sub passivation layer has the same conductivity type as the first doped semiconductor part; the multi-sub passivation layer includes a third doped semiconductor part arranged on the non-electrode collection area.

15. The method for manufacturing a back contact battery according to claim 14, characterized in that: The first doped semiconductor portion and the majority passivation layer are formed simultaneously.

16. The method for manufacturing a back contact battery according to claim 14, characterized in that: In the first surface, a region between the majority subregion and the minority subregion along the first direction is a spacing region; After providing a semiconductor substrate, the method for manufacturing a back contact battery further includes: forming a first doped semiconductor material disposed on the first surface in its entirety; Selectively removing the portion of the first doped semiconductor material corresponding to the minority carrier region, so that the first doped semiconductor material remaining in the majority carrier region and the spacer region forms the first doped semiconductor portion, and the first doped semiconductor material remaining in the non-electrode collection region forms the majority carrier passivation layer; Forming a whole layer of a second doped semiconductor material on the minority carrier region, the first doped semiconductor portion and the majority carrier passivation layer; The portion of the second doped semiconductor material corresponding to the majority-carrier region is selectively removed so that the second doped semiconductor material remaining in the minority-carrier region and the spacer region forms the second doped semiconductor portion, and the second doped semiconductor material remaining in the non-electrode collection region forms at least a partial hydrogen-containing passivation layer.

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