A self - calibrating high - precision hybrid DAC

Abstract

The present invention belongs to the technical field of analog integrated circuits, and specifically relates to a self-calibrating high-precision hybrid DAC. The present invention uses a high N-M bit R-2R resistor type DAC and a low M bit I-DAC to form a hybrid DAC, and the resistor to ground is composed of 2 M‑2 resistors with a single resistor value of r in series, and utilizes the circuit structure characteristics of the lower bits of the hybrid DAC; therefore, in the present invention, the voltage of 2 M LSB can be obtained by dividing the voltage of the high-bit R-2R resistor type DAC, or can be obtained by multiplying 16I in the low-bit I-DAC ref ×2 M‑2 ×r, without the need to compare with an additional reference voltage and the voltage division of the high-bit R-2R resistor type DAC, and the circuit itself can use the lower bits to calibrate the higher bits. The calibration current I cal multiplied by r gives 0.25 LSB, so the calibration circuit can calibrate the minimum voltage to reach 0.25 LSB, making the accuracy of the hybrid DAC higher; and the calibration circuit adopts foreground calibration, with calibration and output separated, which will not affect the speed of the DAC and will not generate additional power consumption during the DAC output.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, relates to digital-to-analog converters in integrated circuits, and specifically relates to a self-calibrated high-precision hybrid DAC. Background Art

[0002] In recent years, with the continuous improvement of requirements in various aspects such as industry, automotive, and communication, the digital-to-analog converter, as a module connecting digital circuits and the analog world, has become increasingly important. Therefore, the research and design of high-precision and high-performance digital-to-analog converters have become an important trend.

[0003] As an important direction of digital-to-analog converters, the use of hybrid DACs can greatly improve the performance of high-precision DACs. Therefore, a hybrid structure is often adopted in high-precision DACs.

[0004] Due to different output structures, hybrid DACs, like traditional segmented DACs, will generate a large deviation at the segmentation point and there will also be a problem of reduced accuracy of high-order outputs. And traditional high-precision DACs will have a problem of mismatch between high-order and low-order due to the segmentation point.

[0005] In order to improve the accuracy of hybrid DACs and ensure that there is no large offset at high orders in hybrid DACs, it is necessary to calibrate the hybrid DACs. Classified by the working mode of calibration, it can be divided into background calibration and foreground calibration; background calibration means that the calibration is always on during operation. Since the signal transmission between the signal paths of the DAC is carried out in parallel, almost no module can exit the normal working mode during the conversion operation. Therefore, background calibration is difficult to implement in hybrid DACs; foreground calibration means that the calibration work is completed before the DAC operates normally, but an additional calibration working state is required. Summary of the Invention

[0006] Aiming at the above existing problems or deficiencies, in order to solve the problems that the high-order output accuracy of existing hybrid DACs decreases due to the use of different architectures and the high-order and low-order mismatch of high-precision DACs themselves due to segmentation, the present invention provides a self-calibrated high-precision hybrid DAC, which utilizes the circuit structure characteristics of the low-order part of the hybrid DAC to calibrate the high-order voltage with the low-order voltage.

[0007] In the high-precision hybrid DAC of the present invention, the low-order part uses an electrical I-DAC to output current, and outputs voltage after passing through the ground resistors in the R-2R resistor array. The high-order part uses an R-2R structure to divide the voltage for output. The output mode is the sum of the high-order and low-order voltages, and the output is at the output point of the high-order R-2R structure. This hybrid structure can combine the advantages of traditional I-DACs having good DNL performance and fast speed and traditional R-2R resistor-type DACs having a compact area and low power consumption.

[0008] A self-calibrating high-precision hybrid DAC has two operating modes: output and calibration. The circuit includes a hybrid DAC, a sample-and-hold circuit, a comparator, a register, and a calibration I-DAC (as shown in the appendix). Figure 1 Shown

[0009] The hybrid DAC is N-bit and includes an I-DAC, a reference voltage source, and an R-2R resistor array (as shown in the appendix). Figure 2 Shown. The reference voltage source and the R-2R resistor array form an R-2R resistor-type DAC. The high N-M bits of the hybrid DAC are an R-2R resistor-type DAC, and the low M bits are an I-DAC.

[0010] The high N-M bits output a voltage by dividing the reference voltage source through the R-2R resistor array. The reference voltage source generates a reference voltage V ref , which is divided by the R-2R resistor array; the R-2R resistor array consists of (N-M-1) resistors R and (N-M+1) resistors 2R, and its resistance to ground is composed of 2 M-2 resistors with a single resistance value of r in series, and the resistance value of the resistance to ground is 2R. The R-2R resistor array converts the reference voltage V ref into V ref / 2, V ref / 4,... V ref / 2 (N-M) , generating the output voltage of the high (N-M) bits of the hybrid DAC. Among them, V ref / 2 (N-M) = 2 M LSB.

[0011] The low M-bit I-DAC consists of a current source array and an I-DAC switch. The current source array generates a reference current I ref and replicates to generate 2I ref and 16I ref . The I-DAC switch controls the number of resistors with a resistance value of r in the resistor to ground through which the current flows. The I ref , 2I ref and 16I ref generated by the current source array flow through the resistor to ground in the R-2R resistor array and output a voltage.

[0012] The size of the LSB of the hybrid DAC is I ref × 4r, 2I ref × 4r = 2LSB, 16I ref × 2 M-2 × r = 2 M LSB. The output V OUT of the hybrid DAC is the superposition of the outputs of the I-DAC and the R-2R resistor-type DAC.

[0013] The input terminal of the sample and hold circuit is connected to the output of the hybrid DAC, and the output terminal is connected to the positive terminal of the comparator; the sample and hold circuit is used to hold the output of the sampled hybrid DAC and input it to the positive terminal of the comparator.

[0014] The positive input terminal of the comparator is connected to the output terminal of the sample and hold circuit, the negative input terminal is connected to the output of the hybrid DAC, and the output terminal is connected to the register; the comparator is used to compare the magnitudes of the inputs at both ends. When the voltage at the positive terminal is greater than the voltage at the negative terminal, a high level is output, otherwise a low level is output, and the comparison result is stored in the register.

[0015] The input terminal of the register is connected to the output terminal of the comparator, and the output terminal is connected to the calibration I-DAC module; the register is used to store the comparison result of the comparator and output the comparison result to the calibration I-DAC as the control signal for the calibration switch.

[0016] The calibration I-DAC includes a calibration switch and a calibration current source array (as shown in the appendix Figure 3 ), where the calibration current I in the calibration current source array cal = I ref . The result stored in the register is used as the control signal for the calibration switch to control the turn-off and closure of the calibration switch of the calibration I-DAC; the calibration switch is used to control the number of connections between the calibration current I cal and the resistor with a resistance value of r in the resistor to ground. The calibration current I cal flows through the resistor to ground in the R-2R resistor array and outputs a calibration voltage. Each bit of the high N-M bit digital input has a corresponding calibration switch and calibration current.

[0017] The entire self-calibrating high-precision hybrid DAC only calibrates the output voltages when the (M + 1)-th bit of the digital input is 1 and the rest are 0, when the (M + 2)-th bit is 1 and the rest are 0... and when the N-th bit is 1 and the rest are 0. Among the voltages output from the hybrid DAC to the sample and hold circuit, 16I ref ×2 M-2 ×r is used to replace the output voltage V ref / 2 (N -M) .

[0018] For the above self-calibrating high-precision hybrid DAC, its control logic (as shown in the appendix Figure 4 ):

[0019] Calibration working mode:

[0020] K = M + 1, that is, when the digital input is that the (M + 1)-th bit is 1 and the rest are 0: First, the sample and hold circuit samples the output voltage 16I generated by the hybrid DAC through the low bitsref ×2 M-2 ×r is connected to the positive terminal of the comparator, and the actual output voltage V of the hybrid DAC ref / 2 (N-M) is connected to the negative terminal of the comparator. Secondly, the comparator compares the magnitudes of the positive and negative terminals and outputs high and low levels. When the output of the comparator is high level, calibration is required. At this time, the calibration switch controls the calibration current I cal flows through the resistor with resistance r in the resistor to ground, and the number of such resistors increases by one, then the voltage at the negative terminal of the comparator increases by I cal ×r = 0.25 LSB of voltage, which is superimposed on the output of the hybrid DAC and continues to be compared. If the comparator outputs a high level, repeat the above calibration process to continue calibration until the comparator outputs a low level, and the calibration mode ends. Finally, the control signal of the calibration switch at this time is stored in the register, and the register stores the calibration switch signal when the (M + 1)-th bit of the digital input is 1 and the rest are 0. At this time, the calibration of the (M + 1)-th bit of the digital input being 1 and the rest being 0 is completed, and the calibration of the (M + 2)-th bit of the digital input being 1 and the rest being 0 is carried out.

[0021] K = M + 2. When the (M + 2)-th bit of the digital input is 1 and the rest are 0: First, the sample and hold circuit samples the output voltage of the hybrid DAC and connects it to the positive terminal of the comparator. Use 16I ref ×2 M-2 ×r to replace the output voltage V when the (M + 1)-th bit of the digital input is 1 and the rest are 0 ref / 2 (N-M) , and the specific voltage is the output voltage V when the (M + 1)-th bit of the digital input is 1 and the rest are 0 ref / 2 (N-M) plus the output voltage 16I ref ×2 M-2 ×r generated by the lower bits. The actual output voltage V of the hybrid DAC ref / 2 (N-M-1) is connected to the negative terminal of the comparator. The remaining process is the same as the case of K = M + 1.

[0022] For other values of K, it is the same as the cases of K = M + 1 and K = M + 2 above; until the calibration of the (N)-th bit of the digital input being 1 and the rest being 0 is completed, which represents the end of the self-calibration work of the entire hybrid DAC. The calibration switch signals corresponding to each bit from the (M + 1)-th bit of the digital input being 1 and the rest being 0 to the (N)-th bit of the digital input being 1 and the rest being 0 are also stored in the register, and the hybrid DAC switches to the output mode.

[0023] Output working mode: For the corresponding digital input, the register controls the calibrated output to be the superposition of the output of the hybrid DAC and the calibrated voltage output by the calibrated I-DAC through the R-2R resistor type DAC.

[0024] In summary, the present invention uses a high N-M bit R-2R resistor type DAC and a low M bit I-DAC to form a hybrid DAC, and the resistor to ground of the R-2R resistor type DAC is composed of 2 resistors in series with a single resistor value of r; by using the circuit structure characteristics of the lower bits of the hybrid DAC, the voltage of the higher bits is calibrated by the voltage of the lower bits. Therefore, in the present invention, the voltage of 2 LSBs can be obtained by dividing the voltage of the higher bit R-2R resistor type DAC, or can be obtained by multiplying 16I in the lower bit I-DAC by 2 × r, without comparing with an additional reference voltage and dividing the voltage of the higher bit R-2R resistor type DAC, and the circuit itself can calibrate the higher bits with the lower bits. The calibration current I multiplied by r gives 0.25 LSB, so the calibration circuit can calibrate the minimum voltage to reach 0.25 LSB, making the accuracy of the hybrid DAC higher; and the calibration circuit uses foreground calibration, with calibration separated from output, which will not affect the speed of the DAC and will not generate additional power consumption during the DAC output. M-2 Figure 16 is a schematic block diagram of the structure of the self-calibrating high-precision hybrid DAC of the present invention. M Figure 17 is a circuit structure diagram of the hybrid DAC of the present invention. ref Figure 18 is a schematic diagram of the connection relationship between the calibration I-DAC and the R-2R resistor array of the present invention. M-2 Figure 19 is a schematic diagram of the self-calibration logic of the present invention. cal Figure 20 is a schematic diagram of the self-calibration logic of the embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Figure 16 is a schematic block diagram of the structure of the self-calibrating high-precision hybrid DAC of the present invention.

[0026] Figure 2 Figure 17 is a circuit structure diagram of the hybrid DAC of the present invention.

[0027] Figure 3 Figure 18 is a schematic diagram of the connection relationship between the calibration I-DAC and the R-2R resistor array of the present invention.

[0028] Figure 4 Figure 19 is a schematic diagram of the self-calibration logic of the present invention.

[0029] Figure 5 Figure 20 is a schematic diagram of the self-calibration logic of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0030] The technical solution of the present invention will be described in detail below with reference to the drawings and embodiments.

[0031] In this embodiment, a 16-bit hybrid DAC is taken as an example, with the higher 8 bits using an R-2R resistor type DAC and the lower 8 bits using an I-DAC. In the self-calibration logic schematic diagram, K represents that the Kth bit of the digital input of the hybrid DAC is 1 and the other bits are 0. The control logic of the above self-calibrating high-precision hybrid DAC is as follows: Figure 5 When the circuit is in the calibration mode: all calibration switches are kept off in the initial state.

[0032] When the circuit is in the calibration mode: all calibration switches are kept off in the initial state.

[0033] K = 9, that is, when the 9th digit of the digital input is 1 and the rest are 0: First, the sample and hold circuit samples the output voltage 16I generated by the hybrid DAC through the lower bits ref ×64×r is connected to the positive terminal of the comparator, and the actual output voltage V of the hybrid DAC ref / 2 8 is connected to the negative terminal of the comparator. Secondly, the comparator compares the magnitudes of the positive and negative terminals and outputs high and low levels. When the comparator outputs a high level, calibration is required. At this time, the calibration switch controls the calibration current I cal flowing through the resistor with a resistance value of r in the resistor to the ground increases by one, then the voltage at the negative terminal of the comparator increases by I cal ×r = 0.25LSB-sized voltage, which is superimposed on the output of the hybrid DAC and continues to be compared. If the comparator outputs a high level, repeat the above steps to continue calibration until the comparator outputs a low level, and the calibration mode ends. Finally, store the control signal of the calibration switch at this time in the register, and the register stores the calibration switch signal when the 9th digit of the digital input is 1 and the rest are 0.

[0034] At this time, the calibration of the 9th digit of the digital input being 1 and the rest being 0 is completed, and the calibration of the 10th digit of the digital input being 1 and the rest being 0 is carried out.

[0035] K = 10, when the 10th digit of the digital input is 1 and the rest are 0: First, the sample and hold circuit samples the output voltage of the hybrid DAC and connects it to the positive terminal of the comparator, and uses 16I ref ×64×r to replace the output voltage V when the 9th digit of the digital input is 1 and the rest are 0 ref / 2 8 , and the specific voltage is the output voltage V when the 9th digit of the digital input is 1 and the rest are 0 ref / 2 8 and the output voltage 16I generated by the lower bits ref ×64×r, and the actual output voltage V of the hybrid DAC ref / 2 7 is connected to the negative terminal of the comparator. The remaining process is the same as the case of K = 9.

[0036] For the cases of K = 11, K = 12, K = 13, K = 14, K = 15, K = 16, they are similar to the cases of K = 9 and K = 10 above. Until the calibration of the 16th digit of the digital input being 1 and the rest being 0 is completed, it represents the end of the self-calibration work of the entire hybrid DAC. The calibration switch signals corresponding to each digit from the 9th digit of the digital input being 1 and the rest being 0 to the 16th digit of the digital input being 1 and the rest being 0 are also stored in the register, and the hybrid DAC switches to the output mode.

[0037] When the circuit is in the output mode: for the corresponding digital input register control, the calibrated output is the superposition of the output of the hybrid DAC and the calibrated voltage output by the calibrated I-DAC through the R-2R resistor DAC.

[0038] As can be seen from the above embodiments, the hybrid DAC architecture of the present invention and its grounding resistor are composed of multiple resistors with a resistance value of r in series. The voltage of the lower level can be used to calibrate the voltage of the higher level, and the accuracy is higher; moreover, the calibration circuit adopts foreground calibration, and the calibration is separated from the output, which will not affect the speed of the DAC and will not generate additional power consumption when the DAC outputs.

Claims

1. A self - calibrating high - precision hybrid DAC, characterized in that: It includes a hybrid DAC, a sample-and-hold circuit, a comparator, a register, and a calibration I-DAC; The hybrid DAC is N-bit and includes an I-DAC, a reference voltage source, and an R-2R resistor array; the reference voltage source and the R-2R resistor array form an R-2R resistor-type DAC. The high N-M bits of the hybrid DAC are the R-2R resistor-type DAC, and the low M bits are the I-DAC; The high N-M bits divide the reference voltage source through an R-2R resistor array to output a voltage, and the reference voltage source generates a reference voltage V ref , and voltage division is performed through the R-2R resistor array; the R-2R resistor array is composed of N-M-1 resistors R and N-M+1 resistors 2R, and its resistance to ground is composed of a number of 2 M-2 resistors with a single resistance value of r in series, and the resistance value of the resistance to ground is 2R; the R-2R resistor array converts the reference voltage V ref into V ref / 2, V ref / 4, … V ref / 2 (N-M) , and generates the output voltage of the high N-M bits of the hybrid DAC, where V ref / 2 (N-M) = 2 M LSB; The low M-bit I-DAC consists of a current source array and I-DAC switches. The current source array generates a reference current I ref and duplicates it to generate 2I ref and 16I ref . The I-DAC switches control the number of resistors with a resistance value of r in the resistors to ground. The I ref , 2I ref and 16I ref generated by the current source array flow through the resistors to ground in the R-2R resistor array and output a voltage. The LSB size of the hybrid DAC is I ref ×4r, 2I ref ×4r = 2LSB, 16I ref ×2 M-2 ×r = 2 M LSB; The output V of the hybrid DAC OUT is the superposition of the outputs of the I-DAC and the R-2R resistor DAC; The input end of the sample-and-hold circuit is connected to the output of the hybrid DAC. The sample-and-hold circuit is used to hold the output of the sampled hybrid DAC and input it to the positive terminal of the comparator; The positive input terminal of the comparator is connected to the output terminal of the sample-and-hold circuit, the negative input terminal is connected to the output of the hybrid DAC, and the output terminal is connected to the register; the comparator is used to compare the magnitudes of the inputs at both positive and negative terminals. When the positive terminal voltage is greater than the negative terminal voltage, it outputs a high level, otherwise it outputs a low level, and the comparison result is stored in the register; The input terminal of the register is connected to the output terminal of the comparator, and the output terminal is connected to the calibration I-DAC module; the register is used to store the comparison result of the comparator and output the comparison result to the calibration I-DAC as the control signal of the calibration switch; The calibration I-DAC includes a calibration switch and a calibration current source array, where the calibration current I in the calibration current source array cal = I ref ; The result stored in the register is used as the control signal of the calibration switch to control the turn-off and closure of the calibration switch of the calibration I-DAC; The calibration switch is used to control the calibration current I cal the number of connections with the resistor with a resistance value of r in the resistance to ground, and output a calibration voltage; each digit of the high N-M bit digital input has a corresponding calibration switch and calibration current; The entire self-calibrating high-precision hybrid DAC only calibrates the output voltages when the (M + 1)-th digit of the digital input is 1 and the rest are 0, when the (M + 2)-th digit is 1 and the rest are 0... and when the N-th digit is 1 and the rest are 0; among the voltages output from the hybrid DAC to the sample-and-hold circuit, 16I ref ×2 M-2 ×r is used to replace the output voltage V when the (M + 1)-th digit of the digital input is 1 and the rest are 0 ref / 2 (N-M) .

2. The self-calibrating high-precision hybrid DAC according to claim 1, wherein The specific control logic is as follows: K = M + 1, that is, when the digital input has a 1 in the (M + 1)-th bit and 0s in the remaining bits: First, the sample-and-hold circuit samples the output voltage 16I generated by the lower bits of the hybrid DAC. ref ×2 M-2 ×r is connected to the positive terminal of the comparator, and the actual output voltage V of the hybrid DAC ref / 2 (N-M) is connected to the negative terminal of the comparator; Second, the comparator compares the magnitudes of the positive and negative terminals and outputs high and low levels. When the comparator outputs a high level, calibration is required. At this time, the calibration switch controls the calibration current I cal flowing through the resistor with a resistance value of r in the resistor to ground increases by one, then the voltage at the negative terminal of the comparator increases by I cal ×r = 0.25 LSB of voltage, which is superimposed on the output of the hybrid DAC and continues to be compared; If the comparator outputs a high level, repeat the above calibration process to continue calibration until the comparator outputs a low level, and the calibration mode ends; Finally, the control signal of the calibration switch at this time is stored in the register, and the register stores the calibration switch signal when the digital input has a 1 in the (M + 1)-th bit and 0s in the remaining bits; At this time, the calibration of the digital input with a 1 in the (M + 1)-th bit and 0s in the remaining bits is completed, and the calibration of the digital input with a 1 in the (M + 2)-th bit and 0s in the remaining bits is carried out; K = M + 2. When the digital input has a 1 at the (M + 2)-th bit and 0s at the other bits: First, the sample-and-hold circuit samples the output voltage of the hybrid DAC and connects it to the positive terminal of the comparator. Use 16I ref ×2 M-2 ×r to replace the output voltage V when the digital input has a 1 at the (M + 1)-th bit and 0s at the other bits ref / 2 (N-M) . The specific voltage is the sum of the output voltage V / 2 when the digital input has a 1 at the (M + 1)-th bit and 0s at the other bits ref / 2 (N-M) and the output voltage 16I ref ×2 M-2 ×r generated by the lower bits. The actual output voltage V of the hybrid DAC ref / 2 (N-M-1) is connected to the negative terminal of the comparator; the remaining process is the same as the case of K = M + 1; For other values of K, it is the same as the cases of K = M + 1 and K = M + 2 above; until the calibration is completed when the Nth digit of the digital input is 1 and the rest are 0, which represents the end of the self-calibration work of the entire hybrid DAC. The calibration switch signals corresponding to each digit from the (M + 1)th digit of the digital input being 1 and the rest being 0 to the Nth digit of the digital input being 1 and the rest being 0 are also stored in the register, and the hybrid DAC switches to the output mode; Output working mode: For the corresponding digital input, the register controls the output after calibration to be the superposition of the output of the hybrid DAC and the calibration voltage output by the calibration I-DAC through the R-2R resistor-type DAC.

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