A method for network-on-chip communication of a spiking neural network and a network-on-chip

Abstract

The present disclosure provides a kind of pulse neural network network-on-chip communication method and network-on-chip, the shortest distance between source neuron and target area is propagated in the present disclosure, and global broadcast, cell broadcast and point-to-point propagation are unified, effectively simplify routing algorithm and calculation process, reduce routing logic complexity and network-on-chip delay;And, the data packet forwarding method driven by destination is mainly used, the logic judgment of event data whether receiving data packet is placed in receiving end node, so that the data packet of propagation can be fixed size, the process of finding routing table is saved in transmission process, effectively reduce the storage capacity of routing table, flexibly handle the receiving determination of broadcast communication;At the same time, the uniform field format is used for a variety of types of data packet in the embodiment of the present disclosure, the logic of router processing data packet is simplified, and then the delay generated by data packet through router is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of electronic information technology, and in particular to an on-chip network communication method for a spiking neural network and an on-chip network. Background Technology

[0002] Neuromorphic computing is a novel computing technology that draws upon the computational theories of information processing patterns and structures in biological nervous systems. It fundamentally transforms existing computing architectures and systems at multiple levels, including hardware implementation and software algorithms, resulting in significant improvements in energy consumption, computing power, and computational efficiency. One software-level attempt at neuromorphic computing is the Spiking Neural Network (SNN). Unlike Artificial Neural Networks (ANNs), neurons in a Spiking Neural Network generate very small data packets. However, due to the large number of neurons and the numerous synaptic connections between them, the network is filled with a massive amount of small data packets.

[0003] Network-on-a-Chip (NoC) is attractive for spiking neural networks (SNNs) because it promotes parallelism, reconfigurability, network topology independence, and network scalability, making it a commonly used interconnect architecture in neuromorphic computing platforms. To support the communication characteristics of SNNs, many neuromorphic computing platforms have proposed solutions. SpiNNaker, a computer designed by the University of Manchester specifically to support various brain communications, can carry a large number of very small data packets. It employs a lightweight multicast packet routing mechanism based on a 2D triangular mesh and supports various packet types. However, the output port decision for the multicast path is based on a tri-state CAM, which leads to excessive power consumption. IBM's TrueNorth, Intel's Loihi, and Tsinghua University's Tianji chip all use 2D-mesh topologies but only support unicast mechanisms, failing to effectively alleviate the communication pressure on NoCs. Stanford University's Neurogrid neuromorphic system contains 16 neural chips and uses a tree network to interconnect neural arrays. Its routing strategy is naturally tree-based multicast, which has its structural peculiarities and cannot be widely applied to other topologies.

[0004] Therefore, how to achieve efficient communication between neurons in neuromorphic chips is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this disclosure is to provide an on-chip network communication method and an on-chip network for spiking neural networks, so as to solve the problem that neurons in the prior art cannot achieve efficient communication.

[0006] The embodiments of this disclosure adopt the following technical solution: an on-chip network communication method for a spiking neural network, comprising: determining all region coordinates of all target regions corresponding to each source neuron based on the node coordinates of the target node where the target neuron of each source neuron is located, wherein each target region is a rectangular region in the on-chip network array covering at least a portion of the target nodes, and the target nodes covered by multiple target regions do not overlap; storing the region coordinates in the transmission logic memory of the node where the source neuron is located; when the source neuron generates a spiking event, accessing the transmission logic memory corresponding to the source neuron to obtain the region coordinates, and forming a spiking event data packet based on the region coordinates, the target node label value, and the target node first-level receiver table index value; transmitting the spiking event data packet to the relay node closest to the source neuron in the target region; broadcasting the spiking event data packet in the target region starting from the relay node, wherein each node receiving the spiking event data packet determines whether to receive the event data in the spiking event data packet based on the target node label value and the target node first-level receiver table index value.

[0007] In some embodiments, neurons from the same group of neurons are placed in the same node or multiple adjacent nodes.

[0008] In some embodiments, the region coordinates are the node coordinates of a pair of nodes located diagonally opposite each other in the target region.

[0009] In some embodiments, transmitting the pulse event data packet to the relay node closest to the source neuron in the target region includes: transmitting the pulse event data packet to the relay node closest to the source neuron in the target region using a shortest distance horizontal-vertical deadlock-free routing method.

[0010] In some embodiments, broadcasting the pulse event data packet within the target area starting from the relay node includes: the relay node transmitting the pulse event data packet in directions other than the transmission direction and the direction beyond the target area boundary; after receiving the pulse event data packet, other nodes within the target area, excluding the relay node, broadcast it according to the transmission direction of the pulse event data packet, wherein, when the pulse event data packet is transmitted horizontally, the node transmits the pulse event data packet in directions other than the transmission direction and the direction beyond the target area boundary; when the pulse event data packet is transmitted vertically, the node transmits the pulse event data packet along the original direction.

[0011] In some embodiments, each node receiving the pulse event data packet determines whether to receive the event data in the pulse event data packet based on the target node tag value and the target node and the receiving table index value. This includes: when the node receives the pulse event data packet, it searches the first-level receiving table in the receiving logic memory according to the target node's first-level receiving table index value, and determines whether the tag value in the entry obtained from the first-level receiving table is consistent with the target node tag value in the pulse event data packet; if the entry exists, the node receives the event data in the pulse event data packet; otherwise, it discards the pulse event data packet.

[0012] In some embodiments, before each node that receives the pulse event data packet determines whether to receive the event data in the pulse event data packet based on the target node tag value and the target node first-level receiver table index value, the method further includes: the node comparing the dwell time of the pulse event data packet on the on-chip network with a preset fatigue threshold; if the dwell time is greater than the preset fatigue threshold, the node discards the pulse event data packet; if the dwell time is less than or equal to the preset fatigue threshold, the node determines whether to receive the event data in the pulse event data packet.

[0013] This disclosure also provides an on-chip network for a spiking neural network, comprising at least: nodes arranged in an array, wherein the nodes are used to implement at least the steps of the on-chip network communication method for the spiking neural network described above.

[0014] In some embodiments, each node includes at least a computational core and a router, and the router includes at least a transmit logic memory and a receive logic memory; wherein, the transmit logic memory stores at least a first-level transmit table and a second-level transmit table, the first-level transmit table being indexed by the axon ID of the source neuron, and used to store the base address and number of the second-level transmit table corresponding to the source neuron; the second-level transmit table is used to store the region coordinates of the target region corresponding to the source neuron, the target node label value, and the target node first-level receive table index value; the receive logic memory stores at least a first-level receive table and a second-level receive table, the first-level receive table being indexed by the target node first-level receive table index value, and used to store the label value of the entry and the base address and number of the second-level receive table; the second-level receive table is used to store the target neuron ID and dendrite ID.

[0015] This disclosure also provides an electronic device that includes at least the on-chip network described above.

[0016] The beneficial effects of this disclosure are as follows: it adopts the shortest distance propagation between the source neuron and the target area and unifies global broadcast, cell broadcast and point-to-point propagation, effectively simplifying the routing algorithm and calculation process, reducing the complexity of routing logic and on-chip network latency; furthermore, it adopts a destination-driven packet forwarding method, placing the logical judgment of whether to receive the packet event data in the receiving node, so that the propagated packet can be of a fixed size, eliminating the process of looking up the routing table during transmission, effectively reducing the routing table storage capacity, and flexibly handling the reception determination of broadcast communication; at the same time, this disclosure adopts a unified field format for various types of packets, simplifying the logic of the router in processing packets, thereby reducing the latency caused by packets passing through the router. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the topology of the on-chip network in the first embodiment of this disclosure;

[0019] Figure 2 This is a flowchart of the on-chip network communication method in the first embodiment of this disclosure;

[0020] Figure 3 This is an illustration of the data stored in the transmission logic memory in the first embodiment of this disclosure;

[0021] Figure 4 This is a schematic diagram of the format of the pulse event data packet in the first embodiment of this disclosure;

[0022] Figure 5 This is a schematic diagram illustrating the path of a data packet propagating from a source node to a target region in the first embodiment of this disclosure;

[0023] Figure 6 This is a schematic representation of the data stored in the receiving logic memory in the first embodiment of this disclosure. Detailed Implementation

[0024] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0025] Neuromorphic computing is a novel computing technology that draws upon the computational theories of information processing patterns and structures in biological nervous systems. It fundamentally transforms existing computing architectures and systems at multiple levels, including hardware implementation and software algorithms, resulting in significant improvements in energy consumption, computing power, and computational efficiency. One software-level attempt at neuromorphic computing is the Spiking Neural Network (SNN). Unlike Artificial Neural Networks (ANNs), neurons in a Spiking Neural Network generate very small data packets. However, due to the large number of neurons and the numerous synaptic connections between them, the network is filled with a massive amount of small data packets.

[0026] Network-on-a-Chip (NoC) is attractive for spiking neural networks (SNNs) because it promotes parallelism, reconfigurability, network topology independence, and network scalability, making it a commonly used interconnect architecture in neuromorphic computing platforms. To support the communication characteristics of SNNs, many neuromorphic computing platforms have proposed solutions. SpiNNaker, a computer designed by the University of Manchester specifically to support various brain communications, can carry a large number of very small data packets. It employs a lightweight multicast packet routing mechanism based on a 2D triangular mesh and supports various packet types. However, the output port decision for the multicast path is based on a tri-state CAM, which leads to excessive power consumption. IBM's TrueNorth, Intel's Loihi, and Tsinghua University's Tianji chip all use 2D-mesh topologies but only support unicast mechanisms, failing to effectively alleviate the communication pressure on NoCs. Stanford University's Neurogrid neuromorphic system contains 16 neural chips and uses a tree network to interconnect neural arrays. Its routing strategy is naturally tree-based multicast, which has its structural peculiarities and cannot be widely applied to other topologies.

[0027] To achieve efficient communication between neurons in neuromorphic chips, the first embodiment of this disclosure provides an on-chip network communication method for spiking neural networks. By adjusting the routing strategies of each node in the on-chip network, it unifies various routing mechanisms such as unicast, multicast, and broadcast, and has the characteristics of flexibility, scalability, and extensibility. It can also carry massive data packets, obtain a more balanced link load, effectively reduce average and maximum transmission delays, improve on-chip network throughput and alleviate network congestion, and the storage overhead is within an acceptable range. Figure 1 This diagram illustrates the topology of the on-chip network in this embodiment. Each circle represents a router, and each router corresponds to a computing core. Figure 1 As shown in the square diagram, the computational kernel is used to place the neurons of the spiking neural network. A computational kernel and a router form a node in an on-chip network, and the router facilitates the exchange of information between nodes. It's important to note that a computational kernel typically holds 2^36 neurons. n In this embodiment, a computing core includes 2048 neurons, and the data sent or received by these 2048 neurons are transmitted through the router corresponding to the computing core.

[0028] like Figure 1 As shown, the nodes are arranged in a two-dimensional array and numbered. Figure 1 The network topology uses an 11×12 2-D mesh structure, with each router having five ports: East, South, West, North, and Local. Furthermore, this embodiment uses a two-dimensional Cartesian coordinate system to mark the positions of each node in the network; for example, using... Figure 1 The node in the upper left corner is the origin of the coordinate system. The horizontal direction is used as the x-axis and the vertical direction is used as the y-axis. The position of each node is represented by the (X, Y) coordinates.

[0029] Figure 2 The flowchart of the on-chip network communication method in this embodiment is shown, specifically including steps S10 to S50:

[0030] S10: Based on the node coordinates of the target node where the target neuron of each source neuron is located, determine the coordinates of all target regions corresponding to each source neuron.

[0031] S20, store the region coordinates in the transmit logic memory of the node where the source neuron is located.

[0032] A source neuron is a neuron that generates pulse events, that is, a neuron that forms pulse event data packets and sends them to other neurons. The neuron that receives pulse event data packets is a target neuron. A data packet to be transmitted by a source neuron can have multiple target neurons. Multiple target neurons can be located in different target nodes. Therefore, based on the correspondence between neurons and nodes, the node coordinates of the target node where the target neuron of each neuron is located can be determined.

[0033] Subsequently, the target nodes corresponding to each source neuron are clustered based on their node coordinates to form one or more target clusters. Each target cluster is marked with a rectangle in the network topology, and the area marked by each rectangle corresponds to a target region. Therefore, the number of target regions can be one or more, and each target region can be represented using region coordinates. In this embodiment, each target region covers at least a portion of all target nodes, and the target nodes covered by different target regions do not overlap. The set of all target regions corresponds to the nodes where all target neurons of the source neurons are located. When representing the target region, the node coordinates of a pair of nodes located diagonally opposite each other in the target region can be used to represent the region coordinates. For example, the node coordinates of the top-left and bottom-right nodes in the target region can be used as the region coordinates of the target region, or the node coordinates of the bottom-left and top-right nodes can be used.

[0034] Once the coordinates of the target region of the source neuron are determined, they can be stored in the transmission logic memory of the node where the source neuron resides, facilitating access and retrieval when pulse events are generated subsequently. Specifically, the transmission logic memory is located in the router of the node where the source neuron resides, primarily used to store information related to the target neuron, which is accessed and retrieved when assembling pulse event data packets. In some embodiments, the transmission logic memory stores at least a first-level transmission table and a second-level transmission table, such as... Figure 3 As shown, the first-level sending table uses the axon ID of the source neuron as an index to store the base address (addr) and number (num) of the second-level sending table corresponding to the source neuron; the second-level sending table is accessed based on addr and num, and this second-level sending table is used to store the region coordinates of the target region corresponding to the source neuron. Figure 3 The target area is represented by its top-left coordinate (left_top) and bottom-right coordinate (right_down), the target node's tag value, and the target node's first-level receiving table index value.

[0035] S30: When the source neuron generates a pulse event, access the corresponding transmission logic memory of the source neuron to obtain the region coordinates, and form a pulse event data packet based on the region coordinates, the target node label value, and the target node first-level receiver table index value.

[0036] In this embodiment, the format of the pulse event data packet is as follows: Figure 4 As shown, the size of a single data packet is uniformly 64 bits. The highest two bits represent the data packet type, including unicast (00), multicast (01), and broadcast (10). The next two 8-bit fields represent the upper left coordinate (X0, Y0) and lower right coordinate (X1, Y1) of the target area, respectively, which is sufficient for a mesh network of size 11×12 (132 nodes). The Tag and Index are used to determine whether a node in the target area receives the data packet and do not play a role in the transmission phase. The last field (Data) represents the payload.

[0037] Corresponding to different transmission types, in unicast, there is only one target node, and the target area contains only that target node. In this case, the top-left and bottom-right nodes of the target area are both the target node, and the contents of the second and third fields in the data packet are the node coordinates of the target node. For broadcast, the target node is all nodes of the on-chip network, and the area coordinates of the target area are the top-left and bottom-right coordinates of the on-chip network. For multicast, there may be one or more target areas. Therefore, when forming data packets, data packets with the same payload but different target node information are formed for different target areas.

[0038] S40 transmits the pulse event data packet to the relay node in the target region that is closest to the source neuron.

[0039] S50, the pulse event data packet is broadcast in the target area starting from the relay node. Each node that receives the pulse event data packet determines whether to receive the event data in the pulse event data packet based on the target node tag value and the target node first-level receiver table index value.

[0040] In this embodiment, when actually transmitting the pulse event data packet, it is first transmitted to the relay node closest to the node where the source neuron is located in the target area, and then the data packet is quickly transmitted within the target area by means of broadcasting. Specifically, the node where the source neuron is located can use the shortest-distance horizontal-vertical (X-Y) deadlock-free routing method to transmit the pulse event data packet to the relay node closest to the source neuron in the target area. The shortest-distance X-Y deadlock-free routing method in this embodiment is that for any node not in the target area, when receiving the data packet, if the abscissa X of the current node coordinates (X, Y) is X < X0, the router transmits the data packet to the eastward port; if the abscissa X of the current node coordinates (X, Y) is X > X1, the router transmits the data packet to the westward port; if X0 ≤ X ≤ X1 and Y < Y1, the data packet is transmitted to the northward port, if Y > Y0, the data packet is transmitted to the southward port, and if Y0 ≤ Y ≤ Y1, the data packet is transmitted to the local port, that is, the relay node.

[0041] When the data packet is transmitted to the relay node, it proves that the data packet has been transmitted into the target area. At this time, broadcasting is carried out within the target area starting from the relay node, so that each node in the target area that receives the pulse event data packet judges whether the data packet is sent to itself according to the target node label value and the target node first-level reception table index value in the data packet; if it is judged that the data packet is sent to itself, the event data (i.e., the payload) in the data packet is received, and if the data packet is not sent to itself, the data packet is discarded.

[0042] In the actual process of broadcasting, for any node in the target area, whether the node is the target node or not, it will cooperate with the broadcast logic in the area to transmit the pulse event data packet. Specifically, the data packet is first transmitted to the relay node, and this relay node must be located at the boundary of the target area. Combining the node arrangement of the network-on-chip and the location of the relay node, the relay node transmits the data packet in other directions except the incoming direction and the direction beyond the boundary of the target area; and for other nodes in the target area except the relay node, after receiving the pulse event data packet, they broadcast according to the incoming direction of the pulse event data packet. Among them, when the pulse event data packet comes in from the horizontal direction, the node transmits the pulse event data packet in other directions except the incoming direction and the direction beyond the boundary of the target area; when the pulse event data packet comes in from the vertical direction, the node transmits the pulse event data packet along the original direction.

[0043] Figure 5This diagram illustrates the path of a data packet propagating from a source node (i.e., the node containing the source neuron) to a target region. First, the source node (0,1) generates a data packet destined for regions (3,0) and (4,2). Then, using the shortest distance XY deadlock-free routing method, the intermediate node is determined to be (3,1). At this point, the data packet has been delivered to the target region. Next, broadcast routing is performed. The data packet from the intermediate node (3,1) travels from west to east, and its north-south direction does not exceed the boundary of the target region. Therefore, the intermediate node delivers the data packet to nodes (3,0), (4,1), and (3,2). These three nodes then perform the next broadcast routing step. At this point, for node (3,0), its data packet travels from the Y direction. However, if the data packet continues to be transmitted in its original direction, it will exceed the boundary of the target area. Therefore, node (3,0) will no longer transmit the data packet, and the same applies to node (3,2). As for node (4,1), its data packet is transmitted from west to east and comes from the X direction. In addition to the direction of transmission, it should transmit the data packet to the east, south, and north respectively. However, its transmission to the east will exceed the boundary of the target area. Therefore, node (4,1) only needs to transmit the data packet to the north and south respectively. At this time, all nodes in the target area have received the data packet, so that each node can determine whether it is the target node based on the relevant information carried by the data packet.

[0044] In some embodiments, the size of the target region determines the time it takes for all nodes within the region to receive data packets. Furthermore, since there may be more than one target region, and their locations may be relatively dispersed, the time required for all target nodes to receive data packets is prolonged. Therefore, when configuring the on-chip network, it is preferable to place neurons belonging to the same neuron group in the same node or multiple adjacent nodes to make the target nodes as adjacent as possible after clustering, thereby reducing the number or size of target regions and allowing broadcasting to be completed in a shorter period. It should be noted that the neurons in the same neuron group mentioned in this embodiment refer to neurons located at the same level in the spiking neural network or those that actually perform the same function. These neurons may have the same target neuron or simultaneously serve as a source neuron. By setting up the same or adjacent nodes, the purpose of improving data packet propagation speed and reducing latency is achieved.

[0045] Furthermore, each node receiving a pulse event data packet within the target area will determine whether it is a target node. This determination is made based on the target node tag value carried in the data packet and the target node's first-level receiver table index field. Specifically, corresponding to the design of the transmit logic memory in each router, it should also include a receive logic memory to determine whether to receive a pulse event by referring to the data table stored in the receive logic memory when a node receives a data packet.

[0046] In some embodiments, the receive logic memory stores at least a first-level receive table and a second-level receive table, such as... Figure 6 As shown, the first-level receive table uses the first-level receive table index as an index to store the tag values ​​of the entries, as well as the base addresses and quantities of the second-level receive table. The second-level receive table stores the target neuron ID and dendrite ID. The node first indexes the first-level receive table based on the index field in the data packet. Then, it compares the tag field in the data packet with the tag values ​​of the entries in the first-level receive table. If the tag value of an entry in the first-level receive table matches the tag field in the data packet, the current data packet is considered acceptable; otherwise, the data packet is discarded. Furthermore, the node also retrieves the IDs and dendrite IDs of all target neurons in the second-level receive table based on the base addresses and quantities carried in entries that match the tag field in the data packet. These are used to access the synaptic weights in the core data region, preparing for neuron computation.

[0047] In some embodiments, before each node that receives a pulse event data packet determines whether to receive the event data in the pulse event data packet based on the target node tag value and the target node's first-level receiver table index value, the method further includes: the node comparing the dwell time of the pulse event data packet on the on-chip network with a preset fatigue threshold; if the dwell time is greater than the preset fatigue threshold, it is determined that the transmission delay of the data packet is too high, and there may be congestion and deadlock. In this case, new data packets may have already been transmitted, but the old data packets have not yet arrived. Therefore, in this case, the node discards the data packet without processing it; if the dwell time is less than or equal to the preset fatigue threshold, the node determines that the data packet is valid and then performs the determination process mentioned above. In actual settings, different preset fatigue thresholds can be set to control the maximum transmission delay of the data packet and avoid congestion and deadlock caused by hardware resource limitations in the on-chip network.

[0048] This embodiment employs the shortest distance propagation between the source neuron and the target region and unifies global broadcast, cell broadcast, and point-to-point propagation, effectively simplifying the routing algorithm and calculation process, reducing routing logic complexity and on-chip network latency. Furthermore, it adopts a destination-driven packet forwarding method, placing the logical judgment of whether to receive the packet event data in the receiving node, allowing the propagated packets to be of fixed size. This eliminates the need to look up the routing table during transmission, effectively reducing routing table storage capacity and flexibly handling broadcast communication reception decisions. Simultaneously, this embodiment uses a unified field format for various types of packets, simplifying the router's packet processing logic and reducing latency caused by packets passing through the router. Additionally, this embodiment provides a fatigue packet loss mechanism, mitigating network congestion based on the principle that brain fatigue leads to a reduced probability of pulse firing.

[0049] Based on the same inventive concept, the second embodiment of this disclosure provides an on-chip network of a spiking neural network, the architecture of which refers to... Figure 1 As described in detail in the first embodiment, it will not be repeated here. The nodes arranged in the array in the on-chip network transmit information between the nodes based on the communication method provided in the first embodiment of this disclosure, which can effectively simplify the routing logic, reduce the latency of the on-chip network, and alleviate the bandwidth pressure of the on-chip network.

[0050] In some embodiments, each node includes at least a computational core and a router, and the router includes at least a transmit logic memory and a receive logic memory. The transmit logic memory stores at least a first-level transmit table and a second-level transmit table. The first-level transmit table, indexed by the axon ID of the source neuron, stores the base address and number of entries in the second-level transmit table corresponding to the source neuron. The second-level transmit table stores the region coordinates of the target region corresponding to the source neuron, the target node label value, and the target node's first-level receive table index value. The receive logic memory stores at least a first-level receive table and a second-level table. The first-level receive table, indexed by the target node's first-level receive table index value, retrieves the label value of the entry and the base address and number of entries in the second-level receive table. The second-level receive table stores the target neuron ID and dendrite ID. Additionally, the receive logic memory should also store... Figure 6 The second-level receiving table and data content table shown are for reference only. Figure 6 The format and conventional spiking neural network settings are described in detail in this embodiment, but will not be explained in detail here.

[0051] Based on the same inventive concept, the third embodiment of this disclosure provides an electronic device that includes at least an on-chip network as provided in the second embodiment, in order to realize the transmission and processing of massive pulse data and effectively reduce latency.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method of network-on-chip communication for a spiking neural network, the method comprising: The method comprises the following steps: According to the node coordinates of the target nodes where the target neurons of each source neuron are located, all the region coordinates of all the target regions corresponding to each source neuron are determined, wherein each target region is a rectangular region in the network-on-chip array covering at least a part of the target nodes, and the target nodes covered by the target regions do not overlap with each other; The region coordinates are stored in the sending logic memory of the node where the source neuron is located; When the source neuron generates a pulse event, the sending logic memory corresponding to the source neuron is accessed to obtain the region coordinates, and a pulse event data packet is formed according to the region coordinates, the target node label value and the target node first-level receiving table index value; The pulse event data packet is transmitted to the relay node in the target region closest to the source neuron; The pulse event data packet is broadcasted in the target region starting from the relay node, and each node receiving the pulse event data packet judges whether to receive the event data in the pulse event data packet according to the target node label value and the target node first-level receiving table index value.

2. The network-on-chip communication method of claim 1, wherein, Neurons in the same neuron group are placed in the same node or adjacent nodes.

3. The network-on-chip communication method of claim 1, wherein, The region coordinates are the node coordinates of a pair of nodes located at opposite positions in the target region.

4. The network-on-chip communication method of claim 1, wherein, The pulse event data packet is transmitted to the relay node in the target region closest to the source neuron by using the shortest distance horizontal-vertical deadlock-free routing mode. The pulse event data packet is broadcasted in the target region starting from the relay node by using the shortest distance horizontal-vertical deadlock-free routing mode.

5. The network-on-chip communication method of claim 1, wherein, The pulse event data packet is transmitted by the relay node to other directions except the incoming direction and the direction beyond the target region boundary. After receiving the pulse event data packet, the nodes in the target region except the relay node broadcast the pulse event data packet according to the incoming direction of the pulse event data packet, wherein, in the case that the pulse event data packet comes from the horizontal direction, the nodes transmit the pulse event data packet to other directions except the incoming direction and the direction beyond the target region boundary; in the case that the pulse event data packet comes from the vertical direction, the nodes transmit the pulse event data packet along the original direction. The node receiving the pulse event data packet judges whether to receive the event data in the pulse event data packet according to the target node label value and the target node first-level receiving table index value.

6. The network-on-chip communication method of claim 1, wherein, After receiving the pulse event data packet, the node searches the first-level receiving table in the receiving logic memory corresponding to the node according to the target node first-level receiving table index value, and judges whether the label value in the entry obtained by the first-level receiving table according to the index value is consistent with the target node label value in the pulse event data packet. ​ In the presence of the entry, the node receives event data in the pulse event data packet; otherwise, discards the pulse event data packet.

7. The network-on-chip communication method according to any one of claims 1 to 6, characterized in that, Before each node receiving the pulse event data packet judges whether to receive event data in the pulse event data packet according to the target node tag value and the target node primary receiving table index value, further comprising: The node compares the residence time of the pulse event data packet on the network on a chip with a preset fatigue threshold value; In the case where the residence time is greater than the preset fatigue threshold value, the node discards the pulse event data packet; In the case where the residence time is less than or equal to the preset fatigue threshold value, the node judges whether to receive event data in the pulse event data packet.

8. An on-chip network of spiking neural networks, characterized in that, At least comprising: The nodes arranged in an array, the nodes are used to implement at least the steps of the network on a chip communication method of the spiking neural network according to any one of claims 1 to 7.

9. The network-on-chip of claim 8, wherein, Each node at least includes a computing core and a router, and the router at least includes a sending logic memory and a receiving logic memory; wherein, The sending logic memory at least stores a first level sending table and a second level sending table, the first level sending table is indexed by an axon ID of a source neuron, and is used to store a base address and a number of the second level sending table corresponding to the source neuron; the second level sending table is used to store region coordinates of a target region corresponding to the source neuron, a target node tag value and a target node primary receiving table index value; The receiving logic memory at least stores a first level receiving table and a second level receiving table, the first level receiving table is indexed by a target node primary receiving table index value in the pulse event data packet, and is used to store a tag value of an entry and a base address and a number of the second level receiving table; the second level receiving table is used to store a target neuron ID and a dendrite ID.

10. An electronic device, comprising: At least comprising the network on a chip according to claim 8 or 9.

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