A multi-level memory cell based on igzo thin film resistance change and a preparation method thereof

Abstract

The application relates to the field of microelectronic devices, in particular to a multi-level memory unit based on IGZO thin film resistance change and a preparation method thereof. The multi-level memory unit based on IGZO thin film resistance change comprises a bottom electrode layer, the bottom electrode layer is Ti, a bottom electrode oxide layer is arranged on the bottom electrode layer, and the bottom electrode oxide layer is TiO2. The application can effectively improve the multi-level storage performance of the IGZO thin film resistance change memory unit.

Description

Technical Field

[0001] This invention relates to the field of microelectronic devices, and in particular to a multilevel memory cell based on IGZO thin film resistive switching and its fabrication method. Background Technology

[0002] With the rapid development of big data, artificial intelligence, and cloud computing, the demand for high-performance memory, characterized by large capacity, low cost, and fast storage speed, is increasing. Resistive random access memory (RRAM) has attracted widespread attention and become a research hotspot in recent years due to its advantages such as simple device structure (metal-insulator-metal), low power consumption, fast read / write speed, high on / off ratio, high storage density, long retention time (greater than 10 years), strong scalability, and compatibility with complementary metal-oxide-semiconductor (CMOS) processes. It is expected to become the next generation of non-volatile memory, thereby replacing traditional floating-gate Flash memory.

[0003] RRAM stores information by changing the resistance state of the storage material through an applied voltage signal. A high resistance state represents "0", and a low resistance state represents "1". These high / low resistance states can switch between each other, thus enabling information storage. The process of transitioning from a high resistance state to a low resistance state is called the set process, and the process of transitioning from a low resistance state to a high resistance state is called the reset process. Typically, a limiting current is set during the set process to protect the device from hard breakdown. By changing the limiting current or the set stop voltage during the set process, different resistance states can be obtained, thereby achieving multi-level storage performance.

[0004] Typical multilevel memory requires the ability to achieve multiple stable and repeatable intermediate resistance states between high and low resistance states to meet the performance requirements of multilevel memory. However, when the stability and reliability of the device's cyclic switching are poor, the stability and repeatability of these intermediate resistance states between high and low resistance states are often difficult to control. Therefore, it is necessary to develop RRAM devices with stable performance.

[0005] Currently, one of the important research directions for RRAM devices is how to improve their stability, including the stability of IV characteristics and the switching voltage (V). set / V reset The stability of multi-level storage devices, including the stability of the storage window (HRS / LRS) and the stability of multi-level storage performance, is a concern. Therefore, it is necessary to develop a low-cost, simple, and more efficient fabrication method to obtain stable multi-level storage devices.

[0006] Therefore, those skilled in the art are dedicated to developing a multilevel memory cell based on IGZO thin film resistive switching and its fabrication method. Summary of the Invention

[0007] In view of the above-mentioned deficiencies of the prior art, the technical problem solved by the present invention is to provide an inductively coupled oxygen plasma oxidation treatment method to prepare a stable IGZO thin film multilevel memory cell.

[0008] To achieve the above objectives, the present invention provides a multi-level memory cell based on IGZO thin film resistive switching, including a bottom electrode layer, wherein the bottom electrode layer is Ti, and a bottom electrode oxide layer is provided on the bottom electrode layer, wherein the bottom electrode oxide layer is TiO2.

[0009] Preferably, from bottom to top, it includes a silicon oxide substrate, a bottom lead adhesion layer, a bottom lead layer, the bottom electrode layer, the bottom electrode oxide layer, a dielectric layer, and a top electrode layer.

[0010] Preferably, the silicon oxide substrate is a silicon wafer on which a SiO2 oxide layer is grown by thermal oxidation; the bottom lead adhesion layer material is one of Cr, Ni, and Ti; the bottom lead layer material is one of Pt and Au; the dielectric layer material is an IGZO thin film; and the top electrode layer material is one of Pt and Au.

[0011] Preferably, the SiO2 oxide layer in the silicon oxide substrate has a thickness of 200-500 nm; the bottom lead adhesion layer has a thickness of 2-5 nm; the bottom lead layer has a thickness of 15-20 nm; the bottom electrode layer has a thickness of 25-35 nm; the bottom electrode oxide layer has a thickness of 3-6 nm; the dielectric layer material has a thickness of 15-35 nm; and the top electrode layer has a thickness of 50-100 nm.

[0012] Preferably, the bottom electrode oxide layer is prepared by inductively coupled oxygen plasma surface oxidation.

[0013] This invention also provides a method for fabricating a multi-level memory cell based on IGZO thin-film resistive switching, comprising the following steps:

[0014] 1) Clean the silicon oxide wafer to obtain a clean silicon oxide substrate;

[0015] 2) On a cleaned silicon oxide substrate, a bottom lead adhesion layer, a bottom lead layer, and a bottom electrode layer are formed;

[0016] 3) The bottom electrode layer is oxidized by inductively coupled oxygen plasma surface oxidation to generate a rough TiO2 oxide layer, i.e., the bottom electrode oxide layer;

[0017] 4) Prepare IGZO thin film dielectric layer;

[0018] 5) Prepare the top electrode layer.

[0019] Preferably, in step 3), the oxygen plasma oxidation treatment time is 50-600 s;

[0020] Preferably, in step 1), the cleaning process for the silicon oxide wafer is as follows:

[0021] 11) Place the silicon oxide wafer into the first mixed solution and clean it at 60-90℃ for 10-20 minutes;

[0022] 12) Rinse with deionized water;

[0023] 13) Place in the second mixed solution, wash at 60-90℃ for 10-20 minutes, rinse with deionized water, and finally blow dry with nitrogen.

[0024] The first mixed solution is a solution in which hydrogen peroxide, ammonia and water are mixed in a molar ratio of 1:1:5; the second mixed solution is a solution in which hydrogen peroxide, hydrochloric acid and water are mixed in a molar ratio of 1:1:5.

[0025] Preferably, step 2) specifically includes the following steps:

[0026] 21) On a cleaned silicon oxide substrate, a photoresist mask pattern for the bottom lead layer is prepared;

[0027] 22) The bottom lead adhesion layer and the bottom lead layer are prepared on it by electron beam evaporation, and then the bottom electrode lead layer of the device is prepared by lift-off process. The bottom electrode lead layer of the device is the general term for the bottom lead adhesion layer and the bottom lead layer.

[0028] 23) Fabricate a bottom metal electrode, i.e., a bottom electrode layer, with a patterned structure.

[0029] Preferably, in step 4), an IGZO thin film dielectric layer is prepared by magnetron sputtering, wherein the IGZO target material is composed of In2O3, Ga2O3, and ZnO, the target material purity is above 99.99%, and the IGZO target material is bonded to a 1.8-2.5mm copper backplate.

[0030] The beneficial effects of this invention are: this invention can effectively improve the switching voltage (V) of IGZO thin-film resistive switching devices. set / V reset It exhibits uniformity, stability in high / low resistivity states, and is simple to prepare with low cost, while also providing stable multi-level storage performance. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the device structure according to a specific embodiment of the present invention.

[0032] Figure 2This is an AFM image showing the surface morphology changes of the bottom electrode layer before and after oxygen plasma treatment in a specific embodiment of the present invention.

[0033] Figure 3 This is an XPS analysis characterization diagram of the surface material of the bottom electrode layer before and after oxygen plasma treatment in a specific embodiment of the present invention.

[0034] Figure 4 This is a comparison diagram of the electrical characteristics of the device before and after oxygen plasma treatment of the bottom electrode layer in a specific embodiment and comparative example of the present invention.

[0035] Figure 5 This is a diagram showing the test results of the multi-level storage characteristics of the device before and after oxygen plasma treatment of the bottom electrode layer in a specific embodiment and comparative example of the present invention.

[0036] Figure 6 This is a graph showing the multi-level storage performance results of the device after multiple cycles of testing in a normal atmospheric environment and oxygen plasma treatment for 150 seconds, according to a specific embodiment of the present invention.

[0037] Figure 7 This is a graph showing the test results of the retention characteristics of the multi-level storage performance of the device after 150s of oxygen plasma treatment in a normal atmospheric environment according to a specific embodiment of the present invention. Detailed Implementation

[0038] The present invention will be further described below with reference to the accompanying drawings and embodiments. It should be noted that in the description of the present invention, terms such as "upper," "lower," "left," "right," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific manner. Therefore, they should not be construed as limitations on the present invention. Terms such as "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] like Figure 1 As shown, a multi-level memory cell based on IGZO thin film resistive switching includes, from bottom to top, a silicon oxide substrate S1, a bottom lead adhesion layer S2, a bottom lead layer S3, a bottom electrode layer S4, a bottom electrode oxide layer S5, a dielectric layer S6, and a top electrode layer S7. That is, the present invention is composed of the aforementioned structures stacked sequentially.

[0040] IGZO (indium gallium zinc oxide) refers to indium gallium zinc oxide, which consists of indium, gallium, zinc, and oxide.

[0041] In this design, the silicon oxide substrate S1 is a silicon wafer with a SiO2 oxide layer grown on its surface through thermal oxidation. The bottom lead adhesion layer S2 is made of one or more of Cr, Ni, and Ti. The bottom lead layer S3 is made of one of Pt and Au. The bottom electrode layer S4 is made of Ti. The bottom electrode oxide layer S5 is made of TiO2. The dielectric layer S6 is made of an IGZO thin film. The top electrode layer S7 is made of one of Pt and Au. The bottom electrode oxide layer S5 is obtained by inductively coupled oxygen plasma surface oxidation.

[0042] The thickness of the SiO2 oxide layer in the silicon oxide substrate S1 is 200-500 nm. In this embodiment, the thickness of the SiO2 oxide layer prepared by the following method is 300 nm. In other embodiments, the thickness can be between 200-500 nm. The thickness of the bottom lead adhesion layer S2 is 2-5 nm, the thickness of the bottom lead layer S3 is 15-20 nm, the thickness of the bottom electrode layer S4 is 25-35 nm, the thickness of the bottom electrode oxide layer S5 is 3-6 nm, the thickness of the IGZO thin film dielectric layer S6 is 15-35 nm, and the thickness of the top electrode layer S7 is 50-100 nm.

[0043] The multi-level memory cell based on IGZO thin-film resistive switching in this embodiment can be fabricated by the following method, including the following steps:

[0044] 1) The silicon oxide wafer is cleaned to obtain a clean silicon oxide substrate S1;

[0045] This step includes,

[0046] 11) Place the silicon oxide wafer into the first mixed solution and clean it at 60-90℃ for 10-20 minutes;

[0047] 12) Rinse with deionized water;

[0048] 13) Place in the second mixed solution, wash at 60-90℃ for 10-20 minutes, rinse with deionized water, and finally blow dry with nitrogen.

[0049] The first mixed solution is a mixture of hydrogen peroxide, ammonia, and water in a molar ratio of 1:1:5; the second mixed solution is a mixture of hydrogen peroxide, hydrochloric acid, and water in a molar ratio of 1:1:5.

[0050] In this embodiment, the silicon oxide wafer is a silicon wafer on which a 300nm thick SiO2 oxide layer is grown by thermal oxidation, specifically a SiO2 (300nm) / Si (500μm) substrate.

[0051] 2) On a cleaned silicon oxide substrate, a bottom lead adhesion layer S2, a bottom lead layer S3, and a bottom electrode layer S4 are formed. The bottom lead adhesion layer S2 is made of Cr, Ni, or Ti; the bottom lead layer S3 is made of Pt or Au; and the bottom electrode layer S4 is made of Ti. Specific steps include:

[0052] 21) On a clean silicon oxide substrate, a photoresist mask pattern for the bottom lead is prepared by spin-coating LOR adhesive, baking the adhesive, spin-coating photoresist again, pre-baking, exposure, development, microscopic inspection, and post-baking.

[0053] In this step, the LOR photoresist used is 5A from the LOR photoresist series. Other LOR photoresists can also be used in other embodiments, with the thickness controlled at 500-1500nm. Meanwhile, the photoresist used for the second spin coating is a positive photoresist, which can be one of AZ701, AZ5214, or Ruihong 304. In this embodiment, AZ5214 is used. The thickness of the positive photoresist is 800-1500nm. The solution used in the lift-off process is dimethyl sulfoxide (DMSO). The developer used can be one of the positive photoresist developer RZX-3038 or ZX-238. In this embodiment, the orthogonal developer RZX-3038 is used.

[0054] 22) Electron beam evaporation was used to prepare the bottom lead adhesion layer S2 and the bottom lead layer S3 on it respectively, and then the bottom electrode lead layer of the device was prepared by the lift-off process.

[0055] In this embodiment, the lead adhesion layer S2 is 5 nm in size and is made of Ti. In other embodiments, the bottom lead adhesion layer S2 can also be made of Cr or Ni. The bottom lead layer S3 is 15 nm in size and is made of Au. In other embodiments, the bottom lead layer S3 can also be made of Pt.

[0056] 23) The bottom metal electrode of the device with a patterned structure, namely the bottom electrode layer S4, is prepared by sequentially spin-coating photoresist, pre-baking, exposure, development, microscopic inspection, post-baking, metal evaporation, lift-off and other processes to prepare the bottom metal electrode of the device with a patterned structure, namely the bottom electrode layer S4.

[0057] In steps 21-23), the photolithography process employs conventional photolithography techniques, such as ultraviolet lithography or laser direct-write lithography. In this embodiment, a MicroWriter ML3 maskless laser direct-write lithography machine from Durham Magneto Optics (UK) is used. The photolithography parameters are: laser direct-write exposure wavelength of 385nm, laser direct-write resolution of 0.6μm, and laser direct-write energy density of 120mJ / cm². 2 The exposure mode is the conventional mode, which will not be described in detail in this patent.

[0058] 3) The bottom electrode layer S4 metal surface of the device is oxidized by inductively coupled oxygen plasma surface oxidation to generate a rough TiO2 oxide layer, namely the bottom electrode oxide layer S5. In this embodiment, the inductively coupled oxygen plasma oxidation treatment time is 150s; in other embodiments, the treatment time can be 50-600s. The thickness of the TiO2 layer obtained in this embodiment is approximately 5nm (the thickness of the TiO2 layer is obtained by ellipsometry measurement). The surface morphology of the samples before and after treatment is characterized by atomic force microscopy (AFM), and the results are as follows. Figure 2 As shown. Surface material analysis of samples before and after treatment was performed using X-ray photoelectron spectroscopy (XPS), and the results are as follows. Figure 3 As shown. From Figure 3 It can be seen that, before oxygen plasma oxidation treatment, the Ti metal film at 454.1 eV... 2+ The XPS peaks of the Ti metal film are quite prominent, indicating that the surface of the Ti metal film before oxygen plasma treatment contains a large amount of metallic Ti. Ti also appeared in the XPS spectrum of the sample. 4+ The XPS peaks in the Ti metal film are mainly due to the presence of a small amount of TiO2 on the surface caused by natural oxidation in the air, but the main component of the Ti metal film surface is still metallic Ti. However, after oxygen plasma oxidation treatment for 150 s, the Ti metal film shows peaks at 459.1 eV and 464.5 eV. 4+ The XPS peak of the state is dominant, while the Ti peak at 454.1 eV is dominant. 2+ The XPS peak of the state almost disappeared, indicating that the Ti metal film surface had been oxidized to TiO2 after oxygen plasma oxidation treatment for 150s.

[0059] In this invention, an inductively coupled oxygen plasma surface oxidation method is used: it mainly utilizes a high-frequency electric field to ionize oxygen molecules into oxygen ions and free electrons, and then uses electric and magnetic fields to accelerate and bombard the oxygen ions and inject them into the material surface. Compared with conventional oxygen plasma surface oxidation, it has stronger directionality, stronger bombardment force and better effect, making it easier for the material surface to be oxidized to form a thicker and rougher oxide layer.

[0060] In this embodiment, the parameters for the inductively coupled oxygen plasma surface oxidation method are as follows: the source power of the inductive coupling is 400W, the bias power of the inductive coupling is 100W, the O2 gas flow rate is 100sccm, the working gas pressure is 8mtorr, and the oxygen plasma oxidation treatment time is 150s.

[0061] 4) Preparation of dielectric layer S6: Based on step 3), an IGZO thin film dielectric layer is prepared by magnetron sputtering. The molar ratio of the IGZO target components used is In₂O₃:Ga₂O₃:ZnO = 1:1:1, the target purity is above 99.99%, and the IGZO target is bonded to a 2mm copper backing plate. In this embodiment, the process parameters for preparing the IGZO thin film by magnetron sputtering are: background vacuum of 2.5 × 10⁻⁶ mm. -4 Pa, working pressure is 1 Pa, radio frequency (RF) sputtering power is 100 W, the flow rates of argon and oxygen introduced during sputtering are 50 sccm and 8 sccm respectively, the sample substrate temperature during sputtering is room temperature, the sample tray rotation speed is 9 r / min, and the sputtering rate is approximately 5 nm / min.

[0062] 5) Fabrication of the top electrode layer S7: In this embodiment, Pt is used as the top electrode of the device. The process involves spin-coating photoresist, pre-baking, exposure, development, microscopic inspection, post-baking, metal evaporation, and lift-off to fabricate the top metal electrode with a patterned structure, i.e., the top electrode layer S7. The fabrication process for the top electrode layer is the same as that for the bottom electrode layer, and the thickness is 50 nm. In other embodiments, Au can be used for the top electrode layer, and the thickness can be increased to the range specified in this invention.

[0063] Based on this, photoresist was sequentially spin-coated onto the top electrode layer S7, followed by pre-baking, exposure, development, microscopic inspection, and post-baking to prepare the etching window of the patterned photoresist mask. Then, the IGZO film on the bottom electrode of the device was etched using a GSE200Plus inductively coupled plasma (ICP) system to prepare the probe contact window for the bottom electrode. The sample was then subjected to acetone low-frequency ultrasonic removal of the photoresist, propanol low-frequency ultrasonic cleaning, and finally nitrogen drying to complete the fabrication of the patterned device. In other words, photolithography and dry etching processes were used to etch and expose the metal connecting leads of the bottom electrode. Dry etching parameters: the etching gas was a mixture of argon (Ar), chlorine (Cl2), and boron trichloride (BCl3); the etching power was 300W (Scr RF Power) and 70W (Bias RF Power); the etching chamber pressure was 8 mTorr; and the etching rate was 0.9 nm / s. Finally, a multi-level memory cell with resistive switching of IGZO thin film was successfully fabricated, with a device cell area of ​​15×15μm. 2 .

[0064] The above photolithography processes are all conventional processes and will not be described in detail.

[0065] Comparative Example:

[0066] The present invention provides a comparative embodiment, which differs from the embodiment only in that step 3) is omitted, namely the preparation step of the bottom electrode oxide layer S5—TiO2 oxide layer, as a comparative device.

[0067] The electrical characteristics of the two sets of devices were obtained by connecting the embodiment and comparison devices to a Summit 11000B-M probe station using a Keithley 4200-SCS semiconductor analyzer, as shown below. Figure 4 As shown, from Figure 4 As can be seen from the diagram, the device in this embodiment (left side), which has undergone oxygen plasma oxidation treatment for 150 seconds, exhibits more stable performance, lower operating voltage, and better repeatability of the IV characteristic curve in multiple cycle tests compared to the comparative embodiment on the right side. Figure 5 The test results of the multi-level storage characteristics of the two are as follows: Figure 5 As can be seen from the diagram, the device (i.e., the left side of this embodiment) after oxygen plasma oxidation treatment for 150 seconds is more stable than the comparative embodiment on the right. Figure 6 To assess the multi-level storage performance of devices after multiple cycle tests following a 150s oxygen plasma oxidation treatment, it is possible to... Figure 6 It can be seen that the device after oxygen plasma oxidation treatment for 150 seconds has a multi-level storage performance of more than 4 levels, and there is no degradation after more than 500 continuous cycles. Figure 7 The results show the retention characteristics of the multi-level storage performance of the device at room temperature after 150s of oxygen plasma oxidation treatment. Figure 7 It can be seen that after oxygen plasma oxidation treatment for 150 seconds, the device exhibits good multi-level storage performance retention, with a retention time of over 10 seconds at room temperature. 5 Therefore, it can be shown that the multi-level memory cell based on IGZO thin-film resistive switching of the present invention has very stable multi-level storage performance.

[0068] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A multi-level memory cell based on IGZO resistive switching, characterized in that: Including the bottom The bottom electrode layer (S4) is Ti, and a bottom electrode oxide layer (S5) is provided on the bottom electrode layer (S4), wherein the bottom electrode oxide layer (S5) is TiO2; From bottom to top, it includes a silicon oxide substrate (S1), a bottom lead adhesion layer (S2), a bottom lead layer (S3), a bottom electrode layer (S4), a bottom electrode oxide layer (S5), a dielectric layer (S6), and a top electrode layer (S7). The SiO2 oxide layer in the silicon oxide substrate (S1) has a thickness of 200-500 nm; the bottom lead adhesion layer (S2) has a thickness of 2-5 nm; the bottom lead layer (S3) has a thickness of 15-20 nm; the bottom electrode layer (S4) has a thickness of 25-35 nm; the bottom electrode oxide layer (S5) has a thickness of 3-6 nm; the dielectric layer (S6) has a thickness of 15-35 nm; and the top electrode layer (S7) has a thickness of 50-100 nm. The bottom electrode oxide layer (S5) is prepared by inductively coupled oxygen plasma surface oxidation.

2. The multi-level memory cell based on IGZO resistive switching as described in claim 1, characterized in that: The silicon oxide substrate (S1) is a silicon wafer on which a SiO2 oxide layer is grown by thermal oxidation; the bottom lead adhesion layer (S2) is made of one of Cr, Ni, or Ti; the bottom lead layer (S3) is made of one of Pt or Au; the dielectric layer (S6) is made of IGZO; and the top electrode layer (S7) is made of one of Pt or Au.

3. A method for fabricating a multi-level memory cell based on IGZO resistive switching as described in claim 1 or 2, characterized in that: Includes the following steps: 1) Clean the silicon oxide wafer to obtain a clean silicon oxide substrate (S1). 2) On the cleaned silicon oxide substrate (S1), a bottom lead adhesion layer (S2), a bottom lead layer (S3), and a bottom electrode layer (S4) are formed. 3) The bottom electrode layer (S4) is oxidized by inductively coupled oxygen plasma surface oxidation to generate a thin layer of rough TiO2 oxide layer, namely the bottom electrode oxide layer (S5). 4) Prepare the dielectric layer (S6); 5) Prepare the top electrode layer (S7).

4. The method for fabricating a multi-level memory cell based on IGZO resistive switching as described in claim 3, characterized in that: In step 3), the oxidation treatment time is 50-600s.

5. The method for fabricating a multi-level memory cell based on IGZO resistive switching as described in claim 3, characterized in that, In step 1), the silicon oxide wafer cleaning process is as follows: 11) Place the silicon oxide wafer into the first mixed solution and clean it at 60-90℃ for 10-20 minutes; 12) Rinse with deionized water; 13) Place in the second mixed solution, wash at 60-90℃ for 10-20 minutes, rinse with deionized water, and finally dry with nitrogen gas; The first mixed solution is a solution in which hydrogen peroxide, ammonia and water are mixed in a molar ratio of 1:1:5; the second mixed solution is a solution in which hydrogen peroxide, hydrochloric acid and water are mixed in a molar ratio of 1:1:

5.

6. The method for fabricating a multi-level memory cell based on IGZO resistive switching as described in claim 3, characterized in that, Step 2) specifically includes the following steps: 21) On a cleaned silicon oxide substrate, a photoresist mask pattern for the bottom leads is fabricated; 22) The bottom lead adhesion layer (S2) and the bottom lead layer (S3) are prepared on it by electron beam evaporation, and then the bottom electrode lead layer of the device is prepared by photoresist stripping process. The bottom electrode lead layer of the device is the general term for the bottom lead adhesion layer and the bottom lead layer. 23) Fabricate the bottom metal electrode of the device with a patterned structure, namely the bottom electrode layer (S4).

7. The method for fabricating a multi-level memory cell based on IGZO resistive switching as described in claim 3, characterized in that, In step 4), an IGZO dielectric layer is prepared by magnetron sputtering. The IGZO target used is composed of In2O3, Ga2O3, and ZnO with a purity of 99.99% or higher. The IGZO target is bonded to a 1.8-2.5 mm copper backplate.

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