Integrated planarization method and structure suitable for CrSi resistor laser trimming
By employing multilayer dielectric structure and chemical mechanical polishing, the surface roughness problem of CrSi resistors caused by planarization etching was solved, achieving integrated planarization of CrSi resistors, ensuring the accuracy and reliability of laser trimming, and improving product yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-06
- Publication Date
- 2026-04-07
AI Technical Summary
Existing planarization etching processes, while achieving macroscopic planarization, increase the microscopic roughness of the CrSi resistor surface, affecting the accuracy and reliability of laser trimming, leading to unstable laser absorption, decreased ablation accuracy, and trimming failure.
By employing multilayer dielectric layer structures and chemical mechanical polishing, an integrated planarization structure suitable for CrSi resistors is formed through global planarization etching, surface roughness reduction, and dielectric layer growth, ensuring surface smoothness and uniformity.
Without increasing the difficulty of the process, effective planarization of CrSi resistors was achieved, surface roughness was improved, the stringent requirements of laser trimming were met, and product yield and reliability were improved.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor device manufacturing, in particular to an integrated planarization method and structure suitable for CrSi resistance laser trimming. BACKGROUND
[0002] Integrated circuit manufacturing processes usually involve multiple thin film deposition and patterning steps, which can result in topographical irregularities on the wafer surface. In order to perform subsequent fine lithography and thin film deposition on uneven surfaces, planarization etching becomes a critical process step. This process usually uses plasma bombardment or other methods to etch the wafer surface as a whole, non-selectively, to flatten the surface protrusions and achieve global or local planarization.
[0003] However, this commonly used planarization etching process has an inherent and easily overlooked technical defect: the bombardment of plasma on the material surface, while achieving macroscopic planarization, often destroys the surface lattice structure or chemical bonds at the microscopic level, resulting in a significant increase in surface roughness. This microscopic roughness deterioration is manifested as more nanoscale depressions, scratches, or a more "rough" surface. This surface unevenness introduced by the planarization process itself has a serious negative impact on subsequent processes, especially for devices that are highly sensitive to surface state. A typical application scenario is the laser trimming process of CrSi (chromium-silicon) thin film resistors.
[0004] In semiconductor device manufacturing, in order to obtain accurate resistance values, a laser beam is usually used to precisely ablate the CrSi resistor body to adjust its resistance to the target range. This process requires the resistor body surface to have excellent smoothness and uniformity to ensure stable and controllable laser beam energy absorption and ablation effect. When the surface roughness after planarization etching is too large, the following problems will occur:
[0005] Laser absorption rate is unstable: rough surfaces will cause the laser beam to be diffusely reflected, making the actual laser energy distribution on the CrSi material uneven, difficult to predict and control.
[0006] Ablation precision is reduced: the microscopic unevenness of the surface will interfere with the depth and shape of the laser ablation, causing the trimming amount to deviate from the expected value, and even causing damage to the resistor body or forming micro-cracks.
[0007] Trimming failure: in the worst case, excessive surface roughness will make the laser trimming process completely unable to stabilize and accurately trim the resistance of the CrSi resistor to the preset target value range, resulting in a decrease in product yield.
[0008] In summary, the existing planarization etching process solves the problem of macroscopic flatness, but introduces a new problem of micro roughness deterioration, which seriously affects the performance and manufacturability of precision components such as CrSi resistance, and restricts the improvement of product yield and reliability. Therefore, there is an urgent need in the art for a new technical solution that can achieve effective planarization while avoiding or significantly improving surface roughness to meet the strict requirements of subsequent high-performance devices, especially laser trimming process. SUMMARY
[0009] The purpose of the present application is to provide an integrated planarization method suitable for CrSi resistance laser trimming, comprising the following steps:
[0010] S1 provides a semiconductor substrate, at least one first device area and at least one second device area are divided on the semiconductor substrate.
[0011] Forming an independent first metal layer, a first intermetallic dielectric layer and a second intermetallic dielectric layer in the first device area.
[0012] Forming a first intermetallic dielectric layer and a second intermetallic dielectric layer in the second device area.
[0013] S2 performs global planarization etching treatment on the second intermetallic dielectric layer, and retains a thickness h to form a second intermetallic dielectric layer with large surface roughness.
[0014] S3 reduces the surface roughness of the second intermetallic dielectric layer with large surface roughness to form a second intermetallic dielectric layer with reduced surface roughness.
[0015] Global growth is performed on the surface of the second intermetallic dielectric layer with reduced surface roughness to form a third intermetallic dielectric layer.
[0016] S4 forms a thin film resistance in the second device area and forms a fourth intermetallic dielectric layer by global growth.
[0017] S5 partially removes the first intermetallic dielectric layer, the second intermetallic dielectric layer, the third intermetallic dielectric layer and the fourth intermetallic dielectric layer, thereby exposing part of the surface of the first metal layer and the thin film resistance.
[0018] S6 forms a second metal layer on the fourth intermetallic dielectric layer, so that the second metal layer is in contact with the first metal layer and the thin film resistance, respectively.
[0019] Further, the semiconductor substrate is one of silicon and germanium silicon or a combination thereof.
[0020] The first intermetallic dielectric layer is one of silicon oxide and silicon nitride.
[0021] The second intermetallic dielectric layer is one of silicon oxide and silicon nitride.
[0022] The third intermetallic dielectric layer is one of silicon oxide and silicon nitride.
[0023] The fourth intermetallic dielectric layer is one of silicon oxide and silicon nitride.
[0024] Further, in step S2, the thickness of the second intermetallic dielectric layer removed by the planarization etching process is determined by the thickness of the second intermetallic dielectric layer required to be reserved on the first metal layer structure.
[0025] Further, in step S3, the surface roughness of the second intermetallic dielectric layer with relatively large surface roughness is reduced by chemical mechanical polishing, chemical solution or spin coating method, and the third intermetallic dielectric layer is formed on the first device region and the second device region by deposition.
[0026] Further, in step S4, the step of forming a thin film resistor in the second device region is: depositing a thin film resistor in the second device region, etching the excess thin film resistor, and forming the fourth intermetallic dielectric layer on the first device region and the second device region by deposition.
[0027] Further, the thin film resistor is a CrSi resistor.
[0028] Further, in step S5, the first intermetallic dielectric layer, the second intermetallic dielectric layer, the third intermetallic dielectric layer and the fourth intermetallic dielectric layer above the first metal layer of the first device region are partially etched to expose part of the surface of the first metal layer.
[0029] The first intermetallic dielectric layer, the second intermetallic dielectric layer, the third intermetallic dielectric layer and the fourth intermetallic dielectric layer above the edge of the thin film resistor of the second device region are partially etched to expose part of the surface of the thin film resistor.
[0030] Further, before the deposition of the second metal layer, the deposition of Ti / TIN / W material is also performed.
[0031] Further, in step S6, the step of forming a second metal layer on the fourth intermetallic dielectric layer is: depositing a second metal layer on the fourth intermetallic dielectric layer, making the second metal layer contact the first metal layer and the thin film resistor respectively, etching the excess metal, and forming a metal lead-out end.
[0032] The integrated planarization structure is suitable for laser trimming of CrSi resistors and is prepared by the method.
[0033] The technical effect of the present application is self-evident. The present application can realize an integrated planarization method and structure suitable for CrSi resistance laser trimming without significantly increasing the process difficulty and process complexity, thereby realizing effective planarization, avoiding or significantly improving the surface roughness, and ultimately meeting the strict requirements of laser trimming and other processes. BRIEF DESCRIPTION OF DRAWINGS
[0034] Figure 1 is a flowchart of an embodiment of the integrated planarization method and structure suitable for CrSi resistance laser trimming of the present application.
[0035] Figures 2-10 is a schematic diagram of a semiconductor structure in each step of the embodiment of the present application.
[0036] BRIEF DESCRIPTION OF DRAWINGS:
[0037] 100 - semiconductor substrate; 101 - first intermetallic dielectric layer; 102 - second intermetallic dielectric layer; 102' - second intermetallic dielectric layer with large surface roughness after planarization and etching; 102" - second intermetallic dielectric layer with reduced surface roughness; 103 - first metal layer; 104 - third intermetallic dielectric layer; 105 - thin film resistance; 106 - fourth intermetallic dielectric layer; 107 - second metal layer. DETAILED DESCRIPTION
[0038] The present application will be further described below in conjunction with embodiments, but should not be understood as limiting the above-mentioned subject matter of the present application to the following embodiments. Various substitutions and modifications can be made according to ordinary technical knowledge and conventional means in the art without departing from the above-mentioned technical idea of the present application, and all such substitutions and modifications should be included in the protection scope of the present application.
[0039] Example 1:
[0040] The integrated planarization method suitable for CrSi resistance laser trimming comprises the following steps:
[0041] S1 provides a semiconductor substrate 100, and divides at least one first device region and at least one second device region on the semiconductor substrate 100.
[0042] In the first device region, an independent first metal layer 103, a first intermetallic dielectric layer 101, and a second intermetallic dielectric layer 102 are formed.
[0043] In the second device region, a first intermetallic dielectric layer 101 and a second intermetallic dielectric layer 102 are formed.
[0044] S2 performs global planarization etching on the second intermetallic dielectric layer 102, and keeps a thickness h, to form a second intermetallic dielectric layer 102' with a large surface roughness.
[0045] S3 reduces the surface roughness of the second intermetallic dielectric layer 102' with a large surface roughness, to form a second intermetallic dielectric layer 102'' with a reduced surface roughness.
[0046] Global growth is performed on the surface of the second intermetallic dielectric layer 102'' with a reduced surface roughness, to form a third intermetallic dielectric layer 104.
[0047] S4 forms a thin film resistor 105 in the second device region, and performs global growth to form a fourth intermetallic dielectric layer 106.
[0048] S5 partially removes the first intermetallic dielectric layer 101, the second intermetallic dielectric layer 102'', the third intermetallic dielectric layer 104, and the fourth intermetallic dielectric layer 106, to expose part of the surface of the first metal layer 103 and the thin film resistor 105.
[0049] S6 forms a second metal layer 107 on the fourth intermetallic dielectric layer 106, so that the second metal layer 107 is in contact with the first metal layer 103 and the thin film resistor 105, respectively.
[0050] Embodiment 2:
[0051] The integrated planarization method is suitable for laser trimming of CrSi resistors, and the technical content is the same as that of Embodiment 1. Further, the semiconductor substrate 100 is one of silicon and germanium silicon or a combination thereof.
[0052] Embodiment 3:
[0053] The integrated planarization method is suitable for laser trimming of CrSi resistors, and the technical content is the same as that of any one of Embodiments 1-2. Further, the first intermetallic dielectric layer 101 is one of silicon oxide and silicon nitride.
[0054] Embodiment 4:
[0055] The integrated planarization method is suitable for laser trimming of CrSi resistors, and the technical content is the same as that of any one of Embodiments 1-3. The second intermetallic dielectric layer 102 is one of silicon oxide and silicon nitride.
[0056] Embodiment 5:
[0057] The integrated planarization method is suitable for laser trimming of CrSi resistors, and the technical content is the same as that of any one of Embodiments 1-4. The third intermetallic dielectric layer 104 is one of silicon oxide and silicon nitride.
[0058] Embodiment 6:
[0059] The integrated planarization method for CrSi resistance laser trimming, the technical contents are same as any one of the embodiments 1-5, the fourth intermetallic dielectric layer 106 is one of silicon oxide and silicon nitride.
[0060] Embodiment 7:
[0061] The integrated planarization method for CrSi resistance laser trimming, the technical contents are same as any one of the embodiments 1-6, in the step S2, the thickness of the second intermetallic dielectric layer 102 removed by the planarization etching process is determined by the thickness of the second intermetallic dielectric layer 102 required to be reserved on the structure of the first metal layer 103.
[0062] Embodiment 8:
[0063] The integrated planarization method for CrSi resistance laser trimming, the technical contents are same as any one of the embodiments 1-7, in the step S3, the surface roughness of the second intermetallic dielectric layer 102' with larger surface roughness is reduced by chemical mechanical polishing, chemical solution or spin coating method, and the third intermetallic dielectric layer 104 is formed in the first device area and the second device area by deposition.
[0064] Embodiment 9:
[0065] The integrated planarization method for CrSi resistance laser trimming, the technical contents are same as any one of the embodiments 1-8, in the step S4, the step of forming the thin film resistance 105 in the second device area is: depositing to form the thin film resistance 105 in the second device area, etching the excess thin film resistance 105, and forming the fourth intermetallic dielectric layer 106 in the first device area and the second device area by deposition.
[0066] Embodiment 10:
[0067] The integrated planarization method for CrSi resistance laser trimming, the technical contents are same as any one of the embodiments 1-9, the thin film resistance 105 is CrSi resistance.
[0068] Embodiment 11:
[0069] The integrated planarization method for CrSi resistance laser trimming, the technical contents are same as any one of the embodiments 1-10, in the step S5, the first intermetallic dielectric layer 101, the second intermetallic dielectric layer 102'', the third intermetallic dielectric layer 104 and the fourth intermetallic dielectric layer 106 above the first metal layer 103 of the first device area are partially etched, so that the surface of the first metal layer 103 is partially exposed.
[0070] Partially etching the metal interlayer first dielectric layer 101, the metal interlayer second dielectric layer 102'', the metal interlayer third dielectric layer 104, and the metal interlayer fourth dielectric layer 106 above the edge of the thin film resistor 105 of the second device region, so as to partially expose the surface of the thin film resistor 105.
[0071] Embodiment 12:
[0072] The integrated planarization method suitable for CrSi resistance laser trimming, the technical content of which is the same as any one of embodiments 1-11, further comprises the step of depositing Ti / TIN / W material before depositing the second metal layer 107.
[0073] Embodiment 13:
[0074] The integrated planarization method suitable for CrSi resistance laser trimming, the technical content of which is the same as any one of embodiments 1-12, wherein the step of forming the second metal layer 107 on the metal interlayer fourth dielectric layer 106 in step S6 comprises the steps of: depositing the second metal layer 107 on the metal interlayer fourth dielectric layer 106, so that the second metal layer 107 is in contact with the first metal layer 103 and the thin film resistor 105 respectively, etching the excess metal, and forming a metal lead.
[0075] Embodiment 14:
[0076] The integrated planarization structure suitable for CrSi resistance laser trimming is prepared by any one of the methods described in embodiments 1-13.
[0077] Embodiment 15:
[0078] The integrated planarization method suitable for CrSi resistance laser trimming comprises the steps of:
[0079] S1: providing a semiconductor substrate, dividing at least one first device region and at least one second device region on the semiconductor substrate, and forming an independent first metal layer structure, a metal interlayer first dielectric layer, and a metal interlayer second dielectric layer on the first device region, and forming a metal interlayer first dielectric layer and a metal interlayer second dielectric layer on the second device region;
[0080] S2: performing global planarization etching treatment on the metal interlayer second dielectric layer and retaining a certain thickness;
[0081] S3: reducing the surface roughness of the metal interlayer second dielectric layer retained after etching and globally growing to form a metal interlayer third dielectric layer;
[0082] S4: forming a thin film resistor in the second device region and globally growing to form a metal interlayer fourth dielectric layer;
[0083] S5: removing part of the metal interlayer dielectric layer to the surface of the first metal layer and the surface of the thin film resistor, respectively;
[0084] S6: forming a second metal layer on the fourth metal interlayer dielectric layer, so that the second metal layer is in contact with the first metal layer and the thin film resistor, respectively.
[0085] The semiconductor substrate is one of silicon and germanium silicon or a combination thereof.
[0086] The first metal interlayer dielectric layer is one of silicon oxide and silicon nitride.
[0087] The second metal interlayer dielectric layer is one of silicon oxide and silicon nitride.
[0088] In step S2, the thickness of the second metal interlayer dielectric layer removed by the planarization etching process is determined by the thickness of the second metal interlayer dielectric layer required to be reserved on the first metal layer structure.
[0089] In step S3, the surface roughness of the second metal interlayer dielectric layer reserved after etching is reduced by chemical mechanical polishing (CMP) or chemical solution such as hydrofluoric acid (HF) / phosphoric acid (H3PO4) or spin-on-glass (SOG), and the third metal interlayer dielectric layer is formed in the first device area and the second device area by deposition.
[0090] The third metal interlayer dielectric layer is one of silicon oxide and silicon nitride.
[0091] In step S4, the step of forming a thin film resistor in the second device area is: depositing a thin film resistor in the second device area, etching the excess thin film resistor, and forming the fourth metal interlayer dielectric layer in the first device area and the second device area by deposition.
[0092] The thin film resistor is a CrSi resistor.
[0093] The fourth metal interlayer dielectric layer is one of silicon oxide and silicon nitride.
[0094] In step S5, the metal interlayer dielectric layer above the first metal layer in the first device area is etched to the surface of the first metal layer, and the metal interlayer dielectric layer above the edge of the thin film resistor in the second device area is etched to the surface of the thin film resistor.
[0095] Before depositing the second metal layer, it also includes the deposition of Ti / TIN / W material.
[0096] In step S6, the step of forming a second metal layer on the fourth intermetallic dielectric layer is: depositing a second metal layer on the fourth intermetallic dielectric layer, making the second metal layer contact the first metal layer and the thin film resistor respectively, etching the excess metal, and forming a metal lead.
[0097] Embodiment 16
[0098] Please refer to Figure 1 , Figure 1 The flow chart of the integrated planarization method for the CrSi resistance laser trimming of the present application. The preparation method of the present embodiment comprises:
[0099] S1: providing a semiconductor substrate 100, dividing at least one first device region and at least one second device region on the semiconductor substrate 100, and forming an independent first metal layer structure 103, a first intermetallic dielectric layer 101 and a second intermetallic dielectric layer 102 on the first device region, and forming a first intermetallic dielectric layer 101 and a second intermetallic dielectric layer 102 on the second device region;
[0100] S2: performing global planarization etching treatment on the second intermetallic dielectric layer 102 and retaining a certain thickness;
[0101] S3: reducing the surface roughness of the second intermetallic dielectric layer 102' retained after etching and globally growing to form a third intermetallic dielectric layer 104;
[0102] S4: forming a thin film resistor 105 in the second device region and globally growing to form a fourth intermetallic dielectric layer 106;
[0103] S5: removing the first device region part of the fourth intermetallic dielectric layer 106, the third intermetallic dielectric layer 104, the second intermetallic dielectric layer 102" with reduced surface roughness, the first intermetallic dielectric layer 101 to the first metal layer 103 surface, and the second device region part of the fourth intermetallic dielectric layer 106 to the thin film resistor 105 surface respectively;
[0104] S6: forming a second metal layer 107 on the fourth intermetallic dielectric layer 106, making the second metal layer 107 contact the first metal layer 103 and the thin film resistor 105 respectively.
[0105] Embodiment 17
[0106] The following will specifically describe the integrated planarization method for the CrSi resistance laser trimming in combination with the accompanying Figures 2-10
[0107] S1: please refer to Figure 2 , providing a semiconductor substrate 100, dividing at least one first device region and at least one second device region on the semiconductor substrate 100, and forming an independent first metal layer structure 103 and a first intermetallic dielectric layer 101 and a second intermetallic dielectric layer 102 in the first device region, and forming a first intermetallic dielectric layer 101 and a second intermetallic dielectric layer 102 in the second device region.
[0108] Wherein, please refer to Figure 2 , the semiconductor substrate 100 is one of silicon and germanium silicon or a combination thereof, or other substrate materials known to those skilled in the art. The first intermetallic dielectric layer 101 is one of silicon oxide and silicon nitride. The second intermetallic dielectric layer 102 is one of silicon oxide and silicon nitride.
[0109] S2: please refer to Figure 3 and Figure 4 , the second intermetallic dielectric layer 102 is globally planarized and etched and a certain thickness is retained. The thickness of the second intermetallic dielectric layer 102 removed by the planarization etching process is determined by the thickness of the second intermetallic dielectric layer 102 required to be retained on the first metal layer 103 structure.
[0110] S3: please refer to Figure 5 and Figure 6 , the surface roughness of the second intermetallic dielectric layer 102' retained after etching is reduced and a third intermetallic dielectric layer 104 is globally grown.
[0111] Further, please refer to Figure 5 and Figure 6 , the surface roughness of the second intermetallic dielectric layer 102' retained after etching in S3 is reduced by chemical mechanical polishing (CMP) or hydrofluoric acid (HF) / phosphoric acid (H3PO4) or spin coating (SOG), and the third intermetallic dielectric layer 104 is formed in the first device region and the second device region by deposition. The third intermetallic dielectric layer 104 is one of silicon oxide and silicon nitride.
[0112] S4: please refer to Figure 7 and Figure 8 , a thin film resistor 105 is formed in the second device region and a fourth intermetallic dielectric layer 106 is globally grown.
[0113] Please refer to Figure 7 and Figure 8The step of forming the second device region into a thin film resistor 105 comprises: depositing a thin film resistor 105 on the second device region, etching the excess thin film resistor 105, and depositing a fourth intermetallic dielectric layer 106 on the first device region and the second device region. The thin film resistor 105 is a CrSi resistor. The fourth intermetallic dielectric layer 106 is one of silicon oxide and silicon nitride.
[0114] S5: see Figure 9 The first device region portion of the fourth intermetallic dielectric layer 106, the third intermetallic dielectric layer 104, the second intermetallic dielectric layer 102" with reduced surface roughness, the first intermetallic dielectric layer 101 to the surface of the first metal layer 103, and the second device region portion of the fourth intermetallic dielectric layer 106 to the surface of the thin film resistor 105 are removed, respectively.
[0115] see Figure 9 The fourth intermetallic dielectric layer 106, the third intermetallic dielectric layer 104, the second intermetallic dielectric layer 102" with reduced surface roughness, the first intermetallic dielectric layer 101 to the surface of the first metal layer 103 above the first metal layer 103 of the first device region are etched, and the fourth intermetallic dielectric layer 106 to the surface of the thin film resistor 105 above the edge of the thin film resistor 105 of the second device region are etched.
[0116] S6: see Figure 10 A second metal layer 107 is formed on the fourth intermetallic dielectric layer 106, and the second metal layer 107 is in contact with the first metal layer 103 and the thin film resistor 105, respectively.
[0117] see Figure 10 Before the deposition of the second metal layer 107, the deposition of Ti / TIN / W material is further included.
[0118] see Figure 10 The step of forming the second metal layer 107 on the fourth intermetallic dielectric layer 106 comprises: depositing a second metal layer 107 on the fourth intermetallic dielectric layer 106, so that the second metal layer 107 is in contact with the first metal layer 103 and the thin film resistor 105, respectively, etching the excess metal, and forming a metal lead end. Finally, a planarization process and resistor integrated structure are obtained, so that effective planarization is realized while avoiding or significantly improving surface roughness.
[0119] To sum up, the embodiment provides the integrated planarization method and structure suitable for the CrSi resistance laser trimming, which can realize the integrated planarization method and structure suitable for the CrSi resistance laser trimming without significantly increasing the process difficulty and the process complexity, so that effective planarization is realized, surface roughness is avoided or significantly improved, and finally the strict requirements of the laser trimming process are met.
Claims
1. An integrated planarization method applicable to CrSi resistive laser trimming, characterized in that, Includes the following steps: S1) A semiconductor substrate (100) is provided, wherein at least one first device region and at least one second device region are defined on the semiconductor substrate (100); An independent first metal layer (103), a first intermetallic dielectric layer (101), and a second intermetallic dielectric layer (102) are formed in the first device region; A first intermetallic dielectric layer (101) and a second intermetallic dielectric layer (102) are formed in the second device region; S2) Perform global planarization etching on the second dielectric layer (102) between metal layers and retain the thickness h to form a second dielectric layer (102') between metal layers with a large surface roughness; S3) Reduce the surface roughness of the second dielectric layer (102') between metal layers with large surface roughness to form a second dielectric layer (102'') between metal layers with reduced surface roughness; Global growth is performed on the surface of the second intermetallic dielectric layer (102'') after the surface roughness is reduced to form the third intermetallic dielectric layer (104); S4) A thin film resistor (105) is formed in the second device region, and a fourth dielectric layer (106) is globally grown between the metal layers; S5) Partial removal of the first intermetallic dielectric layer (101), the second intermetallic dielectric layer (102''), the third intermetallic dielectric layer (104), and the fourth intermetallic dielectric layer (106) is performed to expose part of the surface of the first metal layer (103) and the thin film resistor (105). S6) A second metal layer (107) is formed on the fourth dielectric layer (106) between the metal layers, so that the second metal layer (107) is in contact with the first metal layer (103) and the thin film resistor (105).
2. The integrated planarization method for CrSi resistive laser trimming according to claim 1, characterized in that, The semiconductor substrate (100) is one or a combination of silicon and germanium-silicon; The first dielectric layer (101) between the metal layers is one of silicon oxide and silicon nitride; The second dielectric layer (102) between the metal layers is one of silicon oxide and silicon nitride; The third dielectric layer (104) between the metal layers is one of silicon oxide and silicon nitride; The fourth dielectric layer (106) between the metal layers is either silicon oxide or silicon nitride.
3. The integrated planarization method for CrSi resistive laser trimming according to claim 1, characterized in that, In step S2, the thickness of the second intermetallic dielectric layer (102) removed by the planarization etching process is determined by the thickness of the second intermetallic dielectric layer (102) that needs to be retained in the structure of the first metal layer (103).
4. The integrated planarization method for CrSi resistive laser trimming according to claim 1, characterized in that, In step S3, the surface roughness of the second dielectric layer (102') with a large surface roughness is reduced by chemical mechanical polishing, chemical solution or spin coating, and the third dielectric layer (104) between the metal layers is formed in the first device region and the second device region by deposition.
5. The integrated planarization method for CrSi resistive laser trimming according to claim 1, characterized in that, In step S4, the step of forming a thin film resistor (105) in the second device region is as follows: depositing a thin film resistor (105) in the second device region, etching excess thin film resistor (105), and forming the fourth dielectric layer (106) between the metal layers in the first device region and the second device region by deposition.
6. The integrated planarization method for CrSi resistive laser trimming according to claim 1, characterized in that, The thin-film resistor (105) is a CrSi resistor.
7. The integrated planarization method for CrSi resistive laser trimming according to claim 1, characterized in that, In step S5, the first intermetallic dielectric layer (101), the second intermetallic dielectric layer (102''), the third intermetallic dielectric layer (104), and the fourth intermetallic dielectric layer (106) above the first metal layer (103) in the first device region are partially etched, so that the surface of the first metal layer (103) is partially exposed. The first intermetallic dielectric layer (101), the second intermetallic dielectric layer (102''), the third intermetallic dielectric layer (104), and the fourth intermetallic dielectric layer (106) above the edge of the thin film resistor (105) in the second device region are partially etched to expose part of the surface of the thin film resistor (105).
8. The integrated planarization method for CrSi resistive laser trimming according to claim 1, characterized in that, Before the second metal layer (107) is deposited, Ti / TIN / W material is also deposited.
9. The integrated planarization method for CrSi resistive laser trimming according to claim 1, characterized in that, In step S6, the step of forming a second metal layer (107) on the fourth dielectric layer (106) between the metal layers is as follows: the second metal layer (107) is deposited on the fourth dielectric layer (106) between the metal layers, and the second metal layer (107) is in contact with the first metal layer (103) and the thin film resistor (105) respectively, and excess metal is etched to form a metal lead-out terminal.
10. An integrated planarization structure suitable for CrSi resistive laser trimming, characterized in that: It is prepared by the method described in any one of claims 1-9.