Display panel and preparation method thereof

Abstract

The display panel and the preparation method thereof are disclosed. The display panel of the embodiment of the present application is provided with a channel passing through the buffer region on the light emitting device layer, so that the material of the cathode can pass through the channel to the cathode overlap area and overlap on the wire exposed by the first opening. When the electron functional layer is formed by evaporation process, the cathode is formed by sputtering process or evaporation process with a small evaporation angle, and the electron functional layer and the cathode are formed under the same mask plate, due to the channel, the material of the cathode and the electron functional layer can extend to the cathode overlap area through the channel. Since the cathode is formed by sputtering process or evaporation process with a small evaporation angle, the film forming range of the cathode is larger than that of the electron functional layer, and then the cathode can overlap the wire to realize the light emitting of the light emitting device layer, thereby reducing the preparation cost of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a preparation method thereof. BACKGROUND

[0002] In related technologies, an OLED panel can adopt an Ink Jet Printing (IJP) process and an evaporation process / sputtering process. Due to the limited development of inks of electron transport materials and electron injection materials, the IJP OLED panel adopts an IJP process to deposit a hole injection layer, a hole transport layer, a light-emitting layer and other OLED functional layers, and adopts an evaporation / sputtering process to deposit an electron transport layer, an electron injection layer and a cathode and other OLED functional layers.

[0003] The cathode of the OLED panel needs to be connected to the metal tracks on the driving substrate to realize circuit control of OLED light-emitting. Therefore, the film-forming area of the cathode needs to be larger than the film-forming area of the electron transport layer and the electron injection layer, so that the cathode film layer is directly connected to the cathode tracks. The evaporation / sputtering process realizes different film-forming areas based on the change of the opening design of the mask plate, so the opening size of the mask plate for cathode film-forming needs to be larger than the opening size of the mask plate for electron transport layer and electron injection layer film-forming. That is, two mask plates are needed to form the OLED functional layers, resulting in a large increase in preparation cost. SUMMARY

[0004] Embodiments of the present application provide a display panel and a preparation method thereof, which can reduce the preparation cost of the display panel.

[0005] Embodiments of the present application provide a display panel, which comprises a display area and a non-display area located on at least one side of the display area, the non-display area comprising a buffer area and a cathode connecting area located on a side of the buffer area away from the display area, and the display panel comprising:

[0006] a thin film transistor structure layer, the thin film transistor structure layer comprising a track and an insulating layer covering the track, in the cathode connecting area, a first opening is provided on the insulating layer, and the first opening exposes the track;

[0007] a light-emitting device layer, the light-emitting device layer being provided on the thin film transistor structure layer, the light-emitting device layer comprising an electron functional layer and a cathode covering a side of the electron functional layer away from the thin film transistor structure layer;

[0008] a support member, the support member being provided on the insulating layer and located on a side of the first opening away from the buffer area;

[0009] The light emitting device layer is provided with at least one channel in the buffer area, the channel extends to the first opening and is communicated with the first opening.

[0010] In the non-display area of the orthographic projection pattern of the display panel, the boundary of the cathode is beyond the boundary of the electronic functional layer, the electronic functional layer covers at least the display area and the buffer area, and the cathode covers the display area and the buffer area and is connected with the trace through the channel at the first opening.

[0011] Optionally, in some embodiments of the present application, the support member is configured to support a mask plate, the mask plate comprises a frame and an opening area, the frame is overlapped on the support member, and the display area and at least part of the buffer area are correspondingly arranged in the opening area, and the frame shields at least part of the first opening.

[0012] The cathode and the electronic functional layer are configured to be formed by using the same mask plate.

[0013] Optionally, in some embodiments of the present application, the light emitting device layer comprises a planar layer covering the insulating layer and a pixel definition layer covering the planar layer, and the electronic functional layer covers the pixel definition layer.

[0014] Taking one side of the insulating layer close to the planar layer as a reference surface, the bottom surface height of the channel is lower than the one side of the pixel definition layer in the display area away from the thin film transistor structure layer, and the bottom surface height of the channel is higher than or equal to the reference surface.

[0015] Optionally, in some embodiments of the present application, the channel penetrates the planar layer and the pixel definition layer.

[0016] Optionally, in some embodiments of the present application, the first opening has at least one, in the orthographic projection pattern of the display panel, the extension direction of the channel intersects with the extension direction of the trace, and one first opening is correspondingly arranged in the extension direction of at least one channel.

[0017] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the display panel, the support member is arranged along the extension direction of the trace.

[0018] Optionally, in some embodiments of the present application, the width of the support member is greater than or equal to 10 microns.

[0019] Optionally, in some embodiments of the present application, the thickness of the support member is greater than or equal to 4 microns.

[0020] Optionally, in some embodiments of the present application, at least one of the planar layer and the pixel definition layer is arranged in the same layer and made of the same material as at least part of the support member.

[0021] Optionally, in some embodiments of the present application, the support member comprises a first part, a second part and a third part stacked in sequence on the insulating layer, the first part is arranged in the same layer and made of the same material as the planar layer, and the second part is arranged in the same layer and made of the same material as the pixel definition layer.

[0022] Optionally, in some embodiments of the present application, the electronic functional layer is further connected to the local part of the trace through the channel at the first opening, and the cathode cladding covers the electronic functional layer in the first opening and is connected to the exposed part of the trace.

[0023] Optionally, in some embodiments of the present application, the electronic functional layer comprises at least one of an electron transport layer and an electron injection layer, the light emitting device layer further comprises an anode, a light emitting layer and a hole functional layer, the anode is arranged on the planar layer, the pixel definition layer is provided with a second opening, the second opening exposes the anode, the hole functional layer and the light emitting layer are arranged in sequence on the anode and located in the second opening, and the electronic functional layer is arranged on the light emitting layer.

[0024] Correspondingly, the present application further provides a preparation method of a display panel, the display panel comprising a display area and a non-display area located at least one side of the display area, the non-display area comprising a buffer area and a cathode overlap area located at a side of the buffer area away from the display area, the preparation method comprising the following steps:

[0025] forming an insulating layer and a support member on a thin film transistor structure layer, the thin film transistor structure layer comprising a trace and an insulating layer covering the trace, in the cathode overlap area, the insulating layer is provided with a first opening, the first opening exposes the trace; the support member is arranged on the insulating layer and located at a side of the first opening away from the buffer area; at least one channel is formed in a region of the insulating layer corresponding to the buffer area, and the first opening is located in the extension direction of the channel;

[0026] adopting a mask plate to overlap the support member, the mask plate comprising a frame and an opening area, the frame overlaps the support member, and the opening area is provided with the display area and at least part of the buffer area correspondingly in the region, and the frame shields at least part of the region of the first opening;

[0027] Forming an electronic functional layer and a cathode on the insulating stack in sequence with the same mask plate as a shield, wherein a film forming range of the cathode is larger than a film forming range of the electronic functional layer, a boundary of the cathode exceeds a boundary of the electronic functional layer in the non-display area of the orthographic projection pattern of the display panel, the electronic functional layer covers at least the display area and the buffer area, and the cathode covers the display area and the buffer area and connects the first opening and the trace through the channel.

[0028] The display panel of the embodiment of the present application opens a channel through the buffer area on the light emitting device layer, so that the material of the cathode can enter the cathode overlap area through the channel and overlap on the trace exposed by the first opening.

[0029] It can be understood that when the electronic functional layer adopts the evaporation process, the cathode adopts the evaporation process with a smaller evaporation angle or the sputtering process and the electronic functional layer and the cathode are formed under the same mask plate, the process steps and process equipment are saved. Due to the setting of the channel, the materials of the cathode and the electronic functional layer can extend to the cathode overlap area through the channel. And due to the fact that the cathode adopts the sputtering process or the evaporation process with a smaller evaporation angle, the film forming range of the cathode is larger than the film forming range of the electronic functional layer, and then the cathode can overlap the trace to realize the light emission of the light emitting device layer, thereby reducing the preparation cost of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a schematic view of the orthographic projection of the display panel provided by the embodiment of the present application;

[0031] Figure 2 is a schematic view of the orthographic projection of the display panel provided by the embodiment of the present application; Figure 1 is an enlarged view of the Q part in FIG. 1;

[0032] Figure 3 is a schematic view of the orthographic projection of the display panel provided by the embodiment of the present application; Figure 2 is a schematic view of the cross section along the CC line in FIG. 1;

[0033] Figure 4 is a schematic view of the orthographic projection of the display panel provided by another embodiment of the present application;

[0034] Figure 5 is a schematic view of the curve of the different film thicknesses corresponding to different distances of the cathode and the electronic functional layer;

[0035] Figure 6 is a schematic view of the orthographic projection of the display panel provided by still another embodiment of the present application;

[0036] Figure 7 is a schematic view of the orthographic projection of the display panel provided by still another embodiment of the present application; Figure 6 is a schematic view of the cross section along the SS line in FIG. 4;

[0037] Figure 8is a sectional structure schematic diagram of a display panel provided by another embodiment of the present application.

[0038] Figure 9 is a structural schematic diagram of step B2 of a preparation method of the display panel of the embodiment of the present application.

[0039] Figure 10 is a structural schematic diagram of step B3 of a preparation method of the display panel of the embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the contour of the device; the words "first", "second", "third" and the like are only used as labels, and do not impose numerical requirements or establish sequences.

[0041] The present application provides a display panel and a preparation method thereof, which will be described in detail below. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0042] Please refer to Figures 1 to 3 The present application provides a display panel 100, which includes a display area AA and a non-display area NA located at least one side of the display area AA. The non-display area NA includes a buffer area NA1 and a cathode overlap area NA2 located at a side of the buffer area NA1 away from the display area AA.

[0043] The display panel 100 includes a thin film transistor structure layer 10, a light emitting device layer 20 and a support member 30.

[0044] The thin film transistor structure layer 10 includes a wire 11 and an insulating layer 12 covering the wire 11. In the cathode overlap area NA2, a first opening k1 is provided on the insulating layer 12, and the first opening k1 exposes the wire 11.

[0045] The light emitting device layer 20 is provided on the thin film transistor structure layer 10. The light emitting device layer 20 includes an electron functional layer 21 and a cathode 22 provided at a side of the electron functional layer 21 away from the thin film transistor structure layer 10.

[0046] The support member 30 is arranged on the insulating layer 12 and is located on the side of the first opening k1 away from the buffer area NA1.

[0047] In the buffer area NA1, the light emitting device layer 20 is provided with at least one channel td. The first opening k1 is located in the extension direction of the channel td, that is, the channel td extends to the first opening k1 and is connected to the first opening k1.

[0048] In the non-display area NA of the front projection pattern of the display panel 100, the boundary of the cathode 22 is beyond the boundary of the electron functional layer 21. The electron functional layer 21 covers at least the display area AA and the buffer area NA1, and the cathode 22 covers the display area AA and the buffer area NA1 and is connected to the first opening k1 through the channel td and the wire 11.

[0049] The display panel 100 of the embodiment of the present application is provided with the channel td in the light emitting device layer 20 in the buffer area NA1, so that the material of the cathode 22 can enter the cathode overlap area NA2 through the channel td and overlap on the wire 11 exposed by the first opening k1.

[0050] It can be understood that the support member 30 is configured to support a mask plate, the mask plate includes a frame and an opening, the frame overlaps on the support member 30, the display area AA and at least part of the buffer area NA1 are arranged in the opening area, and the frame shields at least part of the first opening k1; the cathode 22 and the electron functional layer 21 are configured to be formed by using the same mask plate.

[0051] At least part of the first opening k1 is shielded by the mask plate, and the diffusion phenomenon of the material in the process is used to make the cathode material and the electron functional layer material enter the first opening k1 in the cathode overlap area NA2 through the channel td. The part of the material entering the cathode overlap area NA2 is a diffusion part.

[0052] When the electron functional layer 21 is formed by using the evaporation process and the cathode 22 is formed by using the sputtering process or the evaporation process with a smaller evaporation angle and under the same mask plate, the materials of the cathode 22 and the electron functional layer 21 can extend to the cathode overlap area NA2 through the channel td. Since the cathode 22 is formed by using the sputtering process or the evaporation process with a smaller evaporation angle, the film forming range of the cathode 22 is larger than that of the electron functional layer, and thus the cathode 22 can overlap the wire 11 to realize the light emission of the light emitting device layer, thereby reducing the preparation cost of the display panel.

[0053] Optionally, the frame of the mask plate can completely shield the first opening k1 or partially shield the first opening k1.

[0054] Optionally, the non-display area NA is arranged at one side of the display area AA, and the trace 11 is arranged at only one side of the display area AA. In some embodiments, the non-display area NA can also be arranged around the display area AA, and the trace 11 is arranged around the display area AA to form a closed loop structure. In some embodiments, the non-display area NA is arranged at two or three adjacent sides of the display area AA, and the trace 11 is arranged around the display area AA in a zigzag shape.

[0055] Optionally, the electronic functional layer 21 is further connected to a part of the trace 11 through the first opening k1, that is, the electronic functional layer 21 is connected to the part of the trace 11 close to the buffer area NA1. The cathode 22 covers the electronic functional layer 21 in the first opening k1 and is connected to the exposed part of the trace 11. Such arrangement can reduce the width of the non-display area NA. In addition, the electronic functional layer 21 covers the sidewall of the first opening k1 first, which reduces the slope of the first opening k1, improves the continuity of the cathode 22 covering the first opening k1, and reduces the risk of disconnection.

[0056] In an embodiment, the electronic functional layer 21 can not overlap the trace 11 in the first opening k1, which increases the area of the cathode 22 overlapping the trace 11, thereby improving the stability of the connection.

[0057] Optionally, the thin film transistor structure layer 10 can be at least one of a top-gate thin film transistor, a bottom-gate thin film transistor, a dual-gate thin film transistor, and a vertical thin film transistor. The present embodiment is described by taking one of the top-gate thin film transistor architectures as an example, but is not limited thereto.

[0058] Please refer to Figure 3 In an embodiment, the thin film transistor structure layer 10 includes a substrate 13, a light shielding layer 14, a buffer layer 15, an active layer 16, a gate insulating layer 17, a gate electrode g, an interlayer dielectric layer 18, a source electrode s, and a drain electrode d, which are sequentially stacked. The trace 11 is arranged on the interlayer dielectric layer 18 in the same layer as the source electrode s. The insulating layer 12 further covers the source electrode s, the drain electrode d, and the interlayer dielectric layer 18.

[0059] Optionally, the thin film transistor structure layer 10 further includes a signal access line 19 arranged in the same layer as the light shielding layer 14 and spaced apart from the light shielding layer 14. The trace 11 is connected to the signal access line 19 through a via. The signal access line 19 is arranged to access a cathode signal.

[0060] Optionally, in an embodiment, the light emitting device layer 20 includes a planar layer 23 covering the insulating layer 12 and a pixel definition layer 24 covering the planar layer 23. The electronic functional layer 21 covers the pixel definition layer 24.

[0061] The light-emitting device layer 20 further comprises an anode 25, a hole functional layer 26 and a light-emitting layer 27. The anode 25 is disposed on the planar layer 23. The pixel definition layer 24 is provided with a second opening k2 which exposes the anode 25. The hole functional layer 26 and the light-emitting layer 27 are sequentially disposed on the anode 25 and within the second opening k2. The electron functional layer 21 is disposed on the light-emitting layer 27. The anode 25 is connected to the drain d of the thin-film transistor through a via.

[0062] Optionally, the electron functional layer 21 comprises at least one of an electron transport layer and an electron injection layer. The hole functional layer 26 comprises at least one of a hole transport layer and a hole injection layer. In the present embodiment, the electron functional layer 21 comprises an electron transport layer and an electron injection layer which are sequentially stacked on the light-emitting layer 27. The hole functional layer 26 comprises a hole injection layer and a hole transport layer which are sequentially stacked on the anode 25.

[0063] In some embodiments, the hole functional layer 26 can further comprise a light-emitting auxiliary layer / electron blocking layer, and the electron functional layer 21 can further comprise a hole blocking layer.

[0064] Optionally, with the side of the insulating layer 12 close to the planar layer 23 as a reference surface, the bottom surface of the channel td is lower than the side of the pixel definition layer 24 in the display area AA away from the thin-film transistor structure layer 10, and the bottom surface of the channel td is higher than or equal to the reference surface.

[0065] For example, in the buffer area NA1, a hollow opening exposing the insulating layer 12 is formed in the planar layer 23, and the pixel definition layer 24 covers the hollow opening to form a relatively lower-lying recessed part, and the recessed groove (channel td) of the recessed part extends in the direction of the first opening k1 and is connected to the first opening k1, so that the material can enter the first opening k1 of the cathode bonding area NA2 through the recessed groove.

[0066] For another example, in the buffer area NA1, a hollow opening exposing the planar layer 23 is formed in the pixel definition layer 24, and the hollow opening forms a recessed groove (channel td) with the top surface of the planar layer 23, and the recessed groove (channel td) of the recessed part extends in the direction of the first opening k1 and is connected to the first opening k1, so that the material can enter the first opening k1 of the cathode bonding area NA2 through the recessed groove.

[0067] For another example, in an embodiment, the channel td penetrates through the planar layer 23 and the pixel definition layer 24. That is, the bottom surface of the channel td is equal to the reference surface.

[0068] In the orthographic projection pattern of the display panel 100, the extension direction y of the channel td intersects the extension direction of the wire 11. The extension direction of the channel td is from the buffer area NA1 to the cathode bonding area NA2.

[0069] The channel td penetrates the flat layer 23 and the pixel definition layer 24, and the channel td is deepened, so that the front end barrier of the first opening k1 is reduced, more material enters the first opening k1, the overlapping area and the overlapping thickness of the cathode 22 and the wire 11 are increased, and the stability of the cathode 22 overlapping the wire 11 is improved.

[0070] It can be understood that the front end barrier of the first opening k1 refers to a component that blocks the cathode material from entering the first opening k1, such as the part of the flat layer 23 and the pixel definition layer 24 close to and facing the first opening k1.

[0071] The fewer the front end barriers of the first opening k1, the more material enters the first opening k1; in addition, the deeper the depth of the channel td, that is, the lower the front end barrier of the first opening k1, the more material enters the first opening k1, and the stability of the overlapping with the wire 11 is improved.

[0072] Referring to Figure 1 and Figure 2 Optionally, in the orthographic projection pattern of the display panel 100, the end of the channel td extends in a direction parallel to the extension direction of the wire 11, and the end of the channel td extends to the edge of the display panel 100 to form a channel td in the form of a sheet area. In the long direction of the display panel 100, the length of the channel td is equal to or greater than the length of the wire 11, so that the front end of the first opening k1 has no barrier to block the cathode material from passing through, and the success rate of the material entering the first opening k1 is improved.

[0073] Optionally, in the orthographic projection pattern of the display panel 100, the side of the channel td extends in a direction parallel to the short direction of the display panel 100, and the side of the channel td extends in a direction perpendicular to the extension direction of the wire 11, so that the distance of the material entering the first opening k1 is the same, and the partial area of the cathode 22 is prevented from overlapping the wire 11.

[0074] Optionally, please refer to Figure 2 In the orthographic projection pattern of the display panel 100, the first opening k1 has at least one. In the orthographic projection pattern of the display panel 100, the side of the channel td extends in a direction intersecting the extension direction of the wire 11, and one first opening k1 is arranged on the side of the channel td.

[0075] The plurality of first openings k1 are arranged at intervals so that the wire 11 is covered with the insulating layer 12 at intervals, and the risk of peeling of the wire 11 is reduced.

[0076] Optionally, please refer to Figure 4In an embodiment of the present application, the first opening k1 is one, and in the orthographic projection pattern of the display panel 100, the first opening k1 is arranged along the extension direction of the trace 11, and one first opening k1 is arranged in the side extension direction of one channel td. Wherein, the trace 11 is exposed by one long strip-shaped first opening k1, the exposed area of the trace 11 is increased, so that the cathode 22 can more overlap the trace 11, and the overlap area is increased.

[0077] Optionally, in an embodiment, in the orthographic projection pattern of the display panel 100, the support member 30 is arranged along the extension direction of the trace 11. That is, the support member 30 is in a long strip shape, and the support performance of the mask plate is improved.

[0078] Optionally, the width z1 of the support member 30 is greater than or equal to 10 microns, such as 10 microns, 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns, 100 microns, 150 microns, 200 microns, 250 microns, 300 microns, 350 microns or 400 microns, etc.

[0079] Optionally, in an embodiment, the width of the support member 30 is also less than or equal to 400 microns.

[0080] It can be understood that the smaller the width z1 of the support member 30, the smaller the frame width, and the weaker the strength of the support member 30 supporting the mask plate, and the more easily the opening edge of the mask plate deforms. In order to meet the strength requirement of supporting the mask plate and avoid the risk of excessive frame width, the width of the support member 30 is also selected to be less than or equal to 400 microns.

[0081] Optionally, the thickness h of the support member 30 is greater than or equal to 4 microns, such as 4 microns, 5 microns, 6 microns, 7 microns, 8 microns, 9 microns, 10 microns, 11 microns, 12 microns, 13 microns, 14 microns, 15 microns, 16 microns, 17 microns, 18 microns, 19 microns, 20 microns, 21 microns, 22 microns, 23 microns, 24 microns, 25 microns, 26 microns, 27 microns, 28 microns, 29 microns, 30 microns, 35 microns, 40 microns, 45 microns or 50 microns, etc.

[0082] It can be understood that the greater the thickness h of the support member 30, the farther the distance between the mask plate and the bottom surface of the channel td, and the greater the range of material diffusion into the cathode overlap area NA2, and the higher the success rate and stability of the cathode 22 overlapping the trace 11.

[0083] Optionally, in an embodiment, at least one of the planar layer 23 and the pixel definition layer 24 is formed in the same layer and of the same material as at least part of the support member 30. For example, the support member 30 can be formed using the same mask as the planar layer 23 or the pixel definition layer 24. For another example, part of the support member 30 is formed using the same mask as the planar layer 23, and another part of the support member 30 is formed using the same mask as the pixel definition layer 24.

[0084] In an embodiment, the support member 30 can also be formed using the same mask as other film layers different from the planar layer 23 and the pixel definition layer 24. For another example, part of the support member 30 is formed using the same mask as the planar layer 23 or the pixel definition layer 24, and another part of the support member 30 is formed using the same mask as other film layers.

[0085] Optionally, in an embodiment, the support member 30 comprises a first portion 31, a second portion 32 and a third portion 33 stacked in sequence on the insulating layer 12, the first portion 31 being formed in the same layer and of the same material as the planar layer 23. The second portion 32 is formed in the same layer and of the same material as the pixel definition layer 24. The third portion 33 is formed in the same layer and of the same material as the spacer. Such arrangement can simplify the manufacturing process.

[0086] It should be understood that the electronic functional layer 21 of the display panel 100 according to the embodiments of the present application can be formed using an evaporation process, and the cathode 22 can be formed using an evaporation process or a sputtering process. When both the electronic functional layer 21 and the cathode 22 are formed using an evaporation process, the evaporation angle for forming the cathode 22 is smaller than the evaporation angle for forming the electronic functional layer 21. When the electronic functional layer 21 can be formed using an evaporation process and the cathode 22 can be formed using a sputtering process, the angle is not considered and the cathode 22 can be formed using a conventional process.

[0087] When both the electronic functional layer 21 and the cathode 22 are formed using an evaporation process, the evaporation angle for forming the cathode 22 is θ. In the channel td region, the distance L2 from the first opening k1 to the planar layer 23 and the pixel definition layer 24 in the display area AA is greater than or equal to the thickness h of the support member 30 / tanθ, so as to ensure that the material passes through the channel td. The embodiments of the present application are described by taking the example that the electronic functional layer 21 can be formed using an evaporation process and the cathode 22 can be formed using a sputtering process.

[0088] Based on the different principles of film formation by the evaporation process and the sputtering process, the sputtering direction of the material particles is random when the film is formed by the sputtering process, while the sputtering direction of the material particles is limited by the evaporation angle when the film is formed by the evaporation process. Therefore, when the same mask is used for film formation, the diffusion area of the film layer formed by the sputtering process is greater than the diffusion area of the film layer formed by the evaporation process, i.e., when the same opening pattern mask is used, the film layer coverage area of the cathode 22 is greater than the film layer coverage area of the electronic functional layer 21, as shown in FIG. 6. Figure 5 ​

[0089] Since the electron functional layer 21 and the cathode 22 are formed by using the same mask plate, only one film forming chamber can be provided on the production line to form the electron functional layer 21 and the cathode 22, thereby saving one film forming chamber and reducing the production cost.

[0090] In another embodiment, referring to Figure 6 and Figure 7 , compared with the above embodiment, the channel td has multiple channels, and the channels td are arranged at intervals along the extension direction of the trace 11. The planar layer 23 and the pixel definition layer 24 extend to the buffer area NA1. The channel td penetrates the planar layer 23 and the pixel definition layer 24.

[0091] In the above embodiment, the first part 31 of the support member 30 is formed of the same material as the planar layer 23 and by using the same mask plate, and the second part 32 is formed of the same material as the pixel definition layer 24 and by using the same mask plate. In addition, the use of multiple channels td increases the coverage area of the cathode 22, improves the adhesion of the cathode 22, and reduces the cathode voltage drop.

[0092] In an embodiment, as shown in Figure 8 , one of the planar layer 23 and the pixel definition layer 24 does not extend into the buffer area NA1, and the other of the planar layer 23 and the pixel definition layer 24 extends into the buffer area NA1. In addition, the use of multiple channels td increases the coverage area of the cathode 22, improves the adhesion of the cathode 22, and reduces the cathode voltage drop. In addition, the use of one of the planar layer 23 and the pixel definition layer 24 into the buffer area NA1 reduces the climbing height of the cathode 22, thereby reducing the risk of breaking of the cathode 22 and improving the integrity and continuity of the cathode 22.

[0093] Optionally, the pixel definition layer 24 extends into the buffer area NA1, and the second part 32 of the support member 30 is formed of the same material as the pixel definition layer 24 and by using the same mask plate.

[0094] Correspondingly, the application also provides a preparation method of a display panel, the display panel comprising a display area AA and a non-display area NA located on at least one side of the display area AA, the non-display area NA comprising a buffer area NA1 and a cathode overlap area NA2 located on a side of the buffer area NA1 away from the display area AA.

[0095] In the above embodiment, the preparation method is used to prepare the display panel 100. The preparation method comprises the following steps:

[0096] Step B1, forming an insulating stack and a support member 30 on the thin film transistor structure layer 10. The thin film transistor structure layer 10 includes a trace 11 and an insulating layer 12 covering the trace 11. In the cathode overlap area NA2, a first opening k1 is provided on the insulating layer 12, and the first opening k1 exposes the trace 11. The support member 30 is provided on the insulating layer 12 and located on the side of the first opening k1 away from the buffer area NA1. At least one passage td is formed in the area of the insulating stack corresponding to the buffer area NA1, and the first opening k1 is located in the extension direction of the passage td.

[0097] Please refer to Figure 9 , step B2, using a mask plate mk to overlap the support member 30. The mask plate mk includes a frame m1 and an opening area m2, the frame m1 overlaps the support member 30, and the opening area m2 is provided with a display area AA and at least part of the buffer area NA1 in the corresponding area. The frame m1 shields at least part of the first opening k1;

[0098] Please refer to Figure 10 , step B3, using the same mask plate mk as a shield, forming an electronic functional layer 21 and a cathode 22 on the insulating stack in sequence. Among them, the film forming range of the cathode 22 is larger than that of the electronic functional layer 21, in the non-display area NA of the display panel 100, the boundary of the cathode 22 exceeds the boundary of the electronic functional layer 21, the electronic functional layer 21 covers at least the display area AA and the buffer area NA1, and the cathode 22 covers the display area AA and the buffer area NA1 and connects the first opening k1 and the trace 11 through the passage td.

[0099] The preparation method of the display panel of the embodiment of the application opens a passage td through the buffer area NA1 on the insulating stack, so that the material of the cathode 22 can enter the cathode overlap area NA2 through the passage td and overlap on the trace 11 exposed by the first opening k1.

[0100] It can be understood that when the electronic functional layer 21 adopts an evaporation process, the cathode 22 adopts a sputtering process or an evaporation process with a smaller evaporation angle, and the electronic functional layer 21 and the cathode 22 are formed under the same mask plate mk. Due to the provision of the passage td, the materials of the cathode 22 and the electronic functional layer 21 can extend to the cathode overlap area NA2 through the passage td. And because the cathode 22 is evaporated by using a sputtering process or a smaller evaporation angle, the film forming range of the cathode 22 is larger than that of the electronic functional layer 21, and then the cathode 22 can overlap the trace 11 to realize the light emitting of the light emitting device layer 20, thereby reducing the preparation cost of the display panel 100.

[0101] The preparation method of the display panel is described below.

[0102] In step B1, the insulating stack and the support member 30 are formed on the thin film transistor structure layer 10.

[0103] Specifically, step B1 includes sequentially forming the planar layer 23, the first portion 31, the anode 25, the pixel definition layer 24, the second portion 32 and the third portion 33 on the thin film transistor structure layer 10, the planar layer 23 and the pixel definition layer 24 constitute the insulating stack, and the first portion 31, the second portion 32 and the third portion 33 constitute the support member 30.

[0104] Optionally, the planar layer 23 and the first portion 31 are formed by using the same mask plate, and the pixel definition layer 24 and the second portion 32 are also formed by using the same mask plate. The pixel definition layer 24 is provided with the second opening k2 for exposing the anode 25.

[0105] After step B1 and before step B2, the following step is further included: sequentially forming the hole functional layer 26 and the light emitting layer 27 in the second opening k2. Then, step B2 is entered.

[0106] In step B2, please refer to Figure 9 The mask plate mk is overlapped on the support member 30.

[0107] Optionally, the mask plate mk includes a frame m1 and an opening area m2, the frame m1 is overlapped on the support member 30, and the display area AA and at least part of the buffer area NA1 are correspondingly arranged in the area of the opening area m2. The frame m1 shields at least part of the first opening k1.

[0108] Optionally, the frame m1 can fully shield the first opening k1, or can shield part of the first opening k1.

[0109] Optionally, in an embodiment, the frame m1 shields part of the first opening k1. Specifically, the frame m1 shields 1 / 4 to 3 / 4 of the area of the first opening k1, such as 1 / 4, 1 / 2 or 3 / 4 of the area of the first opening k1, so as to ensure that the electronic functional layer 21 does not fully cover the first opening k1 in the subsequent process, and the cathode 22 can directly overlap the wiring 11 in the first opening k1.

[0110] Optionally, the distance L1 from the edge of the opening area m2 to the support member 30 is between 100 nm and 500 nm, such as 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm or 500 nm.

[0111] It is to be understood that if the edge of the opening region m2 is too far away, the more the frame m1 is suspended, the more the part of the frame m1 close to the opening region m2 will be deformed and collapse under the action of gravity, resulting in a smaller distance between the frame m1 and the insulating layer 12, thereby affecting the amount of material of the electronic functional layer 21 and the cathode 22 entering the first opening k1. Therefore, the distance L1 between the edge of the opening region m2 and the support member 30 is between 100 nm and 500 nm, which can prevent the frame m1 from being suspended too much, thereby preventing the edge of the opening region m2 from being deformed due to gravity, reducing the risk of the frame m1 collapsing, and reducing the risk of the amount of cathode 22 material entering the first opening k1 being reduced.

[0112] In addition, if the cathode 22 adopts an evaporation process in subsequent processes, the evaporation angle for preparing the cathode 22 is θ. In the channel td region, the distance L2 between the first opening k1 and the insulating layer located in the display area AA is greater than or equal to the thickness h of the support member 30 / tanθ, so as to ensure that the material passes through the channel td.

[0113] For example, when the evaporation angle θ of the cathode 22 is 45 degrees, since h≥4 microns, the distance L2 is greater than or equal to 4 microns.

[0114] If the cathode 22 adopts a sputtering process in subsequent processes, in order to better cover the material of the cathode 22 in the first opening k1, the distance L2 between the first opening k1 and the insulating layer located in the display area AA is greater than or equal to 100 microns, such as 100 microns, 110 microns, 120 microns, 130 microns, 140 microns, 150 microns, 160 microns, 170 microns, 180 microns, 190 microns, 200 microns, 250 microns, 300 microns, etc.

[0115] In step B3, please refer to Figure 10 The electronic functional layer 21 and the cathode 22 are sequentially formed on the insulating layer under the shielding of the same mask mk.

[0116] Optionally, in an embodiment, the electronic functional layer 21 and the cathode 22 are formed by an evaporation process. The evaporation angle for preparing the cathode 22 is smaller than the evaporation angle for preparing the electronic functional layer 21, such as the evaporation angle for preparing the cathode 22 is 45 degrees, and the evaporation angle for preparing the electronic functional layer 21 is 90 degrees.

[0117] Since the position of the mask mk is unchanged, the film forming range of the cathode 22 is larger than the film forming range of the electronic functional layer 21 when the evaporation angle for preparing the cathode 22 is smaller than the evaporation angle for preparing the electronic functional layer 21.

[0118] Optionally, in an embodiment, the electronic functional layer 21 is formed by an evaporation process, and the cathode 22 is formed by a sputtering process. Since the sputtering process is random in the sputtering direction of the material particles, and the evaporation process is limited by the evaporation angle of the material particles, when the same mask plate mk is used for film formation, the diffusion area of the film layer formed by the sputtering process is larger than the diffusion area of the film layer formed by the evaporation process, that is, the film layer coverage area of the cathode 22 is larger than the film layer coverage area of the electronic functional layer 21, and thus the cathode 22 can be directly connected to the wire 11.

[0119] That is, the preparation method of the display panel provided in the embodiment of the present application forms the electronic functional layer 21 and the cathode 22 by using the same mask plate mk, so that the cathode 22 can be directly connected to the wire 11 in the first opening k1, and the effect of saving the process steps and the process equipment is achieved, and thus the cost of preparing the display panel 100 is saved.

[0120] The display panel and the preparation method thereof provided in the embodiment of the present application are described in detail above, and the principle and the implementation manner of the present application are described by using specific examples; the above embodiment is only used to help understand the method of the present application and the core idea thereof; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and the application range can be changed, and the above description should not be understood as the limitation of the present application.

Claims

1. A display panel comprising a display area and a non-display area located at least on one side of the display area, characterized in that: The non-display area includes a buffer area and a cathode overlapping area located on a side of the buffer area away from the display area, and the display panel includes: a thin film transistor structure layer, the thin film transistor structure layer including a wiring and an insulating layer covering the wiring, wherein a first opening is provided on the insulating layer in the cathode overlapping region, and the first opening exposes the wiring; a light-emitting device layer, the light-emitting device layer being disposed on the thin-film transistor structure layer, the light-emitting device layer comprising an electronic functional layer and a cathode covering the electronic functional layer and away from a side of the thin-film transistor structure layer; a supporting member, the supporting member being disposed on the insulating layer and located on a side of the first opening away from the buffer zone; Wherein, in the buffer zone, the light emitting device layer is provided with at least one channel, the channel extending toward the first opening and connected to the first opening; the cathode material diffuses into the cathode overlapping region through the channel and connects to the trace; In the non-display area of ​​the orthographic projection pattern of the display panel, the boundary of the cathode exceeds the boundary of the electronic functional layer, the electronic functional layer at least covers the display area and the buffer zone, and the cathode covers the display area and the buffer zone and is connected to the wiring at the first opening through the channel.

2. The display panel according to claim 1, wherein: The support member is configured to support a mask The cathode and the electronic functional layer are configured to be formed using the same mask.

3. The display panel according to claim 1, wherein: The light emitting device layer includes a planar layer covering the insulating layer and a pixel definition layer covering the planar layer, and the electronic function layer covers the pixel definition layer; Taking the side of the insulating layer close to the flat layer as the reference plane, the bottom height of the channel is lower than the side of the pixel definition layer in the display area away from the thin film transistor structure layer, and the bottom height of the channel is higher than or equal to the reference plane.

4. The display panel according to claim 3, wherein: The channel penetrates the planar layer and the pixel definition layer.

5. The display panel according to claim 3, wherein: There is at least one first opening. In the orthographic projection pattern of the display panel, the extension direction of the channel intersects with the extension direction of the wiring. One first opening is correspondingly arranged in the extension direction of at least one channel.

6. The display panel according to claim 3, wherein: In the orthographic projection pattern of the display panel, the supporting member is extended along the extending direction of the wiring.

7. The display panel according to claim 3, wherein: The width of the support member is greater than or equal to 10 micrometers.

8. The display panel according to claim 3, wherein: The thickness of the support member is greater than or equal to 4 micrometers.

9. The display panel according to claim 3, wherein: At least one of the planarization layer and the pixel definition layer is provided on the same layer as at least a portion of the support member and is made of the same material.

10. The display panel according to claim 9, wherein: The supporting member includes a first portion, a second portion, and a third portion sequentially stacked on the insulating layer, the first portion being disposed in the same layer and made of the same material as the planar layer, and the second portion being disposed in the same layer and made of the same material as the pixel definition layer.

11. The display panel according to any one of claims 1 to 10, characterized in that: The electronic functional layer is also connected to a portion of the wiring at the first opening through the channel. The cathode covers the electronic functional layer in the first opening and is connected to an exposed portion of the wiring.

12. The display panel according to any one of claims 3 to 10, characterized in that: The electronic functional layer includes at least one of an electron transport layer and an electron injection layer, the light-emitting device layer also includes an anode, a light-emitting layer and a hole functional layer, the anode is arranged on the flat layer, the pixel definition layer is provided with a second opening, the second opening exposes the anode, the hole functional layer and the light-emitting layer are sequentially arranged on the anode and located in the second opening, and the electronic functional layer is arranged on the light-emitting layer.

13. A method for manufacturing a display panel, wherein the display panel comprises a display area and a non-display area located at least on one side of the display area, characterized in that: The non-display area includes a buffer zone and a cathode overlapping area located on a side of the buffer zone away from the display area. The preparation method includes the following steps: An insulating stack and a support member are formed on a thin film transistor structure layer, wherein the thin film transistor structure layer includes a wiring and an insulating layer covering the wiring. In the cathode overlapping region, a first opening is provided on the insulating layer, wherein the first opening exposes the wiring. The support member is provided on the insulating layer and is located on a side of the first opening away from the buffer region. At least one channel is formed in a region of the insulating stack corresponding to the buffer region, wherein the first opening is located in an extension direction of the channel. A mask is overlapped on the support member, the mask including a frame and an opening area, the frame is overlapped on the support member, the display area and at least a portion of the buffer area are correspondingly provided in the area where the opening area is located, and the frame obscures at least a portion of the first opening area; Using the same mask template as a shield, an electronic functional layer and a cathode are sequentially formed on the insulating stack, wherein the film-forming range of the cathode is larger than the film-forming range of the electronic functional layer, and the material of the cathode diffuses into the cathode overlapping area through the channel and connects the wiring; in the non-display area of ​​the orthographic projection pattern of the display panel, the boundary of the cathode exceeds the boundary of the electronic functional layer, the electronic functional layer at least covers the display area and the buffer zone, and the cathode covers the display area and the buffer zone and is connected to the wiring at the first opening through the channel.

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