A memory error correction method, system and device

Abstract

A memory correction method, system and device, in the present application, the memory controller in the computing device is connected with at least one coprocessor through an out-of-band channel. The memory controller sends a correction request to at least one coprocessor after failing to correct the data to be corrected stored in the memory, the correction request is used to request to correct the data to be corrected, the coprocessor corrects the data to be corrected to obtain the corrected data, and feeds back the corrected data to the memory controller. The memory controller corrects the UCE with the help of the coprocessor, the memory controller can obtain the corrected data from the coprocessor, the UCE is corrected, the processor can obtain the correct data, and the operation of the processor will not be interrupted.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical storage field, and in particular to a memory error correction method, system and device. BACKGROUND

[0002] The memory itself has certain error detection and correction (ECC) capability, and the internal controller can correct some data errors in the memory. If the internal controller cannot correct the data errors in the memory, it means that an uncorrectable error (UCE) occurs in the memory. After the internal controller discovers the UCE, it will report it to the processor. The occurrence of the UCE will have a certain impact on the processor, causing the processor to possibly interrupt running. SUMMARY

[0003] The present application provides a memory error correction method, system and device to correct the UCE occurring in the memory and avoid the processor from interrupting due to the UCE occurring in the memory.

[0004] In a first aspect, the present application provides a memory error correction method, which can correct the UCE occurring in the memory of a computing device. The internal controller in the computing device is connected to at least one coprocessor through an out-of-band channel. After the internal controller fails to correct the to-be-corrected data stored in the memory, the internal controller can send a correction request to the at least one coprocessor. The correction request is used to request to correct the to-be-corrected data. The to-be-corrected data includes target data and a check code of the target data. One of the at least one coprocessor corrects the to-be-corrected data to obtain corrected data and feeds back the corrected data to the internal controller.

[0005] Through the above method, the internal controller corrects the UCE with the help of the coprocessor. The internal controller can obtain the corrected data from the coprocessor. The UCE is corrected, the processor can obtain correct data, and the running of the processor will not be interrupted.

[0006] In a possible implementation, the computing device further includes a microcontroller, the internal controller is connected to the microcontroller through the out-of-band channel, and the microcontroller is connected to the at least one coprocessor. The internal controller can send the correction request to the at least one coprocessor through the microcontroller. For example, the internal controller sends the to-be-corrected data to the microcontroller. After the microcontroller obtains the to-be-corrected data, the microcontroller sends the correction request to the at least one coprocessor. The correction request is used to request to correct the to-be-corrected data.

[0007] By the method, the memory controller can reduce workload of the memory controller, and the microcontroller is more convenient to deploy, and the feasibility of the method is ensured.

[0008] In a possible implementation, the computing device further includes a microcontroller, the memory controller is connected to the microcontroller through an out-of-band channel, the microcontroller is connected to the BMC, and the BMC is connected to the at least one coprocessor; when the memory controller sends the error correction request to the at least one coprocessor, the memory controller can send the error correction request to the at least one coprocessor through the microcontroller and the BMC. The memory controller can transmit the to-be-corrected data to the BMC through the microcontroller. After receiving the to-be-corrected data, the BMC sends the error correction request to the at least one coprocessor, and the error correction request carries the to-be-corrected data.

[0009] By the method, in a cabinet or a data center including a plurality of computing devices, a BMC is usually deployed. The BMC itself is connected to a plurality of devices (such as devices where coprocessors are located), and the BMC can send an error correction request to the coprocessor according to actual needs. The memory controller of the computing device sends the error correction request to the at least one coprocessor through the microcontroller and the BMC, which is suitable for such a cabinet and a data center, and effectively expands the use range of the memory error correction method.

[0010] In a possible implementation, there are many ways for any coprocessor to correct the to-be-corrected data. For example, the coprocessor can correct the to-be-corrected data by using a chipkill technology.

[0011] For another example, the coprocessor can correct the to-be-corrected data by means of historical CE information. First, the coprocessor acquires the historical CE information, and the historical CE information indicates error bits of a CE that has occurred in the memory. Then, the coprocessor determines candidate error bits in the to-be-corrected data according to the historical CE information. The coprocessor calls an error detection and correction (ECC) error correction algorithm to correct the candidate error bits.

[0012] By the method, the coprocessor has flexible and various ways to correct the to-be-corrected data. In the case that there are a plurality of coprocessors, different coprocessors adopt different error correction ways, which can ensure the success rate of error correction. In addition, in the way of correcting the to-be-corrected data by means of the historical CE information, the existence of the historical CE information enables the coprocessor to effectively lock the range of error bits (that is, the candidate error bits), and further improves the success rate of error correction.

[0013] In a possible implementation, the memory controller can send the historical CE information to the coprocessor. If the memory controller is connected to a microcontroller, the microcontroller is connected to the coprocessor, the memory controller can send the historical CE information to the coprocessor through the microcontroller. If the memory controller is connected to a microcontroller, the microcontroller is connected to a BMC, and the BMC is connected to the coprocessor, the memory controller can send the historical CE information to the coprocessor through the microcontroller and the BMC.

[0014] Through the above method, the memory controller can provide the historical CE information to the coprocessor, so as to facilitate the coprocessor to lock the candidate error bit and ensure the efficiency of data correction.

[0015] In a possible implementation, after receiving the corrected data, the memory controller can feed back the corrected target data to a processor of the computing device and save the corrected data.

[0016] Through the above method, the processor can obtain the corrected target data, and the processor can obtain correct data, thereby avoiding interruption of the processor.

[0017] In a possible implementation, the memory controller can save the corrected data in various ways. For example, the memory controller can store the corrected data at a storage address of the to-be-corrected data in the memory. For another example, the memory controller can store the corrected data at a target storage address in the memory, where the target storage address is a storage address allocated by the processor for the corrected data. For another example, the memory controller can store the corrected data in a cache in the memory controller.

[0018] Through the above method, the memory controller can save the corrected data in various ways, which is suitable for different scenarios.

[0019] In a second aspect, an embodiment of the present application provides a memory system, the memory system comprising a memory and a memory controller. The beneficial effects can be referred to the related description of the first aspect, which will not be repeated here. The memory correction system comprises a computing device and at least one coprocessor. The memory controller in the computing device is connected to the at least one coprocessor through an out-of-band channel.

[0020] The memory controller in the computing device is configured to send a correction request to the at least one coprocessor after a correction failure of to-be-corrected data stored in the memory. The correction request is used to request correction of the to-be-corrected data. The to-be-corrected data comprises target data and a check code of the target data.

[0021] One of the at least one coprocessor is configured to correct the to-be-corrected data to obtain corrected data, wherein the corrected data comprises corrected target data and a check code; and feed back the corrected data to the memory controller.

[0022] In a possible implementation, the computing device further includes a microcontroller, the memory controller is connected to the microcontroller through an out-of-band channel, and the microcontroller is connected to the at least one coprocessor.

[0023] The memory controller sends the data to be corrected to the microcontroller when sending the error correction request to the at least one coprocessor. The microcontroller sends the error correction request to the at least one coprocessor after obtaining the data to be corrected.

[0024] In a possible implementation, the computing device further includes a microcontroller, the memory controller is connected to the microcontroller through an out-of-band channel, the microcontroller is connected to the BMC, and the BMC is connected to the at least one coprocessor; the memory controller can send the data to be corrected to the microcontroller when sending the error correction request to the at least one coprocessor. The microcontroller transmits the data to be corrected to the BMC after obtaining the data to be corrected. The BMC sends the error correction request to the at least one coprocessor after obtaining the data to be corrected.

[0025] In a possible implementation, the coprocessor can use the historical CE information to correct the data to be corrected when correcting the data to be corrected. The coprocessor first obtains historical correctable error CE information, the historical CE information indicating error bits of a CE that has occurred in the memory; determines candidate error bits in the data to be corrected according to the historical CE information; and then calls an ECC error correction algorithm to correct the candidate error bits.

[0026] In a possible implementation, the memory controller can further send the historical CE information to the coprocessor.

[0027] In a possible implementation, the memory controller feeds back the target data after the error correction to a processor of the computing device, and further saves the data after the error correction.

[0028] In a possible implementation, the memory controller can store the data after the error correction in a storage address of the data to be corrected in the memory, or store the data after the error correction in a target storage address in the memory, the target storage address being a storage address allocated by the processor for the data after the error correction, or store the data after the error correction in a cache in the memory controller.

[0029] In a third aspect, the embodiments of the present application further provide a computing device, which includes the memory controller in the second aspect, and optionally, a microprocessor.

[0030] In a fourth aspect, the present application provides a computer readable storage medium, having stored therein instructions which, when executed on a computer, cause the computer to perform the method of the first aspect and each possible implementation of the first aspect.

[0031] In a fifth aspect, the present application provides a computer program product having instructions which, when executed on a computer, cause the computer to perform the method of the first aspect and each possible implementation of the first aspect.

[0032] In a sixth aspect, the present application provides a computer chip connected to a memory, the chip being configured to read and execute a software program stored in the memory, and perform the method of the first aspect and each possible implementation of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A schematic diagram of a memory correction system according to the present application;

[0034] Figure 2 A schematic diagram of a computing device according to the present application;

[0035] Figure 3 A schematic diagram of a memory controller according to the present application;

[0036] Figure 4 A schematic diagram of a memory correction method according to the present application. DETAILED DESCRIPTION

[0037] The memory inside the computing device has certain error checking and correcting (ECC) capability, which can correct errors in the data in the memory to a certain extent.

[0038] When the memory controller needs to write data into the memory, the memory controller generates a check code for the data by invoking an ECC correction algorithm when writing the data, and writes the data and the check code for the data into the memory.

[0039] Here, the ECC correction algorithm does not refer to a specific algorithm, but refers to a class of algorithms that can implement ECC.

[0040] When the memory controller reads data under the processor's instruction, it not only reads the data from memory but also retrieves the checksum of that data. The controller then uses the ECC error correction algorithm to verify the read data against this checksum, determining if it contains errors. If errors are found, the memory controller corrects them using the checksum; if correction is successful, the corrected data is sent back to the processor. Errors that can be corrected by the memory controller are called correctable errors (CE).

[0041] The larger the data volume of the checksum, the stronger its error correction capability. A strong error correction code can correct more erroneous data. Considering the limited storage space in memory, practical applications do not allow checksums to occupy a large amount of storage space; checksums must be concentrated in a small number of memory chips. This limits the ECC capability of the memory itself.

[0042] Therefore, there will always be some errors that the memory controller cannot correct; these are called uncorrectable errors (UCEs). When the memory controller detects a UCE, it reports it to the processor. The occurrence of a UCE can have a certain impact on the processor; the processor may be interrupted due to the inability to obtain correct data, and the computing device may crash.

[0043] To address this issue, this application provides a memory error correction method. In this embodiment, after a UCE (Unique Error Correction) occurs, the memory controller in the computing device sends the data of the UCE and its checksum to the coprocessor via an out-of-band channel. The coprocessor corrects the UCE data and checksum and returns the corrected data and checksum. The memory controller then returns the corrected data to the processor and saves the corrected data and checksum. In this embodiment, the memory controller uses the coprocessor to correct the UCE, and the processor can obtain the corrected data, effectively avoiding the impact of memory UCEs on the processor and ensuring the normal operation of the processor.

[0044] like Figure 1 The diagram shown is a schematic representation of a memory error correction system provided in an embodiment of this application. The system includes at least one computing device 100 and one or more coprocessors 300. Optionally, it also includes a baseboard management controller (BMC) 200.

[0045] For any computing device 100, the computing device 100 can be connected with the one or more co-processors 300 through an out-of-band channel, and the computing device 100 can send data in which UCE occurs in the memory 130 and a check code of the data to the one or more co-processors 300.

[0046] Embodiments of the present application do not limit the connection mode of the computing device 100 and the co-processors 300. For example, the computing device 100 can be directly connected with each co-processor 300 through an out-of-band channel. For another example, the computing device 100 can be connected with the one or more co-processors 300 through the BMC 200.

[0047] The BMC 200 is connected with the computing device 100 through an out-of-band channel, and can perform out-of-band management on the computing device 100. The BMC 200 performs maintenance on the computing device 100 through an independent management channel (the independent management channel is referred to as an out-of-band channel). For example, the BMC 200 can manage and monitor the working environment of devices (such as the processor 110, the memory 130, and a hard disk) in the computing device 100, wherein the working environment of the devices includes but is not limited to temperature, working voltage, fan, power supply state, and the like.

[0048] In embodiments of the present application, the BMC 200 obtains data in which UCE occurs in the memory 130 of the computing device 100 and a check code of the data from the computing device 100. The BMC 200 can request the co-processor 300 to perform error correction on the data and the check code of the data, and obtain the data after error correction and the check code of the data from the co-processor 300.

[0049] In some scenarios, the BMC 200 itself also has certain computing capability, and the BMC 200 can perform error correction on the data and the check code of the data by itself, to obtain the data after error correction and the check code of the data.

[0050] The co-processor 300 is connected with the BMC 200 or directly connected with the computing device 100, and the co-processor 300 itself has certain computing capability, and an ECC error correction algorithm with higher error correction performance can be run on the co-processor 300. The co-processor 300 can perform error correction on the obtained data and the check code of the data at the request of the BMC 200 or the computing device 100, and feed back the data after error correction and the check code of the data to the BMC 200.

[0051] This application does not limit the type of coprocessor 300. For example, coprocessor 300 can be a data processing unit (DPU), graphics processing unit (GPU), tensor processing unit (TPU), or neural network processing unit (NPU) or other processors with data processing functions. It can also be an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), artificial intelligence (AI) chip, system on chip (SoC), or complex programmable logic device (CPLD).

[0052] The memory error correction system allows for multiple coprocessors 300. The BMC 200 can simultaneously request these multiple coprocessors 300 to correct the data and its checksum. The BMC 200 only needs to receive the corrected data and checksum from one of the coprocessors 300 to send them back to the computing device 100. The situation is similar when the computing device 100 is directly connected to a coprocessor 300; the computing device 100 can simultaneously request these multiple coprocessors 300 to correct the data and its checksum. The computing device 100 only needs to receive the corrected data and checksum from one of the coprocessors 300.

[0053] In this embodiment, the one or more coprocessors 300 are deployed outside the computing device 100. The deployment location of the coprocessor 300 is not limited in this application. For example, the coprocessor 300 can be deployed on a server used for encoding and decoding. Or, the coprocessor 300 can be located on the same board as the BMC 200.

[0054] like Figure 2 The diagram shown is a structural schematic of a computing device 100 provided in an embodiment of this application. The computing device 100 includes a processor 110, a memory controller 120, and a memory 130. Optionally, it also includes a microcontroller 140, wherein the processor 110, memory controller 120, microcontroller 140, and memory 130 may be located on the motherboard of the computing device 100.

[0055] The processor 110 is the operation core and control core of the computing device 100, which can be a central processing unit (CPU) or other specific integrated circuits. The processor 110 can also be other general-purpose processors 110, digital signal processors (DSPs), ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. In the embodiments of the present application, the processor 110 can access the memory 130 through the memory controller 120, and initiate an access request to the memory 130 to the memory controller 120, such as a read request to read data or a write request to write data.

[0056] The memory 130 is usually used to store computer program instructions related to the operating system. The memory 130 has the advantage of fast access speed. The memory 130 can be a dynamic random access memory (DRAM). In addition to DRAM, the memory 130 can also be other random access memories, such as static random access memory (SRAM), storage class memory (SCM), etc. In addition, the memory 130 can also be a read only memory (ROM). For read only memory, for example, it can be a programmable read only memory (PROM), an erasable programmable read only memory (EPROM), etc. The memory 130 can also be a dual in-line memory module (DIMM), a flash medium (FLASH), etc.

[0057] The memory controller 120 is a hardware device between the core of the processor 110 and the bus connecting the cache and the memory 130, and the memory controller 120 is usually also considered as a part of the processor 110, in which case the operations performed by the memory controller 120 can be considered as the operations performed by the processor 110. In the embodiments of the present application, only the case where the memory controller 120 is an independent hardware device is taken as an example for description. The memory controller 120 is mainly used to process the access request initiated by the processor 110 to the memory 130, and read data from the memory 130 or write data to the memory 130 according to the access request.

[0058] The process of reading and writing data from and to the memory 130 by the memory controller 120 can refer to the foregoing description, which will not be repeated here. In the embodiment of the present application, the memory controller 120 sends the data and the check code of the data where the UCE occurs to the coprocessor 300 through the out-of-band after discovering the UCE.

[0059] For example, the memory controller 120 is directly connected with the one or more coprocessors 300 through the out-of-band channel, and the memory controller 120 can directly initiate the error correction request to the coprocessor 300, requesting the coprocessor 300 to correct the error of the data and the check code of the data where the UCE occurs.

[0060] For another example, the memory controller 120 is connected with the microcontroller 140 through the out-of-band channel, the microcontroller 140 is connected with the coprocessor 300, and the microcontroller 140 initiates the error correction request to the coprocessor 300.

[0061] For another example, the memory controller 120 is connected with the microcontroller 140 through the out-of-band channel, the microcontroller 140 is connected with the BMC 200, the BMC 200 is connected with the coprocessor 300, the microcontroller 140 sends the data and the check code of the data where the UCE occurs to the BMC 200, and the BMC 200 initiates the error correction request to the coprocessor 300, requesting the coprocessor 300 to correct the error of the data and the check code of the data where the UCE occurs.

[0062] In the embodiment of the present application, as shown in FIG. 1, the memory controller 120 internally allows to deploy three types of caches. Figure 3

[0063] The first type of cache is the cache used by the memory controller 120 to interact with the processor 110. In order to distinguish different types of caches, this cache can be referred to as an in-band cache.

[0064] The data that the processor 110 needs to write into the memory 130 or the data that the processor 110 needs to read from the memory 130 can be temporarily stored in the in-band cache. For example, when the processor 110 needs to write data into the memory 130, the processor 110 sends the data to the memory controller 120, and the memory controller 120 can temporarily store the data in the in-band cache, and then write the data in the in-band cache into the memory 130. For another example, when the processor 110 needs to read data from the memory 130, the memory controller 130 can temporarily store the data read from the memory 130 in the in-band cache, and then feed back the data in the in-band cache to the processor 110.

[0065] ​The second type of cache is used by the memory controller 120 to interact with the microcontroller 140 or the coprocessor 300. This cache can be referred to as an out-of-band cache to distinguish different types of caches. The following describes an example of the memory controller 120 interacting with the microcontroller 140, and the memory controller 120 interacting with the coprocessor 300 is similar to the memory controller 120 interacting with the microcontroller 140, which is not described herein.

[0066] In an embodiment of the present application, the memory controller 120 can temporarily save the data and the check code of the data in which the UCE occurs in the out-of-band cache, and the memory controller 120 can also notify the microcontroller 140 to read the data and the check code of the data from the out-of-band cache. After the microcontroller 140 obtains the corrected data and the check code of the data from the BMC 200, the microcontroller 140 can also write the corrected data and the check code of the data into the out-of-band cache, and notify the memory controller 120 that the corrected data is stored in the out-of-band cache or notify the memory controller 120 that the data correction is successful.

[0067] The third type of cache is a cache set in the memory controller 120 to replace part of the storage space in the memory 130. This cache can be referred to as a hot spare cache to distinguish different types of caches. In some scenarios, the memory controller 120 can not be provided with a hot spare cache.

[0068] The memory controller 120 can isolate part of the storage space in the memory 130, for example, when the UCE occurs on the part of the storage space, the memory controller 120 controls the memory 130 to isolate the part of the storage space, and prohibits reading or writing on the part of the storage space. The data to be written into the part of the storage space or the data in the part of the storage space can be stored in the hot spare cache. Then, the processor 110 needs to access the part of the storage space, which can be converted by the memory controller 120 to access the hot spare cache. The processor 110 does not need to perceive the existence of the hot spare cache.

[0069] In an embodiment of the present application, after the memory controller 120 obtains the corrected data or the check code from the microcontroller 140, the memory controller 120 can write the corrected data and the check code of the data into the original position of the data and the check code of the data in the memory 130 or a new position allocated by the processor 110 in the memory 130 (for example, in a scenario in which the memory controller 120 is not provided with a hot spare cache), or the memory controller 120 can also isolate the original position and write the corrected data and the check code of the data into the hot spare cache.

[0070] The microcontroller 140 can be connected to the memory controller 120 through an out-of-band channel, and the microcontroller 140 is connected to the BMC 200 through the out-of-band channel. The microcontroller 140 is arranged inside the computing device 100.

[0071] In order to avoid occupying a large area of the mainboard of the computing device 100 by the microcontroller 140, the microcontroller 140 can be a processor 110 of a type with a small number of cores, a low working frequency, and a small amount of used memory 130. The specific type of the microcontroller 140 is not limited in the embodiments of the present application. The microcontroller 140 can be a DSP, an ASIC, an FPGA, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like.

[0072] The microcontroller 140 can obtain the data to be corrected and the check code of the data from the out-of-band cache of the memory controller 120, and send the data and the check code of the data to the BMC 200 or the coprocessor 300.

[0073] The following will be described in combination with the accompanying drawings Figure 3 A memory correction method provided by the embodiments of the present application will be described below. The data with UCE and the error correction code of the data are taken as target data and target error correction code, and the computing device 100 internally includes the microcontroller 140, and the microcontroller 140 is connected to the BMC 200. The memory correction method is described below. Figure 4 The memory correction method is similar to that shown in the figure, and the difference is that the data with UCE and the error correction code of the data do not need to pass through the microcontroller 140 or the BMC 200 in the case that the memory controller 120 is directly connected to the coprocessor 300 or the microcontroller 140 is directly connected to the coprocessor 300. Referring to Figure 4 The method includes the following steps.

[0074] Step 401: The processor 110 initiates a read request to the memory controller 120, and the read request is used to read target data from the memory 130. The read request carries a storage address of the target data. The storage address is a storage address capable of pointing to a BANK, a row or a column of the BANK in the memory 130.

[0075] The access of the processor 110 to the memory 130 is in a data granularity of data reading and writing. That is, the processor 110 can only write a fixed amount of data to the memory 130 through the memory controller 120 each time or the processor 110 can only read a fixed amount of data from the memory 130 through the memory controller 120 each time. The data amount of the target data here is the fixed data amount. In actual application, the fixed data amount can be the size of a cacheline. The processor 110 performs a reading operation on the memory 130 through the memory controller 120, and reads the data of a cacheline. The processor 110 performs a writing operation on the memory 130 through the memory controller 120, and writes the data of a cacheline to the memory 130. The cacheline can be 64 bytes.

[0076] Step 402: The memory controller 120 reads the target data and the check code of the target data from the memory 130 according to the storage address. For different types of memories 130, the data amount of the check code of the target data is different. For example, in a memory 130 under the double data rate (DDR) 4 standard, the check code of the target data is usually 8 bytes. In a memory 130 under the DDR5 standard, the check code of the target data is usually 16 bytes.

[0077] Step 403: The memory controller 120 performs error correction on the target data and the check code of the target data, and the error correction fails.

[0078] The target data and the check code of the target data have errors, which can be errors in the target data itself, such as errors in some bits of the data. It can also be errors in the check code of the target data, such as errors in some bits of the check code. It can also be errors in the target data and the check code of the target data. When the memory controller 120 fails to correct the error, it cannot accurately locate the data with errors in the target data and the check code of the target data. Therefore, in the embodiment of the present application, the target data and the check code of the target data are regarded as a whole, and it is considered that the whole composed of the target data and the check code of the target data has UCE. In the embodiment of the present application, the bits are referred to as error bits.

[0079] In addition, when the memory controller 120 finds that the target data and the check code of the target data have UCE, the memory controller 120 can suspend the access of the processor 110 to the memory 130. Until the memory controller 120 obtains the target data and the check code of the target data after error correction.

[0080] Step 404: The memory controller 120 stores the target data and the check code of the target data in the out-of-band cache, and informs the microcontroller 140 to read the target data and the check code of the target data.

[0081] Since the memory controller 120 and the microcontroller 140 are connected through the out-of-band channel. The out-of-band management channel includes two different physical channels, one physical channel is used to transmit control signals, and the other physical channel is used to transmit data. In order to distinguish the two different physical channels, the physical channel for transmitting control signals is called a control physical channel, and the physical channel for transmitting data is called a data physical channel.

[0082] When the memory controller 120 performs step 404, the memory controller 120 can send a notification to the microcontroller 140 through the control physical channel, the notification is used to inform the microcontroller 140 to read the target data and the check code of the target data from the in-band cache, and optionally, the notification can also inform the storage address of the target data and the check code of the target data. The microcontroller 140 obtains the target data and the check code of the target data stored in the out-of-band cache through the data physical channel.

[0083] Step 405: After the microcontroller 140 obtains the target data and the check code of the target data, the microcontroller 140 initiates an error correction request to the BMC 200, the error correction request is used to request to correct the target data and the check code of the target data.

[0084] Step 406: After receiving the error correction request, the BMC 200 corrects the target data and the check code of the target data.

[0085] Two error correction methods of the BMC 200 for the target data and the check code of the target data are provided in the embodiments of the present application, the BMC 200 can adopt any of the following methods, or can simultaneously adopt the following two methods for error correction.

[0086] Method one, the BMC 200 corrects the target data and the check code of the target data by itself.

[0087] The BMC 200 itself has a certain computing capability, the BMC 200 can run an error correction algorithm, and the BMC 200 can correct the target data and the check code of the target data by itself.

[0088] Method two, the BMC 200 corrects the target data and the check code of the target data through the coprocessor 300.

[0089] The BMC 200 can send an error correction request to the coprocessor 300, request the coprocessor 300 to correct the target data and the check code of the target data, and send the target data and the check code of the target data to the coprocessor 300. The coprocessor 300 corrects the target data and the check code of the target data, and feeds back the corrected target data and the check code of the target data to the BMC 200 after the correction is successful.

[0090] The BMC 200 can send an error correction request to each of a plurality of coprocessors 300, and the plurality of coprocessors 300 correct the target data and the check code of the target data. Since the computing capabilities of different coprocessors 300 can be different, the ECC error correction algorithms used by different coprocessors 300 are different, and the speeds of different coprocessors 300 in correcting the target data and the check code of the target data are different. Therefore, the BMC 200 can receive the corrected target data and the check code of the target data fed back by different coprocessors 300 in sequence. For the BMC 200, the BMC 200 only needs to feed back the corrected target data and the check code of the target data received first to the microcontroller 140.

[0091] The BMC 200 can ensure the success rate of correcting the target data and the check code of the target data and improve the efficiency of correcting the target data and the check code of the target data by sending an error correction request to each of a plurality of coprocessors 300. Since different coprocessors 300 use different ECC error correction algorithms, the BMC 200 can evaluate the error correction speeds of different coprocessors 300 or the efficiencies of the ECC error correction algorithms on different coprocessors 300 according to the speeds of the corrected target data and the check code of the target data fed back by each coprocessor 300. When subsequent data and check code of the data need to be corrected, the coprocessor 300 with a faster error correction speed (the error correction speed is greater than a threshold value) or running a more efficient ECC error correction algorithm (for example, the success rate of error correction is greater than a set value) can be preferentially sent an error correction instruction.

[0092] As can be seen from the above, both the BMC 200 and the coprocessor 300 can correct the target data and the check code of the target data. The embodiments of the present application provide several possible error correction methods.

[0093] The first error correction method uses chipkill to correct the target data and the check code of the target data.

[0094] The memory controller 120 can correct the error data in the memory 130 by means of the chipkill technology, and the chipkill technology can correct multi-bit errors in a chip in the memory 130.

[0095] Because a part of bits in a memory 130 grain is used to store data other than data and the check code of data, when the memory controller 120 corrects errors by means of the chipkill technology, the success rate of error correction can not reach 100%. That is, there can be a case that a multi-bit error in a memory 130 grain (chip) cannot be corrected.

[0096] The BMC 200 or the coprocessor 300 can again attempt to correct errors in the target data and the check code of the target data by means of the chipkill technology. When the error bits in the target data and the check code of the target data are concentrated in a memory 130 grain, the BMC 200 or the coprocessor 300 can generally correct the target data and the check code of the target data by means of the chipkill technology.

[0097] The second error correction method, the BMC 200 or the coprocessor 300 estimates candidate error bits that can be erroneous in the target data and the check code of the target data according to historical CE information of the memory 130, and corrects the candidate error bits that can be erroneous by means of an ECC error correction algorithm. The historical CE information is information indicating a CE that has occurred in the memory 130, and the historical CE information can indicate error bits of the CE that has occurred in the memory 130.

[0098] In the historical CE information, for each CE that has occurred, the storage address of the data and the check code of the data in which the CE occurs (hereinafter referred to as the storage address of the CE occurrence) and error bits are recorded. The error bits indicate the positions of the data and the check code of the data in which the CE occurs. The historical CE information can be sent by the memory controller 120 to the BMC 200 through the microcontroller 140. The BMC 200 can send the historical CE information to the coprocessor 300, or store the historical CE information in a memory accessible to the coprocessor 300.

[0099] For the memory controller 120, each time the memory controller 120 discovers a CE, after completing error correction for the CE, the memory controller 120 informs the microcontroller 140 of error bits of the CE and the storage address of the CE occurrence. The microcontroller 140 then sends the error bits and the storage address of the CE occurrence to the BMC 200. The BMC 200 can send the error bits and the storage address of the CE occurrence to the coprocessor 300, or store the error bits and the storage address of the CE occurrence in a memory accessible to the coprocessor 300. As the CEs in the memory 130 are discovered and corrected, the BMC 200 side accumulates the error bits of each CE and the storage address of the CE occurrence, forming the historical CE information. Similarly, the coprocessor 300 (or the memory accessible to the coprocessor 300) side also accumulates the positions of the error bits of each CE and the storage address of the CE occurrence, forming the historical CE information.

[0100] From a physical location, the data and the check code of the data are distributed on the memory 130 grains. In other words, the storage address of the data is mapped to one or more bits on the plurality of memory 130 grains. One bit or multiple bits on each memory 130 grain stores part of the data and the check code of the data.

[0101] The basic principle of the memory 130 storing data is to store data by using the state of the transistor in each cell inside the memory 130 grain in the memory 130. Different data corresponds to different states of the transistor. If a transistor is frequently operated, electrons may rapidly accumulate around the transistor, thereby causing the state of other transistors around the transistor to change, which will also cause the data indicated by the other transistors around the transistor to change. Therefore, for one bit or multiple bits on the memory 130 grain, if the one bit or multiple bits always have errors, such as CE, then the bits around the one bit or multiple bits in the physical location will also be affected.

[0102] It can be seen that based on the analysis of the historical CE information, it can be predicted that the bits around the known error bit may also have errors according to the known error bit.

[0103] If the position of the known error bit always has errors (that is, the error bit of the multiple CEs that have occurred is the same bit), the frequency of the known error bit appearing error data (here, the frequency is defined as the number of times that error data appears on the error bit within a set time period or the number of times that error data appears on the error bit within a set number of times) is greater than the frequency threshold. Then, it can be considered that the bits around the known error bit and the known error bit can be considered as potential bits. The bits around the error bit can be bits within a certain address range determined based on the position of the error bit, such as bits with a distance of 10 bits from the error bit.

[0104] After the BMC 200 or the coprocessor 300 obtains the target data and the check code of the target data, the BMC 200 or the coprocessor 300 determines the candidate error bits in the target data and the check code of the target data that are likely to have errors, the candidate error bits being the potential bits contained in the target data and the check code of the target data.

[0105] The BMC 200 or the co-processor 300 calls the ECC error correction algorithm to correct the potential bit in the target data and the check code of the target data when correcting the target data and the check code of the target data. The type of the ECC error correction algorithm is not limited herein, which can be a hamming code, a Reed-Solomon (RS) encoding algorithm, a cyclic redundancy check (CRC) algorithm, a bose, ray-chaudhuri, hocquenghem (BCH) algorithm, a HASH algorithm, or a redundant array of independent disks (RAID) algorithm (such as a RAID 5 algorithm or a RAID 6 algorithm).

[0106] For example, the decoding can be performed after the potential bit is obtained.

[0107] The third error correction method, the BMC 200 or the co-processor 300 corrects the target data and the check code of the target data by using an erasure code algorithm.

[0108] The BMC 200 or the co-processor 300 obtains the memory 130 grain where the error bit is located in the target data and the check code of the target data, and corrects the error by using the erasure code algorithm.

[0109] The above three error correction methods are only examples, and the BMC 200 or the co-processor 300 does not limit the method used to correct the target data and the check code of the target data. For example, the BMC 200 or the co-processor 300 can also correct only the bits in a specified range in the target data and the check code of the target data.

[0110] Step 407: After obtaining the corrected target data and the check code of the target data, the BMC 200 sends the corrected target data and the check code of the target data to the microcontroller 140 through the microcontroller 140.

[0111] The BMC 200 sends the corrected target data and the check code of the target data to the microcontroller 140, and the microcontroller 140 writes the corrected target data and the check code of the target data to the out-of-band cache controlled by the memory 130 after receiving the corrected target data and the check code of the target data, and notifies the memory controller 120 that the data correction is completed or notifies the memory controller 120 that the corrected target data and the check code of the target data are stored in the out-of-band cache.

[0112] Step 408, the memory controller 120 feeds the corrected target data and the check code of the target data to the processor 110 after obtaining the corrected target data and the check code of the target data.

[0113] The memory controller 120 can migrate the corrected target data and the check code of the target data from the out-of-band cache to the in-band cache after obtaining the corrected target data and the check code of the target data, and feed the corrected target data and the check code of the target data in the in-band cache to the processor 110.

[0114] The memory controller 120 also needs to write the corrected target data and the check code of the target data back to the memory 130, and can also write the corrected target data and the check code of the target data to the hot standby cache. The following describes the two methods.

[0115] (1) The memory controller 120 writes the corrected target data and the check code of the target data back to the memory 130.

[0116] The memory controller 120 can write the corrected target data and the check code of the target data back to the memory 130 at the original position of the target data and the check code of the target data, i.e. the position indicated by the storage address carried in the read request in step 401. The memory controller 120 can also isolate the position indicated by the storage address, request the processor 110 (actually the operating system on the processor 110) to allocate a new storage address for the corrected target data in the memory 130, and write the corrected target data and the check code of the target data to the new storage address after obtaining the new storage address.

[0117] (2) The memory controller 120 writes the corrected target data and the check code of the target data to the hot standby cache.

[0118] In the case where the hot standby cache is deployed in the memory 130, the memory controller 120 can isolate the position indicated by the storage address and write the corrected target data and the check code of the target data to the hot standby cache. In this way, the storage address carried in the read request in step 401 no longer points to the original position in the memory 130, but points to the position in the hot standby cache where the corrected target data and the check code of the target data are stored.

[0119] Those skilled in the art will appreciate that embodiments of the present application can be devised for a variety of other systems which are currently developed or later developed. Therefore, the present application is intended to cover all such modifications and variations of this application that are within the scope of the appended claims and their equivalents. It is intended that each element of claim 1 is implemented independently of each other element. None of the elements of claim 1, singly or in combination, is intended to be a means-plus-function clause.

[0120] The present application is described in reference to the flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart Figure 1 one or more functions specified in the flowchart block or blocks. Figure 1 one or more functions specified in the flowchart block or blocks.

[0121] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure 1 one or more functions specified in the flowchart block or blocks. Figure 1 one or more functions specified in the flowchart block or blocks.

[0122] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more functions specified in the flowchart block or blocks. Figure 1 one or more functions specified in the flowchart block or blocks.

[0123] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A memory error correction method, characterized in that, The method is used to correct uncorrectable errors (UCEs) occurring in the memory of a computing device, the computing device further including a memory controller connected to at least one coprocessor via an out-of-band channel, the method comprising: After the memory controller fails to correct the data to be corrected stored in the memory, it sends an error correction request to the at least one coprocessor. The error correction request is used to request the correction of the data to be corrected, which includes target data and a checksum of the target data. One of the at least one coprocessors performs error correction on the data to be corrected, obtaining corrected data, which includes the corrected target data and a checksum; and feeds back the corrected data to the memory controller.

2. The method as described in claim 1, characterized in that, The computing device further includes a microcontroller, the memory controller is connected to the microcontroller via an out-of-band channel, and the microcontroller is connected to the at least one coprocessor; The memory controller sends an error correction request to the at least one coprocessor, including: The memory controller sends the error-to-correct data to the microcontroller; The microcontroller sends the error correction request to the at least one coprocessor.

3. The method as described in claim 1, characterized in that, The computing device further includes a microcontroller, the memory controller is connected to the microcontroller via an out-of-band channel, the microcontroller is connected to a baseboard management controller (BMC), and the BMC is connected to the at least one coprocessor; The memory controller sends an error correction request to the at least one coprocessor, including: The memory controller transmits the error-to-correct data to the BMC via the microcontroller; The BMC sends the error correction request to the at least one coprocessor.

4. The method as described in claim 3, characterized in that, The coprocessor performs error correction on the data to be corrected, including: The coprocessor acquires historical correctable error (CE) information, which indicates the error bits of CEs that have occurred in the memory; The coprocessor determines candidate error bits in the data to be corrected based on the historical CE information. The coprocessor invokes the Error Detection and Correction (ECC) algorithm to correct the candidate error bits.

5. The method as described in claim 4, characterized in that, The method further includes: The memory controller sends the historical CE information to the coprocessor.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: The memory controller feeds back the corrected target data to the processor of the computing device; The memory controller stores the corrected data.

7. The method as described in claim 6, characterized in that, The memory controller stores the corrected data, including: The memory controller stores the corrected data at the memory address where the data to be corrected is stored; or The memory controller stores the error-corrected data at a target memory address in the memory, where the target memory address is the memory address allocated by the processor for the error-corrected data; or The memory controller is stored in a cache within the memory controller.

8. A memory error correction system, characterized in that, The memory error correction system includes a computing device and at least one coprocessor, wherein the memory controller in the computing device is connected to the at least one coprocessor via an out-of-band channel. The memory controller in the computing device is used to send an error correction request to the at least one coprocessor after the error correction of the data to be corrected stored in the memory fails. The error correction request is used to request the error correction of the data to be corrected, and the data to be corrected includes target data and a checksum of the target data. One of the at least one coprocessors is used to correct the data to be corrected, obtain the corrected data, the corrected data including the corrected target data and the checksum; and to feed back the corrected data to the memory controller.

9. The system as described in claim 8, characterized in that, The computing device further includes a microcontroller, the memory controller is connected to the microcontroller via an out-of-band channel, and the microcontroller is connected to the at least one coprocessor; The memory controller sends an error correction request to the at least one coprocessor for the following purposes: The error-to-be-corrected data is sent to the microcontroller; The microcontroller is configured to: send the error correction request to the at least one coprocessor.

10. The system as described in claim 8, characterized in that, The computing device further includes a microcontroller, the memory controller is connected to the microcontroller via an out-of-band channel, the microcontroller is connected to a baseboard management controller (BMC), and the BMC is connected to the at least one coprocessor; when the memory controller sends an error correction request to the at least one coprocessor, it is used to: The error-to-correct data is transmitted to the BMC via the microcontroller; The BMC is used to send the error correction request to the at least one coprocessor.

11. The system as claimed in claim 10, characterized in that, The coprocessor performs error correction on the data to be corrected, for the following purposes: Obtain historical correctable error (CE) information, which indicates the error bits of CEs that have occurred in the memory; Candidate error bits in the data to be corrected are determined based on the historical CE information. The error detection and correction (ECC) algorithm is invoked to correct the candidate error bits.

12. The system as claimed in claim 11, characterized in that, The memory controller is further configured to: The historical CE information is sent to the coprocessor.

13. The system according to any one of claims 8 to 12, characterized in that, The memory controller is further configured to: The error-corrected target data is fed back to the processor of the computing device; Save the corrected data.

14. The system as described in claim 13, characterized in that, The memory controller stores the corrected data for: The corrected data is stored at the memory address of the data to be corrected; or The error-corrected data is stored at a target storage address in the memory, where the target storage address is the storage address allocated by the processor for the error-corrected data. or It is stored in the cache of the memory controller.

15. A computing device, characterized in that, The computing device includes a memory controller, which is connected to at least one coprocessor via an out-of-band channel; The memory controller is configured to send an error correction request to the at least one coprocessor, the error correction request being used to request error correction of data to be corrected, the data to be corrected being data that the memory controller cannot correct, the data to be corrected including target data and a checksum of the target data; and to obtain corrected data from the at least one coprocessor, the corrected data including the corrected target data and a checksum.

Images