A dynamic random access memory, neuron behavior simulation system and method

Abstract

The application discloses a dynamic random memory, a neuron behavior simulation system and a method. The dynamic random memory comprises a plurality of neuron model circuits, a working control circuit and a data holding circuit. Each neuron model circuit comprises a neuron circuit, the neuron circuit comprising a first switch tube, an energy storage capacitor and a discharge reset circuit. The working control circuit is used for controlling the working state of the neuron circuit by controlling the conduction or shutdown of the first switch tube. When the first switch tube is turned on and receives a stimulating current, the energy storage capacitor is charged. When the voltage value obtained by charging the energy storage capacitor is greater than a preset threshold value, the discharge reset circuit outputs a pulse signal and discharges and resets the charging of the energy storage capacitor. Since the charging of the energy storage capacitor is controlled by controlling the switch of the switch tube to simulate the neuron behavior, the device for pulse neural network operation is faster in calculation speed and more energy-saving, and is more stable and reliable compared with the way of simulating the neuron behavior by using a memristor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of neural network simulation, in particular to a dynamic random access memory, a neuron behavior simulation system and method. BACKGROUND

[0002] Spiking Neural Network (SNN) occupies a core position in the research of brain-like computing and is considered as a new generation of neural network. SNN takes spiking neuron as a computing unit, simulates the information coding and processing process of human brain, and adopts discrete events (spikes) to code and process data. Compared with Artificial Neural Network (ANN), SNN has significantly reduced energy consumption and more outstanding computing ability. In terms of neuron model, SNN adopts non-differential neuron model with memory, such as Hodgkin-Huxley (H-H) model and Leaky Integrate-and-Fire (LIF) model. Such model has the advantages of extracting data space-time features, lower power consumption and being more suitable for parallel computing, and thus has been widely applied in the fields of speech recognition, visual processing, medical diagnosis and the like. The neuron information of SNN is transmitted through spike sequence, and no longer has the characteristics of continuous differentiability, so the traditional learning algorithm of artificial neural network is difficult to be directly applied to SNN. On the basis of fully considering the differences between neuron model and information coding and balancing biological rationality and computational feasibility, a plurality of innovative training algorithms have been proposed, which mainly cover direct training algorithm based on back propagation (BP), unsupervised learning algorithm and ANN to SNN conversion algorithm and the like.

[0003] At present, the neuron hardware implementation or accelerator for SNN all adopt memristor, which is a new type of electronic element with memory characteristics. The resistance of the memristor changes with the change of the current and voltage passing through it, and has nonlinear characteristics. The memristor can store and read information, and has non-volatile storage characteristics. However, the memristor also has obvious defects in building SNN, such as:

[0004] 1) The performance of the memristor is greatly affected by the environment and is unstable;

[0005] 2) High power consumption;

[0006] 3) Limited computing ability;

[0007] 4) Difficulty in hardware implementation of the memristor spiking neural network. SUMMARY

[0008] The technical problem solved by the present application is how to design and build a neuron behavior simulation circuit for a spiking neural network.

[0009] According to a first aspect, a dynamic random memory for performing operation of a spiking neural network is provided in an embodiment, comprising a plurality of neuron model circuits, a working control circuit and a data holding circuit;

[0010] Each of the neuron model circuits comprises a neuron circuit for simulating neuron behavior, the neuron circuit comprising a stimulus signal input end, a spike signal output end, a first switch tube, an energy storage capacitor and a discharge reset circuit;

[0011] The stimulus signal input end is used for input of a stimulus current;

[0012] The spike signal output end is used for output of a spike signal;

[0013] The gate of the first switch tube is connected with the working control circuit, the source of the first switch tube is connected with the discharge reset circuit, and the drain of the first switch tube is connected with the stimulus signal input end;

[0014] The positive connection end of the energy storage capacitor is connected with the source of the first switch tube, and the negative connection end of the energy storage capacitor is connected with the data holding circuit;

[0015] The discharge reset circuit is connected with the spike signal output end;

[0016] The working control circuit is used for controlling the working state of the neuron circuit by controlling the conduction or turn-off of the first switch tube; when the first switch tube is turned on and the stimulus signal input end inputs the stimulus current, the energy storage capacitor is charged; when the voltage value obtained by charging the energy storage capacitor is greater than a preset threshold value, the discharge reset circuit outputs the spike signal through the spike signal output end, and discharges and resets the charging of the energy storage capacitor;

[0017] The data holding circuit is connected with each of the neuron circuits, and is used for holding the electrical potential of the negative connection end of the energy storage capacitor in each of the neuron circuits.

[0018] In an embodiment, the neuron model circuit further comprises a synapse circuit, the synapse circuit comprising a signal receiving end, a stimulus current output end, a second switch tube and a discharge capacitor;

[0019] The signal receiving end is used for receiving the spike signal output by the neuron model circuit of a previous cascade;

[0020] The stimulus current output end is used for output of the stimulus current;

[0021] a gate of the second switch tube is connected with the working control circuit, a source of the second switch tube is connected with the stimulating current output end, and a drain of the second switch tube is connected with the signal receiving end;

[0022] a positive connection end of the discharge capacitor is connected with the drain of the second switch tube, and a negative connection end of the discharge capacitor is connected with the data holding circuit;

[0023] the working control circuit is further configured to control the working state of the neuron circuit by controlling the conduction or the closing of the second switch tube; when the second switch tube is conducted and the signal receiving end inputs the pulse signal, the discharge capacitor is discharged, and the stimulating current is output through the stimulating current output end.

[0024] In an embodiment, the first switch tube of the neuron circuit and the second switch tube of the synapse circuit are the same switch tube.

[0025] In an embodiment, the discharge reset circuit is connected with the gate of the first switch tube; the discharge reset circuit controls the potential difference V GS between the gate and the source of the first switch tube to realize the discharge reset of the energy storage of the energy storage capacitor.

[0026] In an embodiment, the discharge reset of the energy storage of the energy storage capacitor by the discharge reset circuit includes hard reset and soft reset.

[0027] The hard reset refers to that, after the discharge reset of the energy storage capacitor by the discharge reset circuit, the voltage value of the energy storage capacitor is 0.

[0028] The soft reset refers to that, after the discharge reset of the energy storage capacitor by the discharge reset circuit, the voltage value of the energy storage capacitor is reduced by a preset value.

[0029] According to the second aspect, in an embodiment, a neuron behavior simulation system is provided, which includes a neuron model circuit, the neuron model circuit including a neuron circuit for simulating neuron behavior, the neuron circuit including a stimulating signal input end, a pulse signal output end, a third switch tube T, an energy storage capacitor, and a discharge reset circuit;

[0030] The stimulating signal input end is configured to input a stimulating current.

[0031] The pulse signal output end is configured to output a pulse signal.

[0032] A source of the third switch tube is connected with the discharge reset circuit, and a drain of the third switch tube is connected with the stimulating signal input end.

[0033] The positive connection end of the energy storage capacitor is connected with the source of the third switch tube, and the negative connection end of the energy storage capacitor is connected with a data holding circuit;

[0034] The data holding circuit is connected with each of the neuron circuits, and is used for keeping the negative connection end of the energy storage capacitor in each of the neuron circuits at the same potential;

[0035] The discharge reset circuit is connected with the pulse signal output end;

[0036] The neuron model circuit controls the working state of the neuron circuit by controlling the conduction or the closing of the third switch tube; when the third switch tube is conducted and the stimulating current is input into the stimulating signal input end, the energy storage capacitor is charged; when the voltage value obtained by charging the energy storage capacitor is greater than a preset threshold value, the discharge reset circuit outputs the pulse signal through the pulse signal output end, and discharges and resets the energy storage capacitor.

[0037] In an embodiment, the neuron model circuit further comprises a synapse circuit, and the synapse circuit comprises a signal receiving end, a stimulating current output end, a second switch tube and a discharge capacitor;

[0038] The signal receiving end is used for receiving the pulse signal output by the neuron model circuit of a previous cascade;

[0039] The stimulating current output end is used for outputting the stimulating current;

[0040] The source of the second switch tube is connected with the stimulating current output end, and the drain of the second switch tube is connected with the signal receiving end;

[0041] The positive connection end of the discharge capacitor is connected with the drain of the second switch tube, and the negative connection end of the discharge capacitor is connected with the data holding circuit;

[0042] The neuron model circuit controls the working state of the neuron circuit by controlling the conduction or the closing of the second switch tube; when the second switch tube is conducted and the pulse signal is input into the signal receiving end, the discharge capacitor is discharged, and the stimulating current is output through the stimulating current output end.

[0043] In an embodiment, the third switch tube of the neuron circuit and the second switch tube of the synapse circuit are the same switch tube.

[0044] In an embodiment, the neuron behavior simulation system comprises a plurality of neuron model circuits, each of which comprises at least one neuron circuit; each of the neuron circuits is connected to each other in cascade and / or in parallel, and the pulse signal output end of the neuron circuit is connected to the stimulation signal input end of at least one next-stage neuron circuit to output the pulse signal as the stimulation signal of the next-stage neuron circuit.

[0045] According to a third aspect, in an embodiment, a neuron behavior simulation method is provided, which is applied to the neuron behavior simulation system according to the second aspect, and the neuron behavior simulation method comprises:

[0046] converting the stimulation signal into a stimulation current input into the neuron circuit;

[0047] the neuron circuit stores the stimulation current through an energy storage capacitor;

[0048] when the voltage value obtained by the energy storage capacitor is greater than a preset threshold value, the neuron circuit outputs a pulse signal and discharges and resets the energy storage capacitor.

[0049] According to the dynamic random memory of the above-mentioned embodiment, the energy storage capacitor is controlled by controlling the switch of the switch tube to simulate the neuron behavior, so that the device for pulse neural network operation is faster and more energy-saving, and compared with the traditional memristor, the neuron behavior simulation is more stable and reliable. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 is an equivalent circuit diagram of an LIF neuron;

[0051] Figure 2 is a schematic diagram of the circuit connection of a neuron model circuit in an embodiment;

[0052] Figure 3 is a schematic diagram of the circuit connection of a neuron model circuit in another embodiment;

[0053] Figure 4 is a schematic diagram of the cascade of neuron circuits of a neuron behavior simulation system in an embodiment;

[0054] Figure 5 is a schematic diagram of the flow of a neuron behavior simulation method in an embodiment. DETAILED DESCRIPTION

[0055] The application will be described in further detail below with specific reference being made to the figures. Like elements in different embodiments are denoted by like reference numerals. In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the application. However, it will be apparent to one skilled in the art that the application can be practiced without the specific details given herein. In other instances, well-known features are not described in detail to avoid obscuring the application. In this description, references to various configurations and embodiments do not imply that the application is directed to more than one device, apparatus, or method, unless otherwise indicated. That is, as would be apparent from the disclosure and elicited from the description given, a single feature can be included in some embodiments, implementations or configurations, and multiple features can be included in other embodiments, implementations or configurations.

[0056] In addition, features, operations, or steps described in the detailed description can be performed in any order, unless otherwise specified. In some embodiments, features, operations, or steps can be optional depending on the circumstances. Furthermore, certain features, operations, or steps can be performed more than once, depending on the circumstances. The sequence in which steps are described is not necessarily the sequence in which the steps are performed. Some steps can be performed simultaneously. The description, therefore, is not to be taken in a literal sense, and is merely intended to illustrate the general nature of the application. Other embodiments can be apparent to those of ordinary skill in the art from the full description and claims provided herein.

[0057] The sequence of numbering of components in the text, such as "first", "second", etc., is used only to distinguish the described objects, and does not have any order or technical meaning. The "connection" and "coupling" in the application, unless otherwise specified, include direct and indirect connections (couplings).

[0058] The basic computing unit of SNN is the spiking neuron, whose activity is in the form of discrete spikes, unlike the continuous activation value of traditional neurons. Spiking neurons transmit information by firing spikes, simulating the behavior of biological neurons. After years of research and development, various spiking neuron models have been established, such as H-H model, LIF model, Izhikevich model, and Spike Response Model (SRM).

[0059] Please refer to Figure 1 The working principle of the spiking neuron is introduced below taking the LIF neuron model as an example. The differential version equation of the LIF neuron is represented as:

[0060] ;

[0061] The discrete version equation of the LIF neuron is represented as:

[0062] ;

[0063] ;

[0064] .

[0065] To simulate neuron behavior, one needs to understand the basic functions of a neuron, which include:

[0066] 1) Input summation.

[0067] A spiking neuron receives signals from other neurons or external inputs, each with a corresponding synaptic weight. These input signals are summed up through the synaptic weights to form the neuron's total input. Input signals are represented as 0 or 1 in computation, i.e., 1 if the other neuron sends a signal (called a spike) to the current neuron, and 0 if there is no signal. In the neuron equation above, X t is the input summation.

[0068] 2) Membrane potential.

[0069] A spiking neuron maintains an internal electrical potential, called the membrane potential. The membrane potential is determined by the input summation and the neuron's own characteristics, such as capacitance and resistance. The membrane potential changes over time due to the influence of input signals. In the neuron equation above, H t+1 and V t+1 are the membrane potentials after different activities; H t+1 is the voltage after accumulating input signals to the membrane potential; V t+1 is the voltage after a spike is emitted.

[0070] 3) Threshold activation.

[0071] When the membrane potential exceeds the neuron's threshold, the neuron generates a spike (or action potential). The threshold is a trigger condition for the spiking neuron to generate a spike, and it is usually a fixed parameter.

[0072] 4) Spike transmission.

[0073] Once the neuron's membrane potential exceeds the threshold, the neuron generates a spike. This spike is sent to other neurons connected to it, affecting their membrane potentials and propagating to other parts of the network over time.

[0074] 5) Membrane potential reset.

[0075] After generating a spike, the membrane potential of the spiking neuron is reset to a baseline value, usually zero. This process simulates the recovery process of biological neurons after generating an action potential.

[0076] 6) Absolute refractory period.

[0077] After generating a pulse, the neuron enters a state of absolute refractory period, during which the neuron cannot generate another pulse. During this time window, even if the input signal exceeds the threshold again, the neuron will not generate a new pulse.

[0078] In Figure 1 The neuron simulation circuit shown is to simulate the working principle of human nervous system by using the memory characteristics of the memristor.

[0079] In the embodiments of the present application, a capacitor-based dynamic random access memory (DRAM) is adopted, which stores information by a series structure of a transistor and a capacitor. The capacitor stores data in the form of electric charge, and the presence or absence of the electric charge represents binary data "0" or "1". According to the formula Q = C * V, the two states "0" or "1" in the DRAM can be represented by the size of the capacitor voltage. However, the DRAM in the prior art still has problems. In order to distinguish the two states "0" or "1" in the DRAM, the capacitor needs to be large enough to store sufficient electric charge to avoid data loss caused by a small amount of leakage. According to the capacitor size calculation formula:

[0080] ;

[0081] In order to increase the capacitance, a material with a larger dielectric constant can be selected, and at the same time the gap between the two plates of the capacitor can be reduced. However, in the current DRAM, these two items have basically reached the physical limit and cannot be further increased.

[0082] However, the natural leakage phenomenon of the capacitor can realize the linear time-varying characteristic, as long as the leakage process of the capacitor is linear. Based on the capacitor-based DRAM, each storage unit includes a transistor and a capacitor, and the capacitor discharge equation of the unit can be expressed as:

[0083] ;

[0084] Obviously, the discharge curve of the capacitor is modulated by the size of the resistance R. The transistor is regarded as a variable resistance connected in series with the capacitor. In order to realize the controllable discharge of the capacitor, the transistor should be in the saturation region (V GS >V th and V DS ≥V GS −V th ), the current thereof is independent of V DS and only related to V GS , that is:

[0085] ;

[0086] Combining the discharge equation of the capacitor, we have:

[0087] ;

[0088] At the same time, the integral of both sides can be obtained:

[0089] ;

[0090] It is not difficult to find that at this time the discharge of the capacitor is linear, and the discharge speed is modulated by V GS .

[0091] By applying the controllable discharge characteristics of the energy storage capacitor in the above-mentioned switch tube capacitor circuit, the neuron behavior simulation can be realized by controlling the voltage value of the energy storage capacitor. Not only can the operation of the spiking neural network be performed in a storage and calculation integrated manner, but also the computing speed of the operation device for the spiking neural network can be faster and more energy-saving.

[0092] Embodiment one:

[0093] Please refer to Figure 2 , a circuit connection diagram of a neuron model circuit in an embodiment, the dynamic random access memory disclosed in the embodiment is used to perform the operation of the spiking neural network, and includes a plurality of neuron model circuits 1, a working control circuit 2, and a data retention circuit 3. Each neuron model circuit 1 includes a neuron circuit 11 for simulating the behavior of a neuron, the neuron circuit 11 includes a stimulation signal input end, a pulse signal output end, a first switch tube T out , an energy storage capacitor C out , and a discharge reset circuit. The stimulation signal input end is used for input of a stimulation current, and the pulse signal output end is used for output of a pulse signal. The gate of the first switch tube T out is connected with the working control circuit 2, the source of the first switch tube T out is connected with the discharge reset circuit, and the drain of the first switch tube T out is connected with the stimulation signal input end. The positive connection end of the energy storage capacitor C out is connected with the source of the first switch tube T out , and the negative connection end of the energy storage capacitor C out is connected with the data retention circuit 3. The discharge reset circuit is connected with the pulse signal output end, and the working control circuit is used to control the working state of the neuron circuit by controlling the conduction or closing of the first switch tube T out . When the first switch tube T out is turned on and the stimulation signal input end inputs the stimulation current, the energy storage capacitor C out is charged; when the voltage value obtained by charging the energy storage capacitor C out is greater than a preset threshold value, the discharge reset circuit outputs a pulse signal through the pulse signal output end, and discharges the energy storage capacitor C outThe stored energy is discharged and reset. Data retention circuit 3 is connected to each neuron circuit to maintain the negative connection terminal of the energy storage capacitor in each neuron circuit at the same potential.

[0094] In one embodiment, the neuron model circuit 1 further includes a synaptic circuit 12, which includes a signal receiving terminal, a stimulation current output terminal, and a second switching transistor T. in and discharge capacitor C in The signal receiving terminal is used to receive the pulse signal output from the previous cascaded neuron model circuit 1. The stimulation current output terminal is used to output the stimulation current, and the second switch T... in The gate of the second switching transistor T is connected to the working control circuit 2. in The source of the second switching transistor T is connected to the output terminal of the stimulation current. in The drain of the capacitor is connected to the signal receiving terminal. The discharge capacitor C... in The positive connection terminal is connected to the second switching transistor T. in The drain connection, discharge capacitor C in The negative connection terminal is connected to the data holding circuit 3. The operation control circuit 2 is also used to control the second switching transistor T. in The switching on or off of the second switch transistor T controls the operating state of the neuron circuit. in When the circuit is turned on and a pulse signal is input to the signal receiving terminal, the discharge capacitor C... in Discharge, and output stimulation current through stimulation current output terminal.

[0095] Please refer to Figure 3 This is a circuit connection diagram of the neuron model circuit in another embodiment. In one embodiment of this application, the first switch T of the neuron circuit 11... out and the second switching transistor T of the synaptic circuit 12 in It is the same switching transistor T.

[0096] like Figure 2 As shown, in one embodiment, the discharge reset circuit and the first switching transistor T out The gate connection, the discharge reset circuit controls the first switching transistor T out The potential difference V between the gate and the source GS The value of C is used to control the energy storage capacitor C. out The stored energy is discharged and reset. Specifically, the discharge reset circuit discharges and resets the energy storage capacitor C. out The energy storage circuit performs discharge reset, which includes hard reset and soft reset. Hard reset refers to the discharge reset circuit resetting the energy storage capacitor C. out After discharge, the energy storage capacitor C out The voltage value is 0. A soft reset refers to the discharge reset circuit affecting the energy storage capacitor C. out After discharge, the energy storage capacitor C outThe voltage value decreases by a preset value. Because in practical applications, each neuron model circuit can connect to multiple preceding neuron circuits, resulting in the simultaneous receipt of multiple pulse signals, the energy storage capacitor C... out If the voltage value is directly set to 0 (hard reset), some stimulation signals will be lost. Soft reset does not guarantee that no pulse signal information will be lost (for example, the preset reduction value is 0.5, and the energy storage capacitor C...). out Simultaneously, 0.8 kJ of energy is stored, and while the discharge reset circuit outputs a pulse signal, the energy storage capacitor C... out The voltage value was set from 0.8 to 0.3, so that the stimulation signal at 0.3 was preserved.

[0097] Please refer to Figure 4 This is a schematic diagram of a cascaded neuron circuit in a neuron behavior simulation system according to one embodiment. This application also discloses a neuron behavior simulation system for simulating the nervous system. The neuron behavior simulation system includes a neuron model circuit 1, which includes neuron circuits for simulating neuron behavior. Each neuron circuit includes a stimulation signal input terminal, a pulse signal output terminal, a third switch, an energy storage capacitor, and a discharge reset circuit. The stimulation signal input terminal is used to input a stimulation current, and the pulse signal output terminal is used to output a pulse signal. The source of the third switch T is connected to the discharge reset circuit, and the drain of the third switch T is connected to the stimulation signal input terminal. The positive connection terminal of the energy storage capacitor is connected to the source of the third switch T, and the negative connection terminal of the energy storage capacitor is connected to a data holding circuit. The data holding circuit is connected to each neuron circuit to maintain the negative connection terminal of the energy storage capacitor in each neuron circuit at the same potential. The discharge reset circuit is connected to the pulse signal output terminal. The neuron model circuit controls the working state of the neuron circuit by controlling the on or off state of the third switch T. When the third switch T is on and a stimulation current is input to the stimulation signal input terminal, energy is stored in the energy storage capacitor. When the voltage value obtained by the energy storage capacitor exceeds a preset threshold, the discharge reset circuit outputs a pulse signal through the pulse signal output terminal to discharge and reset the energy storage of the energy storage capacitor. For example... Figure 2As shown, in one embodiment, the neuron model circuit further includes a synaptic circuit, which includes a signal receiving terminal, a stimulation current output terminal, a second switch, and a discharge capacitor. The signal receiving terminal is used to receive the pulse signal output by the previous cascaded neuron model circuit. The stimulation current output terminal is used to output a stimulation current. The source of the second switch is connected to the stimulation current output terminal, and the drain of the second switch is connected to the signal receiving terminal. The positive connection terminal of the discharge capacitor is connected to the drain of the second switch, and the negative connection terminal of the discharge capacitor is connected to the data holding circuit. The neuron model circuit controls the working state of the neuron circuit by controlling the conduction or deactivation of the second switch. When the second switch is on and a pulse signal is input to the signal receiving terminal, the discharge capacitor discharges and outputs a stimulation current through the stimulation current output terminal. In one embodiment, the third switch T of the neuron circuit and the second switch of the synaptic circuit are the same switch. In one embodiment, the neuron behavior simulation system includes multiple neuron model circuits 1, and each neuron model circuit 1 includes at least one neuron circuit. The individual neuron circuits are interconnected by cascading and / or paralleling. The pulse signal output terminal of the neuron circuit is connected to the stimulation signal input terminal of at least one subsequent neuron circuit, so that the output pulse signal is used as the stimulation signal of the subsequent neuron circuit.

[0098] Please refer to Figure 5 The diagram above illustrates a flowchart of a neuron behavior simulation method in one embodiment. In another embodiment, this application also discloses a neuron behavior simulation method for use in the neuron behavior simulation system described above. This neuron behavior simulation method includes:

[0099] Step 101, stimulus signal conversion.

[0100] The stimulus signal is converted into a stimulus current and input into the neuronal circuit.

[0101] Step 102: Store the stimulation current.

[0102] The neuronal circuit stores the stimulation current through an energy storage capacitor.

[0103] Step 103: Output pulse signal.

[0104] When the voltage value obtained by the energy storage capacitor exceeds a preset threshold, the neuron circuit outputs a pulse signal and discharges and resets the energy storage capacitor.

[0105] The dynamic random access memory disclosed in this application includes multiple neuron model circuits, a working control circuit, and a data retention circuit. Each neuron model circuit includes a neuron circuit, which includes a first switching transistor, an energy storage capacitor, and a discharge reset circuit. The working control circuit controls the working state of the neuron circuit by controlling the on / off state of the first switching transistor. When the first switching transistor is on and receives a stimulation current, it stores energy in the energy storage capacitor. When the voltage value obtained by the energy storage capacitor exceeds a preset threshold, the discharge reset circuit outputs a pulse signal and discharges and resets the energy stored in the energy storage capacitor. Because the energy storage capacitor is controlled by switching the transistor on and off to simulate neuron behavior, the device used for spiking neural network computation is faster and more energy-efficient, and more stable and reliable than the method of simulating neuron behavior using memristors.

[0106] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A dynamic random access memory, characterized in that, The dynamic random access memory (DRAM) is used to perform operations on a spiking neural network and includes multiple neuron model circuits, an operation control circuit, and a data retention circuit. Each of the neuron model circuits includes a neuron circuit for simulating neuron behavior, the neuron circuit including a stimulation signal input terminal, a pulse signal output terminal, a first switching transistor, an energy storage capacitor, and a discharge reset circuit; The stimulation signal input terminal is used for inputting a stimulation current; The pulse signal output terminal is used to output pulse signals; The gate of the first switching transistor is connected to the working control circuit, the source of the first switching transistor is connected to the discharge reset circuit, and the drain of the first switching transistor is connected to the stimulation signal input terminal. The positive terminal of the energy storage capacitor is connected to the source of the first switching transistor, and the negative terminal of the energy storage capacitor is connected to the data holding circuit. The discharge reset circuit is connected to the pulse signal output terminal; The working control circuit is used to control the working state of the neuron circuit by controlling the conduction or de-conduction of the first switch; when the first switch is turned on and the stimulation current is input at the stimulation signal input terminal, the energy storage capacitor is used to store energy; when the voltage value obtained by the energy storage capacitor is greater than a preset threshold, the discharge reset circuit outputs the pulse signal through the pulse signal output terminal and discharges and resets the energy storage of the energy storage capacitor. The data holding circuit is connected to each of the neuron circuits and is used to maintain the negative connection potential of the energy storage capacitor in each of the neuron circuits. The neuron model circuit also includes a synaptic circuit, which includes a signal receiving end, a stimulation current output end, a second switching transistor, and a discharge capacitor. The signal receiving end is used to receive the pulse signal output by the previous cascaded neuron model circuit; The stimulation current output terminal is used to output the stimulation current; The gate of the second switching transistor is connected to the working control circuit, the source of the second switching transistor is connected to the stimulation current output terminal, and the drain of the second switching transistor is connected to the signal receiving terminal. The positive terminal of the discharge capacitor is connected to the drain of the second switching transistor, and the negative terminal of the discharge capacitor is connected to the data holding circuit. The operating control circuit is also used to control the operating state of the synapse circuit by controlling the conduction or de-conduction of the second switch; when the second switch is turned on and the pulse signal is input to the signal receiving terminal, the discharge capacitor discharges and outputs the stimulation current through the stimulation current output terminal; The first switch of the neuron circuit and the second switch of the synapse circuit are the same switch.

2. The dynamic random access memory as described in claim 1, characterized in that, The discharge reset circuit is connected to the gate of the first switching transistor; the discharge reset circuit controls the potential difference V between the gate and source of the first switching transistor. GS The value is used to discharge and reset the energy stored in the energy storage capacitor.

3. The dynamic random access memory as described in claim 2, characterized in that, The discharge reset circuit discharges and resets the energy stored in the energy storage capacitor, including hard reset and soft reset. The hard reset refers to the voltage value of the energy storage capacitor being 0 after the discharge reset circuit discharges the energy storage capacitor. The soft reset refers to the voltage value of the energy storage capacitor decreasing by a preset value after the discharge reset circuit discharges the energy storage capacitor.

4. A neuronal behavior simulation system, characterized in that, The system includes a neuron model circuit, which includes a neuron circuit for simulating neuron behavior. The neuron circuit includes a stimulation signal input terminal, a pulse signal output terminal, a third switching transistor, an energy storage capacitor, and a discharge reset circuit. The stimulation signal input terminal is used for inputting a stimulation current; The pulse signal output terminal is used to output pulse signals; The source of the third switch is connected to the discharge reset circuit, and the drain of the third switch is connected to the stimulation signal input terminal. The positive terminal of the energy storage capacitor is connected to the source of the third switching transistor, and the negative terminal of the energy storage capacitor is connected to a data holding circuit. The data holding circuit is connected to each of the neuron circuits and is used to maintain the negative connection potential of the energy storage capacitor in each of the neuron circuits. The discharge reset circuit is connected to the pulse signal output terminal; The neuron model circuit controls the working state of the neuron circuit by controlling the conduction or deactivation of the third switch; when the third switch is turned on and the stimulation current is input at the stimulation signal input terminal, energy is stored in the energy storage capacitor; when the voltage value obtained by the energy storage capacitor is greater than a preset threshold, the discharge reset circuit outputs the pulse signal through the pulse signal output terminal and discharges and resets the energy stored in the energy storage capacitor. The neuron model circuit also includes a synaptic circuit, which includes a signal receiving end, a stimulation current output end, a second switching transistor, and a discharge capacitor. The signal receiving end is used to receive the pulse signal output by the previous cascaded neuron model circuit; The stimulation current output terminal is used to output the stimulation current; The source of the second switching transistor is connected to the stimulation current output terminal, and the drain of the second switching transistor is connected to the signal receiving terminal. The positive terminal of the discharge capacitor is connected to the drain of the second switching transistor, and the negative terminal of the discharge capacitor is connected to the data holding circuit. The neuron model circuit controls the working state of the synapse circuit by controlling the conduction or de-conduction of the second switch; when the second switch is turned on and the pulse signal is input at the signal receiving terminal, the discharge capacitor discharges and outputs the stimulation current through the stimulation current output terminal. The third switch of the neuron circuit and the second switch of the synapse circuit are the same switch.

5. The neuronal behavior simulation system as described in claim 4, characterized in that, The system includes multiple neuron model circuits, each of which includes at least one neuron circuit. The neuron circuits are interconnected by cascading and / or paralleling. The pulse signal output terminal of each neuron circuit is connected to the stimulation signal input terminal of at least one subsequent neuron circuit, so that the output pulse signal is used as the stimulation signal of the subsequent neuron circuit.

6. A method for simulating neuronal behavior, characterized in that, For use in a neuron behavior simulation system as described in any one of claims 4 to 5, the neuron behavior simulation method comprises: The stimulus signal is converted into a stimulus current and input into the neuron circuit. The neuron circuit stores the stimulation current through an energy storage capacitor; When the voltage value obtained by the energy storage capacitor is greater than a preset threshold, the neuron circuit outputs a pulse signal and discharges and resets the energy storage capacitor.

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