Gate-commutated thyristor, its manufacturing method, and electronic device

Abstract

The present disclosure relates to a gate commutated thyristor, a preparation method thereof, and an electronic device. At least one functional unit of the gate commutated thyristor includes a stacked structure, a first gate, a cathode, a second gate that are located on a first side of the stacked structure and are sequentially distributed in a first direction, and an anode that is located on a second side of the stacked structure; the first side and the second side are two sides of the stacked structure that face away from each other in a second direction; the stacked structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer that are sequentially stacked in the second direction; an emitter region that is located between the first gate and the second gate and is electrically connected to the cathode is included in the third epitaxial layer; the second epitaxial layer includes a wide bandgap semiconductor material and has a target lattice, and the first epitaxial layer and the third epitaxial layer have the same conductivity type; the second epitaxial layer and the emitter region have the same conductivity type, and the conductivity type is opposite to that of the first epitaxial layer, and at least the thickness and volume of the chip can be reduced without reducing the breakdown voltage amplitude of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, particularly to the field of power semiconductor devices, and specifically to a gate commutated thyristor, a preparation method thereof, and an electronic device. Background Art

[0002] The long-distance transmission and conversion of electric energy require high-voltage and large-capacity power semiconductor devices. The Gate Commutated Thyristor (GCT) has many advantages such as strong current-carrying capacity, large turn-off current, low on-state loss, and controllable commutation. When it is used for long-distance electric energy transmission, the power loss can be minimized, and the ability of the DC system to resist commutation failure can be effectively improved.

[0003] However, due to the breakdown voltage limit of silicon-based materials, if the breakdown voltage of the GCT chip is increased, the thickness of the chip needs to be thickened. For example, the thickness of an 8 kV reverse-blocking GCT chip is more than 1.4 mm, while the thickness of a general chip is generally less than 1 mm. If a breakdown voltage above 10 kV is to be achieved, the chip thickness will be even larger. The increased chip size poses a great obstacle to process processing and the improvement of chip yield. Summary of the Invention

[0004] Based on this, the present disclosure provides a gate commutated thyristor, a preparation method thereof, and an electronic device, which can at least reduce the thickness and volume of the chip without reducing the breakdown voltage amplitude of the chip; or improve the breakdown voltage level of the chip while keeping the chip thickness and volume unchanged.

[0005] According to various embodiments of the present disclosure, on the one hand, a gate commutated thyristor is provided, at least one functional unit of which includes a stacked structure, a first gate, a cathode, a second gate that are located on the first side of the stacked structure and are sequentially distributed along a first direction, and an anode that is located on the second side of the stacked structure; the first side and the second side are two sides of the stacked structure that face away from each other along a second direction; the second direction intersects with the first direction; the stacked structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer that are sequentially stacked along the second direction; an emitter region that is located between the first gate and the second gate and is electrically connected to the cathode is included in the third epitaxial layer; the second epitaxial layer includes a wide-bandgap semiconductor material and has a target lattice; wherein, the first epitaxial layer and the third epitaxial layer have the same conductivity type; the second epitaxial layer and the emitter region have the same conductivity type, and are opposite to the conductivity type of the first epitaxial layer.

[0006] For the gate commutated thyristor in the above embodiments, by setting the stacked structure to include a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer stacked in sequence, the first epitaxial layer and the third epitaxial layer have the same conductivity type and are opposite to the conductivity type of the second epitaxial layer. The second epitaxial layer includes a wide bandgap semiconductor material and has a target lattice, and a drift region can be formed within the second epitaxial layer. As a typical representative of wide bandgap semiconductors, the breakdown field strength of silicon carbide is 10 times that of silicon materials. For chips with the same withstand voltage capacity, its thickness can be made 1 / 10 of that of silicon chips. Therefore, using silicon carbide material to form the N-drift region can effectively reduce the chip thickness, lower the process difficulty, or increase the withstand voltage level of the chip while keeping the chip thickness and volume unchanged. By providing a first gate, a cathode, and a second gate on the side of the third epitaxial layer facing away from the first epitaxial layer, an anode on the side of the first epitaxial layer facing away from the third epitaxial layer, and an emitter region located between the first gate and the second gate and electrically connected to the cathode within the third epitaxial layer, a heterojunction gate commutated thyristor is formed. Since the second epitaxial layer including silicon carbide can effectively reduce the thickness of the stacked structure, improve the withstand voltage level of the heterojunction gate commutated thyristor, and reduce the conduction loss of the heterojunction gate commutated thyristor, this embodiment can effectively reduce the thickness, volume, and processing difficulty of the gate commutated thyristor while improving the electrical performance and reliability of the gate commutated thyristor.

[0007] In one of the embodiments, the top surface of the emitter region is higher than the top surfaces of the first gate and the second gate; the bottom surface of the emitter region is lower than the top surface of the third epitaxial layer, which can increase the volume of the emitter region and its contact area with the third epitaxial layer, and increase the insulation area between the emitter region and the first gate and the second gate without increasing the overall thickness of the chip, thereby reducing the leakage current between the emitter region and the first gate and the second gate, and thus improving the withstand voltage level of the heterojunction gate commutated thyristor, reducing the conduction loss of the heterojunction gate commutated thyristor, and improving the reliability of the gate commutated thyristor.

[0008] In one of the embodiments, it further includes a dielectric layer, the dielectric layer covers the top surface of the third epitaxial layer between the first gate and the second gate, and the outer surface of the emitter region; wherein, the dielectric layer includes an opening exposing a part of the top surface of the emitter region, the cathode is in ohmic contact with the top surface of the emitter region exposed by the opening, and the dielectric layer also circumferentially covers at least part of the sidewall of the cathode. By setting the top surface of the emitter region to be higher than the top surfaces of the first gate and the second gate, and setting the bottom surface of the emitter region to be lower than the top surface of the third epitaxial layer, the contact area between the dielectric layer and the outer surface of the emitter region is increased, and the leakage current between the emitter region and the first gate and the second gate is reduced; since the volume of the emitter region is also increased, the withstand voltage level of the heterojunction gate commutated thyristor can be improved, and the conduction loss of the heterojunction gate commutated thyristor can be reduced.

[0009] In one embodiment, a protective layer is further included. The protective layer covers the top surfaces of the first gate and the second gate, the outer surface of the dielectric layer, and circumferentially surrounds the cathode, increasing the insulation between the emission region and the first gate and the second gate, and protecting the first gate, the second gate, and the cathode with the protective layer to prevent the first gate, the second gate, and the cathode from being oxidized or contaminated by external dust or particles, etc., thereby improving the reliability of the gate commutated thyristor and increasing its service life.

[0010] In one embodiment, the top surface of the cathode is higher than the top surface of the protective layer, facilitating the extraction of the cathode.

[0011] In one embodiment, the crystal forms of silicon carbide in the second epitaxial layer include 4H type, 3C type, 6H type or a combination thereof.

[0012] In one embodiment, the first epitaxial layer is P-type and the second epitaxial layer is N-type; or, the first epitaxial layer is N-type and the second epitaxial layer is P-type.

[0013] According to various embodiments of the present disclosure, on the other hand, an electronic device is provided, including: the above-mentioned gate commutated thyristor. Since the gate commutated thyristor in the embodiments of the present disclosure can effectively reduce the thickness, volume, and processing difficulty of the gate commutated thyristor while improving the electrical performance and reliability of the gate commutated thyristor, it is helpful to reduce the volume of the electronic device and improve the electrical performance and reliability of the electronic device.

[0014] According to various embodiments of the present disclosure, on yet another aspect, a method for manufacturing a gate commutated thyristor is provided, including:

[0015] Providing a stacked structure; the stacked structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer stacked in sequence; the second epitaxial layer includes a wide-bandgap semiconductor material and has a target lattice;

[0016] Forming an emission region in the third epitaxial layer;

[0017] Forming a first gate, a second gate, and a cathode located between the first gate and the second gate on a side of the third epitaxial layer facing away from the first epitaxial layer, and the cathode is electrically connected to the emission region;

[0018] Forming an anode on a side of the first epitaxial layer facing away from the second epitaxial layer.

[0019] In the above-described embodiment of the method for fabricating a gate-commutated thyristor, by providing a stacked structure including a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer stacked in sequence, the first epitaxial layer and the third epitaxial layer have the same conductivity type and are opposite to the conductivity type of the second epitaxial layer. The second epitaxial layer includes a wide-bandgap semiconductor material and has a target lattice, and a drift region can be formed within the second epitaxial layer. As a typical representative of wide-bandgap semiconductors, silicon carbide has a breakdown field strength 10 times that of silicon materials. For chips with the same withstand voltage capability, its thickness can be made 1 / 10 of that of silicon chips. Therefore, using silicon carbide material to form an N-drift region can effectively reduce the chip thickness and lower the process difficulty. By forming a first gate, a cathode, and a second gate on the side of the third epitaxial layer facing away from the first epitaxial layer, and forming an anode on the side of the first epitaxial layer facing away from the third epitaxial layer, and including an emitter region within the third epitaxial layer that is located between the first gate and the second gate and is electrically connected to the cathode, a heterojunction gate-commutated thyristor is formed. Since the second epitaxial layer including silicon carbide can effectively reduce the thickness of the stacked structure, improve the withstand voltage level of the heterojunction gate-commutated thyristor, and reduce the conduction loss of the heterojunction gate-commutated thyristor, therefore, this embodiment can effectively reduce the thickness, volume, and processing difficulty of the gate-commutated thyristor while improving the electrical performance and reliability of the gate-commutated thyristor.

[0020] In one embodiment, a stacked structure is provided, including:

[0021] A substrate is provided;

[0022] A second epitaxial layer is formed on the substrate;

[0023] A third epitaxial layer is formed on the surface of the second epitaxial layer facing away from the substrate;

[0024] The substrate is removed;

[0025] A first epitaxial layer is formed on the surface of the second epitaxial layer facing away from the third epitaxial layer;

[0026] In one embodiment, a stacked structure is provided, including:

[0027] A substrate is provided;

[0028] A second epitaxial layer is formed on the substrate; the second epitaxial layer includes a first surface close to the substrate and a second surface facing away from the substrate;

[0029] The substrate is removed;

[0030] A first epitaxial layer is formed on the first surface of the second epitaxial layer, and a third epitaxial layer is formed on the second surface of the second epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0032] Figure 1 It is a schematic longitudinal sectional structure diagram of a gate commutated thyristor provided in an embodiment of the present disclosure;

[0033] Figure 2 It is a schematic flowchart of a method for manufacturing a gate commutated thyristor provided in an embodiment of the present disclosure;

[0034] Figure 3 It is a schematic longitudinal sectional structure diagram of a semiconductor structure obtained after forming a second epitaxial layer in a method for manufacturing a gate commutated thyristor according to an embodiment of the present disclosure;

[0035] Figure 4a It is a schematic longitudinal sectional structure diagram of a semiconductor structure obtained after forming a third epitaxial layer in a method for manufacturing a gate commutated thyristor according to an embodiment of the present disclosure;

[0036] Figure 4b It is a schematic longitudinal sectional structure diagram of a semiconductor structure obtained after forming a stacked structure in a method for manufacturing a gate commutated thyristor according to an embodiment of the present disclosure;

[0037] Figure 5a It is a schematic longitudinal sectional structure diagram of a semiconductor structure obtained after forming a second epitaxial layer in a method for manufacturing a gate commutated thyristor according to another embodiment of the present disclosure;

[0038] Figure 5b It is a schematic longitudinal sectional structure diagram of a semiconductor structure obtained after forming a third epitaxial layer in a method for manufacturing a gate commutated thyristor according to another embodiment of the present disclosure;

[0039] Figure 6 It is a schematic longitudinal sectional structure diagram of a semiconductor structure obtained after forming an initial doped layer in a method for manufacturing a gate commutated thyristor according to an embodiment of the present disclosure;

[0040] Figure 7 It is a schematic longitudinal sectional structure diagram of a semiconductor structure obtained after forming an intermediate doped layer and a boss in a method for manufacturing a gate commutated thyristor according to an embodiment of the present disclosure;

[0041] Figure 8 It is a schematic longitudinal sectional structure diagram of a semiconductor structure obtained after forming an emitter region in a method for manufacturing a gate commutated thyristor according to an embodiment of the present disclosure;

[0042] Figure 9 Schematic cross-sectional structure diagram of a semiconductor structure obtained after forming a dielectric layer in a method for manufacturing a gate-commutated thyristor according to an embodiment of the present disclosure;

[0043] Figure 10 Schematic cross-sectional structure diagram of a semiconductor structure obtained after forming a first gate, a second gate, and a cathode in a method for manufacturing a gate-commutated thyristor according to an embodiment of the present disclosure;

[0044] Figure 11 Schematic cross-sectional structure diagram of a semiconductor structure obtained after forming an anode in a method for manufacturing a gate-commutated thyristor according to an embodiment of the present disclosure.

[0045] Wherein, the ox direction can be the first direction, the oy direction can be the second direction, and the oy direction can be the height / thickness direction.

[0046] Explanation of reference numerals:

[0047] 10. Stacked structure; 101. First epitaxial layer; 102. Second epitaxial layer; 103. Third epitaxial layer; 104. Emitter region; 401. First gate; 402. Second gate; 30. Cathode; 50. Dielectric layer; 105. Protective layer; 111. Substrate; 20. Anode; 202. Opening; 2011. Initial doping layer; 2011'. Intermediate doping layer; 2012. Boss. Detailed implementation manners

[0048] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0050] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0051] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0052] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups are not excluded from the presence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the related listed items.

[0053] Note that the mutual insulation between the two described in the embodiments of the present disclosure includes, but is not limited to, the presence of one or more of insulating materials, insulating gas, or gaps between the two.

[0054] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present disclosure. Although only the components related to the present disclosure are shown in the illustrations and are not drawn according to the number, shape, and size of the components in actual implementation, the types, quantities, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0055] Please refer to Figure 1 , in some embodiments, a gate commutated thyristor is provided, at least one functional unit of which includes a stacked structure 10, a first gate 401, a cathode 30, a second gate 402 that are located on the first side of the stacked structure 10 and are sequentially distributed in a first direction (such as the ox direction), and an anode 20 that is located on the second side of the stacked structure 10; the first side and the second side are two sides of the stacked structure 10 that face away from each other in a second direction (such as the oy direction); the second direction intersects with the first direction, for example, is perpendicular. The stacked structure 10 includes a first epitaxial layer 101, a second epitaxial layer 102, and a third epitaxial layer 103 that are sequentially stacked in the second direction; an emitter region 104 that is located between the first gate 401 and the second gate 402 and is electrically connected to the cathode 30 is included in the third epitaxial layer 103; the second epitaxial layer 102 includes silicon carbide; wherein, the first epitaxial layer 101 and the third epitaxial layer 103 have the same conductivity type; the second epitaxial layer 102 and the emitter region 104 have the same conductivity type, and are opposite to the conductivity type of the first epitaxial layer 101.

[0056] As an example, please continue to refer to Figure 1, by setting the stacked structure 10 to include a first epitaxial layer 101, a second epitaxial layer 102, and a third epitaxial layer 103 stacked in sequence, the first epitaxial layer 101 and the third epitaxial layer 103 have the same conductivity type and are opposite to the conductivity type of the second epitaxial layer 102. The second epitaxial layer 102 includes a wide-bandgap semiconductor material and has a target lattice, so that a drift region can be formed within the second epitaxial layer 102. As a typical representative of wide-bandgap semiconductors, the breakdown field strength of silicon carbide is 10 times that of silicon materials. For chips with the same withstand voltage capacity, their thickness can be made 1 / 10 of that of silicon chips. For example, using silicon carbide material to form an N-drift region can effectively reduce the chip thickness and lower the process difficulty. By providing a first gate 401, a cathode 30, and a second gate 402 on a side of the third epitaxial layer 103 facing away from the first epitaxial layer 101, providing an anode 20 on a side of the first epitaxial layer 101 facing away from the third epitaxial layer 103, and providing an emitter region 104 within the third epitaxial layer 103 that is located between the first gate 401 and the second gate 402 and is electrically connected to the cathode 30, a heterojunction gate commutated thyristor is formed. Since the second epitaxial layer 102 including silicon carbide can effectively reduce the thickness of the stacked structure 10, improve the withstand voltage level of the heterojunction gate commutated thyristor, and reduce the conduction loss of the heterojunction gate commutated thyristor, therefore, this embodiment can effectively reduce the thickness, volume, and processing difficulty of the gate commutated thyristor while improving the electrical performance and reliability of the gate commutated thyristor.

[0057] Further, existing MOS devices or diodes generally form a single-sided heterojunction on a substrate. To avoid damaging the quality of the single-sided heterojunction, the substrate is not removed. Additionally, other semiconductor devices can be fabricated in the substrate to improve the integration level. The second epitaxial layer in the embodiment of the present application is made of a wide-bandgap semiconductor material and has a target lattice, capable of forming a heterojunction with the third epitaxial layer on the top surface of the second epitaxial layer and forming a heterojunction with the first epitaxial layer on the bottom surface of the second epitaxial layer, that is, a double-sided heterojunction is formed; and since the substrate is removed and only the high-quality second epitaxial layer grown epitaxially is retained, and then the first epitaxial layer and the third epitaxial layer are grown on the bottom surface and the top surface of the second epitaxial layer respectively using the heteroepitaxial growth process, it is possible to reduce the thickness and volume of the chip without reducing the withstand voltage amplitude of the chip; or it is possible to improve the withstand voltage level of the chip while keeping the chip thickness and volume unchanged.

[0058] Exemplarily, in the embodiment of the present application, by controlling the parameters of the epitaxial growth process, the defect density of the second epitaxial layer grown on the substrate using a wide-bandgap semiconductor material can be no greater than 1 per cm -2 , and then the substrate is removed; or after growing the third epitaxial layer or the first epitaxial layer on the second epitaxial layer, the substrate is removed, thereby fabricating a second epitaxial layer with better crystal quality than that of the substrate crystal.

[0059] Exemplarily, the wide bandgap semiconductor material may include at least one of silicon carbide, gallium nitride, diamond, etc.

[0060] As an example, please continue to refer to Figure 1 , the top surface of the emitter region 104 is higher than the top surfaces of the first gate 401 and the second gate 402; the bottom surface of the emitter region 104 is lower than the top surface of the third epitaxial layer 103, which can increase the volume of the emitter region 104 and its contact area with the third epitaxial layer 103 without increasing the overall thickness of the chip, and increase the insulation area between the emitter region 104 and the first gate 401 and the second gate 402, thereby reducing the leakage current between the emitter region 104 and the first gate 401 and the second gate 402, and thus improving the breakdown voltage rating of the heterojunction gate commutated thyristor, reducing the conduction loss of the heterojunction gate commutated thyristor, and improving the reliability of the gate commutated thyristor.

[0061] As an example, please continue to refer to Figure 1 , the gate commutated thyristor further includes a dielectric layer 50, and the dielectric layer 50 covers the top surface of the third epitaxial layer 103 between the first gate 401 and the second gate 402, and the outer surface of the emitter region 104; wherein, the dielectric layer 50 includes an opening ( Figure 1 not shown in the figure) exposing a part of the top surface of the emitter region 104, the cathode 30 is in ohmic contact with the top surface of the emitter region 104 exposed by the opening, and the dielectric layer 50 also circumferentially covers at least part of the side wall of the cathode 30. By setting the top surface of the emitter region 104 higher than the top surfaces of the first gate 401 and the second gate 402, and setting the bottom surface of the emitter region 104 lower than the top surface of the third epitaxial layer 103, the contact area between the dielectric layer 50 and the outer surface of the emitter region 104 is increased, and the leakage current between the emitter region 104 and the first gate 401 and the second gate 402 is reduced; since the volume of the emitter region 104 is also increased, the breakdown voltage rating of the heterojunction gate commutated thyristor can be improved, and the conduction loss of the heterojunction gate commutated thyristor can be reduced.

[0062] As an example, please continue to refer to Figure 1 , the gate commutated thyristor further includes a protective layer 105, and the protective layer 105 covers the top surface of the first gate 401, the top surface of the second gate 402, and the outer surface of the dielectric layer 50, and circumferentially surrounds the cathode 30, increasing the insulation between the emitter region 104 and the first gate 401 and the second gate 402, and protecting the first gate 401, the second gate 402, and the cathode 30 with the protective layer 105 to prevent the first gate 401, the second gate 402, and the cathode 30 from being oxidized or contaminated by external dust or particles, etc., thereby improving the reliability of the gate commutated thyristor and increasing its service life.

[0063] Exemplarily, the protective layer can be made of polyimide film (PI). PI has outstanding high-temperature resistance, radiation resistance, chemical corrosion resistance, and electrical insulation properties, and can be used in air at 250°C to 280°C for a long time. Therefore, using PI as the protective layer can improve the reliability of the gate commutated thyristor while ensuring the insulation performance between the first gate 401 and the cathode 30, and between the second gate 402 and the cathode 30.

[0064] As an example, please continue to refer to Figure 1 , the top surface of the cathode 30 is higher than the top surface of the protective layer 105, which is convenient for leading out the cathode 30. Since the doping concentration of the emitter region 104 is generally greater than that of the third epitaxial layer 103, the conductivity of the emitter region 104 is generally greater than that of the third epitaxial layer 103. By setting the cathode 30 to be connected to the third epitaxial layer 103 via the emitter region 104, the on-resistance of the cathode 30 can be reduced.

[0065] As an example, please continue to refer to Figure 1 , the crystal form of silicon carbide in the second epitaxial layer 102 includes 4H type, 3C type, 6H type, or a combination thereof.

[0066] Exemplarily, SiC single crystals have more than 200 polytypes, and different polytypes have different physical properties, especially showing their respective characteristics in terms of semiconductor properties. Among them, 4H-SiC is relatively common and the growth technology is relatively mature. The embodiments of the present disclosure can select the crystal form of SiC in the second epitaxial layer according to the actual requirements of different application scenarios.

[0067] In some embodiments, please continue to refer to Figure 1 , the first epitaxial layer 101 is P-type, and the second epitaxial layer 102 is N-type. The doping concentration of P-type ions in the first epitaxial layer 101 is 1e16 cm -3 -1e20 cm -3 , for example, the doping concentration of P-type ions in the first epitaxial layer 101 can be 1e16 cm -3 , 1e17 cm -3 , 1e18 cm -3 , 1e19 cm -3 or 1e20 cm -3 and so on. The doping concentration of N-type ions in the second epitaxial layer 102 is 1e14 cm -3 -5e15 cm -3 , for example, the doping concentration of N-type ions in the second epitaxial layer 102 can be 1e14 cm -3 , 1e15 cm -3 , 3e15 cm -3 or 5e15 cm -3and so on. The doping concentration of P-type ions in the third epitaxial layer 103 is 1e16 cm -3 -1e18 cm -3 , for example, the doping concentration of P-type ions in the third epitaxial layer 103 can be 1e16 cm -3 , 1e17 cm -3 or 1e18 cm -3 and so on.

[0068] In some embodiments, please continue to refer to Figure 1 , the thickness of the first epitaxial layer 101 is 10 μm - 50 μm. For example, the thickness of the first epitaxial layer 101 can be 10 μm, 20 μm, 30 μm, 40 μm or 50 μm and so on.

[0069] In some embodiments, please continue to refer to Figure 1 , the thickness of the second epitaxial layer 102 is 40 μm - 140 μm. For example, the thickness of the second epitaxial layer 102 can be 40 μm, 60 μm, 80 μm, 100 μm, 120 μm or 140 μm and so on.

[0070] In some embodiments, please continue to refer to Figure 1 , the thickness of the third epitaxial layer 103 is 60 μm - 180 μm. For example, the thickness of the third epitaxial layer 103 can be 60 μm, 100 μm, 140 μm, 160 μm or 180 μm and so on.

[0071] In some embodiments, please continue to refer to Figure 1 , the doping concentration of N-type ions in the emitter region 104 is 1e18 cm -3 -1e21 cm -3 , for example, the doping concentration of N-type ions in the emitter region 104 can be 1e18 cm -3 , 1e19 cm -3 , 1e20 cm -3 , or 1e21 cm -3 and so on.

[0072] In some embodiments, please continue to refer to Figure 1 , the thickness of the emitter region 104 is 10 μm - 30 μm. For example, the thickness of the emitter region 104 can be 10 μm, 20 μm or 30 μm and so on.

[0073] In some embodiments, please continue to refer to Figure 1, the first epitaxial layer 101 can also be set as N-type and the second epitaxial layer 102 as P-type. In some embodiments, an electronic device is provided, including: the gate-commutated thyristor described above. Since the gate-commutated thyristor in the embodiments of the present disclosure can effectively reduce the thickness, volume and processing difficulty of the gate-commutated thyristor while improving the electrical performance and reliability of the gate-commutated thyristor, it is helpful to reduce the volume of the electronic device and improve the electrical performance and reliability of the electronic device.

[0074] In some embodiments, the electronic device is, for example but not limited to, electronic products related to DC power transmission, electronic products related to industrial variable frequency speed regulation, electronic products related to wind power grid connection, electronic products related to rail transit, and electronic products related to metallurgy, etc.

[0075] Please refer to Figure 2 , in some embodiments, a method for manufacturing a gate-commutated thyristor is provided, including:

[0076] Step S310: Provide a stacked structure; the stacked structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer stacked in sequence; the second epitaxial layer includes a wide-bandgap semiconductor material and has a target lattice;

[0077] Step S312: Form an emitter region in the third epitaxial layer;

[0078] Step S314: Form a first gate, a second gate, and a cathode located between the first gate and the second gate on the side of the third epitaxial layer facing away from the first epitaxial layer, and the cathode is electrically connected to the emitter region;

[0079] Step S316: Form an anode on the side of the first epitaxial layer facing away from the second epitaxial layer.

[0080] Exemplarily, please continue to refer to Figure 2By setting a stacked structure including a first epitaxial layer, a second epitaxial layer and a third epitaxial layer stacked in sequence, the first epitaxial layer and the third epitaxial layer have the same conductivity type and are opposite to the conductivity type of the second epitaxial layer, the second epitaxial layer includes a wide bandgap semiconductor material and has a target lattice, and a drift region can be formed in the second epitaxial layer. As a typical representative of wide bandgap semiconductors, silicon carbide has a breakdown field strength that is 10 times that of silicon material. The thickness of a chip with the same voltage resistance can be 1 / 10 of that of a silicon chip. Therefore, using silicon carbide material to form an N-drift region can effectively reduce the chip thickness and reduce the process difficulty. A heterojunction gate-commutated thyristor is formed by forming a first gate, a cathode, and a second gate on a side of the third epitaxial layer away from the first epitaxial layer, and forming an anode on a side of the first epitaxial layer away from the third epitaxial layer, and the third epitaxial layer includes an emitter region located between the first gate and the second gate and electrically connected to the cathode. Since the second epitaxial layer including silicon carbide can effectively reduce the thickness of the stacked structure, improve the withstand voltage level of the heterojunction gate-commutated thyristor, and reduce the conduction loss of the heterojunction gate-commutated thyristor, this embodiment can effectively reduce the thickness, volume and processing difficulty of the gate-commutated thyristor while improving the electrical performance and reliability of the gate-commutated thyristor.

[0081] Please refer to Figures 2 - 4b In step S310, a stacked structure 10 is provided, comprising:

[0082] Step S3111: providing a substrate 111.

[0083] For example, the substrate 111 may be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 111 may be a single-layer structure or a multi-layer structure. For example, the substrate 111 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 111 may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 111 should not limit the scope of protection of the present disclosure. P-type ions may be implanted into the substrate 111 using an ion implantation process to form a first type doped well region (not shown), and the P-type ions may include but are not limited to any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions or indium (In) ions, etc. In some other embodiments, an ion implantation process may be used to implant N-type ions into the substrate 111 . The N-type ions may include, but are not limited to, any one or more of phosphorus ions, arsenic ions, or antimony ions.

[0084] Step S3112 : forming a second epitaxial layer 102 on the substrate 111 .

[0085] For example, the substrate 111 may include an N-type 4H—SiC substrate, and an epitaxial doping process may be used to form the second epitaxial layer 102 on the substrate 111 . The second epitaxial layer 102 may include an N-type drift region.

[0086] Step S3114 : forming a third epitaxial layer 103 on a surface of the second epitaxial layer 102 facing away from the substrate 111 .

[0087] For example, an epitaxial doping process may be used to form the third epitaxial layer 103 on a surface of the second epitaxial layer 102 facing away from the substrate 111 . The third epitaxial layer 103 may include a P-type base region.

[0088] Step S3115: removing the substrate 111.

[0089] By way of example, the substrate 111 may be removed using a laser lift-off process.

[0090] Step S3116 : forming a first epitaxial layer 101 on a surface of the second epitaxial layer 102 away from the third epitaxial layer 103 .

[0091] For example, an epitaxial doping process may be used to form the first epitaxial layer 101 on the surface of the second epitaxial layer 102 away from the third epitaxial layer 103. The first epitaxial layer 101 may include a P-type base region. A heterojunction may be formed using the P-type base region, the N-type drift region, and the P-type base region.

[0092] As an example, by forming a silicon carbide drift region in the second epitaxial layer 102, not only can the chip thickness be effectively reduced and the process difficulty be lowered, but also the probability and / or number of defective positions can be reduced, and the probability of lattice mismatch can be reduced.

[0093] Please refer to Figure 2 , Figure 3 , Figure 5a , Figure 5b and Figure 4b In step S310, a stacked structure 10 is provided, comprising:

[0094] Step S3111: providing a substrate 111.

[0095] By way of example, the substrate 111 may include an N-type 4H—SiC substrate.

[0096] Step S3112 : forming a second epitaxial layer 102 on the substrate 111 .

[0097] By way of example, the second epitaxial layer 102 includes a first surface close to the substrate 111 and a second surface facing away from the substrate 111. The second epitaxial layer 102 may include an N-type drift region.

[0098] Step S3115: Remove the substrate 111.

[0099] Exemplarily, the substrate 111 can be removed by a laser lift-off process to obtain the second epitaxial layer 102 as shown in Figure 5a .

[0100] Step S3116’: Form a first epitaxial layer 101 on the first surface of the second epitaxial layer 102, and form a third epitaxial layer 103 on the second surface of the second epitaxial layer 102.

[0101] Exemplarily, a single-sided epitaxial growth process can be used to form the first epitaxial layer 101 on the first surface of the second epitaxial layer 102 and the third epitaxial layer 103 on the second surface of the second epitaxial layer 102, respectively.

[0102] Exemplarily, a double-sided epitaxial growth process can be used to simultaneously form the first epitaxial layer 101 on the first surface of the second epitaxial layer 102 and the third epitaxial layer 103 on the second surface of the second epitaxial layer 102.

[0103] Please refer to Figures 6 - 8 , in step S312, forming the emitter region 104 in the third epitaxial layer 103 includes:

[0104] Step S3121: Form an initial doping layer 2011 on the surface of the third epitaxial layer 103 facing away from the second epitaxial layer 102.

[0105] Exemplarily, an epitaxial doping process can be used to form the initial doping layer 2011 on the surface of the third epitaxial layer 103 facing away from the second epitaxial layer 102. Alternatively, after epitaxially growing a film layer material, an ion implantation process can be performed on the film layer material to form the initial doping layer 2011. The initial doping layer 2011 can be an N-type doping layer.

[0106] Step S3122: The initial doping layer 2011 includes a target region for defining the shape and position of the emitter region. Etch the initial doping layer 2011 and the third epitaxial layer 103 outside the target region to obtain a boss 2012, and the initial doping layer remaining on the top surface of the boss 2012 is used to form an intermediate doping layer 2011’.

[0107] Exemplarily, a patterned photoresist layer (not shown) can be formed on the surface of the initial doping layer 2011 facing away from the second epitaxial layer 102. The patterned photoresist layer covers the target region and exposes the initial doping layer 2011 outside the target region. Then, using the patterned photoresist layer as a mask, dry-etch the initial doping layer 2011 and the third epitaxial layer 103 outside the target region to obtain the boss 2012 and the intermediate doping layer 2011’.

[0108] Step S3123: The intermediate doped layer 2011’ can be treated at a preset temperature to form the emitter region 104.

[0109] Exemplarily, please continue to refer to Figure 7 , the intermediate doped layer 2011’ and the boss 2012 can be heated at a temperature of 950°C - 1250°C to intensify the thermal motion of atoms in the intermediate doped layer 2011’ and the boss 2012, so that some atoms in the boss 2012 obtain high enough energy to leave the lattice positions and leave vacancies, and the impurity atoms in the intermediate doped layer 2011’ can enter and occupy these vacancies, and thus enter the boss 2012 to form the emitter region 104.

[0110] Exemplarily, please continue to refer to Figure 8 , the temperature for heat-treating the intermediate doped layer 2011’ and the boss 2012 can be 950°C, 1000°C, 1050°C, 1100°C, 1150°C or 1250°C, etc.

[0111] Exemplarily, please continue to refer to Figure 8 , the outer surface of the emitter region 104 is a rounded rear arc surface to avoid sharp-corner discharge phenomenon.

[0112] Exemplarily, please continue to refer to Figure 8 , the dimension of the emitter region 104 along the first direction (such as the ox direction) gradually decreases along the direction away from the second epitaxial layer 102, which is convenient for forming the emitter region 104 with a gradually increasing dimension along the direction close to the second epitaxial layer 102, thereby increasing the contact area between the emitter region 104 and the third epitaxial layer 103.

[0113] Please refer to Figures 9 - 10 , after forming the emitter region 104 in the third epitaxial layer 103 in step S312, it further includes:

[0114] Step S313: Form a dielectric layer 50, and the dielectric layer 50 covers the top surface of the third epitaxial layer 103 between the first gate 401 and the second gate 402, and the outer surface of the emitter region 104.

[0115] Exemplarily, the dielectric layer 50 includes an opening 202 exposing a part of the top surface of the emitter region 104, the cathode 30 is in ohmic contact with the top surface of the emitter region 104 exposed by the opening, and the dielectric layer 50 also circumferentially covers at least part of the side wall of the cathode 30.

[0116] Exemplarily, a dielectric material layer (not shown) covering the outer surface of the emission region 104 and the exposed top surface of the third epitaxial layer 103 can be formed by a deposition process. Then, a photolithography and etching process can be used to remove a part of the dielectric material layer to obtain the dielectric layer 50. The dielectric layer 50 exposes a part of the top surface of the emission region 104, the top surface of the third epitaxial layer 103 in the first gate region (not shown), and the top surface of the third epitaxial layer 103 in the second gate region (not shown). Then, the first gate 401 is formed in the first gate region, and the second gate 402 is formed in the second gate region. The deposition process can include, but is not limited to, one or more of processes such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, Plasma Enhanced Deposition process, and Spin-on Dielectric (SOD). The etching process can include, but is not limited to, one or more of Reactive Ion Etching (RIE), Inductively Coupled Plasma Etching (ICP), or High Density Plasma Etching (HDP).

[0117] Please refer to Figures 9 - 10 , the cathode 30 is formed in the opening 202, and the cathode 30 is ohmically connected to the emission region 104.

[0118] Please refer to Figure 11 , the anode 20 is formed on the surface of the first epitaxial layer 101 facing away from the second epitaxial layer 102.

[0119] Exemplarily, the anode 20 can be formed on the surface of the first epitaxial layer 101 facing away from the second epitaxial layer 102 by a deposition process.

[0120] Please continue to refer to Figure 1 , a protective layer 105 is formed. The protective layer 105 covers the top surfaces of the first gate 401, the second gate 402, and the outer surface of the dielectric layer 50, and circumferentially surrounds the cathode 30, increasing the insulation between the emission region 104 and the first gate 401 and the second gate 402, and using the protective layer 105 to protect the first gate 401, the second gate 402, and the cathode 30, preventing the first gate 401, the second gate 402, and the cathode 30 from being oxidized or contaminated by external dust or particles, etc., thereby improving the reliability of the gate turn-off thyristor and increasing its service life.

[0121] Exemplarily, the protective layer can be a Polyimide Film (PI).

[0122] Exemplarily, please continue to refer to Figure 1The material of any one or more of the first gate 401, the second gate 402, the anode 20, and the cathode 30 includes one or more of cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanide TaTi, tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0123] Exemplarily, please continue to refer to Figure 1 The material of the dielectric layer 50 may include silicon oxide and / or silicon oxynitride.

[0124] It should be understood that although Figure 2 the steps in the flowchart of Figure 2 are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover,

[0125] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to the present disclosure.

[0126] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0127] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0128] The above embodiments only represent several implementation manners of the present disclosure. Their descriptions are relatively specific and detailed, but they should not be construed as a limitation to the scope of the disclosed patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent shall be subject to the appended claims.

Claims

1. A gate-commutated thyristor, characterized in that: At least one functional unit thereof includes a stacked structure, a first gate electrode, a cathode electrode, a second gate electrode, which are located on a first side of the stacked structure and are sequentially distributed along a first direction, and an anode electrode, which is located on a second side of the stacked structure; the first side and the second side are two sides of the stacked structure that are away from each other along a second direction; the second direction intersects with the first direction; The stacked structure comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer sequentially stacked along the second direction; The third epitaxial layer includes an emitter region located between the first gate electrode and the second gate electrode and electrically connected to the cathode; the second epitaxial layer includes a wide bandgap semiconductor material and has a target lattice; Among them, the first epitaxial layer and the third epitaxial layer have the same conductivity type; the second epitaxial layer and the emitter region have the same conductivity type, and are opposite to the conductivity type of the first epitaxial layer; the second epitaxial layer is used to form a heterojunction with the third epitaxial layer, and the second epitaxial layer is also used to form a heterojunction with the first epitaxial layer.

2. The gate-commutated thyristor according to claim 1, characterized in that: The top surface of the emitter region is higher than the top surfaces of the first gate electrode and the second gate electrode; A bottom surface of the emitter region is lower than a top surface of the third epitaxial layer.

3. The gate-commutated thyristor according to claim 2, characterized in that: Also includes: A dielectric layer covering a top surface of the third epitaxial layer between the first gate electrode and the second gate electrode, and an outer surface of the emitter region; The dielectric layer includes an opening exposing a portion of the top surface of the emitter region, the cathode is in ohmic contact with the top surface of the emitter region exposed by the opening, and the dielectric layer also circumferentially covers at least a portion of the side wall of the cathode.

4. The gate-commutated thyristor according to claim 3, characterized in that: Also includes: The protection layer covers the top surface of the first gate, the top surface of the second gate, and the outer surface of the dielectric layer, and circumferentially surrounds the cathode.

5. The gate-commutated thyristor according to claim 4, characterized in that: The top surface of the cathode is higher than the top surface of the protection layer.

6. The gate-commutated thyristor according to any one of claims 1 to 5, characterized in that: The crystal type of silicon carbide in the second epitaxial layer includes 4H type, 3C type, 6H type or a combination thereof.

7. The gate-commutated thyristor according to any one of claims 1 to 5, characterized in that: The first epitaxial layer is of P type, and the second epitaxial layer is of N type; or The first epitaxial layer is of N type, and the second epitaxial layer is of P type.

8. An electronic device, characterized in that: include: A gate-commutated thyristor as claimed in any one of claims 1 to 7.

9. A method for preparing a gate-commutated thyristor, characterized in that: include: A stacked structure is provided; the stacked structure comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer stacked in sequence; the second epitaxial layer comprises a wide bandgap semiconductor material and has a target lattice; the second epitaxial layer is used to form a heterojunction with the third epitaxial layer, and the second epitaxial layer is also used to form a heterojunction with the first epitaxial layer; forming an emitter region in the third epitaxial layer; Forming a first gate electrode, a second gate electrode, and a cathode located between the first gate electrode and the second gate electrode on a side of the third epitaxial layer away from the first epitaxial layer, wherein the cathode is electrically connected to the emitter region; An anode is formed on a side of the first epitaxial layer facing away from the second epitaxial layer.

10. The method for preparing a gate-commutated thyristor according to claim 9, characterized in that: The laminated structure provided comprises: providing a substrate; forming the second epitaxial layer on the substrate; forming a third epitaxial layer on a surface of the second epitaxial layer facing away from the substrate; removing the substrate; forming the first epitaxial layer on a surface of the second epitaxial layer facing away from the third epitaxial layer; or providing a substrate; forming the second epitaxial layer on the substrate; the second epitaxial layer comprises a first surface close to the substrate and a second surface away from the substrate; removing the substrate; A first epitaxial layer is formed on the first surface of the second epitaxial layer, and a third epitaxial layer is formed on the second surface of the second epitaxial layer.

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