A low-distortion rail-to-rail operational amplifier and operational amplifier circuit

Abstract

This invention relates to the field of operational amplifier technology, and in particular to a low-distortion rail-to-rail operational amplifier and its circuit. The operational amplifier circuit includes an output stage circuit, which comprises a linearization auxiliary circuit and a driver circuit. The linearization auxiliary circuit includes a first auxiliary circuit, a second auxiliary circuit, a third auxiliary circuit, and a fourth auxiliary circuit, each composed of PNP transistors, NPN transistors, and resistors. The driver circuit includes a first driver circuit, a second driver circuit, a third driver circuit, and a fourth driver circuit, each composed of PNP transistors and resistors. The active devices in this design all use bipolar junction transistors, and the circuit is highly symmetrical, structurally eliminating nonlinear distortion in the output stage, thereby improving the linearity of the amplifier circuit and reducing distortion.

Description

Technical Field

[0001] This invention relates to the field of operational amplifier technology, and in particular to a low-distortion rail-to-rail operational amplifier and operational amplifier circuit. Background Technology

[0002] Operational amplifiers are a crucial component of analog electronics, performing operations and amplification of analog signals. Linearity is a key performance indicator for amplifier circuits, describing their ability to faithfully reproduce the input signal. In traditional analog circuit design, improving linearity typically involves various techniques to ensure the output signal accurately reflects changes in the input signal. While numerous methods exist for improving linearity, each has its advantages and limitations.

[0003] Emitter degradation resistors are a common technique for improving linearity, especially in common-emitter amplifier circuits. This method creates a negative feedback mechanism by introducing a resistor at the emitter of the transistor, thereby stabilizing the amplification factor and improving linearity. However, the improvement in linearity is limited because it cannot fundamentally eliminate the source of nonlinear distortion. Furthermore, the introduction of emitter degradation resistors can lead to other electrical parameter problems, such as reduced amplifier gain and increased noise.

[0004] With the development of electronic technology, the requirements for the linearity of operational amplifiers are becoming increasingly stringent, especially in high-precision and high-fidelity systems. Traditional methods for improving linearity can no longer meet the needs of modern electronic devices. Therefore, there is an urgent need to provide a low-distortion rail-to-rail operational amplifier circuit to improve the linearity of the amplifier circuit and reduce distortion. Summary of the Invention

[0005] This invention provides a low-distortion rail-to-rail operational amplifier and operational amplifier circuit, which can improve the linearity of the amplifier circuit and reduce distortion.

[0006] The basic solution provided by this invention is as follows:

[0007] A low-distortion rail-to-rail operational amplifier circuit includes a positive power supply pin, a negative power supply pin, a positive output pin, and an output stage circuit.

[0008] The output stage circuit includes a linearization auxiliary circuit and a driving circuit; the linearization auxiliary circuit includes a first auxiliary circuit, a second auxiliary circuit, a third auxiliary circuit, and a fourth auxiliary circuit; the driving circuit includes a first driving circuit and a second driving circuit.

[0009] The first driving circuit includes a resistor R3 and a PNP transistor P5. The emitter of the PNP transistor P5 is connected to the resistor R3, and the collector is connected to the positive output pin.

[0010] The second driving circuit includes a resistor R7 and an NPN transistor N5. The emitter of the NPN transistor N5 is connected to the resistor R7, and the collector is connected to the positive output pin.

[0011] The first auxiliary circuit includes an NPN transistor N1, a resistor R1, and a PNP transistor P3; the collector of the NPN transistor N1 is connected to the positive power supply pin, and the emitter is connected to the base of the PNP transistor P3; one end of the resistor R1 is connected to the positive power supply pin, and the other end is connected to the emitter of the PNP transistor P3.

[0012] The fourth auxiliary circuit includes an NPN transistor N4, a resistor R6, and a PNP transistor P2; the collector of the PNP transistor P2 is connected to both the negative power supply pin and the resistor R7, and the emitter is connected to both the base of the NPN transistor N4 and the base of the NPN transistor N5; one end of the resistor R6 is connected to the negative power supply pin, and the other end is connected to the emitter of the NPN transistor N4;

[0013] The emitter of the NPN transistor N1 is connected to the collector of the NPN transistor N4; the collector of the PNP transistor P3 is connected to the emitter of the PNP transistor P2.

[0014] The third auxiliary circuit includes an NPN transistor N3, a resistor R5, and a PNP transistor P1; the collector of the PNP transistor P1 is connected to the negative power supply pin, and the emitter is connected to the base of the NPN transistor N3; one end of the resistor R5 is connected to the negative power supply pin, and the other end is connected to the emitter of the NPN transistor N3.

[0015] The second auxiliary circuit includes an NPN transistor N2, a resistor R2, and a PNP transistor P4; the collector of the NPN transistor N2 is connected to both the positive power supply pin and the resistor R3, and the emitter is connected to both the base of the PNP transistor P4 and the base of the PNP transistor P5; one end of the resistor R2 is connected to the positive power supply pin, and the other end is connected to the emitter of the PNP transistor P4;

[0016] The emitter of the PNP transistor P1 is connected to the collector of the PNP transistor P4; the collector of the NPN transistor N3 is connected to the emitter of the NPN transistor N2.

[0017] The principle and advantages of this invention are as follows: The output stage circuit structure in this solution includes a linearization auxiliary circuit and a driving circuit. Each auxiliary circuit in the linearization auxiliary circuit is composed of an emitter follower and a current source (NPN transistors constitute the emitter follower; resistors and PNP transistors constitute the current source), achieving the effect of current synchronization. In addition, all active devices use bipolar junction transistors, and the circuit is highly symmetrical, which eliminates the nonlinear distortion of the output stage from the structure, thereby improving the linearity of the amplifier circuit and reducing distortion.

[0018] Furthermore, it also includes a negative output pin, and the driving circuit further includes a third driving circuit and a fourth driving circuit;

[0019] The third driving circuit includes a resistor R4 and a PNP transistor P6; one end of the resistor R4 is connected to the resistor R3, and the other end is connected to the emitter of the PNP transistor P6; the base of the PNP transistor P6 is connected to the emitter of the NPN transistor N1, and the collector is connected to the negative output pin.

[0020] The fourth driving circuit includes a resistor R8 and an NPN transistor N6; one end of the resistor R8 is connected to a resistor R7, and the other end is connected to the emitter of the NPN transistor N6; the base of the NPN transistor N6 is connected to the emitter of the PNP transistor P1, and the collector is connected to the negative output pin.

[0021] Beneficial effects: The output stage circuit can be selected for single-ended or dual-ended output as needed. When resistors R4 and R8, NPN transistor N6, and PNP transistor P6 are included, and the negative output pin is retained, it is a dual-ended output; when resistors R4 and R8, NPN transistor N6, and PNP transistor P6 are removed, and the negative output pin is also eliminated, it is a single-ended output.

[0022] Furthermore, the resistance values ​​of resistors R1, R2, R5, and R6 are equal; the resistance values ​​of resistors R3, R4, R7, and R8 are also equal.

[0023] Beneficial effect: Makes the output stage circuit highly symmetrical, so that the current in each part of the output stage circuit always maintains a proportional relationship.

[0024] Furthermore, the emitter regions of NPN transistors N1, NPN transistor N2, NPN transistor N3, and NPN transistor N4 are all equal in area; the emitter regions of NPN transistors N5 and NPN transistor N6 are also equal in area.

[0025] The emitter regions of PNP transistors P1, P2, P3, and P4 are all equal in area; the emitter regions of PNP transistors P5 and P6 are also equal in area.

[0026] Beneficial effect: Makes the output stage circuit highly symmetrical, so that the current in each part of the output stage circuit always maintains a proportional relationship.

[0027] Furthermore, the area S of the emitter region in the NPN transistor N1 N1 The area S of the emitter region in NPN transistor N6 N6 The relationship between the resistance value 'a' of resistor R8 and the resistance value 'b' of resistor R6 is as follows:

[0028]

[0029] The area S of the emitter region in PNP transistor P1 P1 The area S of the emitter region in PNP transistor P6 P6 The relationship between the resistance value 'a' of resistor R4 and the resistance value 'b' of resistor R2 is as follows:

[0030]

[0031] Beneficial effects: The output stage circuit in this design ensures that the transconductance remains constant regardless of changes in the output current, effectively improving linearity and reducing harmonic distortion. If ideal components are used, the output stage circuit in this design will not introduce any distortion.

[0032] The second basic solution provided by this invention is an operational amplifier that uses the aforementioned low-distortion rail-to-rail operational amplifier circuit. Attached Figure Description

[0033] Figure 1 This is a circuit diagram of a traditional operational amplifier.

[0034] Figure 2 Circuit diagram for adding an emitter degradation resistor to a traditional operational amplifier.

[0035] Figure 3 This is a circuit diagram of the output stage circuit in a low-distortion rail-to-rail operational amplifier circuit according to the present invention.

[0036] Figure 4 This is a schematic diagram of the circuit structure of a low-distortion rail-to-rail operational amplifier circuit of the present invention, in which the input stage circuit uses bipolar junction transistors as differential pairs.

[0037] Figure 5This is a schematic diagram of the circuit structure of a low-distortion rail-to-rail operational amplifier circuit of the present invention, in which the input stage circuit uses an enhancement-type pseudo-junction field-effect transistor as a differential pair.

[0038] Figure 6 This is a schematic diagram of the circuit structure of a low-distortion rail-to-rail operational amplifier circuit of the present invention, in which the input stage circuit uses bipolar transistors as differential pairs. Detailed Implementation

[0039] The following detailed description illustrates the specific implementation method:

[0040] The reference numerals in the accompanying drawings include: output stage circuit 100, first auxiliary circuit 101, second auxiliary circuit 102, third auxiliary circuit 103, and fourth auxiliary circuit 104.

[0041] Example 1:

[0042] like Figure 1 As shown, a traditional operational amplifier consists of PNP transistors P1′ and P2′, NPN transistors N1′, N2′, and N3′ forming the input stage, and PNP transistor P3′ and NPN transistor N4′ forming the output stage. R0′ is the external load resistor, VCC is the positive power supply pin, and VEE is the negative power supply pin. In traditional amplifier circuits, both the input and output stages introduce distortion.

[0043] The NPN transistor N4' is a current mirror; its collector current is a fixed current of magnitude I. N4′C .

[0044] In this embodiment, I PXY P indicates a PNP type transistor. X The current at port Y in (X = 1, 2, 3…n); if Y = C, it represents the current at the collector port; if Y = B, it represents the current at the base port; if Y = E, it represents the current at the emitter port. NXY N indicates N in an NPN transistor X The current at port Y in (X = 1, 2, 3…n); if Y = C, it represents the current at the collector port; if Y = B, it represents the current at the base port; if Y = E, it represents the current at the emitter port.

[0045] like Figure 1 As shown, the collector voltage of the PNP transistor P3' is the output voltage of the operational amplifier, with a magnitude of V. P3′C .

[0046] In this embodiment, V PXY P indicates a PNP type transistor. XThe voltage at port Y in (X = 1, 2, 3…n); if Y = C, it represents the voltage at the collector port; if Y = B, it represents the voltage at the base port; if Y = E, it represents the voltage at the emitter port. V NXY N indicates N in an NPN transistor X The voltage at port Y in (X = 1, 2, 3…n); if Y = C, it represents the voltage at the collector port; if Y = B, it represents the voltage at the base port; if Y = E, it represents the voltage at the emitter port.

[0047] The current across the external load resistor R0′ is as follows:

[0048]

[0049] In this embodiment, I RX Indicates that current flows through resistor R X The current (X = 1, 2, 3...n).

[0050] Due to the negative feedback of the operational amplifier, when the input voltage V of the output stage... IN When determined, the collector current of the PNP transistor P3′ is as follows:

[0051]

[0052] In this embodiment, V BEPX P indicates a PNP type transistor. X The BE junction (emitter junction) voltage (V) of (X = 1, 2, 3…n) BENX N indicates N in an NPN transistor X The BE junction voltage (X = 1, 2, 3…n); I SPX P indicates a PNP type transistor. X The reverse saturation current of the collector junction of (X = 1, 2, 3…n), I SNX N indicates N in an NPN transistor X The reverse saturation current of the collector junction of (X = 1, 2, 3…n); V T This is the thermal voltage, approximately 26mV at room temperature. In this embodiment, V is determined to be... T =26mV.

[0053] like Figure 1 As shown, when the input voltage V of the output stage IN Introducing a small signal change ΔV IN At that time, there were:

[0054]

[0055] Therefore I P3′C The change is:

[0056]

[0057] like Figure 1 As shown, the transconductance of the output stage is:

[0058]

[0059] In the formula, G is the transconductance of the output stage.

[0060] like Figure 1 As shown, because:

[0061] I P3′C =I N4′C +I R0′

[0062] Therefore, the transconductance of the output stage is:

[0063]

[0064] Therefore, the transconductance G of the output stage varies with the output voltage V. P3′C Changes. With R0′ as 1kΩ, the static bias current of P3′ is I... N4′C Taking 1mA as an example, when the output voltage is 0V, the output stage transconductance G is about 38.5mS; when the output voltage is 1V, the output stage transconductance G is about 76.9mS, which is 100% higher than when the output voltage is 0.

[0065] For the aforementioned traditional operational amplifiers, linearity is typically improved by increasing the emitter degradation resistor. For example... Figure 2 As shown, the input stage consists of PNP transistors P1′ and P2′, NPN transistors N1′, N2′ and N3′, and resistors R1′, R2′, R4′, R5′ and R6′. The output stage consists of PNP transistor P3′, NPN transistor N4′, and resistors R3′ and R7′. R0′ is an external load resistor, VCC is the positive power supply pin, and VEE is the negative power supply pin.

[0066] like Figure 2 As shown, ignoring the base current of the PNP transistor P3', we have I P3′C =I R3′ When the input voltage V of the output stage IN Introducing a small signal change ΔV IN At that time, there were:

[0067]

[0068] Therefore I R3′ The change is:

[0069]

[0070] like Figure 2 As shown, the output stage transconductance G is:

[0071]

[0072] like Figure 2 As shown, because:

[0073] I R3′ =I P3′C =I N4′C +I R0′

[0074] Therefore, the transconductance of the output stage is:

[0075]

[0076] like Figure 2 As shown, the output stage transconductance G varies with the transconductance gP3′ of P3′, while the transconductance gP3′ of P3′ varies with the output voltage V. P3′C Changes. With R0′ as 1kΩ, the static bias current of P3′ is I... N4′C Taking 1mA and R3′ as an example, when the output voltage is 0V, the output stage transconductance G is about 7.94mS; when the output voltage is 1V, the output stage transconductance G is about 8.85mS. The output stage transconductance G increases by 12% compared to when the output voltage is 0.

[0077] Therefore, it can be seen that adding a 100Ω degradation resistor R3′ reduces the output positive voltage swing by 200mV when the output current is 1mA. However, since adding the emitter degradation resistor cannot fundamentally eliminate the source of nonlinear distortion, this method has a very limited effect on improving linearity.

[0078] To address this, this solution provides a low-distortion rail-to-rail operational amplifier circuit. All active devices in this circuit are bipolar junction transistors, which can structurally eliminate nonlinear distortion in the output stage, thereby improving the linearity of the amplifier circuit and reducing distortion.

[0079] like Figure 3As shown, a low-distortion rail-to-rail operational amplifier circuit includes a positive power supply pin, a negative power supply pin, a positive output pin, a negative output pin, and an output stage circuit 100. The output stage circuit 100 is entirely composed of bipolar junction transistors and resistors, suitable for bipolar, BICMOS, and BCD (double-diffused metal-oxide-semiconductor) processes. It employs transistor BE junction voltage increment compensation technology to structurally eliminate nonlinear distortion in the output stage; and uses emitter follower current synchronization technology to ensure that the emitter follower current and output current always maintain a proportional relationship. In principle, the output stage transconductance in this design does not change with the output voltage, fundamentally improving the linearity of the output stage and reducing distortion. The specific circuit results and principles are as follows:

[0080] The output stage circuit 100 includes a linearization auxiliary circuit and a driving circuit; the linearization auxiliary circuit includes a first auxiliary circuit 101, a second auxiliary circuit 102, a third auxiliary circuit 103 and a fourth auxiliary circuit 104; the driving circuit includes a first driving circuit, a second driving circuit, a third driving circuit and a fourth driving circuit.

[0081] The first driving circuit includes a resistor R3 and a PNP transistor P5. The emitter of the PNP transistor P5 is connected to the resistor R3, and the collector is connected to the positive output pin, serving as the positive output voltage OUT+ of the output stage circuit 100.

[0082] The second driving circuit includes a resistor R7 and an NPN transistor N5. The emitter of the NPN transistor N5 is connected to the resistor R7, and the collector is connected to the positive output pin.

[0083] The first auxiliary circuit 101 includes an NPN transistor N1, a resistor R1, and a PNP transistor P3; the collector of the NPN transistor N1 is connected to the positive power supply pin, and the emitter is connected to the base of the PNP transistor P3; one end of the resistor R1 is connected to the positive power supply pin, and the other end is connected to the emitter of the PNP transistor P3.

[0084] The fourth auxiliary circuit 104 includes an NPN transistor N4, a resistor R6, and a PNP transistor P2. The collector of the PNP transistor P2 is connected to both the negative power supply pin and the resistor R7, and the emitter is connected to both the base of the NPN transistor N4 and the base of the NPN transistor N5. One end of the resistor R6 is connected to the negative power supply pin, and the other end is connected to the emitter of the NPN transistor N4.

[0085] The emitter of the NPN transistor N1 is connected to the collector of the NPN transistor N4; the collector of the PNP transistor P3 is connected to the emitter of the PNP transistor P2.

[0086] The third auxiliary circuit 103 includes an NPN transistor N3, a resistor R5, and a PNP transistor P1; the collector of the PNP transistor P1 is connected to the negative power supply pin, and the emitter is connected to the base of the NPN transistor N3; one end of the resistor R5 is connected to the negative power supply pin, and the other end is connected to the emitter of the NPN transistor N3.

[0087] The second auxiliary circuit 102 includes an NPN transistor N2, a resistor R2, and a PNP transistor P4; the collector of the NPN transistor N2 is connected to both the positive power supply pin and the resistor R3, and the emitter is connected to both the base of the PNP transistor P4 and the base of the PNP transistor P5; one end of the resistor R2 is connected to the positive power supply pin, and the other end is connected to the emitter of the PNP transistor P4.

[0088] The emitter of the PNP transistor P1 is connected to the collector of the PNP transistor P4; the collector of the NPN transistor N3 is connected to the emitter of the NPN transistor N2.

[0089] The third driving circuit includes a resistor R4 and a PNP transistor P6; one end of the resistor R4 is connected to the resistor R3, and the other end is connected to the emitter of the PNP transistor P6; the base of the PNP transistor P6 is connected to the emitter of the NPN transistor N1, and the collector is connected to the negative output pin, serving as the negative output voltage OUT- of the output stage circuit 100.

[0090] The fourth driving circuit includes a resistor R8 and an NPN transistor N6; one end of the resistor R8 is connected to a resistor R7, and the other end is connected to the emitter of the NPN transistor N6; the base of the NPN transistor N6 is connected to the emitter of the PNP transistor P1, and the collector is connected to the negative output pin.

[0091] The output stage circuit 100 can be configured for single-ended or dual-ended output depending on requirements. It includes resistor R4, resistor R8, NPN transistor N6, and PNP transistor P6, and retains the negative output pin for dual-ended output; it removes resistor R4, resistor R8, NPN transistor N6, and PNP transistor P6, and also eliminates the negative output pin for single-ended output. In this embodiment, a dual-ended output circuit structure is used.

[0092] like Figure 3 As shown, V N1B V N2B V P1B V P2B The input voltage signals for the output stage circuit 100 have the following requirements when used: V N1B V N2BThe DC bias voltages are exactly the same, V P1B V P2B The DC bias voltages are exactly equal; V N1B V P1B The AC signals are of the same amplitude, frequency, and phase, V N2B V P2B The AC signals are of the same amplitude, frequency, and phase; V N1B V P1B AC signal and V N2B V P2B The AC signals are of the same amplitude, same frequency, and opposite phase.

[0093] In this circuit, resistors R1, R2, R5, and R6 have equal resistance values; resistors R3, R4, R7, and R8 have equal resistance values. The emitter regions of NPN transistors N1, NPN transistors N2, NPN transistors N3, and NPN transistors N4 have equal areas; the emitter regions of NPN transistors N5 and NPN transistors N6 have equal areas; the emitter regions of PNP transistors P1, PNP transistors P2, PNP transistors P3, and PNP transistors P4 have equal areas; and the emitter regions of PNP transistors P5 and PNP transistors P6 have equal areas. This ensures complete circuit symmetry.

[0094] The area S of the emitter region in NPN transistor N1 N1 The area S of the emitter region in NPN transistor N6 N6 The relationship between the resistance value 'a' of resistor R8 and the resistance value 'b' of resistor R6 is as follows:

[0095]

[0096] The area S of the emitter region in PNP transistor P1 P1 The area S of the emitter region in PNP transistor P6 P6 The relationship between the resistance value 'a' of resistor R4 and the resistance value 'b' of resistor R2 is as follows:

[0097]

[0098] In this embodiment, S NX N indicates N in an NPN transistor X The area of ​​the emitter region in (X = 1, 2, 3…n), S PX P indicates a PNP type transistor. X The area of ​​the emitter region in (X = 1, 2, 3...n).

[0099] Since the resistance values ​​of resistors R1, R2, R5, and R6 are equal; and the resistance values ​​of resistors R3, R4, R7, and R8 are equal, the resistance value of resistors R1, R2, R5, and R6 is always 'b', and the resistance value of resistors R3, R4, R7, and R8 is always 'a'. The formula directly uses the specific numerical values ​​'a' and 'b', or uses R... X Represents resistance R X The resistance value.

[0100] Adopting such Figure 3 In the circuit structure shown, when the output current is 0 and the base current is ignored, the currents of each transistor satisfy the following relationship:

[0101] I N1C =I N2C =I N3C =I N4C =I P1C =I P2C =I P3C =I P4C

[0102] I P5C =I P6C =I N5C =I N6C

[0103] Since the circuit is perfectly symmetrical, when the output current is 0, the base current is ignored, then:

[0104]

[0105] In this formula, a is the resistance value of resistor R4, and b is the resistance value of resistor R6;

[0106] set up I N1C =I0,I P5C =I1, then:

[0107] I0=kI1

[0108] in:

[0109] I0 = I N1C =I N2C =I N3C =I N4C =I P1C =I P2C =I P3C =I P4C

[0110] I1=I P5C =I P6C =I N5C =I N6C

[0111] Therefore, the above parameter settings ensure that the current of each resistor in the output stage circuit 100 is inversely proportional to its resistance value, and that the collector current of each bipolar junction transistor of the same type is directly proportional to its emitter area. Thus, the voltage across each resistor is equal, and the BE junction voltage of each bipolar junction transistor is equal.

[0112] Since the output stage circuit 100 in this scheme is completely symmetrical, when its input voltage changes, causing changes in current at various points, the following relationship still holds:

[0113] ΔI0=kΔI1

[0114] This ensures that the current at all points remains proportional. Therefore, when the output current is 0:

[0115]

[0116]

[0117] When its input voltage changes, causing changes in current at various points:

[0118]

[0119]

[0120] like Figure 3 As shown, based on the properties of transistors:

[0121]

[0122]

[0123] When the output current is 0:

[0124]

[0125]

[0126] When the input voltage introduces a small signal change ΔV IN When, i.e., V N1B V P1B Change -0.5ΔV IN V N2B V P2B Change +0.5ΔV IN hour:

[0127]

[0128]

[0129] Therefore:

[0130]

[0131]

[0132] because:

[0133] Therefore:

[0134]

[0135] Furthermore, due to:

[0136] Therefore:

[0137]

[0138] Therefore, we can conclude that:

[0139] ΔV BEN1 =ΔV BEP6

[0140] It can be seen that no matter how large the output voltage or current is, the voltage across resistor R4 is always equal to V. N1B The change in V is -0.5ΔV IN Similarly, the voltage across resistor R8 is always equal to -0.5ΔV. IN .

[0141] Since the resistance values ​​of resistors R1, R2, R5, and R6 are equal, the output current of the negative output pin is:

[0142]

[0143] Similarly, the output current of the positive output pin is:

[0144]

[0145] When the operational amplifier has a two-terminal output, the transconductance is

[0146]

[0147] When the operational amplifier uses only the positive output pin for single-ended output, the transconductance is...

[0148]

[0149] Therefore, it can be seen that the transconductance G of the output stage circuit 100 in this scheme always remains at a fixed value, which in principle eliminates the distortion caused by the change of the BE junction voltage of the bipolar junction transistor.

[0150] If R3 has a resistance of 20Ω, the transconductance will be 50mS with single-ended output; if the output current is 1mA, the output voltage swing will decrease by 20mV. It can be seen that, in addition to the advantage in linearity, Figure 3 The circuit structure shown is relative to Figure 2 The circuit structure shown significantly improves transconductance. Furthermore, the reduction in output swing caused by R3 in this scheme is also better than that caused by… Figure 2 In the circuit structure, the reduction in output swing caused by R3 is even more slight.

[0151] The present invention also discloses an operational amplifier that employs the aforementioned low-distortion rail-to-rail operational amplifier circuit.

[0152] In summary, the output stage structure of this scheme employs emitter follower current synchronization technology to achieve a highly symmetrical circuit. This ensures that the collector current of each bipolar junction transistor (BJT) is proportional to its emitter area, and the current of each resistor is inversely proportional to its resistance value, guaranteeing that the current throughout the circuit remains proportional. Furthermore, the scheme utilizes transistor BE junction voltage increment compensation technology to structurally eliminate nonlinear distortion in the output stage. Therefore, this scheme structurally eliminates nonlinear distortion in the output stage, thereby improving the linearity of the amplifier circuit and reducing distortion.

[0153] Example 2:

[0154] The basic principle of Example 2 is the same as that of Example 1. The difference is that in Example 2, the low-distortion rail-to-rail operational amplifier circuit also includes a first input stage circuit, and the first input stage circuit uses bipolar junction transistors as differential pairs, which is a rail-to-rail operational amplifier circuit with dual-ended input and dual-ended output.

[0155] like Figure 4 The first input stage circuit structure shown includes NPN transistors N7, N8, and N9, PNP transistors P7, P8, and P9, and resistors R9 and R1. 10 R 11 R 12 R 13 R 14 R 15 R 16 R 17 R 18 The input stage of an operational amplifier circuit.

[0156] The emitter connection of NPN transistor N7 is R. 14 NPN transistor N8 is connected to resistor R. 15 Resistance R 14 R 15 Connect the collector of NPN transistor N9; connect the emitter of NPN transistor N9 to resistor R.16 The emitter connection resistor R of the PNP transistor P8 12 The emitter connection resistor R of PNP transistor P9 13 Resistance R 12 R 13 Connect the collector of PNP transistor P7; connect the emitter of PNP transistor P7 to resistor R. 11 .

[0157] V P7B V N9B All are fixed bias voltages.

[0158] The base of NPN transistor N8 is connected to the base of PNP transistor P9, serving as the positive input terminal IN+ of the operational amplifier; the base of NPN transistor N7 is connected to the base of PNP transistor P9, serving as the negative input terminal IN- of the operational amplifier.

[0159] The collector connection resistor R9 of NPN transistor N7 and the base of NPN transistor N1 serve as a positive input terminal of output stage circuit 100; the collector connection resistor R of PNP transistor P9... 18 The base of the PNP transistor P1 serves as another positive input terminal of the output stage circuit 100.

[0160] The collector connection resistor R of the NPN transistor N8 10 The base of NPN transistor N2 serves as a negative input terminal of output stage circuit 100; the collector of PNP transistor P8 is connected to resistor R. 17 The base of PNP transistor P2 serves as another negative input terminal of output stage circuit 100.

[0161] Example 3:

[0162] The basic principle of Example 3 is the same as that of Example 1. The difference is that in Example 3, the low distortion rail-to-rail operational amplifier circuit also includes a second input stage circuit, and the second input stage circuit uses a PJFET device (enhancement pseudo-junction field-effect transistor) as a differential pair.

[0163] like Figure 5 The second input stage circuit structure shown includes PJFET devices PJ1, PJ2, and NPN transistors N7, N8, N9, and N1. 10 PNP transistor P7, resistor R9, R 10 R 11 R 12 R 13 R 14 R 15 R 16 R17 The input stage of an operational amplifier circuit.

[0164] The drain of the PJFET device PJ1 is connected to the collector and base of the NPN transistor N9, as well as N... 10 The base of PJFET device PJ2 is connected to the collector and base of NPN transistor N7, and the base of N8; the source of PJFET device PJ1 is connected to R 12 The source connection of PJ2 in the PJFET device is R. 13 ;R 12 R 13 Connect the collector of PNP transistor P7; connect the emitter of PNP transistor P7 to resistor R9; connect the emitter of NPN transistor N9 to resistor R... 14 The emitter connection resistor R of NPN transistor N7 15 .

[0165] V P7B For fixed bias voltage.

[0166] The gate of PJFET device PJ1 serves as the positive input terminal IN+ in the operational amplifier circuit; the gate of PJFET device PJ2 serves as the negative input terminal IN- in the operational amplifier circuit.

[0167] NPN transistor N 10 collector connection resistor R 10 The base of NPN transistor N1 serves as a positive input terminal of output stage circuit 100; the emitter of NPN transistor N8 is connected to resistor R. 17 The base of the PNP transistor P1 serves as another positive input terminal of the output stage circuit 100.

[0168] NPN transistor N 10 emitter connection resistor R 16 The base of PNP transistor P2 serves as a negative input terminal of output stage circuit 100; the collector of NPN transistor N8 is connected to resistor R. 11 The base of the NPN transistor N2 serves as another negative input terminal of the output stage circuit 100.

[0169] Example 4:

[0170] The basic principle of Example 4 is the same as that of Example 1. The difference is that in Example 4, the low-distortion rail-to-rail operational amplifier circuit also includes a third input stage circuit, and the third input stage circuit uses bipolar transistors as differential pairs.

[0171] like Figure 6The third input stage circuit structure shown includes NPN transistors N6, N7, N8, PNP transistors P6, P7, P8, P9, and resistors R6, R7, R8, R9, R... 10 R 11 R 12 R 13 R 14 R 15 The input stage of an operational amplifier circuit.

[0172] The collector of NPN transistor N6 is connected to the collector and base of PNP transistor P6, and the base of P7; the collector of NPN transistor N7 is connected to the collector and base of PNP transistor P8, and the base of PNP transistor P9; the emitter of NPN transistor N6 is connected to resistor R. 11 The emitter connection resistor R of NPN transistor N7 12 resistance R 11 R 12 Connect the collector of NPN transistor N8; connect the emitter of NPN transistor N8 to resistor R. 13 The emitter connection resistor R7 of PNP transistor P6; the emitter connection resistor R8 of PNP transistor P8.

[0173] V P8B For fixed bias voltage.

[0174] The base of NPN transistor N6 is the positive input terminal IN+ of the operational amplifier; NPN transistor N7 is the negative input terminal IN- of the operational amplifier.

[0175] The emitter of PNP transistor P9 is connected to resistor R9 and the base of NPN transistor N1, serving as a positive input terminal of output stage circuit 100; the collector of PNP transistor P7 is connected to resistor R... 15 The base of the PNP transistor P1 serves as another positive input terminal of the output stage circuit 100.

[0176] The collector connection resistor R of the PNP transistor P9 14 The base of PNP transistor P2 serves as a negative input terminal of output stage circuit 100; the emitter of PNP transistor P7 is connected to resistor R. 10 The base of the NPN transistor N2 serves as another negative input terminal of the output stage circuit 100.

[0177] The above are merely embodiments of the present invention. Commonly known structures and characteristics are not described in detail here. Those skilled in the art are aware of all common technical knowledge in the field prior to the application date or priority date, are aware of all existing technologies in that field, and have the ability to apply conventional experimental methods prior to that date. Those skilled in the art can, under the guidance of this application, improve and implement this solution in combination with their own capabilities. Some typical known structures or methods should not be obstacles for those skilled in the art to implement this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention. These should also be considered within the scope of protection of the present invention, and will not affect the effectiveness of the implementation of the present invention or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A low-distortion rail-to-rail operational amplifier circuit, comprising a positive power supply pin, a negative power supply pin, a positive output pin, and an output stage circuit, characterized in that: The output stage circuit includes a linearization auxiliary circuit and a driving circuit; the linearization auxiliary circuit includes a first auxiliary circuit, a second auxiliary circuit, a third auxiliary circuit, and a fourth auxiliary circuit; the driving circuit includes a first driving circuit and a second driving circuit. The first driving circuit includes resistors and PNP type transistors The PNP transistor emitter and resistor Connect the collector to the positive output pin; The second driving circuit includes resistors and NPN transistor The NPN transistor emitter and resistor Connect the collector to the positive output pin; The first auxiliary circuit includes an NPN transistor. ,resistance and PNP type transistors The NPN transistor The collector is connected to the positive power supply pin, and the emitter is connected to the PNP transistor. The base connection; the resistor One end is connected to the positive power supply pin, and the other end is connected to the PNP transistor. emitter connection; The fourth auxiliary circuit includes an NPN transistor. ,resistance and PNP type transistors The PNP transistor collector and negative power supply pin and resistor Both are connected, with the emitter connected to the NPN transistor. The base and NPN transistor The bases of all resistors are connected; One end is connected to the negative power supply pin, and the other end is connected to the NPN transistor. emitter connection; The NPN transistor emitter and NPN transistor The collector connection of the PNP transistor; collector PNP transistor emitter connection; The third auxiliary circuit includes an NPN transistor. ,resistance and PNP type transistors The PNP transistor The collector is connected to the negative power supply pin, and the emitter is connected to the NPN transistor. The base connection; the resistor One end is connected to the negative power supply pin, and the other end is connected to the NPN transistor. emitter connection; The second auxiliary circuit includes an NPN transistor. ,resistance and PNP type transistors The NPN transistor The collector and positive power supply pin and resistor Both are connected, with the emitter connected to the PNP transistor. The base and PNP transistor The bases of all resistors are connected; One end is connected to the positive power supply pin, and the other end is connected to the PNP transistor. emitter connection; The PNP transistor The emitter of the PNP transistor The collector connection of the NPN transistor; collector and NPN transistor emitter connection; The input voltage signal of the output stage circuit includes , , , ,in, , The DC bias voltages are exactly the same. , The DC bias voltages are exactly the same; , The AC signals are of the same amplitude, frequency, and phase. , The AC signals are of the same amplitude, frequency, and phase; , The communication signal and , The AC signals are of the same amplitude, same frequency, and opposite phase.

2. The low-distortion rail-to-rail operational amplifier circuit according to claim 1 further includes a negative output pin, characterized in that: The driving circuit also includes a third driving circuit and a fourth driving circuit; The third driving circuit includes resistors. and PNP type transistors The resistor One end is connected to the resistor Connect the other end to the PNP transistor. The emitter connection; the PNP transistor The base of the NPN transistor The emitter is connected, and the collector is connected to the negative output pin; The fourth driving circuit includes resistors. and NPN transistor The resistor One end is connected to the resistor Connect the other end to the NPN transistor. The emitter connection; the NPN transistor The base of the PNP transistor The emitter is connected, and the collector is connected to the negative output pin.

3. The low-distortion rail-to-rail operational amplifier circuit according to claim 2, characterized in that: resistance ,resistance ,resistance and resistance The resistance values ​​are equal; ,resistance ,resistance and resistance The resistance values ​​are equal.

4. The low-distortion rail-to-rail operational amplifier circuit according to claim 3, characterized in that: NPN transistor NPN transistor NPN transistor NPN transistor The areas of the emitter regions are all equal. NPN transistor and NPN transistor The areas of the emitter regions are equal. PNP transistor PNP type transistor PNP type transistor and PNP type transistors The emitter region areas are all equal; PNP transistor and PNP type transistors The areas of the emitter regions are equal.

5. The low-distortion rail-to-rail operational amplifier circuit according to claim 4, characterized in that: NPN transistor Area of ​​the middle emitter region NPN transistor Area of ​​the middle emitter region ,resistance The resistance value a and the resistance The relationship between the resistance values ​​b is as follows: ； PNP transistor Area of ​​the middle emitter region PNP type transistor Area of ​​the middle emitter region ,resistance The resistance value a and the resistance The relationship between the resistance values ​​b is as follows: 。 6. An operational amplifier, characterized in that: The low-distortion rail-to-rail operational amplifier circuit described in any one of claims 1 to 5 is employed.

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