Gate drive circuit and display panel

Abstract

This application discloses a gate driving circuit and a display panel. The gate driving circuit includes a shift register. The Nth stage shift register includes a pull-up control module, a cascaded module, at least one inverting module, a pull-down feedback module, and a voltage control module. By connecting the pull-down feedback module and the voltage control module in series between the pull-up node of this stage and the first low potential line, the potential of the pull-up node of this stage can be pulled down when both the pull-down feedback module and the voltage control module are in the on state, and the potential of the pull-up node of this stage can be maintained and raised when both the pull-down feedback module and the voltage control module are in the off state. Thus, the high potential of the pull-up node of this stage can be maintained and raised without affecting normal operation.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a gate driving circuit and a display panel. Background Technology

[0002] Gate drive circuits typically include one or more shift registers, each with a pull-up node, which is the key node controlling the output of the shift register.

[0003] The stability of the pull-up node's potential determines the stability of the shift register's output signal. However, due to various reasons, some transistors still exhibit leakage current even when they are off, resulting in poor stability of the pull-up node's potential. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel to alleviate the technical problem of potential drop when the pull-up node is at a high potential.

[0005] In a first aspect, this application provides a gate driving circuit, which includes a shift register. The Nth stage shift register includes a pull-up control module, a cascade module, at least one inverting module, a pull-down feedback module, and a voltage control module. The pull-up control module is connected to the pull-up node of its current stage. The cascade module is connected to the pull-up node of its current stage and outputs an Nth stage cascade signal based on the potential of the pull-up node, where N is a positive integer. The input terminal of each inverting module is connected to the pull-up node of its current stage, and the output terminal of each inverting module is connected to the corresponding pull-down node of its current stage. The pull-down feedback module is connected in series between the pull-up node of its current stage and a first low-potential line. The control terminal of the pull-down feedback module is connected to the (N+M)th stage cascade signal, where M is an integer greater than or equal to 1. The voltage control module is connected in series between the pull-down feedback module and the pull-up node of its current stage or between the pull-down feedback module and the first low-potential line. The control terminal of the voltage control module is connected to the (NX)th stage pull-down node, where X is an integer greater than or equal to 1.

[0006] In some embodiments, the NX-level pull-down node includes the NX-level first pull-down node; at least one inverting module includes the first inverting module, the output of the first inverting module is connected to the first local pull-down node; the voltage control module includes the first transistor, the first transistor is connected in series between the pull-down feedback module and the local pull-up node or between the pull-down feedback module and the first low potential line, and the gate of the first transistor is connected to the NX-level first pull-down node.

[0007] In some embodiments, the NX-level pull-down node further includes an NX-level second pull-down node; at least one inverting module further includes a second inverting module, the output of which is connected to the second local level pull-down node; the voltage control module further includes a second transistor, the first terminal of which is connected to the first terminal of the first transistor, the second terminal of which is connected to the second terminal of the first transistor, and the gate of which is connected to the NX-level second pull-down node.

[0008] In some implementations, the channel type of the first transistor is the same as that of the second transistor.

[0009] In some embodiments, the pull-up control module includes a third transistor and a fourth transistor. The first terminal of the third transistor is connected to a first control signal, and the gate of the third transistor is connected to a second control signal. The first terminal of the fourth transistor is connected to the second terminal of the third transistor, and the gate of the fourth transistor is connected to the first pull-down node of the NXth stage.

[0010] In some embodiments, the pull-up control module further includes a fifth transistor, the first terminal of which is connected to the first terminal of the fourth transistor, the second terminal of which is connected to the second terminal of the fourth transistor, and the gate of which is connected to the NXth stage second pull-down node.

[0011] In some implementations, the channel type of the third transistor is the same as that of the fourth transistor and the fifth transistor.

[0012] In some implementations, the pull-down feedback module and the voltage control module are used to maintain and raise the potential of the pull-up node when the pull-up node is at a high potential.

[0013] In some implementations, in a frame, the turn-on time of the voltage control module precedes the turn-on time of the pull-down feedback module, and the turn-on time of the voltage control module partially overlaps with the turn-on time of the pull-down feedback module.

[0014] Secondly, this application provides a display panel that includes the aforementioned gate driving circuit.

[0015] The gate driving circuit and display panel provided in this application, by connecting a pull-down feedback module and a voltage control module in series between the pull-up node and the first low potential line, can pull down the potential of the pull-up node when both the pull-down feedback module and the voltage control module are in the on state, and can maintain and raise the potential of the pull-up node when both the pull-down feedback module and the voltage control module are in the off state, thereby maintaining and raising the high potential of the pull-up node without affecting normal operation. Attached Figure Description

[0016] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0017] Figure 1 This is a circuit schematic of the gate drive circuit in the related technology.

[0018] Figure 2 This is a circuit schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0019] Figure 3 Another circuit schematic diagram of the gate drive circuit provided in the embodiments of this application.

[0020] Figure 4 The following are waveform simulation diagrams of some nodes provided in the embodiments of this application.

[0021] Figure 5 A comparative diagram of some parameters provided for embodiments of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0024] Figure 1 This is a circuit schematic of a gate drive circuit in related technologies. For example... Figure 1 As shown, the gate drive circuit includes a shift register, in which the first terminal of the third transistor T11 is connected to the first control signal, and the gate of the third transistor T11 is connected to the second control signal; the second terminal of the third transistor T11 is connected to the pull-up node Q of this stage.

[0025] It should be noted that the first control signal can be the (N-4)th stage gate drive signal G(N-4), the (N-2)th stage gate drive signal, or the (N-3)th stage gate drive signal. The second control signal can be the (N-4)th stage cascade signal ST(N-4), the (N-2)th stage cascade signal, or the (N-3)th stage cascade signal.

[0026] The first terminal of the cascaded transistor T22 is connected to the clock signal CK, the second terminal of the cascaded transistor T22 outputs the Nth stage cascade signal ST(N), and the gate of the cascaded transistor T22 is connected to the pull-up node Q of this stage.

[0027] The first terminal of the pull-down feedback transistor T41 is connected to the pull-up node Q of this stage, the second terminal of the pull-down feedback transistor T41 is connected to the first low potential line, and the gate of the pull-down feedback transistor T41 is connected to the cascaded signal ST (N+6) of the N+6th stage.

[0028] The first terminal of the sixth transistor T51 is connected to the gate of the sixth transistor T51 and the first terminal of the eighth transistor T53, and is connected to the first low-frequency control signal LC1. The second terminal of the sixth transistor T51 is connected to the gate of the eighth transistor T53 and the first terminal of the seventh transistor T52. The second terminal of the eighth transistor T53 is connected to the first terminal of the ninth transistor T54 to form the first pull-down node K(N) of this stage. The first low potential line is connected to the second terminal of the seventh transistor T52 and the second terminal of the ninth transistor T54. The pull-up node Q of this stage is connected to the gate of the seventh transistor T52 and the gate of the ninth transistor T54.

[0029] The sixth transistor T51, the seventh transistor T52, the eighth transistor T53, and the ninth transistor T54 can form an inverting module.

[0030] The gate of the tenth transistor T32 is connected to the first pull-down node K(N) of this stage, the first terminal of the tenth transistor T32 is connected to the gate drive line of the Nth stage, and the second terminal of the tenth transistor T32 is connected to the second low potential line.

[0031] It should be noted that the Nth gate drive line is used to transmit the Nth gate drive signal G(N). The second low-potential line is used to transmit the second low-potential signal VSSG.

[0032] The gate of the eleventh transistor T42 is connected to the first pull-down node K(N) of this stage, the first terminal of the eleventh transistor T42 is connected to the pull-up node Q of this stage, and the second terminal of the eleventh transistor T42 is connected to the first low potential line.

[0033] The first terminal of the twelfth transistor T61 is connected to the gate of the twelfth transistor T61 and the first terminal of the fourteenth transistor T63, and is connected to the second low-frequency control signal LC2. The second terminal of the twelfth transistor T61 is connected to the gate of the fourteenth transistor T63 and the first terminal of the thirteenth transistor T62. The second terminal of the fourteenth transistor T63 is connected to the first terminal of the fifteenth transistor T64, forming the second pull-down node P(N) of this stage. The first low potential line is connected to the second terminal of the thirteenth transistor T62 and the second terminal of the fifteenth transistor T64. The pull-up node Q of this stage is connected to the gate of the thirteenth transistor T62 and the gate of the fifteenth transistor T64.

[0034] Among them, the twelfth transistor T61, the thirteenth transistor T62, the fourteenth transistor T63, and the fifteenth transistor T64 can form another inverting module.

[0035] The gate of the sixteenth transistor T33 is connected to the second pull-down node P(N) of this stage, the first terminal of the sixteenth transistor T33 is connected to the gate drive line of the Nth stage, and the second terminal of the sixteenth transistor T33 is connected to the second low potential line.

[0036] The gate of the seventeenth transistor T43 is connected to the second pull-down node P(N) of this stage, the first terminal of the seventeenth transistor T43 is connected to the pull-up node Q of this stage, and the second terminal of the seventeenth transistor T43 is connected to the first low potential line.

[0037] The gate of the eighteenth transistor T44 is connected to the reset control signal Reset. The first terminal of the eighteenth transistor T44 is connected to the pull-up node Q of this stage. The second terminal of the eighteenth transistor T44 is connected to the first low potential line.

[0038] The first terminal of the pull-up transistor T21 is connected to the clock signal CK. The second terminal of the pull-up transistor T21 is connected to one end of the bootstrap capacitor Cbt and outputs the Nth stage gate drive signal G(N). The gate of the pull-up transistor T21 is connected to the other end of the bootstrap capacitor Cbt and the pull-up node Q of this stage.

[0039] The gate drive circuit can also be called the GOA circuit. GOA (Gate Driver on Array) is a design that uses thin-film transistor (TFT) circuits to output gate drive signals row by row.

[0040] Display panels are evolving towards higher response times and higher refresh rates. Common approaches to achieving these include reducing the channel width of thin-film transistors (TFTs) or using LTPS or IGZO TFTs. However, these design choices and material selections can easily lead to severe leakage current at the pull-up node Q in the off state of the TFT, thus affecting the stage transmission of the GOA circuit. Therefore, the design of a leakage-proof structure for the pull-up node Q is essential for achieving high response times in display panels. For example... Figure 1 As shown, the pull-up node Q of the GOA circuit is connected to the first low potential line through T4x series thin-film transistors such as T41, T42, T43, and T44. At the same time, the pull-up node Q is also connected to the gate drive signal through T11. Both the T4x series and T11 may become the leakage path of the pull-up node Q.

[0041] Therefore, it is necessary to provide a leakage protection design for the pull-up node Q of this stage, which can help prevent leakage of the pull-up node Q when it is at a high level while ensuring that the function of the GOA circuit is not affected.

[0042] In view of the aforementioned technical problem of potential drop when the pull-up node is at a high potential, this embodiment provides a gate drive circuit. Please refer to [link to relevant documentation]. Figures 2 to 5 ,like Figure 2 , Figure 3 As shown, the gate drive circuit includes a shift register. The Nth stage shift register includes a pull-up control module 10, a cascade module 20, at least one inverting module, a pull-down feedback module 50, and a voltage control module 60. The pull-up control module 10 is connected to the pull-up node Q of its current stage. The cascade module 20 is also connected to the pull-up node Q of its current stage. The cascade module 20 outputs the Nth stage cascade signal ST(N) according to the potential of the pull-up node Q, where N is a positive integer. The input of each inverting module is connected to the pull-up node Q of its current stage. The output of each inverting module is connected to the corresponding pull-down node of its stage; the pull-down feedback module 50 is connected in series between the pull-up node Q of its stage and the first low potential line, and the control terminal of the pull-down feedback module 50 is connected to the N+Mth stage cascade signal, where M is an integer greater than or equal to 1; the voltage control module 60 is connected in series between the pull-down feedback module 50 and the pull-up node Q of its stage or between the pull-down feedback module 50 and the first low potential line, and the control terminal of the voltage control module 60 is connected to the NXth stage pull-down node, where X is an integer greater than or equal to 1.

[0043] It is understood that the gate drive circuit provided in this embodiment, by connecting the pull-down feedback module 50 and the voltage control module 60 in series between the pull-up node Q and the first low potential line, can both pull down the potential of the pull-up node Q when both the pull-down feedback module 50 and the voltage control module 60 are in the on state, and maintain and raise the potential of the pull-up node Q when both the pull-down feedback module 50 and the voltage control module 60 are in the off state, thereby maintaining and raising the high potential of the pull-up node Q without affecting normal operation.

[0044] Furthermore, since the high potential of the pull-up node Q in this stage is maintained and raised, the stability of the stage transmission signal and the gate drive signal can be improved.

[0045] It should be noted that the pull-down feedback module 50 and the voltage control module 60 can work together to maintain and raise the potential of the pull-up node Q when it is at a high potential. In this case, both the pull-down feedback module 50 and the voltage control module 60 are in the off state, because... Figure 1 Based on this, a voltage control module 60 is connected in series, which can not only reduce the leakage current of the pull-up node Q of this stage, but also maintain and raise the potential of the pull-up node Q of this stage.

[0046] In a frame, the turn-on time of the voltage control module 60 precedes the turn-on time of the pull-down feedback module 50. This ensures the pull-down effect on the pull-up node Q of the same stage when the pull-down feedback module 50 needs to be turned on, thereby avoiding node contention between the voltage control module 60 and the pull-down feedback module 50. This facilitates the normal pull-down function of the pull-down feedback module 50 on the pull-up node Q of the same stage. Furthermore, the turn-on time of the voltage control module 60 and the turn-on time of the pull-down feedback module 50 partially overlap. This allows the potential of the pull-up node Q of the same stage to be pulled down by the synchronous turn-on of the voltage control module 60 and the pull-down feedback module 50 during the overlapping turn-on time.

[0047] In one embodiment, such as Figure 2 , Figure 3 As shown, the NX-level pull-down node includes the NX-level first pull-down node; at least one inverting module includes the first inverting module 30, the output of the first inverting module 30 is connected to the first local pull-down node; the voltage control module 60 includes the first transistor T411, the first transistor T411 is connected in series between the pull-down feedback module 50 and the local pull-up node Q or between the pull-down feedback module 50 and the first low potential line, and the gate of the first transistor T411 is connected to the NX-level first pull-down node.

[0048] It should be noted that the number of inverting modules can be the same as the number of transistors in the voltage control module 60, and the transistors in the voltage control module 60 can be connected in parallel. The first low-potential line is used to transmit the first low-potential signal VSSQ.

[0049] In one embodiment, the NX-level pull-down node further includes an NX-level second pull-down node; at least one inverting module further includes a second inverting module 40, the output of which is connected to the second local level pull-down node; the voltage control module 60 further includes a second transistor T412, the first terminal of which is connected to the first terminal of the first transistor T411, the second terminal of which is connected to the second terminal of the first transistor T411, and the gate of which is connected to the NX-level second pull-down node.

[0050] It should be noted that the channel type of the first transistor T411 is the same as that of the second transistor T412.

[0051] In one embodiment, such as Figure 3 As shown, the pull-up control module 10 includes a third transistor T11 and a fourth transistor T111. The first terminal of the third transistor T11 is connected to a first control signal, and the gate of the third transistor T11 is connected to a second control signal. The first terminal of the fourth transistor T111 is connected to the second terminal of the third transistor T11, and the gate of the fourth transistor T111 is connected to the first pull-down node of the NXth stage.

[0052] It should be noted that the first control signal can be the (N-4)th stage gate drive signal G(N-4), the (N-2)th stage gate drive signal, or the (N-3)th stage gate drive signal. The second control signal can be the (N-4)th stage cascade signal ST(N-4), the (N-2)th stage cascade signal, or the (N-3)th stage cascade signal.

[0053] Since a fourth transistor T111 is added in series between the input terminal of the first control signal and the pull-up node Q of this stage, the leakage current of the pull-up node Q of this stage when it is at a high potential can also be reduced.

[0054] In one embodiment, such as Figure 3 As shown, the pull-up control module 10 also includes a fifth transistor T112. The first terminal of the fifth transistor T112 is connected to the first terminal of the fourth transistor T111, the second terminal of the fifth transistor T112 is connected to the second terminal of the fourth transistor T111, and the gate of the fifth transistor T112 is connected to the second pull-down node of the NXth stage.

[0055] It should be noted that when there are two inverting modules in the same shift register, a fifth transistor T112 needs to be added so that even when different inverting modules work alternately, the pull-up control module 10 can reduce the leakage current of the pull-up node Q without affecting the pull-up control function.

[0056] The channel type of the third transistor T11 is the same as that of the fourth transistor T111 and the fifth transistor T112. This ensures the correct operation of the pull-up control module 10.

[0057] In one embodiment, such as Figure 2 , Figure 3 As shown, the cascade module 20 includes a cascade transistor T22. The first terminal of the cascade transistor T22 is connected to the clock signal CK, and the second terminal of the cascade transistor T22 outputs the Nth stage cascade signal ST(N). The gate of the cascade transistor T22 is connected to the pull-up node Q of this stage.

[0058] It should be noted that the cascaded transistor T22 can output a clock signal CK as the Nth cascaded signal ST(N) under the potential control of the pull-up node Q of this stage.

[0059] In this configuration, the first electrode is one of the source and the drain, and the second electrode is the other of the source and the drain. For example, if the first electrode is the source, the second electrode is the drain; or if the first electrode is the drain, the second electrode is the source.

[0060] In one embodiment, such as Figure 2 , Figure 3 As shown, the pull-down feedback module 50 includes a pull-down feedback transistor T41. The first terminal of the pull-down feedback transistor T41 is connected to the pull-up node Q of the current stage. The second terminal of the pull-down feedback transistor T41 is connected to at least one of the first terminals of the first transistor T411 and the second transistor T412. The gate of the pull-down feedback transistor T41 is connected to the cascaded signal of the N+M stage.

[0061] It should be noted that M equals 6 as an example, and can also be 1, 2, 3, 4, or 5, etc. In some other embodiments, at least one of the first terminals of the first transistor T411 and the second transistor T412 is connected to the pull-up node Q of this stage, and at least one of the second terminals of the first transistor T411 and the second transistor T412 is connected to the first terminal of the pull-down feedback transistor T41. The second terminal of the pull-down feedback transistor T41 is connected to the first low-potential line. This can also maintain and raise the high potential of the pull-up node Q of this stage without affecting normal operation.

[0062] In one embodiment, such as Figure 2 , Figure 3 As shown, the first inverting module 30 includes a sixth transistor T51, a seventh transistor T52, an eighth transistor T53, and a ninth transistor T54. The first terminal of the sixth transistor T51 is connected to the gate of the sixth transistor T51 and the first terminal of the eighth transistor T53, and is connected to the first low-frequency control signal LC1. The second terminal of the sixth transistor T51 is connected to the gate of the eighth transistor T53 and the first terminal of the seventh transistor T52. The second terminal of the eighth transistor T53 is connected to the first terminal of the ninth transistor T54 to form the first pull-down node K(N) of this stage. The first low-potential line is connected to the second terminal of the seventh transistor T52 and the second terminal of the ninth transistor T54. The pull-up node Q of this stage is connected to the gate of the seventh transistor T52 and the gate of the ninth transistor T54.

[0063] It should be noted that the first inverting module 30 can control the first pull-down node K(N) of the same stage to be at a low potential when the pull-up node Q of the same stage is at a high potential; or, the first inverting module 30 can control the first pull-down node K(N) of the same stage to be at a high potential when the pull-up node Q of the same stage is at a low potential.

[0064] In one embodiment, such as Figure 2 , Figure 3 As shown, the shift register also includes a tenth transistor T32. The gate of the tenth transistor T32 is connected to the first pull-down node K(N) of this stage, the first terminal of the tenth transistor T32 is connected to the gate drive line of the Nth stage, and the second terminal of the tenth transistor T32 is connected to the second low potential line.

[0065] It should be noted that the Nth-stage gate drive line is used to transmit the Nth-stage gate drive signal G(N). The second low-potential line is used to transmit the second low-potential signal VSSG. The tenth transistor T32 can pull down the potential of the Nth-stage gate drive signal G(N) to the potential of the second low-potential signal VSSG under the control of the first pull-down node K(N) of this stage.

[0066] In one embodiment, such as Figure 2 , Figure 3 As shown, the shift register also includes an eleventh transistor T42. The gate of the eleventh transistor T42 is connected to the first pull-down node K(N) of this stage, the first terminal of the eleventh transistor T42 is connected to the pull-up node Q of this stage, and the second terminal of the eleventh transistor T42 is connected to the first low potential line.

[0067] It should be noted that the eleventh transistor T42 can pull down the potential of the pull-up node Q of this stage to the potential of the first low potential signal VSSQ under the control of the first pull-down node K(N) of this stage.

[0068] In one embodiment, such as Figure 2 , Figure 3 As shown, the second inverting module 40 includes a twelfth transistor T61, a thirteenth transistor T62, a fourteenth transistor T63, and a fifteenth transistor T64. The first terminal of the twelfth transistor T61 is connected to the gate of the twelfth transistor T61 and the first terminal of the fourteenth transistor T63, and is connected to the second low-frequency control signal LC2. The second terminal of the twelfth transistor T61 is connected to the gate of the fourteenth transistor T63 and the first terminal of the thirteenth transistor T62. The second terminal of the fourteenth transistor T63 is connected to the first terminal of the fifteenth transistor T64, forming the second pull-down node P(N) of this stage. The first low-potential line is connected to the second terminal of the thirteenth transistor T62 and the second terminal of the fifteenth transistor T64. The pull-up node Q of this stage is connected to the gate of the thirteenth transistor T62 and the gate of the fifteenth transistor T64.

[0069] It should be noted that the second inverting module 40 can control the second pull-down node P(N) of the same stage to be at a low potential when the pull-up node Q of the same stage is at a high potential; or, the second inverting module 40 can control the second pull-down node P(N) of the same stage to be at a high potential when the pull-up node Q of the same stage is at a low potential.

[0070] In one embodiment, such as Figure 2 , Figure 3 As shown, the shift register also includes a sixteenth transistor T33. The gate of the sixteenth transistor T33 is connected to the second pull-down node P(N) of this stage. The first terminal of the sixteenth transistor T33 is connected to the gate drive line of the Nth stage. The second terminal of the sixteenth transistor T33 is connected to the second low potential line.

[0071] It should be noted that the sixteenth transistor T33 can pull down the potential of the Nth stage gate drive signal G(N) to the potential of the second low potential signal VSSG under the control of the second pull-down node P(N) of this stage.

[0072] In one embodiment, such as Figure 2 , Figure 3 As shown, the shift register also includes a seventeenth transistor T43. The gate of the seventeenth transistor T43 is connected to the second pull-down node P(N) of this stage, the first terminal of the seventeenth transistor T43 is connected to the pull-up node Q of this stage, and the second terminal of the seventeenth transistor T43 is connected to the first low potential line.

[0073] It should be noted that the seventeenth transistor T43 can pull down the potential of the pull-up node Q of this stage to the potential of the first low potential signal VSSQ under the control of the second pull-down node P(N) of this stage.

[0074] In one embodiment, such as Figure 2 , Figure 3 As shown, the shift register also includes an eighteenth transistor T44. The gate of the eighteenth transistor T44 is connected to the reset control signal Reset. The first terminal of the eighteenth transistor T44 is connected to the pull-up node Q of this stage, and the second terminal of the eighteenth transistor T44 is connected to the first low potential line.

[0075] It should be noted that the eighteenth transistor T44 can pull down the potential of the pull-up node Q of this stage to the potential of the first low potential signal VSSQ under the control of the reset control signal Reset.

[0076] In one embodiment, such as Figure 2 , Figure 3As shown, the shift register also includes a pull-up module 70, which can output the pulse of the clock signal CK based on the potential of the pull-up node Q of this stage as the pulse of the gate drive signal G(N) of the Nth stage.

[0077] In one embodiment, such as Figure 2 , Figure 3 As shown, the pull-up module 70 includes a pull-up transistor T21 and a bootstrap capacitor Cbt. The first terminal of the pull-up transistor T21 is connected to the clock signal CK. The second terminal of the pull-up transistor T21 is connected to one end of the bootstrap capacitor Cbt and outputs the Nth stage gate drive signal G(N). The gate of the pull-up transistor T21 is connected to the other end of the bootstrap capacitor Cbt and the pull-up node Q of this stage.

[0078] It should be noted that the channel type of each transistor in the gate drive circuit can be the same, for example, they can all be N-channel thin film transistors or P-channel thin film transistors. This application uses an N-channel thin film transistor as an example.

[0079] There may be a time conflict between the turn-on of the pull-down feedback transistor T41 and the turn-on of the first transistor T411 and the second transistor T412 (also known as node contention). The first transistor T411 and the second transistor T412 will hinder the pull-down function of the pull-down feedback transistor T41 on the pull-up node Q of this stage. For the inverting module of this stage, when the pull-up node Q of this stage is at a high potential, the first pull-down node K(N) and the second pull-down node P(N) of this stage are at a low potential. At this time, the first transistor T411 and the second transistor T412 are in the off state. When the pulse of the cascaded signal ST(N+6) of the N+6th stage arrives, although the pull-down feedback transistor T41 turns on, the first transistor T411 and the second transistor T412 are still in the off state, and the pull-up node Q of this stage cannot be pulled down. Therefore, it is necessary to ensure that the first transistor T411 and the second transistor T412 are turned on before the pull-down feedback transistor T41 of this stage is turned on. Thus, the gates of the first transistor T411 and the second transistor T412 are connected to the first pull-down node of the NXth stage and the second pull-down node of the NXth stage.

[0080] Figure 4 The figure shows the waveform simulation diagram of the pull-up node Q of this stage, the first pull-down node of the N-1th stage / the second pull-down node of the N-1th stage. In the figure, the voltage of the pull-up node Q of this stage represents the waveform of the pull-up node Q of this stage, K(N-1) represents the voltage waveform of the first pull-down node of the N-1th stage, and P(N-1) represents the voltage waveform of the second pull-down node of the N-1th stage.

[0081] ΔQ refers to the voltage difference between the highest and second-highest potentials of the pull-up node Q in this stage, reflecting leakage current. The smaller ΔQ is, the better the leakage current protection. Q Ripple is the voltage fluctuation of the pull-up node Q in this stage caused by the clock signal CK input when the pull-up transistor is turned off. The smaller Q Ripple is, the more stable the voltage fluctuation of the pull-up node Q in this stage.

[0082] It should be noted that the voltage control module 60 in this application can reduce leakage current during the pre-charging (when the third transistor T11 is turned on) and charging (when the pull-up transistor is turned on) processes of the pull-up node Q. Therefore, the voltage control module 60 can maintain and increase the potential of the pull-up node Q.

[0083] The above effects can be achieved from Figure 5 The data shown indicates that, Figure 5 In the example below, the threshold voltage (Vth) of the pull-down feedback transistor T41 is -5V. Here, Q represents the potential related to the pull-up node Q of this stage, G represents the node that outputs the Nth stage gate drive signal G(N), I represents the current, Rising represents the time required for the Nth stage gate drive signal G(N) to jump from a low potential to a high potential, Falling represents the time required for the Nth stage gate drive signal G(N) to jump from a high potential to a low potential, and leakage represents the magnitude of the leakage current.

[0084] A comparative analysis of the case without voltage control module 60 (Normal) and the case with voltage control module 60 (Inverter Type) revealed that after adding voltage control module 60, the potential of the pull-up node Q in this stage increased from 52.9V to 53.5V. This indicates that voltage control module 60 maintained and raised the potential of the pull-up node. ΔQ and QRipple were also reduced. Rising and Falling were also reduced, indicating that the pulse rising edge and pulse falling edge of the Nth stage gate drive signal G(N) were improved, and the waveform was closer to the ideal waveform. Leakage was also significantly reduced, indicating that the leakage current was reduced.

[0085] In one embodiment, this embodiment provides a display panel that includes the gate driving circuit described above.

[0086] It is understood that, since the display panel provided in this embodiment includes the gate driving circuit described above, it is also possible to pull down the potential of the pull-up node Q by connecting the pull-down feedback module 50 and the voltage control module 60 in series between the pull-up node Q and the first low potential line. This allows the potential of the pull-up node Q to be pulled down when both the pull-down feedback module 50 and the voltage control module 60 are in the on state, and to be maintained and raised when both the pull-down feedback module 50 and the voltage control module 60 are in the off state. Thus, the high potential of the pull-up node Q can be maintained and raised without affecting normal operation.

[0087] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0088] The gate driving circuit and display panel provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A gate driving circuit, characterized in that, The gate drive circuit includes a shift register, wherein the Nth stage shift register includes: A pull-up control module, which is connected to the pull-up node at this level; A cascading module is connected to the pull-up node of the current stage. The cascading module outputs the Nth stage cascading signal according to the potential of the pull-up node of the current stage, where N is a positive integer. At least one inverter module, the input of each inverter module is connected to the pull-up node of the same level, and the output of each inverter module is connected to the corresponding pull-down node of the same level; A pull-down feedback module is connected in series between the pull-up node of this stage and the first low potential line. The control terminal of the pull-down feedback module is connected to the N+Mth stage cascade signal, where M is an integer greater than or equal to 1. A voltage control module is connected in series between the pull-down feedback module and the pull-up node of the same level or between the pull-down feedback module and the first low potential line. The control terminal of the voltage control module is connected to the Nth level pull-down node, where X is an integer greater than or equal to 1.

2. The gate driving circuit according to claim 1, characterized in that, The NXth level drop-down node includes an NXth level first drop-down node; the at least one inverting module includes a first inverting module, and the output terminal of the first inverting module is connected to the first level drop-down node. The voltage control module includes a first transistor, which is connected in series between the pull-down feedback module and the pull-up node of the same stage or between the pull-down feedback module and the first low potential line. The gate of the first transistor is connected to the first pull-down node of the NXth stage.

3. The gate driving circuit according to claim 2, characterized in that, The NX-level drop-down node further includes an NX-level second drop-down node; the at least one inverting module further includes a second inverting module, the output of which is connected to the second local-level drop-down node. The voltage control module further includes a second transistor, the first terminal of which is connected to the first terminal of the first transistor, the second terminal of which is connected to the second terminal of the first transistor, and the gate of which is connected to the NXth level second pull-down node.

4. The gate driving circuit according to claim 3, characterized in that, The channel type of the first transistor is the same as that of the second transistor.

5. The gate driving circuit according to claim 3, characterized in that, The pull-up control module includes: The third transistor has a first terminal connected to a first control signal and a second control signal connected to its gate. The fourth transistor has its first terminal connected to the second terminal of the third transistor, and its gate connected to the first pull-down node of the NXth stage.

6. The gate driving circuit according to claim 5, characterized in that, The pull-up control module further includes a fifth transistor, the first terminal of which is connected to the first terminal of the fourth transistor, the second terminal of which is connected to the second terminal of the fourth transistor, and the gate of which is connected to the NXth level second pull-down node.

7. The gate driving circuit according to claim 6, characterized in that, The channel type of the third transistor is the same as that of the fourth transistor and the fifth transistor.

8. The gate driving circuit according to any one of claims 1-7, characterized in that, The pull-down feedback module and the voltage control module are used to maintain and raise the potential of the pull-up node when the pull-up node is at a high potential.

9. The gate driving circuit according to claim 8, characterized in that, In a frame, the turn-on time of the voltage control module precedes the turn-on time of the pull-down feedback module, and the turn-on time of the voltage control module partially overlaps with the turn-on time of the pull-down feedback module.

10. A display panel, characterized in that, The display panel includes the gate driving circuit as described in any one of claims 1-9.

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