Field effect transistors and logic devices based on metal fluoride superionic conductor dielectric films

Abstract

This invention discloses a field-effect transistor and logic device based on a metal fluoride superionic conductor dielectric thin film. The field-effect transistor includes, from bottom to top, a substrate, a gate electrode, a dielectric layer, a channel layer, and source / drain electrodes deposited on the upper surface of the channel layer. The dielectric layer is a metal fluoride superionic conductor thin film, prepared by thermal evaporation. Because the thermally evaporated metal fluoride superionic conductor thin film has a large capacitive coupling, devices fabricated using it as the dielectric layer exhibit excellent performance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a field-effect transistor and logic device based on a metal fluoride superionic conductor dielectric thin film. Background Technology

[0002] Field-effect transistors (FETs) are one of the cornerstones of modern electronic applications. Since the invention of the first metal-oxide-semiconductor (MODS) FET in 1960, the density of transistors per unit area on a chip has consistently followed Moore's Law. However, with the rapid development of modern electronics and the miniaturization of traditional semiconductor devices approaching physical limits, traditional oxide dielectrics, due to their low capacitive coupling and limited breakdown field strength, struggle to effectively control the switching states of the channel material (short-channel effect). Furthermore, reducing the thickness of the dielectric layer increases gate leakage current, hindering further scaling of FET dimensions. Although researchers have attempted to enhance gate control over the channel and reduce gate leakage current by using high-k dielectric materials (such as HfO2) and employing special gate structures such as non-planar fin field-effect transistors (FinFETs) or all-around field-effect transistors (GAA-FETs), these advanced structures will also reach their limits after the sub-1nm technology node. Unlike traditional oxide dielectrics, novel ionic liquid electric double-layer modulation techniques, developed in recent years based on the concept of "interfacial electric double layer," can construct electric double-layer structures on the surface of electronic materials to achieve huge capacitive coupling and control the carrier concentration on the material surface over a wide range (up to 10) at low operating voltages. 15 cm –2 Organic ionic electrolytes (ICEs) have been developed as an effective technique for controlling the electronic states of materials and strongly correlated quantum phenomena in condensed matter physics. However, these ICEs typically exist in liquid or gel form, making them incompatible with current semiconductor manufacturing processes and hindering the integration of dielectrics based on interfacial electrical double-layer effects into modern electronic devices. On the other hand, due to the advantages of two-dimensional semiconductor materials in reducing short-channel effects in field-effect devices, remarkable progress has been made in electronic devices using two-dimensional semiconductor materials as channel materials over the past 19 years. However, most gate dielectrics suitable for two-dimensional materials do not meet the requirements of large-scale industrial manufacturing. For example, promising dielectrics such as SrTiO3 and hBN can only be grown on special substrates and must be transferred to the relevant channel material using transfer techniques (achieving nanoscale thin-layer material transfer at the wafer scale remains challenging); while directly growing high-κ dielectric layers on substrates or two-dimensional channel materials (such as atomic layer deposition (ALD)) remains costly, and the stability and reliability of the devices are still far from reaching the level of silicon-based technologies.

[0003] Therefore, developing solid-state dielectric materials with high capacitive coupling and compatibility with traditional semiconductor manufacturing processes and even future large-scale two-dimensional semiconductor device manufacturing processes is of great significance for realizing advanced electronic devices and large-scale integrated circuits. Summary of the Invention

[0004] One of the objectives of this invention is to provide a field-effect transistor, comprising a substrate, a gate electrode, a dielectric layer, a channel layer, and source / drain electrodes deposited on the upper surface of the channel layer, distributed from bottom to top.

[0005] The dielectric layer is a metal fluoride superionic conductor film, and the conductivity of the metal fluoride superionic conductor film is 10. -5 -10 -2 S / cm, low-frequency capacitance is 1-25μF / cm 2 The high-frequency capacitance is 0.02-1μF / cm. 2 Leakage current density less than 10 -5 A / cm 2 The root mean square surface roughness is less than 1 nm, and the fluorine vacancy content is 0.01%-15%.

[0006] Furthermore, the metal fluoride superionic conductor film is prepared by thermal evaporation of a metal fluoride superionic conductor, wherein the metal fluoride superionic conductor is selected from one or more of lanthanum fluoride, cerium fluoride, neodymium fluoride, samarium fluoride, europium fluoride, gadolinium fluoride, holmium fluoride, erbium fluoride, ytterbium fluoride, scandium fluoride, yttrium fluoride, titanium fluoride, hafnium fluoride, manganese fluoride, ferrous fluoride, nickel fluoride, calcium fluoride, strontium fluoride, barium fluoride, and tin fluoride.

[0007] Preferably, the specific process of the thermal evaporation method is as follows: first, the metal fluoride superionic conductor is ground, and then it is placed on the heating column of the thermal evaporation system. When the system vacuum degree reaches 10... -5 Evaporation begins when Pa is below a certain level, with metal fluorides used as... The evaporation rate is adjusted to deposit on the substrate surface until the thickness reaches 10nm-20nm. Until the target thickness is achieved, the temperature of the substrate is controlled between 200K and 600K during the vapor deposition process.

[0008] Furthermore, the channel layer is a two-dimensional semiconductor material, an oxide semiconductor material, or a nitride semiconductor material. In one embodiment of the present invention, the two-dimensional semiconductor material is a transition metal chalcogenide compound.

[0009] In one embodiment of the present invention, the substrate is a silicon wafer substrate with an oxide layer, and the gate electrode and source / drain electrode are metal electrodes.

[0010] A second objective of this invention is to provide an inverter, comprising: a first transistor and a second transistor; wherein the first transistor and the second transistor are the aforementioned field-effect transistors;

[0011] The gates of the first transistor and the second transistor are connected; the drain of the first transistor is connected to the power supply voltage; the source of the second transistor is grounded, and its drain is connected to the source of the first transistor and connected to the output terminal.

[0012] A third objective of this invention is to provide a logic AND-OR gate, comprising a first transistor WSe2#1, a second transistor MoS2#1, a third transistor WSe2#2, and a fourth transistor MoS2#2, wherein the first transistor WSe2#1, the second transistor MoS2#1, the third transistor WSe2#2, and the fourth transistor MoS2#2 are the aforementioned field-effect transistors; wherein:

[0013] The source of the fourth transistor MoS2#2 is connected to ground;

[0014] The drain of the fourth transistor MoS2#2 is connected to the source of the second transistor MoS2#1;

[0015] The sources of the first transistor WSe2#1 and the third transistor WSe2#2 are connected to the drain of the second transistor MoS2#1, and connected to the output terminal Vout.

[0016] The drains of the first transistor WSe2#1 and the third transistor WSe2#2 are connected to the power supply voltage;

[0017] The gates of the first transistor WSe2#1 and the second transistor MoS2#1 are connected together and connected to the input terminal V. IN1 The gates of the third transistor WSe2#2 and the fourth transistor MoS2#2 are connected, and connected to the input terminal V. IN2 .

[0018] The fourth objective of this invention is to provide a logic NOR gate, comprising a first transistor WSe2#1, a second transistor MoS2#1, a third transistor WSe2#2, and a fourth transistor MoS2#2, wherein the first transistor WSe2#1, the second transistor MoS2#1, the third transistor WSe2#2, and the fourth transistor MoS2#2 are the aforementioned field-effect transistors; wherein:

[0019] The sources of the fourth transistor MoS2#2 and the second transistor MoS2#1 are connected to ground;

[0020] The drains of the fourth transistor MoS2#2 and the second transistor MoS2#1 are connected to the source of the third transistor WSe2#2, and connected to the output terminal Vout.

[0021] The drain of the third transistor WSe2#2 is connected to the source of the first transistor WSe2#1;

[0022] The drain of the first transistor WSe2#1 is connected to the power supply voltage;

[0023] The gates of the first transistor WSe2#1 and the fourth transistor MoS2#2 are connected together and connected to the input terminal V. IN1 The gates of the third transistor WSe2#2 and the second transistor MoS2#1 are connected to the input terminal V. IN2 .

[0024] The fifth objective of this invention is to provide a logic AND gate, comprising a first transistor WSe2#1, a second transistor MoS2#1, a third transistor WSe2#2, a fourth transistor MoS2#2, a fifth transistor WSe2#3, and a sixth transistor MoS2#3, wherein the first transistor WSe2#1, the second transistor MoS2#1, the third transistor WSe2#2, the fourth transistor MoS2#2, the fifth transistor WSe2#3, and the sixth transistor MoS2#3 are the aforementioned field-effect transistors; wherein:

[0025] The sources of the fourth transistor MoS2#2 and the sixth transistor MoS2#3 are connected to ground;

[0026] The drain of the fourth transistor MoS2#2 is connected to the source of the second transistor MoS2#1;

[0027] The sources of the first transistor WSe2#1 and the third transistor WSe2#2 are connected to the drain of the second transistor MoS2#1, and are connected to the gates of the fifth transistor WSe2#3 and the sixth transistor MoS2#3.

[0028] The drains of the first transistor WSe2#1, the third transistor WSe2#2, and the fifth transistor WSe2#3 are connected to the power supply voltage.

[0029] The gates of the first transistor WSe2#1 and the second transistor MoS2#1 are connected together and connected to the input terminal V. IN1 The gates of the third transistor WSe2#2 and the fourth transistor MoS2#2 are connected, and connected to the input terminal V. IN2 ;

[0030] The drain of the sixth transistor MoS2#3 is connected to the source of the fifth transistor WSe2#3, and then connected to the output terminal V. out .

[0031] The sixth objective of this invention is to provide a logic OR gate, comprising a first transistor WSe2#1, a second transistor MoS2#1, a third transistor WSe2#2, a fourth transistor MoS2#2, a fifth transistor WSe2#3, and a sixth transistor MoS2#3, wherein the first transistor WSe2#1, the second transistor MoS2#1, the third transistor WSe2#2, the fourth transistor MoS2#2, the fifth transistor WSe2#3, and the sixth transistor MoS2#3 are the aforementioned field-effect transistors; wherein:

[0032] The sources of the fourth transistor MoS2#2, the second transistor MoS2#1, and the sixth transistor MoS2#3 are connected to ground;

[0033] The drains of the fourth transistor MoS2#2 and the second transistor MoS2#1 are connected to the source of the third transistor WSe2#2, and to the gates of the fifth transistor WSe2#3 and the sixth transistor MoS2#3.

[0034] The drain of the third transistor WSe2#2 is connected to the source of the first transistor WSe2#1;

[0035] The drains of the first transistor WSe2#1 and the fifth transistor WSe2#3 are connected to the power supply voltage;

[0036] The gates of the first transistor WSe2#1 and the fourth transistor MoS2#2 are connected together and connected to the input terminal V. IN1 The gates of the third transistor WSe2#2 and the second transistor MoS2#1 are connected to the input terminal V. IN2 ,

[0037] The drain of the sixth transistor MoS2#3 is connected to the source of the fifth transistor WSe2#3, and then connected to the output terminal V. out .

[0038] The seventh objective of this invention is to provide a logic circuit comprising at least one logic device, wherein the logic device is the aforementioned inverter, the aforementioned logic AND-OR gate, the aforementioned logic NOR gate, the aforementioned logic AND gate, or the aforementioned logic OR gate.

[0039] In their previous research, the inventors discovered that single-metal fluoride thin films or mixed-metal fluoride thin films prepared by thermal evaporation possess both high coupling capacitance and high dielectric constant, as well as wide bandgap and high insulation properties. Their excellent dielectric properties make them suitable as dielectric layers for fabricating high-performance electronic devices. Therefore, this application utilizes these metal fluoride thin films with excellent dielectric properties in conjunction with two-dimensional semiconductor materials to construct field-effect transistors, CMOS inverters, and other basic logic gate circuits with higher performance and lower power consumption.

[0040] Due to the large capacitive coupling of metal fluoride thin films prepared by thermal evaporation, devices fabricated using them as dielectric layers exhibit excellent performance, achieving operating voltages below 1.0V and on / off ratios above 10 in single field-effect transistor devices. 8 Orders in magnitude, gate leakage current density less than 10 -5 A / cm 2 A voltage gain of up to 167 is achieved in inverter devices, while the total noise margin exceeds 90% and dynamic power consumption is less than 140nW. High-performance NAND, NOR, AND, and OR logic gates can all be implemented by combining fluoride-gated n-type MoS2 transistors and p-type WSe2 transistors, demonstrating the strong potential of fluoride dielectric materials in constructing logic circuits. Attached Figure Description

[0041] Figure 1 This is a flowchart illustrating the fabrication process of the field-effect transistor in Example 1.

[0042] Figure 2 The results are the device performance test results of the field-effect transistor in Example 1.

[0043] Figure 3 The results show the device performance test results of the field-effect transistors based on different metal fluoride dielectric films in Example 2.

[0044] Figure 4 The results are the detection results of the inverter in Example 3.

[0045] Figure 5 These are the logic "NAND" and "OR" gate circuits in Example 4.

[0046] Figure 6 These are the logic "AND" and "OR" gate circuits in Example 4.

[0047] Figure 7 The results show the stability of the WSe2 field-effect transistor.

[0048] Figure 8 The image shows a cross-sectional STEM image of a field-effect transistor and its corresponding energy dispersive spectrum. Detailed Implementation

[0049] The preferred embodiments of the present invention will now be described in detail with reference to specific examples. It should be understood that the following examples are given for illustrative purposes only and are not intended to limit the scope of the invention. Those skilled in the art can make various modifications and substitutions to the present invention without departing from its spirit and essence.

[0050] Unless otherwise specified, the experimental methods used in the following examples are conventional methods.

[0051] Unless otherwise specified, all materials and reagents used in the following examples are commercially available.

[0052] Example 1

[0053] I. The preparation process of fluoride superionic conductor thin films is as follows:

[0054] First, the fluoride powder or lumps are ground into an extremely fine powder with a particle size of less than 200 mesh. The powder is then loaded into a stainless steel mold with a diameter of 10 mm for pressing. In this embodiment, depending on the size of the selected tungsten boat, the fluoride powder is pressed into a column shape with a diameter of 10 mm and a length of 10 mm.

[0055] The compressed columnar fluoride material is placed in a tungsten boat, which is then transferred to the heating column of the thermal evaporation system and secured. Simultaneously, the SiO2 / Si substrate to be deposited (which can be replaced with mica, sapphire, ruby, indium phosphide, strontium titanate, quartz glass, or other commonly used substrates) is adhered using high-temperature resistant yellow tape, and a substrate baffle is placed directly beneath the substrate to seal the cavity. The pneumatic valve between the vacuum pump and the evaporation system is opened, followed by the mechanical pump to obtain a rough vacuum. When the system vacuum level is better than 5 Pa, the molecular pump is activated to evacuate until the system reaches 10 Pa. -5 High vacuum in the Pa range.

[0056] Turn on the water cooling system of the substrate. Increase the current flowing through the tungsten boat. When the heating temperature exceeds the melting point of the fluoride, fluoride molecules begin to deposit on the pre-placed substrate to form a fluoride film. Monitor the thickness of the metal fluoride film on the SiO2 / Si substrate surface using a crystal oscillator film thickness gauge. During the evaporation process, first allow the fluoride material to... The fluoride material is exhaled at a certain rate to remove surface-adsorbed impurities. When the exhaled thickness reaches 10 nm or more, the baffle between the fluoride material and the substrate is opened. Then, the current flowing through the tungsten boat is reduced, and the reading of the crystal oscillator film thickness gauge is observed to maintain the current. The rate of thermal evaporation, maintaining The evaporation rate was increased until the thickness reached over 10 nm; finally, the current flowing through the tungsten boat was increased, and the evaporation rate was increased further by observing the reading of the crystal oscillator film thickness gauge. A faster rate of thermal evaporation, maintaining The rate continues until the target thickness of 200nm is reached.

[0057] The fluoride film was then characterized using atomic force microscopy (AFM), transmission electron microscopy (TEM), and energy-dispersive X-ray spectroscopy (EDX). Its dielectric properties were then tested using a parallel-plate capacitor structure. The relevant results are shown in the table below:

[0058]

[0059] Example 2

[0060] Field-effect transistors based on NdF3 superionic conductor dielectric films.

[0061] The overall configuration of the two-dimensional semiconductor field-effect transistor based on metal fluoride dielectric thin film adopts a bottom gate structure. Rare earth metal fluoride thin film is deposited on a silicon substrate with a 300nm oxide layer as the dielectric layer material of the field-effect transistor, and the channel material is a two-dimensional semiconductor material (MoS2 / WSe2).

[0062] The fabrication process of a field-effect transistor is as follows: Figure 1 As shown, the specific steps are as follows:

[0063] (1) Substrate cleaning: First, put the cut silicon wafer substrate into a mixed solution of acetone, ethanol and isopropanol, and clean it in an ultrasonic machine for 3-5 minutes to remove impurities attached to the surface. Then rinse it with isopropanol solution and treat the surface of SiO2 / Si substrate with oxygen plasma to remove residual organic solution, so that it has a clean surface.

[0064] (2) Preparation of bottom gate electrode: The bottom gate electrode pattern is pre-formed on the SiO2 / Si substrate by photolithography. Titanium gold electrodes (the thickness of the titanium gold metal electrodes is 3 / 9nm) are deposited by electron beam evaporation as the bottom gate. Then, the metal electrodes are stripped in acetone solution and rinsed with isopropanol to obtain a substrate with the bottom gate.

[0065] (3) Gate dielectric deposition: Taking the preparation of NdF3 dielectric thin film as an example, firstly, commercially available NdF3 particles are ground into fluoride powder of about 200 mesh, and the fluoride powder is pressed into a columnar structure using hydraulic equipment (in this embodiment, a cylinder with a diameter of 6 mm and a length of 1 cm is used); then the pressed columnar fluoride is placed on a tungsten boat (or a molybdenum boat), and the tungsten boat is transferred to the heating column of the thermal evaporation system for fixation; at the same time, the SiO2 / Si substrate to be deposited is fixed on the base of the thermal evaporation system using high-temperature resistant yellow tape, and the substrate baffle is placed directly below the substrate to seal the cavity; then the mechanical pump for rough vacuum and the molecular pump for high vacuum are turned on respectively, and the system vacuum degree is reached 10 -5After reaching the Pa level, the heating temperature of the fluoride is increased by gradually increasing the current flowing through the tungsten boat. When the heating temperature exceeds the melting point of the fluoride, fluoride molecules begin to deposit on the pre-placed substrate to form a fluoride solid solution film. The thickness of the metal fluoride film on the silicon substrate surface is monitored using a crystal oscillator film thickness gauge. During the evaporation process, the fluoride material is first... The material is exhaled at a certain rate. Once the exhaled thickness reaches 10 nm, the baffle between the fluoride material and the substrate is opened. Then, the current flowing through the tungsten boat is reduced, and the reading of the crystal oscillator film thickness gauge is observed to maintain the thickness. Slower thermal evaporation rate, maintain The evaporation rate was increased until the thickness reached 10 nm. Then, the current flowing through the tungsten boat was increased, and the evaporation rate was increased further by observing the readings of a crystal oscillator film thickness gauge. A faster rate of thermal evaporation, maintaining The rate continues until the target thickness is reached.

[0066] The following points should be noted when thermally growing fluoride films: First, maintain a slow thermal evaporation rate by precisely controlling the current flowing through the heating column, so that the deposited fluoride film will be more dense; second, control the substrate temperature by using a water cooling system to keep the substrate at a low temperature, which can create more fluorine vacancies, thus helping to improve the ionic conductivity of the fluoride film; third, ensure that the background vacuum of the vacuum chamber before evaporation is sufficiently low (<10). -5 The fluoride solid solution film prepared in this way contains fewer impurities, is less prone to breakdown, and has better insulation properties (on the order of Pa).

[0067] (4) Preparation of two-dimensional channel material: The mechanical peeling method is adopted. First, the layered sheet of two-dimensional material is mechanically peeled off from the bulk MoS2 crystal with tape, and then polydimethylsiloxane (PDMS) is used for further peeling. The sample thickness is determined by optical photographs and suitable thin-layer two-dimensional material samples are found. Then, the MoS2 material sheet is transferred from PDMS to the surface of the metal fluoride film obtained in step (3) by dry transfer.

[0068] (5) Deposition of source and drain metal electrodes: Polymethyl methacrylate (PMMA) is spin-coated onto the substrate surface of the transferred sample. Electrode patterns are formed on the MoS2 sample using photolithography. After development, metal electrodes (Ti / Au, 6+45nm) are deposited by electron beam evaporation. Finally, the metal electrodes are stripped in acetone solution and rinsed with isopropanol to obtain the final two-dimensional field-effect transistor device. To improve the interfacial contact resistance of the metal semiconductor, an annealing treatment is usually performed at 200 degrees Celsius under argon-hydrogen gas (95% Ar and 5% H2) for two hours.

[0069] The aforementioned field-effect transistors were subjected to device performance testing at room temperature. Source-drain voltage and gate voltage were applied using a probe station based on a Keysight 4200 semiconductor analyzer, and source-drain current and gate leakage current were measured simultaneously.

[0070] Figure 2 This paper presents a schematic diagram of a bottom-gate MoS2 field-effect transistor based on a metal fluoride (NdF3) thin-film gate dielectric and its transfer characteristic curves under different source-drain voltages. From this, the following electrical parameters of the MoS2 bottom-gate field-effect transistor based on the NdF3 gate dielectric can be derived: First, the turn-on voltage of the device is approximately 0.5V, which is relatively low compared to traditional oxide dielectrics, resulting in a low operating voltage and thus very low device power consumption; Second, within a certain range of source-drain current variation, 10... -12 ~10 -7 A, the minimum subthreshold swing is 65 mV / dec, which is very close to the limit of the Boltzmann thermodynamic distribution of 60 mV / dec (shown by the horizontal dashed line), and is also within 10 -12 ~10 -9 Third, the field-effect transistor maintains a current on / dec ratio below 80 mV / dec for three orders of magnitude; and fourth, it exhibits an ultra-high current on / off ratio exceeding 10 at a source-drain voltage of 0.7 V and a gate voltage of 1.0 V. 8 Compared to other high-dielectric-constant materials, MoS2 field-effect transistors based on rare-earth metal fluoride gate dielectrics exhibit superior performance in both on / off current ratio and subthreshold swing, demonstrating the excellent control capability of metal fluorides over the conductive channel and reflecting high-quality NdF3 / MoS2 interface coupling. To evaluate the electrical insulation of the fluoride film in practical transistor devices, the gate leakage current density of the rare-earth metal fluoride gate MoS2 field-effect transistor was further measured, such as... Figure 2 As shown in Figure c, the gate leakage current density is less than 10 at all gate voltages. -5 A / cm 2 This is lower than the low power limit of 0.015 A / cm² for CMOS devices. 2 More than three orders of magnitude lower. The extremely low leakage current indicates that the superionic rare-earth metal fluoride dielectric has sufficient insulation to minimize leakage current in high-performance integrated circuits.

[0071] Example 3

[0072] Field-effect transistors based on dielectric thin films of different metal fluoride superionic conductors

[0073] Because the metal fluoride dielectric film preparation method used in this invention is universal, field-effect transistors based on different metal fluoride dielectric films (taking CeF3, LaF3, and SmF3 as examples) can be prepared by changing the type of fluoride material. The preparation method is basically the same as the NdF3 method in Example 1: a bottom gate structure is used, and different metal fluoride films are deposited on a silicon substrate with a 300nm oxide layer as the dielectric layer material of the field-effect transistor. The channel material is a two-dimensional semiconductor material (MoS2 or WSe2).

[0074] Figure 3 The transfer characteristic curves, on / off ratios, and output characteristic curves of these different fluoride field-effect transistors are shown. All of these field-effect transistors have on / off ratios exceeding 10. 6 The leakage current is less than 0.1 nA. It is worth noting that the source-leakage current in the transfer characteristic curves here was measured using a Keithely 2400, therefore the off-state current is relatively high (~10 nA). -11 In fact, the device's off-state current is less than 10. -13 Magnitude (see Figure 2 Therefore, the on / off ratio of the actual device can reach 10. 8 ,and Figure 2 The performance is similar to that of NdF3 dielectric thin-film field-effect transistors.

[0075] Example 4

[0076] Inverters (NOT gate logic devices) based on metal fluoride superionic conductor dielectric films.

[0077] Based on the aforementioned rare-earth metal fluoride thin-film gate dielectric field-effect transistors, a CMOS inverter was further constructed by integrating n-type MoS2 and p-type WSe2 field-effect transistors. For example... Figure 4 Figure a shows a schematic diagram of the inverter's device structure: The gates of the n-type MoS2 and p-type WSe2 field-effect transistors are connected together as the voltage signal input terminal. The drain (D) of the p-type WSe2 field-effect transistor is used as the input terminal for the preset power supply voltage. The source (S) of the n-type MoS2 field-effect transistor is used as the ground terminal. The unconnected sources and drains of the two field-effect transistors are then connected together as the voltage signal output terminal (V). out ).

[0078] Fabrication method: The overall fabrication method is the same as that of a single field-effect transistor. The difference is that during the channel material transfer, a dry transfer method is used to transfer two transition metal chalcogenide (TMDC) materials, n-type MoS2 and p-type WSe2, in sequence. In the subsequent source and drain electrode fabrication steps, source and drain electrode patterns are formed on the MoS2 sample and WSe2 respectively using photolithography. The drain of MoS2 and the source of WSe2 are connected. After development, metal electrodes (Ti / Au, 6+45nm) are deposited by electron beam evaporation. Finally, the metal electrodes are stripped in acetone solution and rinsed with isopropanol to obtain the final CMOS inverter.

[0079] The source-drain voltage is applied to the series-connected MoS2 and WSe2 transistors, supplied by a Keithley 2400 source meter. The MoS2 and WSe2 transistors share the same bottom gate, with the gate voltage applied by another Keithley 2400 source meter, and is used as the input signal (V0) to the inverter. In The voltage drop across the p-type WSe2 transistor is used as the output signal (V). Out ).

[0080] The voltage transfer characteristics of CMOS inverters based on n-type MoS2 and p-type WSe2 field-effect transistors were tested under different power supply voltages. Figure 4 As shown in b, the input signal (V) IN The voltage is increased from 2.0V to 3.0V in 0.2V steps, and the output voltage signal (V) is... OUT It exhibits a step response to the input voltage signal at different preset power supply voltages ranging from 2.0V to 3.0V, displaying the input-output behavior of a classic inverter. Based on Figure 4 The voltage input-output response data shown in b is obtained by calculating its first derivative (dV). oUT / dV In The voltage gain of a CMOS inverter can be obtained. At a power supply voltage V... DD At 2.6V, the voltage gain reaches 167. Compared to other inverters built using 2D TMDC field-effect transistors based on various oxide dielectric materials, this is the highest voltage gain reported to date for this type of inverter. Simultaneously, the total noise margin of the device exceeds 90% across all supply voltages, a level superior to most other 2D TMDC inverters based on other traditional oxide dielectrics. This demonstrates the unique advantage of CMOS inverters based on rare-earth metal fluoride gates in terms of logic circuit noise stability. Another important parameter of an inverter is dynamic power consumption, which directly determines whether the device can be applied to practical electronic devices. When the input logic signal switches from a logic high state to a logic low state, the circuit source-drain current is at its maximum. The power consumption during this logic state switching process is called dynamic power consumption (W = V).DD ×I DD The power consumption when other logic states remain unchanged is the static power consumption. It can be seen that although the peak dynamic power consumption (W) increases with the power supply voltage from 2.0V to 3.0V, the peak dynamic power consumption remains the same. max The maximum value still remains small, increasing from 39.7 nW to 134.8 nW.

[0081] Example 5

[0082] AND, OR, AND-OR, and NAND logic devices based on metal fluoride superionic conductor dielectric films.

[0083] Fabrication method of "AND-OR" and "NAND-NOT" logic devices: The overall fabrication method is consistent with that of a single field-effect transistor. The difference is that during the channel material transfer, a dry transfer method is used to sequentially transfer two n-type MoS2 and two p-type WSe2 materials. In the subsequent source and drain electrode fabrication steps, photolithography is used to form source and drain electrode patterns on the MoS2 sample and WSe2, respectively. After development, metal electrodes (Ti / Au, 6+45nm) are deposited by electron beam evaporation. Finally, the metal electrodes are stripped in acetone solution and rinsed with isopropanol to obtain the final two-dimensional field-effect logic device.

[0084] Testing methods for AND-OR logic devices: (e.g.) Figure 5 As shown in Figure a, two p-type WSe2 field-effect transistors (WSe2#1 and WSe2#2) are connected in parallel to the power supply, and two n-type MoS2 field-effect transistors (MoS2#1 and MoS2#2) are connected in series to signal ground. The source-drain voltages are provided by a Keithley 2400 source meter. MoS2#1 and WSe2#1 use the same bottom gate, and the gate voltage is applied by another Keithley 2400 source meter and used as the input signal V. In1 MoS2#2 and WSe2#2 use the same bottom gate, and the gate voltage is applied by a third Keithley 2400 source meter and used as the input signal V. In2 The output signal V OUT This measures the voltage drop across two n-type MoS2 field-effect transistors (MoS2#1 and MoS2#2) connected in series, measured using a Keithley 2182 source meter.

[0085] Testing methods for NAND logic devices: (e.g.) Figure 5As shown in Figure b, two p-type WSe2 field-effect transistors (WSe2#1 and WSe2#2) are connected in series to the power supply, and two n-type MoS2 field-effect transistors (MoS2#1 and MoS2#2) are connected in parallel to the signal ground. The source-drain voltage is provided by a Keithley 2400 source meter. WSe2#1 and MoS2#2 use the same bottom gate, and the gate voltage is applied by another Keithley 2400 source meter and used as the input signal V. In1 WSe2#2 and MoS2#1 share another bottom gate, with the gate voltage applied by a third Keithley 2400 source meter and used as the input signal V. In2 The output signal V OUT This measures the voltage drop across two parallel n-type MoS2 field-effect transistors (MoS2#1 and MoS2#2), measured using a Keithley 2182 source meter.

[0086] Testing methods for AND logic devices: (e.g.) Figure 6 As shown in Figure a, a NAND circuit is formed by combining two p-type WSe2 field-effect transistors (WSe2#1 and WSe2#2) and two n-type MoS2 field-effect transistors (MoS2#1 and MoS2#2). The source-drain voltage is provided by a Keithley 2400 source meter. MoS2#1 and WSe2#1 use the same bottom gate, and the gate voltage is applied by another Keithley 2400 source meter and used as the input signal V. In1 MoS2#2 and WSe2#2 use the same bottom gate, and the gate voltage is applied by a third Keithley 2400 source meter and used as the input signal V. In2 The remaining p-type WSe2 field-effect transistor (WSe2#3) and n-type MoS2 field-effect transistor (MoS2#3) form an inverter circuit. The output of the NAND circuit is connected to the input of the inverter circuit. The output signal V... OUT This measures the voltage drop across the MoS2#3 field-effect transistor (i.e., the output of the inverter), measured using a Keithley 2182 source meter.

[0087] "OR" logic device testing methods: such as Figure 6 As shown in Figure b, a NOR circuit is formed by combining two p-type WSe2 field-effect transistors (WSe2#1 and WSe2#2) and two n-type MoS2 field-effect transistors (MoS2#1 and MoS2#2). The source-drain voltage is provided by a Keithley 2400 source meter. WSe2#1 and MoS2#2 use the same bottom gate, and the gate voltage is applied by another Keithley 2400 source meter and used as the input signal V. In1WSe2#2 and MoS2#1 use the same bottom gate, and the gate voltage is applied by a third Keithley 2400 source meter and used as the input signal V. In2 The remaining p-type WSe2 field-effect transistor (WSe2#3) and one n-type MoS2 field-effect transistor (MoS2#3) form an inverter circuit. The output of the NOR circuit is connected to the input of the inverter circuit, and the output signal V... OUT This measures the voltage drop across the MoS2#3 field-effect transistor (i.e., the output of the inverter), measured using a Keithley 2182 source meter.

[0088] Experimental results: Taking the logic "NAND" gate circuit as an example, if two input signals V IN1 and V IN2 If any one of the inputs is logic "0" (i.e., an input logic combination of "0-0", "0-1", or "1-0"), then at least one of the p-type WSe2 field-effect transistors WSe2#1 and WSe2#2 will be in the on state, while both the n-type MoS2 transistors MoS2#1 and MoS2#2 will be in the off state. Therefore, when the output terminal is connected to the power supply, the output signal V... OUT The input signal V will be high, so the logic gate outputs a logic "1". In contrast, the output signal V will only be high if the input signal V is high. IN1 and V IN2 When both inputs are logic "1" (i.e., an input "1-1" logic combination), the p-type WSe2 field-effect transistors WSe2#1 and WSe2#2 will operate in the off state, while the n-type MoS2 field-effect transistors MoS2#1 and MoS2#2 will operate in the on state. Therefore, when the output terminal is connected to the signal ground, the output signal V... OUT The gate will be at a low level, and the logic gate will output a logic "0". This logic operation is indicated by the sequence in which different input signals are applied, such as... Figure 5 As shown in diagram a, each cycle contains four logic combinations. It can be seen that in each cycle, only when the input logic combination is "1-1" can an output logic of "1" be generated. This corresponds exactly to the operation of a NAND gate. Similarly, in a NOR gate, only when the input logic combination is "0-0" can an output logic of "1" be generated. This corresponds exactly to the operation of a NOR gate, as shown in diagram a. Figure 5 As shown in b. Similarly, in an AND gate, only when the input logic combination is "1-1" can it produce an output logic of "1". This corresponds exactly to the operation of an AND gate, such as... Figure 6 As shown in diagram a. In an OR gate, only when the input logic combination is "0-0" can it produce an output logic of "0". This corresponds exactly to the operation of an OR gate, as shown in diagram a. Figure 6As shown in b, high-performance NAND, NOR, AND, and OR logic gates can all be implemented by combining fluoride-gated n-type MoS2 transistors and p-type WSe2 transistors, demonstrating the strong potential of fluoride dielectric materials in constructing logic circuits.

[0089] Example 6

[0090] Air stability testing based on fluoride superionic conductor dielectric films

[0091] To further provide evidence of the reversibility and stability of metal fluoride-based TMDC field-effect transistors, this embodiment uses WSe2 as the channel material to fabricate an NdF3-WSe2 field-effect transistor as reference Example 2. After 500 cycles of switching operation and exposure to air for six months, the Raman peak positions of the two-dimensional channel material were examined. Figure 7 As shown, the channel material WSe2 and A 1g The Raman peak positions remained unchanged in the Raman mode, indicating that no chemical reaction occurred between the metal fluoride film and the channel TMDC material even in an atmospheric environment, demonstrating the air and chemical stability of the fluoride. STEM and EDX measurements were also performed on samples of the TMDC channel material in metal fluoride-gated field-effect transistors. Figure 8 As shown, after 500 switching cycles, a clear fluoride / TMDC interface is still visible, and the perfect lattice of the material remains intact, with no obvious degradation, defect clusters, or cracks. Based on EDX measurements, it is confirmed that after modulation of positive and negative gate voltages, no fluoride ion insertion or electrochemical reaction occurs in the TMDC channel material of the metal fluoride gate dielectric field-effect transistor, demonstrating the excellent stability of metal fluoride as a dielectric layer material for field-effect transistors.

Claims

1. A field-effect transistor, comprising, from bottom to top, a substrate, a gate electrode, a dielectric layer, a channel layer, and source / drain electrodes deposited on the upper surface of the channel layer, characterized in that, The dielectric layer is a metal fluoride superionic conductor film; the conductivity of the metal fluoride superionic conductor film is 10. -5 -10 -2 S / cm, low-frequency capacitance is 1-25 μF / cm 2 The high-frequency capacitance is 0.02-1 μF / cm. 2 Leakage current density less than 10 -5 A / cm 2 The root mean square surface roughness is less than 1 nm, and the fluorine vacancy content is 0.01%-15%. The metal fluoride superionic conductor film is prepared by thermal evaporation of a metal fluoride superionic conductor. The thermal evaporation process is as follows: First, the metal fluoride superionic conductor is ground, and then placed on the heating column of the thermal evaporation system. When the system vacuum reaches 10... −5 When the pressure is below Pa, evaporation begins. The metal fluoride is evaporated and deposited on the substrate surface at a rate of 0.2 Å / s-0.4 Å / s until the thickness reaches 10 nm-20 nm. The rate is then adjusted to 0.8 Å / s-1 Å / s until the target thickness is reached. During the evaporation process, the temperature of the substrate is controlled at 200 K-600 K. The metal fluoride superionic conductor is selected from one or more of the following: lanthanum fluoride, cerium fluoride, neodymium fluoride, samarium fluoride, europium fluoride, gadolinium fluoride, holmium fluoride, erbium fluoride, ytterbium fluoride, scandium fluoride, yttrium fluoride, titanium fluoride, hafnium fluoride, manganese fluoride, ferrous fluoride, nickel fluoride, and tin fluoride. The channel layer is a two-dimensional semiconductor material.

2. An inverter, characterized in that, It includes a first transistor and a second transistor; the first transistor and the second transistor are field-effect transistors as described in claim 1; The gates of the first transistor and the second transistor are connected; the drain of the first transistor is connected to the power supply voltage; the source of the second transistor is grounded, and its drain is connected to the source of the first transistor and connected to the output terminal.

3. A logic AND-OR gate, characterized in that, It includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are the field-effect transistors as described in claim 1; wherein: The source of the fourth transistor is connected to ground; The drain of the fourth transistor is connected to the source of the second transistor; The sources of the first and third transistors are connected to the drain of the second transistor, and connected to the output terminal V. out ; The drains of the first and third transistors are connected to the power supply voltage; The gates of the first and second transistors are connected together and connected to the input terminal V. IN1 The gates of the third and fourth transistors are connected to the input terminal V. IN2 .

4. A logic "NOR" gate, characterized in that, It includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are the field-effect transistors as described in claim 1; wherein: The sources of the fourth and second transistors are connected to ground; The drains of the fourth and second transistors are connected to the source of the third transistor, and are connected to the output terminal V. out ; The drain of the third transistor is connected to the source of the first transistor; The drain of the first transistor is connected to the power supply voltage; The gates of the first and fourth transistors are connected to the input terminal V. IN1 The gates of the third and second transistors are connected to the input terminal V. IN2 .

5. A logical AND gate, characterized in that, It includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are the field-effect transistors as described in claim 1; wherein: The sources of the fourth and sixth transistors are connected to ground; The drain of the fourth transistor is connected to the source of the second transistor; The sources of the first and third transistors are connected to the drain of the second transistor, and to the gates of the fifth and sixth transistors. The drains of the first, third, and fifth transistors are connected to the power supply voltage. The gates of the first and second transistors are connected together and connected to the input terminal V. IN1 The gates of the third and fourth transistors are connected to the input terminal V. IN2 ; The drain of the sixth transistor is connected to the source of the fifth transistor, and then connected to the output terminal V. out .

6. A logic OR gate, characterized in that, It includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are the field-effect transistors as described in claim 1; wherein: The sources of the fourth, second, and sixth transistors are connected to ground; The drains of the fourth and second transistors are connected to the source of the third transistor, and to the gates of the fifth and sixth transistors. The drain of the third transistor is connected to the source of the first transistor; The drains of the first and fifth transistors are connected to the power supply voltage; The gates of the first and fourth transistors are connected to the input terminal V. IN1 The gates of the third and second transistors are connected to the input terminal V. IN2 , The drain of the sixth transistor is connected to the source of the fifth transistor, and then connected to the output terminal V. out .

7. A logic circuit comprising at least one logic device, characterized in that, The logic device is the inverter of claim 2, the logical AND-OR gate of claim 3, the logical NOR gate of claim 4, the logical AND gate of claim 5, or the logical OR gate of claim 6.

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