Semiconductor structure

Abstract

A semiconductor structure includes a substrate. A first contact structure is disposed on the substrate, the first contact structure including a T-shaped cross-sectional shape and including a first portion in contact with the substrate and a second portion on the first portion. Two first gate structures are disposed on the substrate and on either side of the first contact structure, wherein a top surface of the first contact structure is flush with top surfaces of the two first gate structures.

Description

[0001] This application is a divisional application of Chinese patent application filed on June 23, 2021 (original application number: 2021106975645, invention title: semiconductor structure and method of fabrication thereof), the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to a semiconductor structure. More specifically, this invention relates to a dynamic random access memory (DRAM) including a memory region and a peripheral region. Background Technology

[0003] Dynamic Random Access Memory (DRAM) is a type of volatile memory. A DRAM device typically includes a memory region consisting of an array of memory cells and a peripheral region consisting of peripheral circuitry for controlling the operation of the memory cells and / or repairing faulty blocks in the memory region. The control circuitry in the peripheral region can address and electrically connect to each memory cell across multiple word lines and bit lines within the memory region to perform data reads, writes, or erases. In advanced semiconductor manufacturing, by employing an architecture with buried word lines or buried bit lines, the chip size of DRAM devices can be significantly reduced. This architecture allows the active regions of the memory cells to be arranged at a denser pitch, achieving higher cell density.

[0004] DRAM typically includes a peripheral region containing peripheral circuitry used to control the operation of memory cells and / or repair faulty blocks within the memory region. During DRAM manufacturing, the memory cells and the peripheral circuitry are formed simultaneously using the same manufacturing process. Therefore, it is crucial to provide peripheral circuitry that is compatible with the manufacturing process of the memory cells. Summary of the Invention

[0005] One objective of this invention is to provide a semiconductor structure and its fabrication method. The semiconductor structure includes a memory region and a peripheral region, and the peripheral region includes a shared contact structure. This shared contact structure and the storage node contact of the memory region are formed simultaneously using the same manufacturing process. This shared contact structure can be used to simultaneously electrically connect two gate structures and a common source / drain terminal between them. For example, it can be applied in a fuse circuit of a peripheral circuit to repair abnormal blocks in the memory region. This facilitates the simultaneous fabrication of the peripheral circuit and the memory cell, thus resulting in a simplified manufacturing process.

[0006] An embodiment of the present invention provides a semiconductor structure including a substrate. A first contact structure is disposed on the substrate, the first contact structure having a T-shaped cross-section and including a first portion in contact with the substrate and a second portion located on the first portion. Two first gate structures are disposed on the substrate and located on both sides of the first contact structure, wherein a top surface of the first contact structure is flush with the top surfaces of the two first gate structures.

[0007] Another embodiment of the present invention provides a semiconductor structure including a substrate and a first contact structure disposed on the substrate and including a T-shaped cross-section. Two first gate structures are disposed on the substrate and located on both sides of the first contact structure, wherein each of the two first gate structures includes an electrode portion and a hard mask portion located on the electrode portion. An outer gap wall is disposed on the outer side of the two first gate structures relative to the first contact structure, wherein the first contact structure directly contacts the electrode portion of the two first gate structures.

[0008] Another embodiment of the present invention provides a method for fabricating a semiconductor structure, the steps of which include forming two first gate structures on a substrate, forming a spacer wall on the sidewalls of the two first gate structures, forming a dielectric layer on the substrate to cover the two first gate structures and the spacer wall, and performing a contact hole etching process to etch the dielectric layer and part of the spacer wall located between the two first gate structures, thereby forming a first contact hole between the two first gate structures to expose part of the substrate, wherein the first contact hole includes a T-shaped cross-section. Attached Figure Description

[0009] The accompanying drawings provide a more detailed understanding of this embodiment and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams for illustrative and drawing convenience, and relative dimensions and scales have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0010] Figure 1 This is a top view of a semiconductor structure according to an embodiment of the present invention.

[0011] Figures 2 to 9 This is a cross-sectional schematic diagram of the steps in a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0012] Figure 10 This is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention.

[0013] The reference numerals in the attached figures are explained as follows:

[0014] 100 Semiconductor Structure

[0015] 10 Substrates

[0016] 10A Outer Area

[0017] 10B memory area

[0018] AA First Component Region

[0019] BB Second Component Area

[0020] CC memory area

[0021] G1 First Gate Structure

[0022] G2 Second Gate Structure

[0023] BL bitline

[0024] 14. Isolation Structure

[0025] 161 doped region

[0026] 162 doped region

[0027] 22 Lower gate portion

[0028] 24 Upper gate portion

[0029] 26 Hard Mask Section

[0030] 32. Spacer wall

[0031] 34 First dielectric layer

[0032] 36 Second dielectric layer

[0033] 38 Patterned Mask Layers

[0034] 38a Mask opening

[0035] 42 First Contact Cave

[0036] 42a Part 1

[0037] 42b Part Two

[0038] 44 Second Contact Hole

[0039] 46 Storage Node Contact Holes

[0040] 47 Semiconductor Materials

[0041] 52 Conductive layer

[0042] C1 First contact structure

[0043] C2 Second Contact Structure

[0044] SNC storage node contact

[0045] CP pad section

[0046] SNCP pad section

[0047] 54 Passivation layer

[0048] 62 Interlayer Dielectric Layer

[0049] E1 Contact Hole Etching Process

[0050] E2 recessed process

[0051] S1 Inner Spacer Wall

[0052] S2 outer spacer wall

[0053] W1 First Width

[0054] W2 Second Width Detailed Implementation

[0055] To enable those skilled in the art to further understand this invention, preferred embodiments are described below, along with accompanying drawings, to explain in detail the structure and desired effects of the invention. It should be understood that the following embodiments can be modified by substituting, recombining, or mixing features from several different embodiments without departing from the spirit of this disclosure to achieve other embodiments.

[0056] Figure 1 This is a schematic top view of a semiconductor structure 100 according to an embodiment of the present invention. Figure 1 As shown, the semiconductor structure 100 includes a substrate 10, which defines a peripheral region 10A and a memory region 10B. Figure 1 The shapes and arrangements of the peripheral region 10A and memory region 10B shown are merely illustrative examples and are not intended to limit the invention.

[0057] Peripheral region 10A may include peripheral circuitry for controlling the operation of memory cells and signal input / output in memory region 10B. For example, peripheral circuitry may include, but is not limited to, drivers, buffers, amplifiers, and decoders. Peripheral region 10A may also include peripheral circuitry, such as fuse circuits, for repairing abnormal blocks in memory region 10B. Memory region 10B may include an array of memory cells, such as an array of memory cells in dynamic random access memory (DRAM). The circuitry elements of the peripheral circuitry in peripheral region 10A and the memory cells in memory region 10B are integrated onto substrate 10 using the same manufacturing process.

[0058] Figures 2 to 9 This is a cross-sectional schematic diagram of the steps in fabricating a semiconductor structure 100 according to an embodiment of the present invention. Figures 2 to 9 The semiconductor structure 100 shown has a substrate 10, and as shown in the figure. Figure 1 The peripheral region 10A and memory region 10B are defined on the substrate 10. Figures 2 to 9 The left side is a cross-sectional view of the first element region AA of the peripheral region of the semiconductor structure 100. Figures 2 to 9 The middle part is a cross-sectional view of the second element region BB of the outer region of the semiconductor structure 100. Figures 2 to 9 The right side is a cross-sectional view of the memory region CC of the semiconductor structure 100.

[0059] Please refer to Figure 2 The method for fabricating the semiconductor structure 100 first includes providing a substrate 10. A plurality of isolation structures 14 (e.g., shallow trench isolation structures) are formed in the substrate 10 to define a plurality of active regions in the substrate 10, such as defining active regions for each circuit element (not shown) in the peripheral region and defining active regions for each memory cell (not shown) in the memory region. In addition, a plurality of buried word lines (not shown) may be provided in the memory region of the substrate 10 to cut through the active regions of each memory cell (not shown).

[0060] Next, using the same semiconductor processes such as deposition, photolithography, and etching, two first gate structures G1 can be formed simultaneously on the substrate 10 of the first element region AA, a second gate structure G2 can be formed on the substrate 10 of the second element region BB, and multiple bit lines BL can be formed on the substrate 10 of the memory region CC. For example, a semiconductor material layer (not shown), a conductive material layer (not shown), and a hard mask material layer (not shown) can be sequentially formed on the substrate 10. Then, a patterning process (e.g., photolithography-etching process) is performed to etch away part of the hard mask material layer to pattern the hard mask material layer. Then, the patterned hard mask material layer is used as an etching mask to etch the conductive material layer and semiconductor material layer below to pattern the conductive material layer and semiconductor material layer. In this way, the first gate structure G1, the second gate structure G2, and the bit lines BL can be fabricated simultaneously on the substrate 10.

[0061] like Figure 2As shown, the first gate structure G1, the second gate structure G2, and the bit line BL each include a lower gate portion 22, an upper gate portion 24 located on the lower gate portion 22, and a hard mask portion 26 located on the upper gate portion 24. According to an embodiment of the present invention, the material of the lower gate portion 22 may include a semiconductor material, such as polysilicon, and the material of the upper gate portion 24 may be a conductive material, such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium-aluminum alloy (TiAl), or other low-resistivity metal materials. The material of the hard mask portion 26 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or other suitable dielectric materials. A gate dielectric layer (not shown) may be provided between the substrate 10 and the lower gate portion 22 of the first gate structure G1, and between the substrate 10 and the lower gate portion 22 of the second gate structure G2.

[0062] Please refer to Figure 3 Next, spacer walls 32 are formed on the sidewalls of the first gate structure G1, the second gate structure G2, and the bit line BL. Then, doped regions 161 and 162 are formed in the substrate 10 between the first gate structures G1 and in the substrates 10 on both sides of the second gate structure G2, respectively. It should be understood that... Figure 3 The shapes and formation areas of doped regions 161 and 162 shown are merely examples and are not intended to limit the invention. Next, a first dielectric layer 34 is formed on the substrate 10, and then a planarization process is performed on the first dielectric layer 34 to remove a portion of the first dielectric layer 34 until the top surfaces of the first gate structure G1, the second gate structure G2, and the bit line BL are exposed. Then, a second dielectric layer 36 is formed to completely cover the first dielectric layer 34 and the exposed top surfaces of the first gate structure G1, the second gate structure G2, and the bit line BL. According to one embodiment of the invention, the materials of the first dielectric layer 34 and the second dielectric layer 36 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or other suitable dielectric materials. According to one embodiment of the invention, the first dielectric layer 34 and the second dielectric layer 36 may include different dielectric materials; for example, the first dielectric layer 34 may include silicon oxide (SiO2), and the second dielectric layer 36 may include silicon nitride (SiN), but are not limited thereto.

[0063] According to an embodiment of the present invention, the spacer wall 32 can be formed by the following steps. First, at least one spacer wall material layer (not shown) is deposited on the substrate 10 to conformally cover the top surface and sidewalls of the substrate 10, the first gate structure G1, the second gate structure G2, and the bit line BL. Then, the spacer wall material layer is etched (e.g., dry etching) to anisotropically remove excess portions of the spacer wall material layer, leaving a portion of the remaining spacer wall material layer covering the sidewalls of the first gate structure G1, the second gate structure G2, and the bit line BL, thus forming the spacer wall 32. The material of the spacer wall 32 may include silicon nitride (SiN), silicon oxide (SiON), silicon carbonitride (SiCN), or other dielectric materials, and may have a single-layer or multi-layer structure. In the following description, the spacer wall 32 disposed on the inner side of the two first gate structures G1 (that is, formed between the first gate structures G1, located on the adjacent sidewalls of the two first gate structures G1) is also referred to as the inner spacer wall S1. The spacer wall 32 disposed on the outer side of the two first gate structures G1 (that is, formed on the side wall of the first gate structure G1 relative to the inner spacer wall S1) is also called the outer spacer wall S2.

[0064] Please refer to Figure 4 Next, a patterned mask layer 38 is formed on the second dielectric layer 36. The patterned mask layer 38 includes a plurality of mask openings 38a that expose a portion of the surface of the second dielectric layer 36.

[0065] Please refer to Figure 5 Next, a contact hole etching process E1 (e.g., dry etching) is performed using the patterned mask layer 38 as an etching mask to etch and remove the portions of the second dielectric layer 36 and the first dielectric layer 34 exposed from the mask opening 38a, thereby simultaneously forming the first contact hole 42 located in the first element region AA, the second contact hole 44 located in the second element region BB, and the memory node contact hole 46 located in the memory region CC. More specifically, as... Figure 5 As shown, the first contact hole 42 is located between the two first gate structures G1, passing through the second dielectric layer 36 and the first dielectric layer 34, and exposing a portion of the doped region 161 of the substrate 10. The second contact hole 44 is located on both sides of the second gate structure G2, passing through the second dielectric layer 36 and the first dielectric layer 34, and exposing a portion of the doped region 162 of the substrate 10 on both sides of the second gate structure G2. The memory node contact hole 46 is located between the bit lines BL, passing through the second dielectric layer 36 and the first dielectric layer 34, and exposing a portion of the substrate 10 (the active region of the memory cell) between the bit lines BL.

[0066] According to one embodiment of the present invention, the hard mask portion 26 of the first gate structure G1 can be partially removed in the contact hole etching process E1, so that the first contact hole 42 can have a T-shaped cross-sectional shape. For example... Figure 5 As shown in the left portion, the first contact hole 42 may include a first portion 42a having a first width W1 and a second portion 42b located above the first portion 42a and having a second width W2, wherein the first width W1 is smaller than the second width W2. The first portion 42a exposes the substrate 10 between the two first gate structures G1. The second portion 42b exposes the top surface of the upper gate portion 24 of the two first gate structures G1 and the sidewall of the hard mask portion 26.

[0067] According to one embodiment of the present invention, during the contact hole etching process E1, the inner gap wall S1 located between the two first gate structures G1 can be partially etched away, so that the sidewalls of the lower gate portion 22 and the upper gate portion 24 of the first gate structure G1 can be exposed from the first portion 42a of the first contact hole 42.

[0068] Please refer to Figure 6 Next, the patterned mask layer 38 is removed, and a semiconductor material 47 is selectively formed at the bottom of the memory node contact hole 46 in the memory region CC. Then, a conductive layer 52 is formed to completely cover the second dielectric layer 36 and completely fill the first contact hole 42, the second contact hole 44, and the memory node contact hole 46. According to one embodiment of the present invention, the material of the conductive layer 52 may include a metal, such as tungsten (W).

[0069] Please refer to Figure 7 Next, another patterned mask layer (not shown) is formed on the conductive layer 52. This patterned mask layer (not shown) is then used as an etching mask to perform a recess process E2 to etch and pattern the conductive layer 52 and the second dielectric layer 36. This simultaneously forms a first contact structure C1 located in the first contact hole 42, a second contact structure C2 located in the second contact hole 44 and including a pad portion CP on the second contact hole 44, and a memory node contact SNC located in the memory node contact hole 46 and including a pad portion SNCP on the memory node contact hole 46. It is noteworthy that the first contact structure C1, the second contact structure C2, and the memory node contact SNC obtained through the recess process E2 are all integrally formed structures.

[0070] According to one embodiment of the present invention, such as Figure 7 As shown, the top surface of the conductive layer 52 of the first contact structure C1 is approximately flush with the top surface of the hard mask portion 26, the top surface of the outer gap wall S2, and the top surface of the first dielectric layer 34.

[0071] Please refer to Figure 8Next, a passivation layer 54 is formed covering the first contact structure C1, the second contact structure C2, and the memory node contact SNC. Then, an etching process (e.g., dry etching) is performed to remove a portion of the passivation layer 54 until the top surface of the first contact structure C1, the top surface of the pad portion CP of the second contact structure C2, and the top surface of the pad portion SNCP of the memory node contact SNC are exposed. A portion of the remaining passivation layer 54 forms a gap wall along the sidewalls of the pad portion CP and the sidewalls of the second dielectric layer 36 beneath the pad portion CP, while another portion of the remaining passivation layer 54 completely fills the gaps between the pad portions SNCP. According to one embodiment, the material of the passivation layer 54 may include silicon nitride (SiN).

[0072] Please refer to Figure 9 Next, an interlayer dielectric layer 62 is formed to cover the first contact structure C1, the second contact structure C2, and the memory node contact SNC, filling the gaps between the pad portions CP of the second contact structure C2. The material of the interlayer dielectric layer 62 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or other dielectric materials. Next, the interlayer dielectric layer 62 may be planarized, and then multiple interconnect structures (not shown) are formed in the interlayer dielectric layer 62 for electrical connection with the pad portions CP of the first contact structure C1, the second contact structure C2, and the pad portions SNCP of the memory node contact SNC.

[0073] Please continue to refer to this. Figure 9 The semiconductor structure 100 provided by the present invention may include a substrate 10, which may define a peripheral region 10A and a memory region 10B. A first contact structure C1 is disposed on a first element region AA of the substrate 10. The first contact structure C1 has an integrally formed structure and a T-shaped cross-sectional shape, which includes a first portion C1b that directly contacts the substrate 10 and a second portion C1a located on the first portion C1b. The width W4 of the second portion C1a is greater than the width W3 of the first portion C1b.

[0074] Two first gate structures G1 are disposed on the substrate 10 and located on both sides of the first contact structure C1. Each first gate structure G1 includes a lower gate portion 22 on the substrate 10, an upper gate portion 24 on the lower gate portion 22, and a hard mask portion 26 on the upper gate portion 24. The lower gate portion 22 and the upper gate portion 24 can be collectively referred to as the electrode portions of the first gate structure G1. Figure 9 As shown, the top surface of the first contact structure C1 (i.e., the top surface of the second part C1a of the first contact structure C1) is approximately flush with the top surface of the first gate structure G1 (i.e., the top surface of the hard mask part 26 of the first gate structure G1).

[0075] The first portion C1b of the first contact structure C1 directly contacts the sidewalls of the lower gate portion 22 and the upper gate portion 24 of the first gate structure G1. The second portion C1a of the first contact structure C1 directly contacts the top surface of the upper gate portion 24 and the sidewall of the hard mask portion 26 of the first gate structure G1. The first contact structure C1 can be used as a shared contact structure, simultaneously electrically connecting the two first gate structures G1 on both sides and the substrate 10 between the first gate structures G1. According to an embodiment of the present invention, the first contact structure C1 can be used to simultaneously electrically connect the two first gate structures G1 and the common source / drain region (doped region 161) between the two first gate structures G1, which can reduce the layout area occupied by the peripheral circuit and achieve the effect of reducing the area of ​​the peripheral region. According to an embodiment of the present invention, the first contact structure C1 can be applied in the fuse circuit of the peripheral circuit for repairing abnormal blocks in the memory region.

[0076] According to one embodiment of the present invention, the semiconductor structure 100 may further include two inner spacer walls S1 disposed on the substrate 10 and sandwiched between the first portion C1b of the first contact structure C1 and the first gate structure G1 on both sides and the substrate 10. The top surface of the inner spacer wall S1 is lower than the top surface of the upper gate portion 24 of the first gate structure G1, that is, the top surface of the inner spacer wall S1 is lower than the top surface of the electrode portion of the first gate structure G1.

[0077] According to one embodiment of the present invention, the semiconductor structure 100 may further include two outer spacer walls S2 disposed on the substrate 10 and respectively located on the sidewalls of the two first gate structures G1 relative to the inner spacer wall S1. The outer spacer walls S2 completely cover the sidewalls of the lower gate portion 22 and the upper gate portion 24 of the first gate structure G1 relative to the inner spacer wall S1, and cover at least a portion of the hard mask portion 26 of the first gate structure G1 relative to the sidewall of the first contact structure C1.

[0078] According to one embodiment of the present invention, the semiconductor structure 100 may further include a second gate structure G2 disposed on the second element region BB of the substrate 10, and two second contact structures C2 disposed on the substrate 10 and located on both sides of the second gate structure G2. The second contact structures C2 may each include a lower portion directly contacting the substrate 10 and surrounded by a first dielectric layer 34, and an upper portion located above the lower portion and surrounded by a second dielectric layer 36. The pad portion CP of the second contact structure C2 may extend laterally and cover the top surface of the second dielectric layer 36 surrounding the upper portion of the second contact structure C2.

[0079] According to one embodiment of the present invention, the semiconductor structure 100 may further include multiple bit lines BL disposed on a memory region CC of the substrate 10, and multiple memory node contacts SNC disposed on the substrate 10 and located between the bit lines BL. Each memory node contact SNC may include a lower portion directly contacting the substrate 10 and surrounded by a first dielectric layer 34, and an upper portion located above the lower portion and surrounded by a second dielectric layer 36. The pad portion SNCP of the memory node contact SNC may extend laterally and cover the top surface of the second dielectric layer 36 surrounding the upper portion of the memory node contact SNC.

[0080] According to one embodiment of the present invention, the top surface of the pad portion CP of the second contact structure C2 and the top surface of the pad portion SNCP of the storage node contact SNC are substantially flush with each other and both are higher than the top surface of the first contact structure C1 (the top surface of the second portion 42b).

[0081] Please refer to Figure 10 This is a schematic cross-sectional view of a semiconductor structure 100 according to another embodiment of the present invention. For the sake of simplicity, Figure 10 The semiconductor structure 100 shown and Figure 7 The same components of the semiconductor structure 100 shown are marked with the same symbols. Figure 10 The semiconductor structure 100 shown is Figure 7 The main difference of the semiconductor structure 100 shown is that, Figure 10 When the semiconductor structure 100 is subjected to the contact hole etching process E1, the inner spacer wall S1 can be completely removed. Therefore, the first part C1b of the first contact structure C1 can directly contact the bottom sidewall of the first gate structure G1, thereby directly contacting the bottom sidewall of the lower gate portion 22.

[0082] In summary, the semiconductor structure and its fabrication method provided by this invention include contact structures of different forms for peripheral circuits, namely a first contact structure C1 and a second contact structure, which can be applied to different circuit elements of the peripheral circuit, for example, as a common contact structure that simultaneously electrically connects the common source / drain terminals between two gate structures, or as a contact structure that only connects the source / drain terminals of a transistor. The contact structures of the peripheral circuits provided by this invention are fabricated simultaneously using the same manufacturing process as the memory node contacts of the memory cell, thus simplifying the manufacturing process.

[0083] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a peripheral region and a memory region; A first contact structure is disposed on the peripheral region of the substrate, the first contact structure including a first portion that contacts the substrate and a second portion located on the first portion, the width of the first portion being smaller than that of the second portion; and Two first gate structures are disposed on the peripheral region of the substrate and located on both sides of the first contact structure; The two first gate structures each include: a lower gate portion; an upper gate portion located on the lower gate portion; and a hard mask portion located on the upper gate portion; the first portion of the first contact structure directly contacts the side surface of the two first gate structures, and the second portion of the first contact structure directly contacts the top surface of the upper gate portion of the two first gate structures. Multiple bit lines are disposed on the memory region of the substrate, and multiple memory node contacts are disposed on the memory region of the substrate and located between the bit lines; wherein the top surface of the memory node contacts is higher than the top surface of the first contact structure.

2. The semiconductor structure as described in claim 1, characterized in that, The first part of the first contact structure directly contacts one side wall of the lower gate portion and one side wall of the upper gate portion.

3. The semiconductor structure as described in claim 2, characterized in that, The first portion of the first contact structure is in direct contact with the bottommost part of the lower gate portion.

4. The semiconductor structure as described in claim 2, characterized in that, Also includes: Two inner gap walls are disposed on the substrate and are respectively sandwiched between the first portion of the first contact structure and the two first gate structures, wherein the top surface of the two inner gap walls is lower than the top surface of the upper gate portion of the two first gate structures.

5. The semiconductor structure as described in claim 2, characterized in that, Also includes: Two outer spacer walls are respectively disposed on one side of the two first gate structures relative to the two inner spacer walls, wherein the lower gate portion and the upper gate portion of the two first gate structures are completely covered by one of the two outer spacer walls, and the hard mask portion of the two first gate structures is at least partially covered by one of the two outer spacer walls.

6. The semiconductor structure as described in claim 1, characterized in that, The first contact structure has a one-piece molded structure.

7. A semiconductor structure, characterized in that, include: A substrate, the substrate including a peripheral region and a memory region; A first contact structure is disposed on the peripheral region of the substrate, including a first portion in contact with the substrate and a second portion located on the first portion, wherein the width of the first portion is smaller than the width of the second portion; Two first gate structures are disposed on the peripheral region of the substrate and located on both sides of the first contact structure. Each of the two first gate structures includes a semiconductor portion, an electrode portion located on the semiconductor portion, and a hard mask portion located on the electrode portion. An outer gap wall is disposed on the outside of the two first gate structures relative to the first contact structure; Two inner gap walls are disposed between the first contact structure and the two first gate structures, and the top surface of the inner gap wall is lower than the top surface of the semiconductor portion. The first contact structure directly contacts the electrode portion and the semiconductor portion of the two first gate structures; Multiple bit lines are disposed on the memory region of the substrate, and multiple memory node contacts are disposed on the memory region of the substrate and located between the bit lines; wherein the top surface of the memory node contacts is higher than the top surface of the first contact structure.

8. The semiconductor structure as described in claim 7, characterized in that, The first contact structure directly contacts the top surface of the electrode portion of the two first gate structures, and the top surface of the first contact structure is flush with the top surface of the hard mask portion of the two first gate structures.

9. The semiconductor structure as described in claim 7, characterized in that, An inner gap wall is disposed on the inner side of the two first gate structures adjacent to the first contact structure, wherein a top surface of the inner gap wall is lower than the top surface of the electrode portion of the two first gate structures.

10. A semiconductor structure, characterized in that, include: A substrate, the substrate including a peripheral region and a memory region; Two first gate structures are disposed on the peripheral region of the substrate; The first gate structure comprises, from bottom to top: a lower gate portion, an upper gate portion, and a gate dielectric material layer, wherein the upper gate portion and the lower gate portion are made of different materials; A first contact structure is disposed between two first gate structures, wherein the first contact structure directly contacts the sidewall of the lower gate portion, the sidewall of the upper gate portion, the top surface of the upper gate portion, and the sidewall of the gate dielectric material layer. Wherein, the topmost surface of the first contact structure is not higher than the topmost surface of the two first gate structures; Multiple bit lines are disposed on the memory region of the substrate, and multiple memory node contacts are disposed on the memory region of the substrate and located between the bit lines; wherein the top surface of the memory node contacts is higher than the top surface of the first contact structure.

11. The semiconductor structure as claimed in claim 10, characterized in that, Also includes: Two inner gap walls are disposed on the substrate and sandwiched between the first contact structure and the two first gate structures, wherein the top surface of the two inner gap walls is lower than the top surface of the upper gate portion of the two first gate structures.

12. The semiconductor structure as claimed in claim 10, characterized in that, The first contact structure has a one-piece molded structure.

Images