Semiconductor device
By employing word line structures of varying thicknesses and dummy word line designs in semiconductor devices, the problem of reduced reliability in semiconductor devices during miniaturization and the increasing complexity of integrated circuits has been solved, thereby improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2024-05-30
- Publication Date
- 2026-07-07
AI Technical Summary
As semiconductor devices become miniaturized and integrated circuits become more complex, the density, size deviation, and positional offset of the pattern structure have an increasing impact on device performance, leading to a decrease in the reliability of semiconductor devices.
In semiconductor devices, word line structures with different thicknesses are used, especially in the third direction perpendicular to the substrate, where the thickness of the second word line is greater than that of the first word line. By designing dummy word lines and insulating structures, the layout and thickness distribution of word lines are optimized to improve the reliability of the device.
By optimizing the word line structure, the reliability of semiconductor devices has been improved, and the performance and stability of the devices have been enhanced.
Smart Images
Figure CN118540944B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology
[0002] As semiconductor devices become miniaturized and integrated circuits become more complex, the size of semiconductor devices continues to decrease. With the increase in the integration level of semiconductor devices, the density, size deviation, and positional offset of the pattern structure in semiconductor devices have a growing impact on device performance, and the reliability of semiconductor devices gradually decreases. How to improve the reliability of semiconductor devices has become an urgent problem to be solved. Summary of the Invention
[0003] Based on this, a semiconductor device is provided to improve the reliability of the semiconductor device.
[0004] This disclosure provides a semiconductor device, including:
[0005] The substrate includes the first and second regions;
[0006] An isolation structure is located in the substrate, which isolates a plurality of spaced-apart first active regions in the substrate;
[0007] Multiple word lines are located in the substrate, each word line is spaced apart along the first direction and extends along a second direction in a plane parallel to the substrate and crosses multiple first active regions, the second direction intersects the first direction, and the word lines include first word lines located in the first region and second word lines located in the second region;
[0008] In a third direction perpendicular to the substrate, the thickness of at least one second word line in the first active region is greater than the thickness of the first word line.
[0009] In some embodiments, both the first word line and the second word line include:
[0010] The first work function layer is located in the substrate;
[0011] The second work function layer is located on the top surface of the first work function layer, and the top surface of the second work function layer is lower than the surface of the substrate.
[0012] In some embodiments, in the third direction, the thickness of the second power function layer of the second word line located in the first active region is greater than or equal to the thickness of the second power function layer of the first word line.
[0013] In some embodiments, the second word line is a dummy word line, and the number of dummy word lines is greater than or equal to 3.
[0014] In some embodiments, the semiconductor device further includes:
[0015] The second active region is located in the second region on the side away from the first region and is adjacent to several of the first active regions;
[0016] Among them, at least one of the second word lines crosses the second active region and the first active region respectively.
[0017] In some embodiments, the semiconductor device further includes:
[0018] An insulating structure is located in the substrate on the side of the second region away from the first region;
[0019] The third letter is located in the insulating structure, spaced apart from the second letter, and extends along the second direction.
[0020] In some embodiments, in the third direction, the bottom surface of the third character line is lower than the bottom surface of the first character line and the bottom surface of the second character line, respectively.
[0021] In some embodiments, in the third direction, the distance between the bottom surface of the insulating structure and the top surface of the first active region is greater than the distance between the bottom surface of the isolation structure and the top surface of the first active region.
[0022] In some embodiments, the semiconductor device further includes:
[0023] Multiple bit lines, each bit line being spaced apart along the second direction and extending along the first direction and crossing the insulating structure and multiple first active regions;
[0024] The bit line includes:
[0025] The bit line dielectric layer is located on the top surface of the insulating structure and extends along the first direction to the top surface of the first active region and the top surface of the isolation structure;
[0026] The bit line conductive layer extends from the top surface of the bit line dielectric layer into the first active region along the third direction, and extends to the top surface of the bit line dielectric layer along the first direction.
[0027] Wherein, the top surface of the bit line dielectric layer in the bit line located on the top surface of the insulating structure is not lower than the top surface of the bit line conductive layer.
[0028] In some embodiments, the word lines further include:
[0029] The fourth character line, located in the second zone, includes:
[0030] The first work function layer is located in the substrate;
[0031] Specifically, within the first active region, the distance between the top surface of the first work function layer in the fourth word line and the top surface of the first active region is equal to the distance between the top surface of the first work function layer in the first word line and the top surface of the first active region, and is also equal to the distance between the top surface of the first work function layer in the second word line and the top surface of the first active region; the top surface of the first work function layer in the fourth word line is the top surface of the fourth word line, the top surface of the second work function layer in the first word line is the top surface of the first word line, and the top surface of the second work function layer in the second word line is the top surface of the second word line.
[0032] In some embodiments, the second word line and the fourth word line cross the same first active region.
[0033] In the aforementioned semiconductor device, the word line includes a first word line located in the first region and a second word line located in the second region. In a third direction perpendicular to the substrate, the thickness of at least one second word line in the first active region is greater than the thickness of the first word line, thereby improving the reliability of the semiconductor device. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0035] Figure 1 This is a top view schematic diagram of the semiconductor device in some embodiments;
[0036] Figure 2 In some embodiments, the semiconductor device along Figure 1 A schematic cross-sectional view along the AA direction is shown.
[0037] Figure 3 This is a top view schematic diagram of the semiconductor device in some embodiments;
[0038] Figure 4 For some embodiments along Figure 3 A schematic cross-sectional view of the semiconductor device in the AA direction is shown.
[0039] Figure 5 For other embodiments along Figure 3 A schematic cross-sectional view of the semiconductor device in the AA direction is shown.
[0040] Figure 6 In some embodiments along Figure 3 A schematic cross-sectional view of the semiconductor device in the AA direction is shown.
[0041] Figure 7 This is a top view schematic diagram of the semiconductor device in some embodiments;
[0042] Figure 8 For some embodiments along Figure 7 A schematic cross-sectional view of a semiconductor device along the BB direction is shown.
[0043] Figure 9 This is a top view schematic diagram of the semiconductor device in some embodiments;
[0044] Figure 10 For some embodiments along Figure 9 The diagram shows a cross-sectional view of a semiconductor device along the BB direction.
[0045] Explanation of reference numerals in the attached figures:
[0046] Region 1, Region 2, Substrate 102, Isolation Structure 104, First Active Region 106, Word Line 108, Second Active Region 110, Insulating Structure 112, Gate Dielectric Layer 114, First Word Line 202, Second Word Line 204, Third Word Line 206, Fourth Word Line 208, Bit Line 210, First Work Function Layer 302, Second Work Function Layer 304, First Work Function Material 306, Barrier Layer 308, Bit Line Dielectric Layer 310, Bit Line Conductive Layer 312, First Work Function Layer 402, Second Work Function Layer 404, First Work Function Layer 502, Second Work Function Layer 504, First Work Function Layer 602. Detailed Implementation
[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0049] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first work function layer may be referred to as the second work function layer, and similarly, the second work function layer may be referred to as the first work function layer; the first work function layer and the second work function layer are different work function layers.
[0050] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0051] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0052] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.
[0053] Figure 1 This is a top view schematic diagram of a semiconductor device in some embodiments. Figure 2 In some embodiments, the semiconductor device along Figure 1 The cross-sectional diagram shown in the AA direction is exemplary. Figure 1 In the figure, the X direction is the first direction in the plane parallel to the base, the Y1 direction is the second direction in the plane parallel to the base, the Y2 direction is the third direction perpendicular to the base 1, and the Z direction is the fourth direction in the plane parallel to the base. The first direction X, the second direction Y1, and the fourth direction Z intersect each other.
[0054] like Figure 1 , Figure 2 As shown, in this embodiment, a semiconductor device is provided, including: a substrate 102, an isolation structure 104, and a plurality of word lines 108. The substrate 102 includes a first region 1 and a second region 2 adjacent along a first direction X in a plane parallel to the substrate 102; the isolation structure 104 is located in the substrate 102, isolating a plurality of spaced-apart first active regions 106 in the substrate 102; the word lines 108 are located in the substrate 102, each word line 108 is spaced-apart along the first direction X, and extends along a second direction Y1 in a plane parallel to the substrate 102 and crosses the plurality of first active regions 106, the second direction Y1 intersects the first direction X, and the word lines 108 include a first word line 202 located in the first region 1 and a second word line 204 located in the second region 2; wherein, in a third direction Y2 perpendicular to the substrate 102, the thickness of at least one second word line 204 in the first active region 106 is greater than the thickness of the first word line 202.
[0055] The substrate 102 includes a first region 1 and a second region 2 adjacent to each other in the first direction X. Exemplarily, the first region 1 is a device region, and the second region 2 is a peripheral region located on one side of the first region 1. The constituent materials of the substrate 102 include undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. As an example, in this embodiment, the constituent material of the substrate 102 is selected as single-crystal silicon.
[0056] The isolation structure 104 extends from the first surface of the substrate 102 into the substrate 102, isolating a plurality of first active regions 106 in the substrate 102. The subsequently formed device structure is located in the first active regions 106, which extend along the fourth direction Z. Exemplarily, the material of the isolation structure 104 includes one or more of silicon oxide (e.g., silicon dioxide), silicon nitride (e.g., silicon oxynitride), and nitride (e.g., silicon nitride).
[0057] The word line 108 extends along the second direction Y1, passing through the first active regions 106 arranged along the second direction Y1. It is understood that, in the fourth direction Z, the size of the isolation structure 104 between adjacent first active regions 106 is larger than the size of the word line 108 located between adjacent first active regions 106.
[0058] Furthermore, in the third direction Y2, the distance between the bottom surface of the word line 108 located in the first active region 106 and the first surface (i.e., the top surface of the first active region 106) is less than the distance between the bottom surface of the first active region 106 and the first surface (the thickness of the first active region 106 in the third direction Y2). Also, the distance between the bottom surface of the word line 108 located in the isolation structure 104 and the first surface (i.e., the top surface of the isolation structure 104) is less than the distance between the bottom surface of the isolation structure 104 and the first surface (the thickness of the isolation structure 104 in the third direction Y2). Adjacent word lines 108 are isolated by the isolation structure 104, thereby improving the performance of the semiconductor device.
[0059] In the aforementioned semiconductor device, the word line 108 includes a first word line 202 located in the first region 1 and a second word line 204 located in the second region 2. In a third direction Y2 perpendicular to the substrate 102, the thickness of at least one of the second word lines 204 in the first active region 106 is greater than the thickness of the first word line 202, thereby improving the reliability of the semiconductor device.
[0060] like Figure 1 , Figure 2As shown, in some embodiments, the first word line 202 includes: a first work function layer 302 and a second work function layer 304 stacked on a third direction Y2; the first work function layer 302 is located in the substrate 102; the second work function layer 304 is located on the top surface of the first work function layer 302, and the top surface of the second work function layer 304 is lower than the surface of the substrate 102; the second word line 204 includes: a first work function layer 402 and a second work function layer 404 stacked on a third direction Y2; the first work function layer 402 is located in the substrate 102; the second work function layer 404 is located on the top surface of the first work function layer 402, and the top surface of the second work function layer 404 is lower than the surface of the substrate 102. It can be understood that the top surface of the second work function layer 304 in the first word line 202 is the top surface of the first word line 202, and the top surface of the second work function layer 404 in the second word line 204 is the top surface of the second word line 204.
[0061] like Figure 2 As shown, in some embodiments, both the first work function layer 302 and the first work function layer 402 include a first work function material 306 and a barrier layer 308. The barrier layer 308 surrounds and contacts the side surface and bottom surface of the first work function material 306. The side surface of the first work function material 306 is the surface of the first work function material 306 in the third direction Y2.
[0062] For example, the materials of the second work function layer 304, the second work function layer 404, and the first work function material 306 include one or more of polycrystalline silicon, metal, metal nitride, metal oxide, and metal silicide, wherein the metal can be tungsten (W), nickel (Ni), or titanium (Ti); the metal nitride includes titanium nitride (TiN); the metal oxide includes iridium oxide (IrO2) and indium tin oxide (ITO); and the metal silicide includes titanium silicide (TiSi). The material of the barrier layer 308 includes titanium metal and titanium nitride. As an example, in this embodiment, the materials of the second work function layer 304 and the second work function layer 404 are polycrystalline silicon, and the material of the first work function material 306 is tungsten metal.
[0063] like Figure 2 As shown, in some embodiments, the distance between the top surface of the barrier layer 308 and the first surface is greater than or equal to the distance between the top surface of the first work function material 306 and the first surface. In this case, the bottom surface of the second work function layer 304 is in contact with the top surface of the barrier layer 308 and the top surface of the first work function material 306, respectively.
[0064] like Figure 2As shown, in some embodiments, on the third direction Y2, the thickness of the second power function layer 404 of the second word line 204 located within the first active region 106 is greater than or equal to the thickness of the second power function layer 304 of the first word line 202.
[0065] like Figure 2 As shown, in some embodiments, on the third direction Y2, the distance between the top surface of the first work function layer 402 of the second word line 204 located in the first active region 106 and the first surface of the substrate 102 is equal to the distance between the top surface of the first work function layer 302 of the first word line 202 located in the first active region 106 and the first surface.
[0066] like Figure 2 As shown, in some embodiments, the second character line 204 is a dummy character line, and the number of dummy character lines is greater than or equal to 3. It is understood that the specific number of second character lines 204 can vary depending on actual needs. Furthermore, the spacing between the dummy character lines is the same as the spacing between the first character lines 202. The dummy character lines and the first character lines 202 can be formed together using the same photolithography process. This simplifies the manufacturing process while maintaining the overall density of all character lines 108, preventing the manufacturing process of the first character lines 202 from being affected by the dummy character lines.
[0067] like Figure 1 , Figure 2 As shown, in some embodiments, the semiconductor device further includes: a second active region 110, located in the second region 2 on the side away from the first region 1, and the second active region 110 is adjacent to a plurality of the first active regions 106 in the second region 2; wherein at least one second word line 204 crosses the second active region 110 and the first active regions 106 respectively. It is understood that the second region 2 further includes the second active region 110.
[0068] Figure 3 This is a top view schematic diagram of a semiconductor device in some embodiments. Figure 4 For some embodiments along Figure 3 The diagram shows a cross-sectional view of a semiconductor device along the AA direction. Figure 5 For other embodiments along Figure 3 The diagram shows a cross-sectional view of a semiconductor device along the AA direction. Figure 6 In some embodiments along Figure 3 The schematic cross-sectional view of the semiconductor device in the AA direction is shown below. Figures 3-6As shown, in some embodiments, the semiconductor device further includes: an insulating structure 112 and a third word line 206; the insulating structure 112 is located in the substrate 102 on the side of the second region 2 away from the first region 1; the third word line 206 is located in the insulating structure 112, the third word line 206 is spaced apart from the second word line 204 in the second region 2, and the third word line 206 extends along the second direction Y1.
[0069] In some embodiments, the second region 2 includes an insulating structure 112 adjacent to the second active region 110.
[0070] like Figure 4 As shown, in some other embodiments, the insulating structure 112 is adjacent to the second region 2.
[0071] For example, the material of the insulating structure 112 includes one or more of silicon oxide (e.g., silicon dioxide), silicon nitride (e.g., silicon oxynitride), and nitride (e.g., silicon nitride).
[0072] like Figure 4 As shown, in some embodiments, on the third direction Y2, the bottom surface of the third character line 206 is lower than the bottom surface of the first character line 202 and the bottom surface of the second character line 204, respectively.
[0073] like Figure 4 As shown, in some embodiments, the third word line 206 includes: a first work function layer 502 and a second work function layer 504 stacked on a third direction Y2; the first work function layer 502 in the third word line 206 is located in the insulating structure 112; the second work function layer 504 in the third word line 206 is located on the top surface of the first work function layer 502, and the top surface of the second work function layer 504 is lower than the surface of the insulating structure 112. The first work function layer 502 in the third word line 206 is similar to the first work function layer 302 and the first work function layer 402, and the second work function layer 504 is similar to the first work function layer 302 and the first work function layer 402, and will not be described in detail here. It can be understood that the top surface of the second work function layer 504 in the third word line 206 is the top surface of the third word line 206.
[0074] like Figure 4As shown, in some embodiments, on the third direction Y2, the distance between the top surface of the first power function layer 502 of the third word line 206 located in the insulating structure 112 and the top surface of the insulating structure 112 is slightly equal to the distance between the top surface of the first power function layer 402 of the second word line 204 located in the first active region 106 and the top surface of the first active region 106, and the distance between the top surface of the first power function layer 502 of the third word line 206 located in the insulating structure 112 and the top surface of the insulating structure 112 is equal to the distance between the top surface of the first power function layer 302 of the first word line 202 located in the first active region 106 and the top surface of the first active region 106.
[0075] like Figure 4 As shown, in some embodiments, on the third direction Y2, the distance between the bottom surface of the insulating structure 112 and the top surface of the first active region 106 is greater than the distance between the bottom surface of the isolation structure 104 and the top surface of the first active region 106.
[0076] like Figure 5 As shown, in some embodiments, the third word line 206 includes: a first power function layer 502, which is located in the insulating structure 112, and the top surface of the first power function layer 502 is lower than the top surface of the insulating structure 112; wherein the top surface of the first power function layer 502 is the top surface of the third word line 206.
[0077] like Figure 6 As shown, in some embodiments, the third word line 206 includes: a first work function layer 502, which is located in the insulating structure 112, and the distance between the top surface of the first work function layer 502 and the bottom surface of the insulating structure 112 is equal to the distance between the top surface of the insulating structure 112 and the bottom surface of the insulating structure 112; wherein, the top surface of the first work function layer 502 is the top surface of the third word line 206.
[0078] like Figure 2 , Figure 4 , Figures 5-6 As shown, in some embodiments, the word line 108 further includes a fourth word line 208, which is located in the second region 2; the fourth word line 208 includes a first work function layer 602, located in the substrate 102; wherein, the top surface of the first work function layer 602 in the fourth word line 208 is the top surface of the fourth word line 208, the top surface of the second work function layer 304 in the first word line 202 is the top surface of the first word line 202, and the top surface of the second work function layer 404 in the second word line 204 is the top surface of the second word line 204.
[0079] like Figure 4 , Figure 5 As shown, in some embodiments, within the first active region 106, the distance between the top surface of the first work function layer 602 in the fourth word line 208 and the top surface of the first active region 106 is approximately equal to the distance between the top surface of the first work function layer 302 in the first word line 202 and the top surface of the first active region 106, and the distance between the top surface of the first work function layer 602 in the fourth word line 208 and the top surface of the first active region 106 is approximately equal to the distance between the top surface of the first work function layer 402 in the second word line 204 and the top surface of the first active region 106.
[0080] like Figure 6 As shown, in some embodiments, within the first active region 106, the distance between the top surface of the first work function layer 602 in the fourth word line 208 and the top surface of the first active region 106 is less than the distance between the top surface of the first work function layer 302 in the first word line 202 and the top surface of the first active region 106, and the distance between the top surface of the first work function layer 602 in the fourth word line 208 and the top surface of the first active region 106 is less than the distance between the top surface of the first work function layer 402 in the second word line 204 and the top surface of the first active region 106.
[0081] Specifically, such as Figure 2 As shown, in some embodiments, the fourth word line 208 is located in the first active region 106 of the second region 2. For example... Figure 4 As shown, in some embodiments, the fourth word line 208 is located in the first active region 106 of the second region 2 and the second active region 110 of the second region 2, respectively.
[0082] like Figure 4 As shown, the distance between the top surface of the fourth character line 208 and the top surface of the first active region 106 is greater than the distance between the top surface of the first character line 202 and the top surface of the first active region 106, and the distance between the top surface of the fourth character line 208 and the top surface of the first active region 106 is greater than the distance between the top surface of the second character line 204 and the top surface of the first active region 106.
[0083] like Figure 3 , Figure 4 As shown, in some embodiments, the second word line 204 and the fourth word line 208 cross the same first active region 106.
[0084] like Figure 3 , Figure 4As shown, in some embodiments, the second word line 204 and the second word line 202 cross the same first active region 106.
[0085] like Figure 2 , Figure 4 As shown, in some embodiments, the semiconductor device further includes a gate dielectric layer 114 surrounding the word line 108 and contacting the side surface and bottom surface of the word line 108, respectively. The side surface of the word line 108 is the surface where the word line 108 intersects with the first surface, and the bottom surface of the word line 108 is the surface of the word line 108 away from the first surface of the substrate 102. Further, the gate dielectric layer 114 extends along the side surface of the word line 108 to the first surface of the substrate 102. In the third direction Y2, the distance between the top surface of the gate dielectric layer 114 and the first surface of the substrate 102 is greater than or equal to 0 and less than or equal to the distance between the top surface of the word line 108 and the first surface of the substrate 102.
[0086] For example, the material of the gate dielectric layer 114 includes silicon oxide, silicon nitride, silicon oxynitride, or a high-k material. High-k materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc. Silicon oxide is preferred in the preferred embodiment. The formation process of the gate dielectric layer 114 can employ any existing technology well known to those skilled in the art, such as chemical vapor deposition (CVD) or atomic layer chemical vapor deposition (ALVDC).
[0087] like Figure 4 As shown, in some embodiments, the gate dielectric layer 114 surrounds the third word line 206 and contacts the side and bottom surfaces of the third word line 206, respectively. The side surface of the third word line 206 is the surface of the third word line 206 in the third direction Y2, and the bottom surface of the third word line 206 is away from the top surface of the insulating structure 112. Further, the gate dielectric layer 114 extends along the side surface of the third word line 206 to the top surface of the insulating structure 112. In the third direction Y2, the distance between the top surface of the gate dielectric layer 114 and the top surface of the insulating structure 112 is greater than or equal to 0 and less than or equal to the distance between the top surface of the third word line 206 and the top surface of the insulating structure 112.
[0088] Figure 7 This is a top view schematic diagram of a semiconductor device in some embodiments. Figure 8 For some embodiments along Figure 7 The diagram shows a cross-sectional view of a semiconductor device along the BB direction. Figure 9 This is a top view schematic diagram of a semiconductor device in some embodiments. Figure 10 For some embodiments along Figure 9 The schematic cross-sectional view of the semiconductor device along the BB direction is shown below. Figures 7-10As shown, in some embodiments, the semiconductor device further includes:
[0089] A plurality of bit lines 210 are arranged at intervals along the second direction Y1 and extend along the first direction X, crossing the plurality of isolation structures 104 and the plurality of first active regions 106. Each bit line 210 includes a bit line dielectric layer 310 and a bit line conductive layer 312. The bit line dielectric layer 310 is located on the substrate 102 and extends along the first direction X to the top surface of the first active region 106 and the top surface of the insulating structure 112. The bit line conductive layer 312 is located on the bit line dielectric layer 310. The thickness H1 of the bit line dielectric layer 310 located on the top surface of the isolation structure 104 is greater than or equal to the thickness H2 of the bit line dielectric layer 310 located on the top surface of the first active region 106.
[0090] For example, such as Figure 8 As shown, the bit line conductive layer 312 is located on the bit line dielectric layer 310; wherein, the thickness H1 of the bit line dielectric layer 310 located on the top surface of the isolation structure 104 is equal to the thickness H2 of the bit line dielectric layer 310 on the top surface of the first active region 106, thereby improving the performance of the semiconductor device.
[0091] For example, such as Figure 10 As shown, the top surface of the insulating structure 112 has a recess facing the substrate 102. The bit line dielectric layer 310 in the bit line 210 located on the top surface of the insulating structure 112 is concentrated at the recess, such that the bit line conductive layer 312 is located on the bit line dielectric layer 310 in the third direction Y2. The thickness H1 of the bit line dielectric layer 310 located on the top surface of the isolation structure 104 is greater than or equal to the thickness H2 of the bit line dielectric layer 310 on the top surface of the first active region 106. This disclosure also provides an electronic device including the semiconductor device of any of the preceding claims. This electronic device may include a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal. This application does not impose any special limitations on the specific form of the above-described electronic device.
[0092] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0093] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A semiconductor device, characterized in that, include: The substrate includes the first and second regions; An isolation structure is located in the substrate, which isolates a plurality of spaced-apart first active regions in the substrate; Multiple word lines are located in the substrate, and each word line is spaced apart along a first direction and extends along a second direction in a plane parallel to the substrate and crosses multiple first active regions. The second direction intersects the first direction, and the word lines include first word lines located in the first region and second word lines located in the second region. Wherein, in a third direction perpendicular to the substrate, the thickness of at least one second word line in the first active region is greater than the thickness of the first word line in the first active region; The second word line is a dummy word line, and the number of dummy word lines is greater than or equal to 3.
2. The semiconductor device according to claim 1, characterized in that, Both the first character line and the second character line include: The first work function layer is located in the substrate; The second work function layer is located on the top surface of the first work function layer, and the top surface of the second work function layer is lower than the surface of the substrate.
3. The semiconductor device according to claim 2, characterized in that, In the third direction, the thickness of the second work function layer of the second word line located in the first active region is greater than or equal to the thickness of the second work function layer of the first word line.
4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: The second active region is located in the second region on the side away from the first region and is adjacent to several of the first active regions; Among them, at least one of the second word lines crosses the second active region and the first active region respectively.
5. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: An insulating structure is located in the substrate on the side of the second region away from the first region; The third letter is located in the insulating structure, spaced apart from the second letter, and extends along the second direction.
6. The semiconductor device according to claim 5, characterized in that, In the third direction, the bottom surface of the third character line is lower than the bottom surface of the first character line and the bottom surface of the second character line, respectively.
7. The semiconductor device according to claim 5, characterized in that, In the third direction, the distance between the bottom surface of the insulating structure and the top surface of the first active region is greater than the distance between the bottom surface of the isolation structure and the top surface of the first active region.
8. The semiconductor device according to claim 5, characterized in that, The semiconductor device further includes: Multiple bit lines, each bit line being spaced apart along the second direction and extending along the first direction and crossing the isolation structure and multiple first active regions; The bit line includes: Bit line dielectric layer, located on the substrate, and extending along the first direction to the top surface of the first active region and the top surface of the insulating structure; Bit line conductive layer, located on the bit line dielectric layer; The thickness of the bit line dielectric layer located on the top surface of the insulating structure is greater than the thickness of the bit line dielectric layer located on the top surface of the first active region.
9. The semiconductor device according to claim 2, characterized in that, The word lines also include: The fourth character line, located in the second zone, includes: The first work function layer is located in the substrate; Specifically, within the first active region, the distance between the top surface of the first work function layer in the fourth word line and the top surface of the first active region is equal to the distance between the top surface of the first work function layer in the first word line and the top surface of the first active region, and is also equal to the distance between the top surface of the first work function layer in the second word line and the top surface of the first active region; the top surface of the first work function layer in the fourth word line is the top surface of the fourth word line, the top surface of the second work function layer in the first word line is the top surface of the first word line, and the top surface of the second work function layer in the second word line is the top surface of the second word line.
10. The semiconductor device according to claim 9, characterized in that, The second word line and the fourth word line cross the same first active region.