Analog operational amplifier LDO design applied to microprocessor DVFS technology

Abstract

The application provides an analog operational amplifier LDO design applied to a microprocessor DVFS technology, adopts a switching mode architecture, converts a loop control signal from a voltage domain to a time domain, generates 15-phase pulse width modulation signals and active voltage positioning through an analog operational amplifier structure, realizes equivalent increase of a switching frequency of the switching mode LDO and reduction of a load capacitor on the basis of constraint of an output voltage ripple, and adopts a double-loop structure to make the loop generate an additional zero point, compensate for an output pole moved forward when the LDO is lightly loaded, and realize stable output of the LDO in a full load range.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits and LDO (linear voltage regulator), and in particular relates to an analog operational amplifier LDO design applied to a microprocessor DVFS technology. Background Art

[0002] Reducing power consumption is a key research focus for high-performance microprocessors. Dynamic Voltage and Frequency Scaling (DVFS) technology optimizes power consumption by independently powering and controlling each core. However, with advancements in process technology and improvements in microprocessor performance, the design of microprocessor core power supplies is facing many new challenges. Wide power supply, high current supply, and full integration are fundamental requirements for microprocessor core power supplies. Traditional analog and digital LDOs can address some of these challenges, but they struggle to meet all requirements simultaneously.

[0003] For a given processor task, F*t is a constant. Only by simultaneously reducing frequency and voltage can a microprocessor truly reduce energy consumption. The core of DVFS technology lies in the simultaneous integration of a power gate (PG) and an LDO within the chip. The PG completely shuts down unused cores, while the LDO individually adjusts the supply voltage based on the actual load of each core. Together, these two optimize microprocessor efficiency.

[0004] Instructions attached Figure 1 This article demonstrates the energy consumption of microprocessor cores using both DFS and DVFS technologies. In DFS, all cores are powered by a single voltage, VIN, with each core controlled solely through power gates, PG. Because the VIN voltage is determined by the most heavily loaded core (Core0), the remaining cores either operate at the VIN corresponding to Core0 or are shut down. Consequently, with DFS, a significant amount of energy is wasted in the less heavily loaded cores (Core2 and Core3). In contrast, with DVFS, each core is powered by an independent LDO. This allows the system to adjust the supply voltage based on the core's actual operating conditions, minimizing energy loss. With advancements in process technology and increased performance, the requirements placed on the LDOs used to power microprocessor cores are becoming increasingly stringent.

[0005] Although microprocessor core power supply applications present numerous challenges for LDOs, recent developments in low input voltage, high current supply, and capacitor-free LDO architectures have led to the development of several LDO architectures for microprocessors. These include analog LDOs, digital LDOs, and switching LDOs.

[0006] Solution 1: Analog LDO

[0007] Reference [1] Luria K, Shor J, Zelikson M, et al. Dual-mode low-drop-out regulator / power gate with linear and on–off conduction for microprocessor core on-die supply voltages in 14 nm[J]. IEEE Journal of Solid-State Circuits, 2016, 51(3): 752-762. Figure 2 The advantage of an FVF LDO lies in its fast transient response. Through the fast loop formed by M2, M4, and M5 in the figure, output voltage fluctuations are quickly fed back to the gate of transistor M1, readjusting the output voltage VCCG. However, under large signals, the transient response speed of the FVF LDO is not only related to the small-signal bandwidth of the fast loop, but also the slew rate of node n3. Since the slew rate of node n3 is determined by the bias current of MOS transistors M3 and M4, and the gate capacitance of power transistor M1 can reach the nF level, in this circuit, to improve the slew rate of node n3, the LDO's static power consumption reaches 10mA.

[0008] Regarding loop stability in FVF LDOs, the primary poles are located at the output and at node n3. Due to the feedback loop, the resistance at the LDO output is very low, placing the output pole at a high position. Similarly, due to the very large bias current at node n3, the n3 pole is also at a high position. Therefore, a compensation capacitor at node n3 is required to ensure loop stability. Without further action, the compensation capacitor at this node would reach 50nF, consuming a significant amount of chip area.

[0009] Solution 2: Digital LDO

[0010] Due to the different control characteristics, digital LDO can work in low voltage and large load current application scenarios compared with analog LDO. To this end, a digital LDO solution designed using 14nm Tri-gate CMOS process is proposed in the literature [2]Muthukaruppan R, Mahajan T,Krishnamurthy HK, et al. Adigitally controlled linear regulator for per-core wide-range DVFS of atom™cores in 14nmtri-gate CMOS featuring non-linear control, adaptive gain andcode roaming[C] / / ESSCIRC 2017-43rd IEEE European Solid State CircuitsConference. IEEE, 2017: 275-278., which solves the problems existing in digital LDO to a certain extent.

[0011] like Figure 3 As shown in the figure, the digital LDO in this scheme achieves fast transient response by adopting Type-Ⅱ control, adaptive gain and Flash ADC sampling. In addition, a roaming coding algorithm is proposed in the literature [2] to eliminate the reliability problems of self-heating and electromigration in digital LDO. This literature solves the problems of digital LDO in terms of transient response speed and reliability. However, although the Flash ADC sampling method can achieve faster transient response speed, since the accuracy of Flash ADC is geometrically related to the area, only a 2.5-bit Flash ADC is used in the literature [1], resulting in very limited output voltage accuracy. Similarly, the power tube array of the LDO also only uses 10-bit coding control, corresponding to the number of power tubes is 2047. At the maximum supply current of 2.5A, the output current of a single power tube is 1.2mA. This means that the minimum output current of the LDO is 1.2mA, which greatly limits the output current range and brings about serious limit loop oscillation (LCO) effect.

[0012] Solution 3: Switching LDO

[0013] Switching LDO has the advantages of large current and fast transient response speed, and does not have the reliability problems of self-heating and electromigration in digital LDO. Therefore, in recent years, many related architectures of switching LDO have been proposed. However, there are many problems with traditional switching LDO. First, the switching LDO has severe output voltage ripple and is basically not applicable to the power supply scenario of analog circuits. Second, the duty cycle signal of the traditional switching LDO is only modulated by the comparator. This results in a very low open-loop gain of the switching LDO, often only about 20dB. Therefore, the switching LDO is even inferior to the digital LDO in terms of linear regulation rate and output voltage accuracy. In order to take advantage of the switching LDO's ability to meet the large load current and transient response requirements of the microprocessor, the document [3] proposed a new four-phase switching LDO designed with a 28nm CMOS process to power the microprocessor core. Its framework is shown in the attached manual. Figure 4 As shown:

[0014] In order to solve the problem of low open-loop gain of traditional switching LDO, reference [3] added a slow loop composed of operational amplifiers on the basis of the traditional architecture. Under the action of the slow loop, the open-loop gain of the switching LDO is expanded by A0 times, improving the various performance parameters of the LDO. When the load steps, the slow loop composed of the operational amplifier basically does not work, and the output voltage fluctuation is quickly modulated by the fast loop to adjust the duty cycle, thereby retaining the fast transient response speed of the switching LDO. The dual-loop design solves the problem of poor performance parameters of the switching LDO, but the addition of the operational amplifier also causes the switching LDO in reference [3] to be unable to work completely under low voltage conditions. For this reason, reference [3] also adopts a multi-voltage domain design method in which the operational amplifier and comparator are powered separately.

[0015] In order to solve the problem of large output voltage ripple of switching LDO, the literature [3] adopted three measures. First, in terms of driving mode, the literature [3] Mao X, Lu Y, Martins R P. A scalable high-current high-accuracy dual-loop four-phase switching LDO for microprocessors [J]. IEEE Journal of Solid-State Circuits, 2021, 57(6): 1841-1853. proposed a four-phase 500MHz pulse width modulation method, which reduced the output voltage ripple by about 16 times. Secondly, a current limiting circuit is used to fix the output current of the power tube to reduce the fluctuation of the output voltage ripple with PVT. Finally, a hybrid fast and slow power tube is used to compensate for the ripple voltage. The final output voltage ripple is controlled below 7mV, and the load capacitance is only 5nF. However, since the four-phase 500MHz pulse signal modulation uses four high-speed comparators, the quiescent current of the LDO reaches 1.8mA. Summary of the Invention

[0016] Solution 3 in the above prior art solution is the solution most similar to the solution of the present invention. However, it has the following problems:

[0017] (1) Since LDO uses a traditional operational amplifier, it cannot fully operate at low input voltage.

[0018] (2) Four high-speed comparators are used to make the quiescent current of the LDO reach 1.8mA.

[0019] To this end, this paper proposes a new switching LDO solution to provide a new solution for the design of microprocessor core power supply. The main technical problems that this solution needs to solve include:

[0020] ① The problem of large output voltage ripple of switching LDO;

[0021] ② The switching gain of the switching LDO is low, resulting in poor performance of parameters such as the LDO line regulation rate and load regulation rate;

[0022] ③ The problem of high static current caused by duty cycle modulation of the sampling high-speed comparator in Solution 3.

[0023] The technical solution specifically adopted by the present invention to solve the technical problem is:

[0024] An analog operational amplifier LDO used in microprocessor DVFS technology includes three loop structures:

[0025] The first loop is the main loop, including a voltage-time-domain converter (VTC), a first charge pump, a 15-phase pulse-width modulation circuit, and 15-phase switching power transistors. Distributed power switching transistors provide high current for the LDO, while the integration circuit of the 15-phase pulse-width modulation circuit provides DC gain at low voltage. The 15-phase control signal output by the 15-phase pulse-width modulation circuit reduces the output voltage ripple of the switching LDO.

[0026] The second loop is an auxiliary loop, including a second charge pump, a switched capacitor resistor RSC, and an analog auxiliary power transistor MP. The auxiliary loop is connected in parallel with the main loop to generate a zero point inside the LDO to compensate for the forward shift of the output pole when the LDO is lightly loaded, so that the LDO can operate stably within the full load range.

[0027] The third loop is a transient enhancement loop; it includes a transient detection circuit and a third charge pump, and is used to enhance the transient response speed of the LDO. It only works when a load step occurs. When no load step occurs, the loop is in a closed state.

[0028] Furthermore, the voltage-time domain converter VTC is composed of a differential input stage Gm, a current-controlled delay line CCDL, a time amplifier TA, and a non-overlapping phase-frequency detector NO_PFD; wherein the differential input stage Gm converts the voltage difference signal into a differential current signal, which drives two current-controlled delay lines CCDL: CCDL1 and CCDL2 respectively; the two current-controlled delay lines CCDL generate clock signals CLK with different delays according to the input current. P0 and CLK N0 , to achieve the transition from voltage difference to phase difference; CLK P0 and CLK N0 The phase difference between them is further amplified by the time amplifier TA to obtain CLK PTA and CLK NTA Finally, the amplified phase error is converted into a pulse signal output through the non-overlapping phase frequency detector NO_PFD to obtain the pulse signals UP and DN.

[0029] Furthermore, the 15-phase duty cycle signal modulation circuit is composed of two 15-stage ring oscillators CCO, a phase frequency detector SPFD, and current mode feedback, forming a structure similar to an op amp with negative feedback; wherein, when the circuit is in a closed-loop state, the LDO is in AVP mode to improve the transient response characteristics of the LDO; when the circuit is in an open-loop state, the circuit is in high-precision mode to improve the problem of poor DC accuracy under low voltage.

[0030] Furthermore, a 15-phase PWM signal is generated by connecting two 15-stage ring oscillators (CCO) in parallel. The 15-stage ring oscillators also output 15 clock signals whose initial phases increase in an arithmetic progression. The 15 clock signals output by CCO2 serve as phase reference signals. The 15-phase clock signals output by CCO1 increase or decrease in frequency based on the input current Iin. When the frequency changes, the phase accumulation speed will also change:

[0031] When Iin=0, the clock frequencies of the output signals of CCO1 and CCO2 are the same, and the output phase difference remains unchanged;

[0032] When Iin>0, the output frequency of CCO1 increases, and the accumulation speed of each phase clock is greater than the accumulation speed of the reference clock phase;

[0033] When Iin<0, the phase accumulation speed of each phase clock of CCO1 is slower than that of the reference clock. Finally, the phase frequency detector SPFD obtains the phase difference signal generated by the change of input current Iin, which corresponds to the 15-phase PWM signal.

[0034] Furthermore, the transient detection circuit is composed of two DFFs; utilizing the characteristics of input and output pulse signals of the time amplifier TA in the voltage time domain converter VTC; and detecting whether a large load step occurs in the LDO through logical judgment.

[0035] Furthermore, in the auxiliary loop, the switched capacitor resistor is equivalently implemented by a switched capacitor bias circuit to avoid introducing a new pole;

[0036] The auxiliary loop is controlled by the output signal UP and / or DN of the voltage-time converter VTC, and the clock signal CLK is delayed to obtain CLK A Signal; in steady state, since UP and / or DN are only on CLK A Output when CLK is high; A When the signal is low, in the switch capacitor bias circuit connected to the second charge pump, the MOS tube M P3 and M N6 The second charge pump does not output current, and the voltage at point P is equal to M P4 Diode bias voltage V B ; and when CLK A When the signal is high, M P3 and M N6 Shutdown; when there is no UP and / or DN signal input, the charge on point P is constant and the voltage remains at V BWhen the UP and / or DN pulse signals are input, the second charge pump injects or extracts charges to the P point, at which time the voltage of the P point changes and lasts until the CLK becomes low again; for one signal input, the voltage change AVp of the P point is equivalent to the form of pulse; by averaging the amplitude of the change of Vp in a period, the switched-capacitor bias circuit is equivalent to a switched-capacitor resistance R SC The size is equal to:

[0037]

[0038] Wherein, Cp is the total of the parasitic capacitance of the P point, and D is the time of maintaining AVp.

[0039] And a design method of an analog operational amplifier LDO applied to a microprocessor DVFS technology, which adopts a switching architecture, generates 15-phase pulse width modulation signals and active voltage positioning through converting a loop control signal from a voltage domain to a time domain in an analog operational amplifier structure, realizes equivalent increase of a switching frequency of the switching LDO and reduction of a load capacitor on the basis of constraint of output voltage ripple; in order to maintain the loop stability of the LDO, a double-loop structure is adopted to make the loop generate an additional zero point, and the output pole moved forward when the LDO is lightly loaded is compensated, so that the LDO maintains stable output in a full load range.

[0040] Compared with the prior art, the application and the preferred scheme thereof design an analog operational amplifier structure of the 15-phase pulse modulation circuit, the structure has an AVP mode and a high-precision mode, and can generate 15-phase pulse signals in a way of oscillator frequency modulation to reduce the ripple of the switching LDO.

[0041] The main features and advantages at least include:

[0042] (1) The output voltage ripple of the switching LDO is reduced to below 1 mV through the 15-phase pulse modulation circuit

[0043] (2) The problem of large static current of a high-speed comparator is solved in a way of oscillator frequency modulation

[0044] (3) The traditional operational amplifier is not used in the circuit, but an analog operational amplifier composed of an oscillator is used. The circuit can work completely under low-voltage conditions. BRIEF DESCRIPTION OF DRAWINGS

[0045] The application will be further described in detail below in combination with the drawings and specific embodiments:

[0046] Figure 1 It is an energy-saving comparison diagram of prior art DFS and DVFS technologies;

[0047] Figure 2 It is a prior art FVF LDO architecture diagram;

[0048] Figure 3 This is a functional block diagram of a digital LDO in the prior art;

[0049] Figure 4 This is a functional block diagram of a switching LDO in the prior art;

[0050] Figure 5 This is the overall architecture diagram of the switching LDO according to an embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of a voltage time domain converter circuit according to an embodiment of the present invention;

[0052] Figure 7 This is a CCDL circuit diagram according to an embodiment of the present invention;

[0053] Figure 8 This is a circuit diagram of TA according to an embodiment of the present invention;

[0054] Figure 9 This is a circuit diagram of NO_PFD according to an embodiment of the present invention;

[0055] Figure 10 This is a circuit diagram of a 15-phase pulse signal modulation circuit according to an embodiment of the present invention;

[0056] Figure 11 This is a circuit diagram of a 15-stage ring oscillator according to an embodiment of the present invention;

[0057] Figure 12 This is a circuit diagram of a saturated frequency and phase detector according to an embodiment of the present invention;

[0058] Figure 13 This is a transient detection circuit diagram of an embodiment of the present invention;

[0059] Figure 14 This is a transient detection logic waveform diagram of an embodiment of the present invention;

[0060] Figure 15 This is an auxiliary loop circuit diagram of an embodiment of the present invention;

[0061] Figure 16 This is a waveform diagram of the auxiliary loop according to an embodiment of the present invention;

[0062] Figure 17 This is a diagram showing the PSRR simulation results of an embodiment of the present invention;

[0063] Figure 18 Among them, (a) is a high-precision mode transient response simulation diagram of an embodiment of the present invention, and (b) is a AVP mode transient response simulation diagram;

[0064] Figure 19 This is a simulation diagram of the linear adjustment rate of an embodiment of the present invention.

[0065] Figure 20 The output voltage ripple graph of the embodiment of the present application when the load current is 1A. DETAILED DESCRIPTION

[0066] In order to make the features and advantages of the patent more obvious and easy to understand, the following specific examples are described in detail as follows:

[0067] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise indicated, all technical and scientific terms used in the present description have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs.

[0068] It should be noted that the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise, and it should also be understood that when the terms "comprise" and / or "include" are used in the present description, there is a feature, step, operation, device, component and / or combination thereof.

[0069] 1 Overall scheme principle

[0070] In the embodiment of the present application, the microprocessor core considered is composed of digital circuits, which requires a power supply with large current supply and wide power input capability. For the requirement of large current supply, since the microprocessor core has low requirements for power supply ripple, the LDO of the present application adopts a switching architecture. The switching LDO can provide an ampere-level large current, respectively solving the limitations of traditional analog LDO and digital LDO in stability and reliability. For the requirement of wide power input, the present application converts the loop control signal from the voltage domain to the time domain, and designs a class operational amplifier structure, solving the problem of insufficient transistor voltage margin of traditional analog LDO at low voltage, so that the precision, PSR and other parameters of LDO at low input voltage are greatly improved. The class operational amplifier structure can also generate 15-phase pulse width modulation signals and active voltage positioning (AVP) functions. The switching frequency of the switching LDO is equivalent to 15 times, and the load capacitance is reduced by about 500 times on the basis of an output voltage ripple of less than 1.5mV. Finally, in order to maintain the loop stability of the LDO, the present application adopts a double-loop structure. The design of the double-loop makes the loop produce an additional zero point, which compensates for the forward-shifted output pole of the LDO at light load, so as to maintain stable output of the LDO in the full load range.

[0071] The overall architecture of the new switching high-performance LDO designed in the embodiment of the present application is as follows: Figure 5As shown, it contains three loops. Among them, the first loop is the main loop, which is composed of voltage time domain converter (VTC), charge pump 1, 15-phase pulse width modulation circuit, 15-phase switching power tube. In this loop, the distributed large-size power switch tube can provide the ability of large current supply for LDO, and there is an integral circuit inside the 15-phase pulse width modulation circuit, which theoretically has infinite low-frequency gain, solving the problem of poor performance such as low-voltage DC precision and load regulation of LDO. The second loop is the auxiliary loop, which is composed of charge pump 2, switched capacitor resistor RSC, analog auxiliary power tube MP. The auxiliary loop generates a zero point in the LDO by parallel connection with the main loop, compensates for the forward shift of the output pole of the LDO under light load, and enables the LDO to work stably in the range of 0-1.2A load, so that the LDO has the ability to output in the full load range. The third loop is the transient enhancement loop. It is composed of transient detection circuit and charge pump 3, which enhances the transient response speed of LDO and solves the problem of poor transient response without off-chip capacitor. And this loop only works when the load occurs step, and the loop is in the off state when there is no load step.

[0072] 2 Key circuit principle and implementation

[0073] ① Voltage time domain converter circuit

[0074] The architecture of voltage time domain converter circuit (VTC) is as shown in Figure 6 . The circuit is composed of differential input stage Gm, current-controlled delay line (CCDL), time amplifier (TA), non-overlapping phase frequency detector (NO_PFD). Among them, the Gm unit converts the voltage difference signal into a differential current signal, which drives CCDL1 and CCDL2 respectively. Two CCDLs will generate clock signals CLK P0 and CLK N0 with different delays according to the input current, thereby realizing the conversion from voltage difference to phase difference. At this time, the phase difference between CLK P0 and CLK N0 is small, which needs to be further amplified by the TA module to obtain CLK PTA and CLK NTA . Finally, the NO_PFD circuit converts the amplified phase error into pulse signal output, obtaining pulse signals UP and DN. The circuit diagrams of CCDL, TA, NO_PFD are shown in Figure 7 , Figure 8 , Figure 9 respectively.

[0075] ② 15-phase duty cycle signal modulation circuit

[0076] In order to solve the problems of large quiescent current and low DC precision under low voltage in traditional switching LDO, the present invention innovatively proposes a 15-phase pulse width modulation circuit. Figure 10 As shown, the 15-phase pulse-width modulation circuit consists of a current-controlled oscillator (CCO), a phase-frequency detector (SPFD), and current-mode feedback, similar to an op amp with negative feedback. When the circuit is in a closed-loop state, the LDO operates in AVP mode, which improves the LDO's transient response. When the circuit is in an open-loop state, it operates in high-precision mode, improving poor DC accuracy at low voltages. This circuit also effectively addresses the high quiescent current issue of the high-speed comparator used in Solution 3, reducing the overall LDO's quiescent power consumption by over 50%.

[0077] The 15-phase PWM signal is generated by connecting two 15-stage ring oscillators in parallel. The quiescent current of the 15-stage ring oscillator is only tens of uA, which greatly reduces the static power consumption of the LDO. In addition, the 15-stage ring oscillator will output 15 clock signals with initial phases increasing in an arithmetic progression. Figure 10 In the figure, the 15 clock signals output by CCO2 are all used as phase reference signals, and the 15-phase clock signals output by CCO1 will increase or decrease the frequency according to the input current Iin. When the frequency changes, the accumulation speed of the phase will also change. Therefore, when Iin=0, the clock frequencies of the output signals of CCO1 and CCO2 are the same, and the output phase difference will remain unchanged. When Iin>0, the output frequency of CCO1 increases, and the accumulation speed of its phase of each phase clock will be greater than the accumulation speed of the reference clock phase. Similarly, when Iin<0, the accumulation speed of the phase of each phase clock of CCO1 will be less than the accumulation speed of the phase of the reference clock. Finally, the phase difference signal generated by the change of the input current Iin, that is, the 15-phase PWM signal, can be obtained through SPFD. The schematic diagrams of CCO and SPFD are shown as follows. Figure 11 and Figure 12 shown.

[0078] ③ Transient enhancement loop

[0079] The transient enhancement loop provided by the embodiment of the present invention is composed of a transient detection circuit and a charge pump 3. As described in the background technology, the transient enhancement loop only works when a load step occurs. Therefore, determining whether a large load step occurs in the circuit is the key to the design of the transient enhancement loop. Figure 13 As shown, the transient detection circuit of the present invention consists of only two DFFs. It utilizes the characteristics of the VTC's time amplifier (TA) input and output pulse signals. Through simple logic analysis, the transient detection circuit can determine whether the LDO has experienced a large load step.

[0080] Figure 14The logic waveform of the transient detection circuit is shown in Figure 2. OUT and V REF The relationship can be divided into three cases. When V OUT ≈V REF When CLK P0 and CLK N0 Delay T D Fixed delay T less than TA BD .therefore, Figure 13 The reset signal CLK of DFF1 N0 Will precede the clock rising edge CLK PTA Arrival, UP SE The signal always remains high. OUT < <V REF When the input pressure difference is large, T D Greater than T BD At this time, the rising edge of the DFF1 clock is faster than the reset signal, UP SE Outputs a low-level pulse signal. This pulse signal controls the charge pump 3 to input current into the 15-phase pulse circuit. As mentioned above, the gain of the charge pump 3 is much greater than the gain of the charge pump 1, so it can greatly enhance the transient response speed of the LDO. Similarly, when V OUT >>V REF When the voltage is high, DFF2 will output a high level to enhance the transient response speed of LDO.

[0081] ④ Auxiliary loop

[0082] like Figure 15 As shown in FIG, the auxiliary loop mainly consists of a charge pump 2, a switched capacitor bias circuit, and a power transistor. The use of switched capacitors and resistors avoids introducing new poles in the auxiliary loop.

[0083] like Figure 15 As shown, the auxiliary loop is controlled by the output signal UP / DN of VTC, and the clock signal CLK is obtained after delay. A Signal. In steady state, UP / DN will only be on CLK A Output when CLK is high. A When the signal is low, the MOS tube M P3 and M N6 When the charge pump 2 is turned on, it will not output current, and the voltage at point P is equal to M P4 Diode bias voltage V B . And when CLK A When the signal is high, M P3 and M N6 Shut down. Figure 15As shown, when there is no UP / DN signal input, the charge at point P is constant, and the voltage remains V B When UP / DN pulse signal is input, the charge pump 2 injects or extracts charge to point P, at which time the voltage of point P changes and lasts until CLK becomes low again. For a small signal input, the pulse width of UP / DN is small, and thus the voltage change AVp of point P can be equivalent to a pulse. By averaging the amplitude of the change of Vp in a period, the switched-capacitor bias circuit can be equivalent to a switched-capacitor resistance R SC , which is equal to

[0084]

[0085] wherein Cp is the total parasitic capacitance of point P, and D is the time during which AVp is maintained. The working waveform is shown in Figure 16 .

[0086] 3 Simulation of key parameters

[0087] In one specific design example of the present application, a wide power supply and large current supply high-performance LDO is designed using SMIC 55NLL process. The LDO has an input voltage range of 0.7-1.2V, an output voltage range of 0.5-1.12V, and a maximum current supply capability of 1.2A. The post-simulation results show that the PSRR of the LDO reaches -43dB at 1MHz, the load regulation is 0.446mV / A, the overshoot and undershoot are both less than 65mV when the load current changes from 0.2-0.8A@40ns, the area of the core part of the layout is only 585um*261um, and a LDO design suitable for high-performance processors is realized. The key parameter waveform is shown in Figure 17 .

[0088] Figure 17 The pre-simulation results of the PSRR of the LDO at V IN =0.7V, V OUT =0.5. As can be seen from the figure, the PSRR of the LDO is 43dB at less than 1MHz, and the PSRR is higher than 29dB in the entire simulation frequency band. This shows that the LDO of the present application can effectively suppress the noise from the power supply to the output voltage.

[0089] Figure 18 The transient response simulation of the LDO in high-precision mode and AVP mode, respectively. The simulation conditions are V IN =1.2V, V OUT= 0.8, and the load increases from 0.2A to 0.8A within 40ns. From this, we can see that in high-precision mode, the LDO undershoot = 50mV and overshoot = 67.6mV. In AVP mode, the output voltage DC accuracy is even worse, but the LDO undershoot = 37mV and overshoot = 46mV, demonstrating better transient response.

[0090] V IN =1.2V, load current is 0.1-1.1A, simulation results of different output voltages are as follows Figure 19 As shown. Among them, the load regulation appears at V OUT =0.6, the load adjustment rate is:

[0091]

[0092] Assume that the ESR resistance of the output capacitor is 5mΩ. Figure 20 As shown, at V IN =1.2V, V OUT =0.8V, I L =1A, the output voltage ripple of the LDO is 0.87mV.

[0093] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any other manner. Any person skilled in the art may utilize the above-disclosed technical content to modify or modify the present invention into equivalent embodiments. However, any simple modifications, equivalent variations, and modifications to the above embodiments that do not depart from the technical content of the present invention and are based on the technical essence of the present invention remain within the scope of protection of the present invention.

[0094] This patent is not limited to the above-mentioned best embodiment. Anyone can derive various other forms of analog op amp LDO designs for microprocessor DVFS technology based on the inspiration of this patent. All equivalent changes and modifications made within the scope of the patent application of this invention shall be covered by this patent.

Claims

1. An analog operational amplifier LDO for microprocessor DVFS technology, characterized by: It includes three loop structures: The first loop is the main loop, including a voltage-time-domain converter (VTC), a first charge pump, a 15-phase pulse-width modulation circuit, and 15-phase switching power transistors. The distributed switching power transistors provide high current for the LDO, and the integration circuit of the 15-phase pulse-width modulation circuit provides DC gain at low voltage. The 15-phase control signal output by the 15-phase pulse-width modulation circuit reduces the output voltage ripple of the switching LDO. The second loop is the auxiliary loop, which includes the second charge pump, the switched capacitor resistor RSC, and the analog auxiliary power transistor MP. The auxiliary loop is connected in parallel with the main loop to generate a zero point inside the LDO to compensate for the forward shift of the output pole when the LDO is lightly loaded, ensuring stable operation of the LDO over the full load range. The third loop is a transient enhancement loop, which includes a transient detection circuit and a third charge pump. It is used to enhance the transient response speed of the LDO. It only works when a load step occurs. When no load step occurs, the loop is in a closed state. The voltage-time domain converter VTC consists of a differential input stage Gm, a current-controlled delay line CCDL, a time amplifier TA, and a non-overlapping phase-frequency detector NO_PFD. The differential input stage Gm converts the voltage difference signal into a differential current signal, which drives two current-controlled delay lines CCDL: CCDL1 and CCDL2. The two current-controlled delay lines CCDL generate clock signals CLK with different delays according to the input current. P0 and CLK N0 , to achieve the transition from voltage difference to phase difference; CLK P0 and CLK N0 The phase difference between them is further amplified by the time amplifier TA to obtain the signal CLK PTA and CLK NTA Finally, the amplified phase error is converted into a pulse signal output through the non-overlapping phase frequency detector NO_PFD to obtain the pulse signals UP and DN; The 15-phase pulse width modulation circuit consists of two 15-stage ring oscillators (CCOs), a phase frequency detector (SPFD), and current mode feedback. When the circuit is in a closed-loop state, the LDO is in AVP mode to improve the transient response characteristics of the LDO. When the circuit is in an open-loop state, the circuit is in high-precision mode to improve the problem of poor DC accuracy under low voltage.

2. The analog operational amplifier LDO applied to the microprocessor DVFS technology according to claim 1, characterized in that: The 15-phase PWM signal is generated by connecting two 15-stage ring oscillators (CCO) in parallel. The 15-stage ring oscillator also outputs 15 clock signals whose initial phases increase in an arithmetic progression. The ring oscillators (CCO) include CCO1 and CCO2. The 15 clock signals output by CCO2 serve as phase reference signals. The 15-phase clock signals output by CCO1 increase or decrease in frequency based on the input current Iin. When the frequency changes, the phase accumulation speed also changes: When Iin=0, the clock frequencies of the output signals of CCO1 and CCO2 are the same, and the output phase difference remains unchanged; When Iin>0, the output frequency of CCO1 increases, and the accumulation speed of each phase clock is greater than the accumulation speed of the reference clock phase; When Iin<0, the phase accumulation speed of each phase clock of CCO1 is slower than that of the reference clock. Finally, the phase frequency detector SPFD obtains the phase difference signal generated by the change of input current Iin, which corresponds to the 15-phase PWM signal.

3. The analog operational amplifier LDO applied to the DVFS technology of a microprocessor according to claim 1, characterized in that: The transient detection circuit is composed of two DFFs; it utilizes the characteristics of input and output pulse signals of the time amplifier TA in the voltage time domain converter VTC; and detects whether a large load step occurs in the LDO through logical judgment.

4. The analog operational amplifier LDO applied to the microprocessor DVFS technology according to claim 1, characterized in that: In the auxiliary loop, the switched capacitor resistor is equivalently implemented by a switched capacitor bias circuit to avoid introducing a new pole; The auxiliary loop is controlled by the output signal UP and / or DN of the voltage-time converter VTC, and the clock signal CLK is delayed to obtain CLK A Signal; in steady state, since UP and / or DN are only on CLK A Output when CLK is high; A When the signal is low, in the switch capacitor bias circuit connected to the second charge pump, the MOS tube M P3 and M N6 The second charge pump does not output current, and the voltage at point P is equal to M P4 Diode bias voltage V B ; and when CLK A When the signal is high, M P3 and M N6 Shutdown; When there is no UP and / or DN signal input, the charge on point P is constant and the voltage remains at V B When the UP and / or DN pulse signals are input, the second charge pump injects or extracts charge to point P. At this time, the voltage at point P changes and lasts until CLK becomes low again. For a signal input, the voltage change ∆Vp at point P is equivalent to a pulse. By averaging the amplitude of Vp changes within a cycle, the switched capacitor bias circuit is equivalent to a switched capacitor resistor R. SC , whose size is equal to: Where Cp is the sum of the parasitic capacitances at point P, and D is the duration for which △Vp is maintained.

5. A design method for an analog operational amplifier (LDO) applied to a microprocessor DVFS technology according to any one of claims 1 to 4, characterized in that: By adopting a switching architecture, the loop control signal is converted from the voltage domain to the time domain. A 15-phase pulse-width modulation signal and active voltage positioning are generated with an op amp-like structure. This effectively increases the switching frequency of the switching LDO and reduces the load capacitance while constraining the output voltage ripple. To maintain the LDO loop stability, a dual-loop structure is used to generate an additional zero in the loop to compensate for the forward-shifted output pole of the LDO under light load, thereby achieving stable output across the full load range of the LDO.

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