FPGA real-time simulation method and system for power transformer considering hysteresis effect

Abstract

The present invention belongs to the technical field of power system simulation and discloses a method and system for implementing FPGA real-time simulation of a power transformer taking into account the hysteresis effect. The method establishes a linear model of the power transformer based on the admittance matrix method; converts the control equation of the transformer into a continuous-time differential equation and then discretizes it using the trapezoidal integration method; connects nonlinear elements outside the linear model to include nonlinear characteristics such as saturation and hysteresis effects; solves the nonlinear part using a compensation method; according to the compensation method, superimposes a current injection vector on the linear part of the network, and then solves the entire network to obtain a final solution; and determines whether the simulation time t reaches the set total simulation time T. max The present invention reduces hardware resource utilization and improves calculation speed, which is conducive to realizing larger-scale electromagnetic transient simulation.

Description

Technical Field

[0001] The present invention belongs to the technical field of power system simulation, and in particular relates to a method and system for realizing FPGA real-time simulation of a power transformer taking hysteresis effect into consideration. Background Art

[0002] With the development of complex modern power grids, the demand for more accurate and faster real-time simulation of electromagnetic transients has greatly increased. However, traditional modeling methods either completely omit the transformer model or represent it with a simplified equivalent model that only includes the winding leakage impedance. This makes it difficult to reflect the actual operating physical scenario of the device under test. To date, transformer modeling has been limited to low-order, piecewise linear, and low-frequency behavior. Babak Asghari et al. proposed the "Sen" transformer model, which ignores the geometry of the transformer core. The nonlinear component is represented by a piecewise linear representation based on the BH curve, but the hysteresis characteristics are completely omitted. Therefore, it is necessary to develop a detailed and efficient transformer model. The most commonly used method for hysteresis modeling is curve fitting, which ignores the behavior of magnetic materials. While this method can simplify the model, it cannot reflect the hysteresis phenomenon of transformer cores in actual projects, which has a certain impact on the accuracy of power grid simulations. More complex methods use the Jiles-Atherton model and the Preisach model. The difficulty lies in determining the parameters involved in describing the magnetization mechanism, but it can effectively describe the hysteresis characteristics of the transformer core.

[0003] In real-time systems built using sequential hardware based on general-purpose CPUs or DSPs, the sequential execution of instructions limits their computational speed and simulation accuracy, making real-time performance often difficult to meet engineering requirements. Increased computational complexity and the lack of real-time feedback for simulation results also make CPUs less suitable platforms for real-time hardware simulation. Nonlinearities in transformer models in offline electromagnetic transient tools (such as ATP and PSCAD / EMTDC) are represented by piecewise linear representations, such as nonlinear inductances. However, frequent switching between segments still leads to numerical oscillations. Field Programmable Gate Arrays (FPGAs), with their parallel hardware architecture, deep pipeline architecture, reprogrammability, and high clock speeds, have shown great potential in real-time transient simulation systems, enabling real-time computation. Real-time simulation requires testing control devices in a hardware-in-the-loop configuration. This real-time simulation method possesses hardware-in-the-loop simulation testing capabilities, enabling online testing of power systems and control devices. Combining historical data generated during operation with real-time feedback data, it can reflect the actual operating status of the system in real time, indirectly reflecting the operating characteristics of the power transformer, effectively reducing R&D and testing costs. Therefore, it is of great significance to develop a method for implementing FPGA real-time simulation of power transformers that considers hysteresis effects. Summary of the Invention

[0004] In view of the problems existing in the prior art, the present invention provides a method for implementing FPGA real-time simulation of a power transformer taking into account the hysteresis effect.

[0005] The present invention is implemented as follows: a method for implementing FPGA real-time simulation of a power transformer taking into account hysteresis effect, the method comprising:

[0006] S1: Establish a linear model of the power transformer based on the admittance matrix method;

[0007] S2: Convert the transformer control equation in step S1 into a continuous-time differential equation, then discretize it using the trapezoidal integration method to obtain a Norton equivalent circuit form containing the admittance matrix and the historical current term. Since the transformer parameters such as R, L, and G are fixed, the transformer parameter matrix is ​​pre-calculated and stored in the random access memory of the FPGA. The linear solver calculates the obtained historical current term and saves the updated historical current term. The linear solver includes two matrix-vector multiplication units and a floating-point adder.

[0008] S3: Connect nonlinear elements outside the linear model to account for nonlinear characteristics such as saturation and hysteresis effects. The n-node power system is divided into linear and nonlinear parts, and the node voltages in the linear part are solved using a nodal analysis method. Because the inverse admittance matrix is ​​sparse, a compact sparse matrix storage method is defined, and the calculation of unknown node voltages is implemented in the FPGA using a fast sparse matrix-vector multiplication unit.

[0009] S4: Solve the nonlinear part using the compensation method. After finding the node voltages of the linear network, solve the n-node power system with nonlinear elements. Linearize the nonlinear equations using the Newton-Raphson method and apply a first-order Taylor series expansion to the nonlinear functions to solve the nonlinear equations and thus solve the current injection vectors of the nonlinear elements. These nonlinear functions are generated using Preisach theory to simultaneously represent saturation and hysteresis effects.

[0010] S5: According to the compensation method, the current injection vector obtained in step S4 is superimposed on the linear part of the network, and then the entire network is solved to obtain the final solution;

[0011] S6: Determine whether the simulation time t reaches the set total simulation time T max , if the set total simulation time T is reached max , the simulation ends; otherwise, the simulation time advances one time step, t=t+Δt, and returns to step S2 to update the historical current term through the linear solution unit.

[0012] Furthermore, the model in S1 is a linear model, which is connected to an external circuit to include nonlinear characteristics such as saturation and hysteresis effects. Under transient conditions, the expression of the three-phase transformer control equation is:

[0013] di TE / dt=L -1 v TE -L -1 Ri TE (1)

[0014] where v TE with i TE are the instantaneous terminal voltage and current, R and L are the winding resistance and winding leakage inductance measured by the short-circuit test, respectively.

[0015] Furthermore, the Norton equivalent circuit expression is as follows:

[0016] i TE (t) = Gv TE (t)+i hist (t-Δt)

[0017] i hist (t-Δt)=αv TE (t-Δt)+βi hist (t-2Δt)(2)

[0018] Where G is the admittance matrix, α = 2(G-GRG), β = (I-2GR), i hist (t-Δt) is the historical current term, Δt is the simulation time step; the linear solver unit includes two matrix-vector multiplication units and a floating-point adder, and the floating-point adder consumes 7 clock cycles; the historical current term i is obtained by differentiating the transformer differential equation using the trapezoidal integral method. hist (t-Δt) is updated at each time step, and the updated historical current term is calculated and saved in the linear solver unit; to reduce the computational complexity and delay, instead of pre-storing a single fixed parameter, α=2(G-GRG) and β=(I-2GR) are pre-stored in the FPGA random access memory RAM_α and RAM_β respectively; the node voltage v TE (t) Store to RAM_v TE , the historical current term i of the previous time step hist (t-Δt) is stored in RAM_i h In the updated historical current term i hist (t) Store to RAM_i hnew middle.

[0019] Furthermore, the pre-storage format of the transformer parameter matrix stored in the FPGA consists of two memories: a 32-bit memory val that stores matrix values ​​in row order until all parameter matrix values ​​are stored in the FPGA; a 9-bit memory, the high 8 bits col that stores the column index values ​​of the matrix in row order, and the lowest bit row uses 0 or 1 to represent the same row of the stored matrix; the IEEE754 standard 32-bit single-precision floating-point format is used, except that the accumulation operation in the adder uses a fixed-point number form; to ensure range and accuracy, the fixed-point number is set to 64-bit data, of which the integer part is 30 bits and the decimal part is 34 bits; the matrix-vector multiplication unit includes a floating-point multiplier, a A floating-point to fixed-point converter, a fixed-point to floating-point converter, two fixed-point adders, a multiplexer, and a row counter CNT complete row vector multiplication in the form of a deep pipeline. The multiplexer selects the two adders by counting the row by the row counter CNT. Whenever a change in the row value is detected, the row counter CNT increments by 1. The two fixed-point adders have opposite reset conditions. When fixed-point adder 1 accumulates the first matrix row vector multiplication, fixed-point adder 2 is cleared to prepare for the next row vector multiplication, and the accumulation cycle continues until completion. The floating-point multiplier consumes 5 clock cycles, and the fixed-point adder consumes 1 clock cycle.

[0020] Furthermore, the linear part is solved by the node analysis method, and the expression is as follows:

[0021] Yv0=i (3)

[0022] Where Y is the admittance matrix without nonlinear elements, v0 and i are the unknown node voltage and known node current, respectively. The unknown node voltage v0 can be divided into the unknown node voltage A and the known node voltage B. Formula (3) can be rewritten as:

[0023]

[0024] Further deformation, i A Obtained from the historical current term, the unknown node voltage v A The solution of is given by:

[0025]

[0026]

[0027] In the process of solving the linear equations by node analysis, due to the admittance matrix Y AB and the inverse admittance matrix For sparse matrices, pre-calculated and stored in FPGA memory RAM_Y AB and memory RAM_Y -1 AAIn the node current i A Stored in memory RAM_i A In the middle, the current i b Stored in memory RAM_i b In the equation, the node voltage v is known. B Stored in memory RAM_v B The compact sparse matrix storage method is the same as the matrix-vector multiplication unit, except that only non-zero elements are stored in the sparse matrix. Each non-zero element value is stored row by row through a 32-bit memory val until all non-zero elements of the matrix are stored in the memory. The current i is realized by the fast sparse matrix-vector multiplication unit. b The calculation process implemented in FPGA is as follows: the column index value of the sparse matrix is ​​stored in col in row order, the non-zero matrix value is stored in col, val stores the non-zero value of each row of the matrix in row order, and row uses 0 or 1 to represent the same row of the storage matrix, so the memory RAM_v is taken out according to the column index value stored in col B The known node voltage v corresponding to the row vector B Column vector, and then realize the current i through the matrix vector multiplication unit b The calculation includes a floating-point subtractor to implement the subtraction operation solution of formula (5); the inverse admittance matrix is ​​multiplied by the current i through the fast sparse matrix vector multiplication unit. b To calculate the unknown node voltage v A .

[0028] Furthermore, the current injection vector solution process of the nonlinear element in step S4 is implemented by a Newton-Raphson nonlinear solution module:

[0029] f(i km )=v oc -r thev i km (7)

[0030] Where f(i km ) is a nonlinear function, v oc is the open circuit voltage without nonlinear elements (v0 subset), r thev is the Thevenin equivalent resistance matrix obtained from Y, i km is the current injection vector of the nonlinear element;

[0031] Formula (6) is linearized successively by the Newton-Raphson method, and the expression is:

[0032]

[0033] Where J is the Jacobian matrix and k is the number of iterations; the calculation of J and -F is given by the following formula:

[0034]

[0035] The convergence condition of the Newton-Raphson iteration is given by the following formula, and the values ​​of the thresholds ∈1 and ∈2 are small enough;

[0036]

[0037] Specifically, when the external nonlinear element is a nonlinear inductor, the characteristic function is expressed as:

[0038] λ(t)=f λ (i km (t)) (11)

[0039] Among them, the magnetic flux λ(t) is the integral of the node voltage within one simulation time step. The integral is differentiated by the trapezoidal integration method and expressed as:

[0040]

[0041] According to formulas (11) and (12), we can determine i km The nonlinear equations are expressed as:

[0042]

[0043] Then formula (9) can be restated as:

[0044]

[0045] In the FPGA, the global control module implements the ordered solution of the linear solver module and the Newton-Raphson nonlinear solver module, allowing each module and unit to operate in parallel or sequentially according to the requirements of the transient algorithm. The Newton-Raphson nonlinear solver module includes the Preisach hysteresis unit, the Jacobian matrix calculation unit, and the Gauss-Jordan elimination method unit. The solution process includes the following steps:

[0046] S41: Hysteresis nonlinear modeling based on Preisach theory, with the main hysteresis loop function represented by a hyperbolic function. In the Preisach hysteresis unit, the nonlinear function of the Newton-Raphson iteration is calculated in real time using a lookup table, leveraging the parallel computing capabilities of the FPGA.

[0047] S42: After the nonlinear function calculation is completed, the Jacobian matrix and the value of the nonlinear equation are calculated by the Jacobian matrix calculation unit in the FPGA, and the result is substituted into the parallel Gauss-Jordan elimination method unit to calculate the current injection vector of the nonlinear element; if the current injection vector meets the Newton-Raphson iteration convergence condition, go to step S5; if it has not converged yet, return to the Preisach hysteresis unit in step S41 and use the current injection vector as input for the next iteration, iter=iter+1, until the iterative convergence condition is met or the maximum number of iterations is reached.

[0048] Furthermore, the hysteresis main loop function in S41 is expressed by a hyperbolic function as follows:

[0049]

[0050] Where a u 、b u 、c u is the hyperbolic template parameter, i km is the current injection vector flowing through the nonlinear inductor, λ p-m The magnetic flux density corresponding to the current in the main circuit, subscript p_m Represents the Preisach main loop; when the hysteresis main loop function is determined, from the reversal point (i re ,λ re )All small loop trajectories starting from follow this function;

[0051] The expressions for the magnetic flux density of the rising and falling branches of the small loop are as follows:

[0052] λ p_u (i km )=-λ p_m (-i km )-λ p_m (i re )+λ re +2K(-i re )K(i km )(16)

[0053] λ p_d (i km )=λ p_m (i km )+λ p_m (-i re )+λ re -2K(i re )K(-i km )(17)

[0054] Where K=[K1 K2 … K nq ], j = 1, 2, 3…, nq;

[0055]

[0056] The derivative expressions of the ascending branch and descending branch of the small loop are as follows:

[0057]

[0058]

[0059] The nonlinear function f(i km ) and its derivative df(i km ) / di km Parallel computing is achieved through a lookup table in the FPGA; in the Preisach hysteresis unit, the lookup table stores λ p_m (±i km )、K(±i km )、K(±i re ) and dλ p_m (±i km ) and other values, an address generation unit is designed to convert the 32-bit floating point number i km Converted into integers to address the lookup table; Based on formulas (16)-(19), the calculation of nonlinear functions and their derivatives is solved through the lookup table, floating-point adder unit, floating-point multiplier unit, and multiplexer; Since the calculation of formulas (16)-(19) depends on the rising branch or the falling branch, K(±i km ) Two lookup tables, through the multiplexer according to i km with -i km The first bit of the is used to select which lookup tables participate in the operation.

[0060] Furthermore, the output end of the Jacobian matrix calculation unit is connected to the input end of the Gauss-Jordan elimination method unit. Since it contains nonlinear elements, if the LU decomposition method is used, it needs to be re-factored, and the efficiency of the LU decomposition forward and back-substitution solution processes will become low. However, the Gauss-Jordan elimination method can eliminate the rows of the matrix in parallel and then decompose it, and the hardware implementation in the FPGA is simpler; if the current injection vector i obtained by the Gauss-Jordan elimination method unit is km If the Newton-Raphson iteration convergence condition is met, the final solution is obtained by using the matrix-vector multiplication unit through the multiplexer; if i km If it has not converged yet, it returns to step S41 through the multiplexer and the Preisach hysteresis unit sets i km As input for the next iteration, iter = iter + 1, until the iterative convergence condition is met or the maximum number of iterations Iter is reached max .

[0061] Furthermore, the compensation formula in S5 is:

[0062] v=v0-R Thev i km (20)

[0063] Where v is the node voltage of the nonlinear branch, R Thev is the nxnq Thevenin matrix obtained from Y.

[0064] Another object of the present invention is to provide a system for implementing the above-mentioned power transformer FPGA real-time simulation method, the system comprising:

[0065] Virtual FPGA device 101, physical system device to be tested 102, high-speed data acquisition device 201, analog-to-digital converter device 202, digital-to-analog converter device 203, amplifier device 204;

[0066] The virtual FPGA device 101 is a digital virtualized power transformer object generated in the FPGA development board. It receives historical operating data from the power transformer via the analog-to-digital converter device 202 and compares the real-time simulation results captured by the oscilloscope with the test results of the real system. Various physical quantity data can be used for visualization processing to reflect the real-time status of the power transformer.

[0067] The physical system device 102 to be tested is a physical system including a real power transformer, which is mapped to a virtual power transformer object established in the simulation environment FPGA;

[0068] The high-speed data acquisition device 201 collects the operating status data of the real power transformer in the physical system device 102 to be tested in real time through multiple sensors, and then transmits the operating data to the analog-to-digital converter device 202;

[0069] The analog-to-digital converter device 202 is used to convert the analog data collected by the high-speed data acquisition device 201 into digital data and then feed it back to the virtual FPGA device 101 in the form of digital quantity;

[0070] The digital-to-analog converter device 203 is used to convert the digital data generated in real time in the virtual FPGA device 101 into digital-to-analog data and then transmit it to the amplifier device 204 in the form of analog data;

[0071] The amplifier device 204 is used to amplify the analog low-level signal output by the digital-to-analog converter device 203 to a high-level signal that can be tested by the physical system device 102 to be tested.

[0072] In combination with the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solutions to be protected by the present invention are as follows:

[0073] First, the present invention provides a method for implementing real-time FPGA simulation of power transformers that considers hysteresis effects. This method incorporates a nonlinear simulation model based on Preisach theory and uses Newton-Raphson iteration to perform a real-time nonlinear solution. This method considers the impact of core hysteresis on the electromagnetic transients of power transformers, accurately simulating the core's hysteresis effects with high accuracy and fast computation speed, enabling accurate evaluation of electromagnetic transient characteristics of power transformers.

[0074] To address the real-time simulation of power transformers, researchers have developed a linear solver unit, a matrix-vector multiplication unit, and a fast sparse matrix-vector multiplication unit, combining the advantages of FPGA parallel architecture and deep pipeline architecture. These units are pipelined within the FPGA to achieve high computational throughput and fast simulation steps, significantly improving the real-time performance of the simulation. A compact sparse matrix storage method is also proposed, leveraging sparsity technology to improve simulation efficiency. This method leverages the advantages of high floating-point precision and fast fixed-point computation speed, conserving logic resources and reducing clock latency while ensuring solution accuracy. This approach can be used to address the poor real-time performance and numerical precision inherent in traditional models, further improving the accuracy of electromagnetic transient simulations in power systems.

[0075] The FPGA-based hardware-in-the-loop (HIL) implements a precise closed-loop simulation output. The real-time simulation results for each simulation time step are sent from the FPGA to the oscilloscope via the DAC board and verified against the offline software simulation results. This simulation method adopts a global control architecture, and the global control module implements the ordered solution of the linear solver module and the Newton-Raphson nonlinear solver module. This real-time simulation method has the capability of hardware-in-the-loop simulation testing and can realize online testing of power systems and control equipment. Combining historical data generated during operation with real-time feedback data, it can reflect the actual operating status of the system in real time and indirectly reflect the dynamic characteristics of the power transformer. It can effectively reduce R&D and testing costs and provide support for subsequent transformer optimization structural design to improve its efficiency and stability.

[0076] Second, the present invention provides a method for implementing FPGA real-time simulation of power transformers that takes into account the hysteresis effect. A linear model of the transformer is established through the admittance matrix method, and the hysteresis nonlinearity of the power transformer is modeled according to the Preisach theory. Due to the good nonlinear description ability of the hyperbolic function, the Preisach model based on the hyperbolic function can more accurately describe the rising and falling sections of the hysteresis loop, and it is more convenient to fit the secondary curve attached to the main loop through coordinate transformation. A compensation method is used, and the Newton-Raphson iterative method is used for real-time nonlinear solution. In response to the problem of real-time simulation of power transformers, the advantages of FPGA parallel architecture and pipeline architecture are combined, and sparse technology is used to improve simulation efficiency, so as to reduce hardware resource utilization and increase calculation speed, which is conducive to the realization of larger-scale electromagnetic transient simulation.

[0077] Third, as auxiliary evidence for the inventiveness of the claims of the present invention, it is also reflected in the following important aspects:

[0078] (1) The expected benefits and commercial value of the technical solution of the present invention after transformation are:

[0079] In power systems, electromagnetic transients are crucial to the safe operation of equipment and systems. Real-time simulation methods can accurately predict power transformer failures, enabling timely action to avoid equipment damage and power outages, thereby improving power system reliability and reducing operational costs. Furthermore, improved power system efficiency and reliability reduce energy waste and carbon emissions, aligning with sustainable development strategies. Based on accurate transformer models, hardware-in-the-loop simulation testing can reduce design iterations and physical prototype testing, shortening product development cycles, accelerating return on investment, and significantly reducing R&D costs. Furthermore, the application of advanced simulation technology allows companies to offer differentiated solutions in the market. This can help them attract more customers, increase market share, and boost profitability. The application of this technical solution will enhance companies' technological competitiveness and, through continuous R&D and technological innovation, establish a leading position in the industry.

[0080] (2) The technical solution of the present invention fills the technical gap in the industry at home and abroad:

[0081] Accurate transformer models are crucial for power system simulation and analysis. However, due to the complex nature of transformers, accurately describing their characteristics has always been a challenge. Traditional transformer modeling often ignores hysteresis nonlinearities and uses linear or equivalent circuit models, resulting in poor model accuracy and adaptability issues. Recent technical literature has demonstrated that the Preisach model can be improved by using hyperbolic functions, making it more flexible and accurate in describing nonlinear hysteresis phenomena, particularly under dynamic conditions. This improvement simplifies complex integral operations, reduces the difficulty of numerical solutions, requires fewer model parameters, and can integrate multiple intelligent algorithms for parameter identification. By integrating the nonlinear model established by Preisach theory with the Newton-Raphson iterative algorithm, a more accurate solution is provided for nonlinear electromagnetic transient simulation. Furthermore, the introduction of hardware-in-the-loop testing enables real-time output of simulation results and interaction with the physical system, providing a method for online testing and verification of power systems and control equipment, thereby accurately evaluating transformer operating characteristics. This is crucial for power system analysis and protection requiring rapid response. Currently, there is limited research on real-time simulation of transformer nonlinear characteristics. This invention provides an efficient, real-time simulation solution for power systems, filling a gap in the field of transformer electromagnetic transient simulation both domestically and internationally. The application of this technology will help improve the accuracy and efficiency of power system analysis, promoting stable operation and safety assurance of power systems.

[0082] Third, the present invention provides a method for implementing FPGA real-time simulation of a power transformer taking into account the hysteresis effect. Its technical characteristics and application advantages are mainly reflected in the following aspects:

[0083] First, this method significantly improves the efficiency of electromagnetic transient simulation by leveraging the parallel computing capabilities of FPGAs. The parallel nature of FPGAs allows multiple simulation steps to be executed in parallel, effectively compressing the simulation computational process and improving parallel performance. This parallel computing capability can significantly shorten simulation time and improve efficiency, particularly when simulating large-scale power systems.

[0084] Secondly, this method improves the computational accuracy of multi-rate decoupled parallel simulation of controllers by combining error compensation with an improved linear interpolation algorithm based on Lagrangian interpolation. In power systems, multi-rate decoupling calculations are necessary due to differences in the operating rates of controllers and devices such as power electronic switches. By introducing an interpolation algorithm, this method can effectively compensate for errors caused by these rate differences and improve simulation accuracy.

[0085] The proposed method also focuses on analyzing different modeling approaches for power electronic switching devices and compares simulation results using examples, validating the accuracy of the proposed method. This is of great significance for accurately simulating the behavior of power electronic devices and, consequently, accurately predicting and analyzing electromagnetic transient processes in power systems.

[0086] In industrial applications, this method has overcome existing issues such as low simulation efficiency and insufficient accuracy, achieving significant technological progress. For example, in the design and optimization of power electronics systems, this method can provide fast and accurate simulation results, helping engineers better understand and analyze system behavior, thereby optimizing system design and improving performance and stability.

[0087] The technical challenges addressed by the mathematical models and methods described in the "Characteristics" section primarily focus on the precise description and efficient calculation of electromagnetic transient processes. By constructing precise models of power electronic switching devices and employing efficient parallel computing and interpolation algorithms, this method enables precise simulation and efficient calculation of electromagnetic transient processes, thus addressing the limitations of existing simulation techniques in terms of accuracy and efficiency.

[0088] Finally, the method proposes a compensation formula in S5 to compensate for node voltages in nonlinear branches, rather than directly solving the entire nonlinear system. This reduces the computational effort and further improves the accuracy and real-time performance of the simulation. The introduction of this compensation formula enables the method to more accurately reflect the actual behavior of nonlinear components, thereby improving the reliability of the simulation results.

[0089] The FPGA real-time simulation implementation method of power transformer considering hysteresis effect is efficient and accurate, and has important application value in the simulation and analysis of power systems.

[0090] Fourth, the present invention provides a method for implementing real-time FPGA simulation of power transformers that accounts for hysteresis effects, providing an efficient and accurate solution for power system simulation, particularly when addressing the behavior of power transformers during nonlinear transient processes. The following details the existing technical problems addressed by this invention and the significant technological advancements achieved in industrial applications.

[0091] Existing technical problems solved:

[0092] 1. Slow simulation speed:

[0093] Existing simulation tools, most of which are based on general-purpose computer systems, are often slow when processing complex power system models, especially when performing high-precision electromagnetic transient analysis, due to limited computing resources. This invention implements simulation on an FPGA, leveraging its parallel processing capabilities to significantly increase simulation speed.

[0094] 2. Insufficient precision:

[0095] Traditional simulation methods often rely on simplified or approximate mathematical models to address the nonlinear behavior of power transformers (such as saturation and hysteresis), which can lead to deviations between simulation results and actual conditions. This invention improves simulation accuracy through more sophisticated mathematical models and algorithms, such as the trapezoidal integration method and Preisach theory.

[0096] 3. High resource consumption:

[0097] Complex electromagnetic transient simulations typically require extensive computing resources and storage space, which results in low resource utilization and high costs on traditional computing platforms. This invention optimizes data storage and processing, specifically by introducing compact sparse matrix storage and efficient matrix-vector operations, significantly reducing the required resources.

[0098] Significant technological advancements in industrial applications:

[0099] 1. Real-time simulation capability:

[0100] The FPGA infrastructure implemented in this paper allows for real-time electromagnetic transient simulation of power transformers, which is crucial for real-time monitoring and control of power systems. Systems that provide immediate feedback on simulation results are crucial for preventing and responding to grid failures.

[0101] 2. Enhanced system stability and reliability:

[0102] By accurately simulating the behavior of transformers under various load and fault conditions, the present invention helps system engineers better understand the potential risks and dynamic response of the system, thereby optimizing system design and improving operational safety.

[0103] 3. Cost-effectiveness:

[0104] The use of FPGAs reduces the need for high-end computing resources and offers a more cost-effective solution compared to traditional CPU- or GPU-based simulation platforms. This approach can significantly reduce the power industry's system analysis and testing expenses in the long term.

[0105] 4. Scalability and flexibility:

[0106] The FPGA implementation of this invention is not only applicable to power transformers but can also be extended to the simulation of other power equipment. In addition, the programmability of FPGAs allows the simulation algorithm to be updated according to new research results or industry standards, adapting to new technical requirements without replacing hardware.

[0107] This invention provides an innovative solution that significantly improves the simulation efficiency and accuracy of electromagnetic transient analysis of power transformers and related power equipment by combining advanced mathematical models, simulation technology and the high-performance processing capabilities of FPGAs, providing strong technical support for the design, testing and operation of power systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0108] Figure 1 A flow chart of a method for implementing FPGA real-time simulation of a power transformer taking into account hysteresis effect provided by an embodiment of the present invention;

[0109] Figure 2 A schematic diagram of a linear solution unit provided in an embodiment of the present invention;

[0110] Figure 3 A schematic diagram of a matrix-vector multiplication unit of a linear solution unit provided in an embodiment of the present invention;

[0111] Figure 4 A schematic diagram of a network of external nonlinear elements provided in an embodiment of the present invention;

[0112] Figure 5 The fast sparse matrix vector multiplication unit provided by the embodiment of the present invention solves the current i b Schematic diagram;

[0113] Figure 6 The fast sparse matrix vector multiplication unit provided by the embodiment of the present invention solves the voltage v A Schematic diagram;

[0114] Figure 7 A schematic diagram of the overall architecture provided for an embodiment of the present invention;

[0115] Figure 8 This is a schematic diagram of the structure of an FPGA-based system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0116] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0117] The present invention's method for implementing real-time FPGA simulation of power transformers taking into account hysteresis effects can be widely used in the design, testing, and real-time monitoring of power systems. The following are two specific industrial application examples:

[0118] Example 1: Power Grid Fault Analysis and Response System

[0119] Power grid systems frequently experience faults caused by various natural and human factors, such as short circuits, equipment failures, and weather conditions. Real-time electromagnetic transient analysis of power transformers in the grid can quickly locate the source and nature of faults, enabling the implementation of effective response measures.

[0120] System setup: Integrate the FPGA-based simulation system into the power control center to receive signals from various nodes of the power grid in real time.

[0121] Operation process:

[0122] Real-time monitoring: The system continuously monitors the operating status of the transformer and the power grid, and collects data such as voltage and current in real time.

[0123] Fault detection and analysis: When an abnormal signal is detected, the system immediately starts electromagnetic transient simulation to simulate the transformer's response when a fault occurs.

[0124] Rapid location and diagnosis: By comparing simulation results with actual measurement data, the system can quickly and accurately locate the source of the fault and analyze the fault type.

[0125] Response and control: Based on the analysis results, the control center can quickly take measures such as disconnecting the faulty part and reconfiguring the network to minimize the impact of the fault.

[0126] Improve the reliability and stability of the power grid: Timely response and accurate handling of power grid faults can avoid greater losses caused by fault expansion.

[0127] Reduce power outage time: Rapid fault handling significantly reduces system recovery time and improves power supply stability and reliability.

[0128] Example 2: Transformer Design Optimization and Evaluation

[0129] During the design and manufacture of new power transformers, their performance under various operating conditions needs to be evaluated in detail to ensure that they meet safety and efficiency requirements.

[0130] System Setup: Designers use an FPGA-based simulation system to simulate the electromagnetic transient behavior of a newly designed transformer.

[0131] Operation process:

[0132] Design Input: Enter transformer design parameters such as windings, core materials, geometry, etc.

[0133] Performance simulation: The system performs electromagnetic transient simulation based on the input design parameters, simulating the behavior of the transformer under various conditions such as normal operation, overload, and short circuit.

[0134] Result analysis: Analyze simulation results and evaluate transformer performance, such as efficiency, thermal stability, and electromagnetic compatibility.

[0135] Design iteration: Adjust and optimize the design based on simulation results, and iterate multiple times until the expected performance standards are achieved.

[0136] Improve design efficiency and accuracy: Through simulation evaluation, designers can foresee potential problems and optimize them before actual manufacturing, reducing trial and error costs.

[0137] Shorten product development cycle: Accelerate the design verification process, quickly iterate and optimize, and significantly shorten the time from design to market.

[0138] like Figure 1 As shown, an embodiment of the present invention provides a method for implementing FPGA real-time simulation of a power transformer considering hysteresis effect, the method comprising:

[0139] S1: Establish a linear model of the power transformer based on the admittance matrix method;

[0140] S2: Convert the transformer control equation in step S1 into a continuous-time differential equation, then discretize it using the trapezoidal integration method to obtain a Norton equivalent circuit form containing the admittance matrix and the historical current term. Since the transformer parameters such as R, L, and G are fixed, the transformer parameter matrix is ​​pre-calculated and stored in the random access memory of the FPGA. The linear solver calculates the obtained historical current term and saves the updated historical current term. The linear solver includes two matrix-vector multiplication units and a floating-point adder.

[0141] S3: Connect nonlinear elements outside the linear model to include nonlinear characteristics such as saturation and hysteresis effects; e.g. Figure 4 As shown in the figure, the n-node power system is divided into a linear part and a nonlinear part. The node analysis method is used to solve the node voltage of the linear part. Since the inverse admittance matrix is ​​sparse, a compact sparse matrix storage method is defined. The calculation of unknown node voltage is realized in the FPGA through a fast sparse matrix-vector multiplication unit.

[0142] S4: Solve the nonlinear part using the compensation method. After finding the node voltages of the linear network, solve the n-node power system with nonlinear elements. Linearize the nonlinear equations using the Newton-Raphson method and apply a first-order Taylor series expansion to the nonlinear functions to solve the nonlinear equations and thus solve the current injection vectors of the nonlinear elements. These nonlinear functions are generated using Preisach theory to simultaneously represent saturation and hysteresis effects.

[0143] S5: According to the compensation method, the current injection vector obtained in step S4 is superimposed on the linear part of the network, and then the entire network is solved to obtain the final solution;

[0144] S6: Determine whether the simulation time t reaches the set total simulation time T max , if the set total simulation time T is reached max , the simulation ends; otherwise, the simulation time advances one time step, t=t+Δt, and returns to step S2 to update the historical current term through the linear solution unit.

[0145] Furthermore, the model in S1 is a linear model, which is connected to an external circuit to include nonlinear characteristics such as saturation and hysteresis effects. Under transient conditions, the expression of the three-phase transformer control equation is:

[0146] di TE / dt=L -1 v TE -L -1 Ri TE (1)

[0147] where v TE with i TE are the instantaneous terminal voltage and current, R and L are the winding resistance and winding leakage inductance measured by the short-circuit test, respectively.

[0148] Furthermore, the Norton equivalent circuit expression is as follows:

[0149] i TE (t) = Gv TE (t)+i hist (t-Δt)

[0150] i hist (t-Δt)=αv TE (t-Δt)+βi hist (t-2Δt) (2)

[0151] Where G is the admittance matrix, α = 2(G-GRG), β = (I-2GR), α and β have no specific meaning, i hist (t-Δt) is the historical current term, and Δt is the simulation time step; Figure 2 As shown, the linear solution unit includes two matrix vector multiplication units and a floating point adder, and the floating point adder consumes 7 clock cycles; the historical current term i is obtained by differentiating the transformer differential equation using the trapezoidal integral method. hist (t-Δt) is updated at each time step, and the updated historical current term is calculated and saved in the linear solver unit; to reduce the computational complexity and delay, instead of pre-storing a single fixed parameter, α=2(G-GRG) and β=(I-2GR) are pre-stored in the FPGA random access memory RAM_α and RAM_β respectively; the node voltage v TE(t) Store to RAM_v TE , the historical current term i of the previous time step hist (t-Δt) is stored in RAM_i h In the updated historical current term i hist (t) Store to RAM_i hnew middle.

[0152] Furthermore, the pre-storage format of the transformer parameter matrix stored in the FPGA consists of two memories: a 32-bit memory val that stores matrix values ​​in row order until all parameter matrix values ​​are stored in the FPGA; a 9-bit memory, the high 8 bits col that stores the column index values ​​of the matrix in row order, and the lowest bit row that uses 0 or 1 to indicate the same row of the stored matrix; the IEEE754 standard 32-bit single-precision floating-point format is used, except that the accumulation operation in the adder uses a fixed-point number form; to ensure range and accuracy, the fixed-point number is set to 64-bit data, of which the integer part is 30 bits and the decimal part is 34 bits; as shown in FIG. Figure 3 As shown, the matrix-vector multiplication unit includes a floating-point multiplier, a floating-point to fixed-point converter, a fixed-point to floating-point converter, two fixed-point adders, a multiplexer and a row counter CNT. The multiplication of row vectors is completed in the form of a deep pipeline. The multiplexer selects the two adders by counting the row by the row counter CNT. Whenever a change in the value of the row is detected, the row counter CNT increments by 1. The two fixed-point adders have opposite reset conditions. When the fixed-point adder 1 accumulates the first matrix row vector multiplication, the fixed-point adder 2 is cleared to prepare for the accumulation of the next row vector multiplication, and the accumulation is cyclic until completion. The floating-point multiplier consumes 5 clock cycles and the fixed-point adder consumes 1 clock cycle.

[0153] Furthermore, the linear part is solved by the node analysis method, and the expression is as follows:

[0154] Yv0=i (3)

[0155] Where Y is the admittance matrix without nonlinear elements, v0 and i are the unknown node voltage and known node current, respectively. The unknown node voltage v0 can be divided into the unknown node voltage A and the known node voltage B. Formula (3) can be rewritten as:

[0156]

[0157] Further deformation, i A Obtained from the historical current term, the unknown node voltage v A The solution of is given by:

[0158]

[0159]

[0160] In the process of solving the linear equations by node analysis, due to the admittance matrix Y AB and the inverse admittance matrix For sparse matrices, pre-calculated and stored in FPGA memory RAM_Y AB and memory RAM_Y -1 AA In the node current i A Stored in memory RAM_i A In the middle, the current i b (no specific meaning) stored in memory RAM_i b In the equation, the node voltage v is known. B Stored in memory RAM_v B The compact sparse matrix storage method is the same as the matrix-vector multiplication unit, except that only non-zero elements are stored in the sparse matrix, and each non-zero element value is stored row by row through a 32-bit memory val until all non-zero elements of the matrix are stored in the memory; Figure 5 As shown, the current i is realized by the fast sparse matrix vector multiplication unit b The calculation process implemented in FPGA is as follows: the column index value of the sparse matrix is ​​stored in col in row order, the non-zero matrix value is stored in col, val stores the non-zero value of each row of the matrix in row order, and row uses 0 or 1 to represent the same row of the storage matrix, so the memory RAM_v is taken out according to the column index value stored in col B The known node voltage v corresponding to the row vector B Column vector, and then realize the current i through the matrix vector multiplication unit b The calculation includes a floating-point subtractor to implement the subtraction operation solution of formula (5); Figure 6 As shown, the inverse admittance matrix is ​​multiplied by the current i through the fast sparse matrix vector multiplication unit b To calculate the unknown node voltage v A .

[0161] Furthermore, the current injection vector solution process of the nonlinear element in step S4 is implemented by a Newton-Raphson nonlinear solution module:

[0162] f(i km )=v oc -r thev i km (7)

[0163] Where f(i km ) is a nonlinear function, v oc is the open circuit voltage without nonlinear elements (v0 subset), r thevis the Thevenin equivalent resistance matrix obtained from Y, i km is the current injection vector of the nonlinear element;

[0164] Formula (6) is linearized successively by the Newton-Raphson method, and the expression is:

[0165]

[0166] Where J is the Jacobian matrix and k is the number of iterations; the calculation of J and -F is given by the following formula:

[0167]

[0168] The convergence condition of the Newton-Raphson iteration is given by the following formula, and the values ​​of the thresholds ∈1 and ∈2 are small enough;

[0169]

[0170] Specifically, when the external nonlinear element is a nonlinear inductor, the characteristic function is expressed as:

[0171] λ(t)=f λ (i km (t)) (11)

[0172] The magnetic flux λ(t) is the integral of the node voltage within one simulation time step. The integral is differentiated using the trapezoidal integration method and expressed as:

[0173]

[0174] According to formulas (11) and (12), we can determine i km The nonlinear equations are expressed as:

[0175]

[0176] Then formula (9) can be restated as:

[0177]

[0178] like Figure 7 As shown, in the FPGA, the global control module implements the orderly solution of the linear solution module and the Newton-Raphson nonlinear solution module, so that each module and unit can operate in parallel or sequentially according to the requirements of the transient algorithm; the Newton-Raphson nonlinear solution module includes the Preisach hysteresis unit, the Jacobian matrix calculation unit and the Gauss-Jordan elimination method unit; the solution process includes the following steps:

[0179] S41: Hysteresis nonlinear modeling based on Preisach theory, with the main hysteresis loop function represented by a hyperbolic function. In the Preisach hysteresis unit, the nonlinear function of the Newton-Raphson iteration is calculated in real time using a lookup table, leveraging the parallel computing capabilities of the FPGA.

[0180] S42: After the nonlinear function calculation is completed, the Jacobian matrix and the value of the nonlinear equation are calculated by the Jacobian matrix calculation unit in the FPGA, and the result is substituted into the parallel Gauss-Jordan elimination method unit to calculate the current injection vector of the nonlinear element; if the current injection vector meets the Newton-Raphson iteration convergence condition, go to step S5; if it has not converged yet, return to the Preisach hysteresis unit in step S41 and use the current injection vector as input for the next iteration, iter=iter+1, until the iterative convergence condition is met or the maximum number of iterations is reached.

[0181] Furthermore, the hysteresis main loop function in S41 is expressed by a hyperbolic function as follows:

[0182]

[0183] Where a u 、b u 、c u is the hyperbolic template parameter, i km is the current injection vector flowing through the nonlinear inductor, λ p_m The magnetic flux density corresponding to the current in the main circuit, subscript p_m Represents the Preisach main loop; when the hysteresis main loop function is determined, from the reversal point (i re ,λ re )All small loop trajectories starting from follow this function;

[0184] The expressions for the magnetic flux density of the rising and falling branches of the small loop are as follows:

[0185] λ p_u (i km )=-λ p_m (-i km )-λ p_m (i re )+λ re +2K(-i re )K(i km ) (16)

[0186] λ p_d (i km )=λ p_m (i km )+λ p_m (-i re )+λ re -2K(ire )K(-i km ) (17)

[0187] Where K=[K1 K2 … K nq ], j = 1, 2, 3…, nq;

[0188]

[0189] The derivative expressions of the ascending branch and descending branch of the small loop are as follows:

[0190]

[0191]

[0192] The nonlinear function f(i km ) and its derivative df(i km ) / di km Parallel computing is achieved through a lookup table in the FPGA; in the Preisach hysteresis unit, the lookup table stores the λ p_m (±i km )、K(±i km )、K(±i re ) and dλ p_m (±i km ) and other values, an address generation unit is designed to convert the 32-bit floating point number i km Converted into integers to address the lookup table; Based on formulas (16)-(19), the calculation of nonlinear functions and their derivatives is solved through the lookup table, floating-point adder unit, floating-point multiplier unit, and multiplexer; Since the calculation of formulas (16)-(19) depends on the rising branch or the falling branch, K(±i km ) Two lookup tables, through the multiplexer according to i km with -i km The first bit of the is used to select which lookup tables participate in the operation.

[0193] Furthermore, the output end of the Jacobian matrix calculation unit is connected to the input end of the Gauss-Jordan elimination method unit. Since it contains nonlinear elements, if the LU decomposition method is used, it needs to be re-factored, and the efficiency of the LU decomposition forward and back-substitution solution processes will become low. However, the Gauss-Jordan elimination method can eliminate the rows of the matrix in parallel and then decompose it, and the hardware implementation in the FPGA is simpler; if the current injection vector i obtained by the Gauss-Jordan elimination method unit is km If the Newton-Raphson iteration convergence condition is met, the final solution is obtained by using the matrix-vector multiplication unit through the multiplexer; if i kmIf it has not converged yet, it returns to step S41 through the multiplexer and the Preisach hysteresis unit sets i km As input for the next iteration, iter = iter + 1, until the iterative convergence condition is met or the maximum number of iterations Iter is reached max .

[0194] Furthermore, the compensation formula in S5 is:

[0195] v=v0-R Thev i km (20)

[0196] Where v is the node voltage of the nonlinear branch, R Thev is the nxnq Thevenin matrix obtained from Y.

[0197] like Figure 8 As shown, an embodiment of the present invention provides a system for implementing the method for implementing FPGA real-time simulation of a power transformer considering hysteresis effect, the structure of which includes:

[0198] Virtual FPGA device 101, physical system device to be tested 102, high-speed data acquisition device 201, analog-to-digital converter device 202, digital-to-analog converter device 203, amplifier device 204;

[0199] The virtual FPGA device 101 is a digital virtualized power transformer object generated in the FPGA development board. It receives historical operating data from the power transformer via the analog-to-digital converter device 202 and compares the real-time simulation results captured by the oscilloscope with the test results of the real system. Various physical quantity data can be used for visualization processing to reflect the real-time status of the power transformer.

[0200] The physical system device 102 to be tested is a physical system including a real power transformer, which is mapped to a virtual power transformer object established in the simulation environment FPGA;

[0201] The high-speed data acquisition device 201 collects the operating status data of the real power transformer in the physical system device 102 to be tested in real time through multiple sensors, and then transmits the operating data to the analog-to-digital converter device 202;

[0202] The analog-to-digital converter device 202 is used to convert the analog data collected by the high-speed data acquisition device 201 into digital data and then feed it back to the virtual FPGA device 101 in the form of digital quantity;

[0203] The digital-to-analog converter device 203 is used to convert the digital data generated in real time in the virtual FPGA device 101 into digital-to-analog data and then transmit it to the amplifier device 204 in the form of analog data;

[0204] The amplifier device 204 is used to amplify the analog low-level signal output by the digital-to-analog converter device 203 to a high-level signal that can be tested by the physical system device 102 to be tested.

[0205] It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware portion can be implemented using dedicated logic; the software portion can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. Those skilled in the art will appreciate that the above-mentioned devices and methods can be implemented using computer-executable instructions and / or contained in processor control code, for example, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, or can be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware.

[0206] The present invention provides a method for implementing real-time FPGA simulation of power transformers that takes into account hysteresis effects. Existing literature indicates that traditional transformer models, such as linear models, simplify computational complexity but lack high accuracy; models based on the finite element method are slow to compute and require long simulation times; and models based on magnetic circuits, while incorporating nonlinear characteristics, are computationally intensive. Some literature attempts to simulate hysteresis loops using the first-order rotation curve method, but this method suffers from large errors for some magnetic materials and a complex identification process, impacting the model's accuracy and applicability. This method offers several advantages over traditional transformer models. This invention utilizes the Preisach theory, modified with hyperbolic functions, to establish a new, accurate transformer core hysteresis model to characterize the core's magnetization characteristics. This model has fewer parameters, is relatively simple to identify, and incorporates the Newton-Raphson iterative algorithm to solve for current in real time. This modeling approach provides the required high accuracy and efficiency, ensuring that the model's primary and secondary hysteresis loops match those of actual transformer core materials, making the transformer model more realistic. In offline electromagnetic transient tools (such as ATP and EMTP-RV), nonlinear elements are represented by piecewise linear representation or iterative methods. However, piecewise linear representation will lead to overshoot problems, and the iterative process is very time-consuming, making it difficult to meet high-precision and real-time requirements. The computing power of traditional sequential hardware (such as CPU or DSP) is limited, making it impossible for the iterative method to be completed within the required time step to meet real-time requirements. The present invention utilizes the parallel processing capabilities and pipeline architecture of FPGA, and at the same time uses sparse technology to reduce hardware resource utilization and improve computing speed. The hardware-in-the-loop method can test power systems and control equipment under extreme conditions, thereby analyzing the response of transformers under various fault conditions. It is economical, reliable and safe, and lays the foundation for the realization of large-scale FPGA-based real-time simulation of electronic transients in power systems.

[0207] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with this technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered by the scope of protection of the present invention.

Claims

1. A method for implementing FPGA real-time simulation of a power transformer considering hysteresis effect, characterized in that: The method includes: S1: Establish a linear model of the power transformer based on the admittance matrix method; S2: The transformer control equation in step S1 is converted into a continuous-time differential equation, which is then discretized using the trapezoidal integration method to obtain a Norton equivalent circuit form containing an admittance matrix and historical current terms. Since the transformer R, L, and G parameters are fixed, the transformer parameter matrix is ​​pre-calculated and stored in the FPGA's random access memory. The linear solver calculates the obtained historical current terms and saves the updated historical current terms. The linear solver includes two matrix-vector multiplication units and a floating-point adder. S3: Connect nonlinear elements outside the linear model to account for saturation and hysteresis effects. The n-node power system is divided into linear and nonlinear parts, and the node voltages in the linear part are solved using a nodal analysis method. Because the inverse admittance matrix is ​​sparse, a compact sparse matrix storage method is defined, and the calculation of unknown node voltages is implemented in the FPGA using a fast sparse matrix-vector multiplication unit. S4: Solve the nonlinear part using the compensation method. After finding the node voltages of the linear network, solve the n-node power system with nonlinear elements. Linearize the nonlinear equations using the Newton-Raphson method and apply a first-order Taylor series expansion to the nonlinear functions to solve the nonlinear equations and thus solve the current injection vectors of the nonlinear elements. These nonlinear functions are generated using Preisach theory to simultaneously represent saturation and hysteresis effects. S5: According to the compensation method, the current injection vector obtained in step S4 is superimposed on the linear part of the network, and then the entire network is solved to obtain the final solution; S6: Determine whether the simulation time t reaches the set total simulation time T max , if the set total simulation time T is reached max , the simulation ends; otherwise, the simulation time advances one time step, t=t+Δt, and returns to step S2 to update the historical current term through the linear solution unit.

2. The method for implementing FPGA real-time simulation of a power transformer considering hysteresis effect as claimed in claim 1, characterized in that: The model in S1 is a linear model. By connecting an external circuit, it includes the nonlinear characteristics of saturation and hysteresis effects. Under transient conditions, the expression of the three-phase transformer control equation is: day TE / dt=L -1 v TE -L -1 In TE (1) where v TE with i TE are the instantaneous terminal voltage and current, R and L are the winding resistance and winding leakage inductance measured by the short-circuit test, respectively.

3. The method for implementing FPGA real-time simulation of a power transformer considering hysteresis effect as claimed in claim 1, characterized in that: The Norton equivalent circuit expression is as follows: i TE (t)=Gv TE (t)+i hist (t-Δt) I hist (t-Δt)=αv TE (t-Δt)+βi hist (t-2Δt)(2) Where G is the admittance matrix, α = 2(G-GRG), β = (I-2GR), i hist (t-Δt) is the historical current term, Δt is the simulation time step; the linear solver unit includes two matrix-vector multiplication units and a floating-point adder, and the floating-point adder consumes 7 clock cycles; the historical current term i is obtained by differentiating the transformer differential equation using the trapezoidal integral method. hist (t-Δt) is updated at each time step, and the updated historical current term is calculated and saved in the linear solver unit; to reduce the computational complexity and delay, instead of pre-storing a single fixed parameter, α=2(G-GRG) and β=(I-2GR) are pre-stored in the FPGA random access memory RAM_α and RAM_β respectively; the node voltage v TE (t) Store to RAM_v TE , the historical current term i of the previous time step hist (t-Δt) is stored in RAM_i h In the updated historical current term i hist (t) Store to RAM_i hnew middle.

4. The method for implementing FPGA real-time simulation of a power transformer considering hysteresis effect as claimed in claim 1, characterized in that: The pre-storage format of the transformer parameter matrix stored in the FPGA consists of two memories: a 32-bit memory val that stores matrix values ​​in row order until all parameter matrix values ​​are stored in the FPGA; a 9-bit memory, the high 8 bits col that stores the column index values ​​of the matrix in row order, and the lowest bit row that uses 0 or 1 to represent the same row of the stored matrix; using IEEE 754 standard 32-bit single-precision floating-point format, the difference is that the accumulation operation in the adder uses fixed-point form; to ensure the range and accuracy, the fixed-point number is set to 64-bit data, of which the integer part is 30 bits and the decimal part is 34 bits; the matrix-vector multiplication unit includes a floating-point multiplier, a floating-point to fixed-point converter, a fixed-point to floating-point converter, two fixed-point adders, a multiplexer and a row counter CNT, which completes the multiplication of row vectors in the form of a deep pipeline. The multiplexer selects the two adders by counting the row by the row counter CNT. Whenever a change in the row value is detected, the row counter CNT increments by 1; the two fixed-point adders have opposite reset conditions. When fixed-point adder 1 accumulates the first matrix row vector multiplication, fixed-point adder 2 is cleared to prepare for the accumulation of the next row vector multiplication, and the accumulation cycle continues until completion; the floating-point multiplier consumes 5 clock cycles and the fixed-point adder consumes 1 clock cycle.

5. The method for implementing FPGA real-time simulation of a power transformer considering hysteresis effect as claimed in claim 1, characterized in that: The linear part is solved by the node analysis method, and the expression is as follows: Yv0=i(3) Where Y is the admittance matrix without nonlinear elements, v0 and i are the unknown node voltage and known node current, respectively. The unknown node voltage v0 can be divided into the unknown node voltage A and the known node voltage B. Formula (3) can be rewritten as: Further deformation, i A Obtained from the historical current term, the unknown node voltage v A The solution of is given by: In the process of solving the linear equations by node analysis method, due to the admittance matrix Y AB and the inverse admittance matrix For sparse matrices, pre-calculated and stored in FPGA memory RAM_Y AB and memory RAM_Y -1 In AA, the node current i A Stored in memory RAM_i A In the middle, the current i b Stored in memory RAM_i b In the equation, the node voltage v is known. B Stored in memory RAM_v B The compact sparse matrix storage method is the same as the matrix-vector multiplication unit, except that only non-zero elements are stored in the sparse matrix. Each non-zero element value is stored row by row through a 32-bit memory val until all non-zero elements of the matrix are stored in the memory. The current i is realized by the fast sparse matrix-vector multiplication unit. b The calculation process implemented in FPGA is as follows: the column index value of the sparse matrix is ​​stored in col in row order, the non-zero matrix value is stored in col, val stores the non-zero value of each row of the matrix in row order, and row uses 0 or 1 to represent the same row of the storage matrix, so the memory RAM_v is taken out according to the column index value stored in col B The known node voltage v corresponding to the row vector B Column vector, and then realize the current i through the matrix vector multiplication unit b The calculation includes a floating-point subtractor to implement the subtraction operation solution of formula (5); the inverse admittance matrix is ​​multiplied by the current i through the fast sparse matrix vector multiplication unit. b To calculate the unknown node voltage v A .

6. The method for implementing FPGA real-time simulation of a power transformer considering hysteresis effect as claimed in claim 1, characterized in that: The current injection vector solution process of the nonlinear element in step S4 is implemented by the Newton-Raphson nonlinear solution module: f(i km )=v oc -r thev i km (7) Where f(i km ) is a nonlinear function, v oc is the open circuit voltage without nonlinear elements (v0 subset), r thev is the Thevenin equivalent resistance matrix obtained from Y, i km is the current injection vector of the nonlinear element; Formula (6) is linearized successively by the Newton-Raphson method, and the expression is: Where J is the Jacobian matrix and k is the number of iterations; the calculation of J and -F is given by the following formula: The convergence condition of the Newton-Raphson iteration is given by the following formula, and the values ​​of the thresholds ∈1 and ∈2 are small enough; Specifically, when the external nonlinear element is a nonlinear inductor, the characteristic function is expressed as: λ(t)=f λ (i km (t))(11) The magnetic flux λ(t) is the integral of the node voltage within one simulation time step. The integral is differentiated using the trapezoidal integration method and expressed as: According to formulas (11) and (12), we can determine i km The nonlinear equations are expressed as: Then formula (9) can be restated as: In the FPGA, the global control module implements the ordered solution of the linear solver module and the Newton-Raphson nonlinear solver module, allowing each module and unit to operate in parallel or sequentially according to the requirements of the transient algorithm. The Newton-Raphson nonlinear solver module includes the Preisach hysteresis unit, the Jacobian matrix calculation unit, and the Gauss-Jordan elimination method unit. The solution process includes the following steps: S41: Hysteresis nonlinear modeling based on Preisach theory, with the main hysteresis loop function represented by a hyperbolic function. In the Preisach hysteresis unit, the nonlinear function of the Newton-Raphson iteration is calculated in real time using a lookup table, leveraging the parallel computing capabilities of the FPGA. S42: After the nonlinear function calculation is completed, the Jacobian matrix and the value of the nonlinear equation are calculated by the Jacobian matrix calculation unit in the FPGA, and the result is substituted into the parallel Gauss-Jordan elimination method unit to calculate the current injection vector of the nonlinear element; if the current injection vector meets the Newton-Raphson iteration convergence condition, go to step S5; if it has not converged yet, return to the Preisach hysteresis unit in step S41 and use the current injection vector as input for the next iteration, iter=iter+1, until the iterative convergence condition is met or the maximum number of iterations is reached.

7. A method for implementing FPGA real-time simulation of a power transformer considering hysteresis effect as claimed in claim 6, characterized in that: The hysteresis main loop function in S41 is expressed by a hyperbolic function as follows: Where a u 、b u 、c u is the hyperbolic template parameter, i km is the current injection vector flowing through the nonlinear inductor, λ p_m The magnetic flux density corresponding to the current in the main circuit, the subscript p_m represents the Preisach main circuit; when the hysteresis main circuit function is determined, from the reversal point (i re ,λ re )All small loop trajectories starting from follow this function; The expressions for the magnetic flux density of the rising and falling branches of the small loop are as follows: λ p_u (and km )=-λ p_m (-i km )-λ p_m (and re )+λ re +2K(-i re )K(i km )(16) λ p_d (and km )=λ p_m (and km )+λ p_m (-i re )+λ re -2K(i re )K(-i km )(17) Where K=[K1 K2…K nq ], j = 1, 2, 3…, nq; The derivative expressions of the ascending branch and descending branch of the small loop are as follows: The nonlinear function f(i km ) and its derivative df(i km ) / di km Parallel computing is achieved through a lookup table in the FPGA; in the Preisach hysteresis unit, the lookup table stores λ p_m (±i km )、K(±i km )、K(±i re ) and dλ p_m (±i km ) value, the address generation unit is designed to convert the 32-bit floating point number i km Converted into integers to address the lookup table; Based on formulas (16)-(19), the calculation of nonlinear functions and their derivatives is solved through the lookup table, floating-point adder unit, floating-point multiplier unit, and multiplexer; Since the calculation of formulas (16)-(19) depends on the rising branch or the falling branch, K(±i km ) Two lookup tables, through the multiplexer according to i km with -i km The first bit of the is used to select which lookup tables participate in the operation.

8. The method for implementing FPGA real-time simulation of a power transformer considering hysteresis effect as claimed in claim 6, characterized in that: The output end of the Jacobian matrix calculation unit is connected to the input end of the Gauss-Jordan elimination method unit. Since it contains nonlinear elements, if the LU decomposition method is used, it needs to be re-factored, and the efficiency of the LU decomposition forward and back-substitution solution processes will become low. However, the Gauss-Jordan elimination method can eliminate the rows of the matrix in parallel and then decompose it, and the hardware implementation in the FPGA is simpler; if the current injection vector i obtained by the Gauss-Jordan elimination method unit is km If the Newton-Raphson iteration convergence condition is met, the final solution is obtained by using the matrix-vector multiplication unit through the multiplexer; if i km If it has not converged yet, it returns to step S41 through the multiplexer and the Preisach hysteresis unit sets i km As input for the next iteration, iter = iter + 1, until the iterative convergence condition is met or the maximum number of iterations Iter is reached max .

9. The method for implementing FPGA real-time simulation of a power transformer considering hysteresis effect as claimed in claim 1, characterized in that: The compensation formula in S5 is: v=v0-R Thev and km (20) Where v is the node voltage of the nonlinear branch, R Thev is the nxnq Thevenin matrix obtained from Y.

10. A system for implementing the method for realizing FPGA real-time simulation of a power transformer according to any one of claims 1 to 9, characterized in that: The system includes: a virtual FPGA device, a physical system to be tested device, a high-speed data acquisition device, an analog-to-digital converter device, a digital-to-analog converter device, and an amplifier device; The virtual FPGA device is a digital virtualized power transformer object generated in the FPGA development board. The analog-to-digital converter receives historical operating data from the power transformer and compares the real-time simulation results captured by the oscilloscope with the test results of the real system. Various physical quantity data can be used for visualization processing to reflect the real-time status of the power transformer. The physical system device to be tested is a physical system including a real power transformer, which is mapped to a virtual power transformer object established in the simulation environment FPGA; The high-speed data acquisition device collects the operating status data of the real power transformer in the physical system device to be tested in real time through multiple sensors, and then transmits the operating data to the analog-to-digital converter device; The analog-to-digital converter device is used to convert the analog data collected by the high-speed data acquisition device into digital data and then feed it back to the virtual FPGA device in the form of digital quantity; The digital-to-analog converter device is used to convert the digital data generated in real time in the virtual FPGA device into digital-to-analog data and then transmit it to the amplifier device in the form of analog data; The amplifier device is used to amplify the analog low-level signal output by the digital-to-analog converter device into a high-level signal that can be tested by the physical system device to be tested.

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