A circuit processing method, device and electronic device for analyzing circuit performance

Abstract

The present application relates to a circuit processing method, electronic device and storage medium for analyzing circuit performance, the method comprising the following steps: according to the circuit connectivity relationship of the RC network to be analyzed, the RC network to be analyzed is divided into at least one sub-network, the sub-network has a preset number of ports, and the preset circuit model is a circuit model with a preset number of ports; based on the preset circuit model, at least one sub-network is compressed to obtain a compressed network corresponding to the RC network to be analyzed. The technical solution of the present application compresses the RC network to be analyzed based on the circuit connectivity relationship, reduces the complexity of the RC network to be analyzed, and improves the efficiency of analyzing circuit performance. At the same time, the compression of the RC network is achieved by compressing the sub-network based on the preset circuit model with the same number of ports as the sub-network, which can ensure the accuracy of analyzing circuit performance.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a circuit processing method, device, electronic device and storage medium for analyzing circuit performance. Background Art

[0002] With the advancement of science and technology, chip design has entered the nanoscale era. The number of transistors integrated on a single chip can reach the order of 10^12. How to achieve more powerful functions and higher efficiency in tiny chips has become an important issue in chip design. Taking circuit power consumption as an example, power consumption management is a very important consideration in the chip design process. High power consumption will not only cause the chip to heat up, affecting its performance and reliability, but also limit its available operating frequency and battery life. Therefore, circuit performance analysis and calculation are the basis of chip design optimization. Only by mastering accurate performance analysis methods can we ensure that the chip meets the design requirements.

[0003] Due to the complexity of modern integrated circuit design, accurate performance analysis models usually require a lot of computing resources and time, while the performance optimization process requires rapid feedback of performance analysis results, so performance analysis needs to find a balance between accuracy and efficiency. Therefore, it is necessary to propose an analysis scheme that can improve computing efficiency while also having high accuracy. Summary of the invention

[0004] In response to the above technical problems, the present application provides a circuit processing method, device, electronic device and storage medium for analyzing circuit performance, which can improve the efficiency of analyzing circuit performance while ensuring the accuracy of analyzing circuit performance.

[0005] In order to solve the above technical problems, the present application provides a circuit processing method for analyzing circuit performance, the method comprising the following steps:

[0006] According to the circuit connectivity relationship of the RC network to be analyzed, the RC network to be analyzed is divided into at least one sub-network, the sub-network has a preset number of ports, and the preset circuit model is a circuit model with the preset number of ports;

[0007] At least one of the sub-networks is compressed based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed.

[0008] In some embodiments, the method further comprises:

[0009] A power consumption analysis is performed on the compression network.

[0010] In some embodiments, dividing the RC network to be analyzed into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed includes:

[0011] According to the circuit connectivity relationship of the RC network to be analyzed, the parts of the RC network to be analyzed that are not connected to each other are respectively taken as a sub-network to obtain at least one sub-network.

[0012] In some embodiments, the compressing at least one of the sub-networks based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed includes:

[0013] Performing compression processing on the sub-network to be compressed based on the preset circuit model, and determining compressed first circuit information of the sub-network to be compressed;

[0014] The second circuit information of the compressed network is determined according to the compressed first circuit information of each of the sub-networks to be compressed.

[0015] In some embodiments, the compressing the sub-network to be compressed based on a preset circuit model to determine the compressed first circuit information of the sub-network to be compressed includes:

[0016] Determining the conductivity matrix and the capacitance matrix of the sub-network to be compressed;

[0017] The conductance matrix and the capacitance matrix are subjected to order reduction processing based on the preset circuit model to determine compressed first circuit information of the sub-network to be compressed.

[0018] In some embodiments, determining the conductivity matrix and the capacitance matrix of the sub-network to be compressed includes:

[0019] According to the number of ports and circuit structure information of the sub-network to be compressed, a linear time-independent system equation corresponding to the sub-network to be compressed is determined, wherein the linear time-independent system equation includes a conductance matrix and a capacitance matrix of the sub-network to be compressed.

[0020] In some embodiments, the step of reducing the order of the conductance matrix and the capacitance matrix based on the preset circuit model to determine the compressed first circuit information of the sub-network to be compressed includes:

[0021] Performing order reduction processing on the conductance matrix and the capacitance matrix based on the projection matrix;

[0022] Determine the admittance matrix function corresponding to the reduced-order conductance matrix and capacitance matrix;

[0023] Determining compressed first circuit information of the sub-network to be compressed according to the admittance matrix function;

[0024] Determining the second circuit information of the compressed network according to the compressed first circuit information of each of the sub-networks to be compressed includes:

[0025] Determine circuit structure information corresponding to the preset circuit model according to the first circuit information;

[0026] The second circuit information of the compressed network is determined according to the circuit structure information of the preset circuit model corresponding to each of the sub-networks to be compressed.

[0027] In some embodiments, before performing order reduction processing on the conductance matrix and the capacitance matrix based on the preset circuit model to determine the compressed first circuit information of the sub-network to be compressed, the method further includes:

[0028] Rearranging the elements in the conductance matrix and the capacitance matrix so that the elements describing the internal nodes of the subnetwork to be compressed in the conductance matrix and the capacitance matrix are located in a first preset area in the corresponding matrix, and the elements describing the port nodes of the subnetwork to be compressed in the conductance matrix and the capacitance matrix are located in a second preset area in the corresponding matrix;

[0029] And / or, before rearranging the elements of the conductivity matrix and the capacitance matrix, the method further comprises:

[0030] The linear time-independent system equations are transformed into the frequency domain.

[0031] In some embodiments, after converting the linear time-independent system equation to the frequency domain and rearranging the elements in the conductance matrix and the capacitance matrix, the system equation is expressed as follows:

[0032]

[0033] in, is an element that describes an internal node. is an element describing a port node, , , , is the sub-matrix that needs to be compressed, , is the sub-matrix that does not need to be compressed, , O stands for dimensional zero matrix, is the current at the input port;

[0034] The projection matrix is ​​expressed as follows:

[0035]

[0036] in, , is the identity matrix;

[0037] The conductivity matrix is ​​reduced in order based on the projection matrix to obtain a reduced-order conductivity matrix. It is expressed as follows:

[0038]

[0039] The capacitance matrix is ​​reduced in order based on the projection matrix to obtain a reduced capacitance matrix. It is expressed as follows:

[0040]

[0041] in, ;

[0042] The admittance matrix function corresponding to the reduced-order conductance matrix and capacitance matrix has the following Dimensional form:

[0043]

[0044] in, , is the reciprocal of resistance, , is the capacitance.

[0045] The present application also provides a circuit processing device for analyzing circuit performance, comprising:

[0046] A sub-network determination module, configured to divide the RC network to be analyzed into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed;

[0047] The compression module is used to compress at least one of the sub-networks based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed.

[0048] The present application also provides an electronic device, including a storage medium and a controller, characterized in that a computer program is stored on the storage medium, and when the computer program is executed by the controller, the steps of the circuit processing method for analyzing circuit performance as described above are implemented.

[0049] The present application also provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the circuit processing method for analyzing circuit performance as described above are implemented.

[0050] The circuit processing method, electronic device and storage medium for analyzing circuit performance of the present application include the following steps: according to the circuit connectivity relationship of the RC network to be analyzed, the RC network to be analyzed is divided into at least one sub-network, the sub-network has a preset number of ports, and the preset circuit model is a circuit model with a preset number of ports; based on the preset circuit model, at least one sub-network is compressed to obtain a compressed network corresponding to the RC network to be analyzed; and the compressed network is analyzed. The technical solution of the present application compresses the RC network to be analyzed based on the circuit connectivity relationship, reduces the complexity of the RC network to be analyzed, and improves the efficiency of analyzing circuit performance. At the same time, the compression of the RC network is achieved by compressing the sub-network based on the preset circuit model, which can ensure the accuracy of analyzing circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 The flowchart of a circuit processing method for analyzing circuit performance is shown according to an embodiment.

[0052] Figure 2 is a schematic diagram of an RC network to be analyzed according to an embodiment.

[0053] Figure 3 is a schematic diagram of a preset circuit model according to an embodiment.

[0054] Figure 4 is a schematic diagram of another preset circuit model according to an embodiment.

[0055] Figure 5 is a schematic diagram of a conductivity matrix according to an embodiment.

[0056] Figure 6 is a schematic diagram of a capacitor matrix according to an embodiment.

[0057] Figure 7 is a schematic diagram of a rearranged conductivity matrix according to an embodiment.

[0058] Figure 8 is a schematic diagram of a rearranged capacitor matrix according to an embodiment.

[0059] Fig. 9 is a schematic diagram of a projection matrix according to an embodiment.

[0060] Fig.10 is a schematic diagram showing comparison of analysis results according to an embodiment.

[0061] Fig.11 is a comparative schematic diagram showing another analysis result according to an embodiment.

[0062] Fig.12It is a schematic diagram of the structure of a circuit processing device for analyzing circuit performance according to an embodiment. DETAILED DESCRIPTION

[0063] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thoroughly understood.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items. In the present invention, "each" includes one and more than two quantities.

[0065] Figure 1 FIG. 1 is a flow chart of a circuit processing method for analyzing circuit performance according to an embodiment. Figure 1 As shown, the circuit processing method for analyzing circuit performance of the present application comprises the following steps:

[0066] S1, dividing the RC network to be analyzed into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed;

[0067] S2, compressing at least one sub-network based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed.

[0068] The RC network to be analyzed may be a power supply RC network under a package structure or at a PCB (Printed circuit board) level, or may be other RC networks that need to be analyzed. Figure 2 The figure shows a schematic diagram of an RC network to be analyzed, specifically a power supply RC network, including a power supply network (VDD) and a ground network (VSS), but the RC network to be analyzed is not limited thereto.

[0069] The sub-network of the RC network to be analyzed may be the RC network to be analyzed itself, that is, the entire RC network to be analyzed is equivalent to a sub-network. The sub-network of the RC network to be analyzed may also be a circuit network in the RC network to be analyzed, that is, the RC network to be analyzed is divided into more than one circuit network, and at least one of the divided circuit networks is used as a sub-network. By compressing the RC network based on a preset circuit model, the accuracy of the analysis can be guaranteed.

[0070] In some embodiments, the sub-network has a preset number of ports, and the preset number of ports can be set as needed, for example, two ports or three ports, and two ports are preferred in this embodiment. The preset circuit model is a circuit model with a preset number of ports, that is, the number of ports of the preset circuit model is the same as the number of ports of the sub-network. The selection of the preset circuit model determines the complexity of the compressed RC network and the efficiency of compression.

[0071] In some embodiments, the preset circuit model can be selected as follows: Figure 3 The double T model shown can also be selected as Figure 4 The circuit model with three ports shown is not limited to this according to the number of ports selected. Preferably, the sub-network selects a two-port network, and the preset circuit model selects a double-T model, so that the compression process can be simpler, and the compressed RC network has a suitable number of nodes, which can better balance the efficiency and accuracy of analyzing circuit performance. In some embodiments, power consumption analysis or other circuit performance analysis can be performed on the compressed network.

[0072] The preset circuit models corresponding to different sub-networks may be the same or different, so that a suitable preset circuit model can be selected according to the circuit information of the sub-network, taking into account both the efficiency and accuracy of the analysis.

[0073] According to the complexity of different sub-networks, you can choose to compress all sub-networks or some sub-networks. In this way, for sub-networks with lower complexity, there is no need to compress them, which improves the compression speed and further ensures the accuracy of analysis. When all sub-networks are compressed, all compressed sub-networks constitute a compressed network. When some sub-networks are compressed, the uncompressed sub-networks and the compressed sub-networks constitute a compressed network.

[0074] Dividing the RC network to be analyzed according to its circuit connectivity relationship can make the compression results of the sub-networks more consistent with the circuit connectivity relationship of the original network, thereby improving the accuracy of compression. In the RC network, there are multiple current paths, which can be interconnected to achieve the flow of current between different paths, or they can be disconnected, and no current flows between disconnected current paths. The circuit connectivity relationship is used to indicate whether the current paths are interconnected.

[0075] In some embodiments, the IO ports specified by the user to be reserved are obtained, and the RC network to be analyzed is divided according to the number and distribution of the ports.

[0076] In some embodiments, the RC network to be analyzed is divided into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed, including:

[0077] According to the circuit connectivity relationship of the RC network to be analyzed, the parts of the RC network to be analyzed that are not connected to each other are respectively taken as a sub-network to obtain at least one sub-network.

[0078] Among them, the io port is reserved according to the circuit connectivity relationship of the RC network to be analyzed, and each sub-network should have a corresponding io port. Figure 2 Taking the RC network shown in the figure as an example, after the circuit is divided, VDD and VSS are respectively regarded as a sub-network, and both are two-port networks. The part without connectivity means that there is no current flow between the two parts of the network. By treating the parts of the RC network to be analyzed that have no connectivity with each other as sub-networks, the compression processes of different sub-networks can be decoupled from each other, simplifying the compression process.

[0079] In some embodiments, compressing at least one sub-network based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed includes:

[0080] Compressing the sub-network to be compressed based on a preset circuit model, and determining compressed first circuit information of the sub-network to be compressed;

[0081] The second circuit information of the compressed network is determined according to the compressed first circuit information of each sub-network.

[0082] The sub-networks to be compressed are compressed respectively to obtain the compressed first circuit information of the sub-networks to be compressed. The first circuit information refers to the mathematical information generated during the compression process for describing the corresponding circuit, such as matrix, resistance, capacitance, conductance and other data. The second circuit information refers to the circuit structure information, which includes resistance, capacitance and their connection relationship, that is, the second circuit information is the information obtained by processing the mathematical information generated during the compression process, which can represent the resistance, capacitance and their connection relationship of the compressed circuit.

[0083] When all sub-networks are compressed, the second circuit information of the compressed network is determined based on the first circuit information of all compressed sub-networks. When some sub-networks are compressed, the circuit structure information of the uncompressed sub-network and the first circuit information of the compressed sub-network are used to determine the second circuit information of the compressed network. A netlist file for describing the compressed network can be obtained based on the second circuit information of the compressed network. Based on step S3, the netlist file corresponding to the compressed network can be used to perform the required analysis, thereby realizing the analysis of the RC network to be analyzed.

[0084] In some embodiments, compressing the sub-network to be compressed based on a preset circuit model to determine compressed first circuit information of the sub-network to be compressed includes:

[0085] S21, determining the conductivity matrix and capacitance matrix of the sub-network to be compressed;

[0086] S22, performing order reduction processing on the conductance matrix and the capacitance matrix based on a preset circuit model to determine compressed first circuit information of the sub-network to be compressed.

[0087] Among them, by reducing the order of the conductance matrix and the capacitance matrix, the number of nodes of the sub-network to be compressed can be reduced to the number of nodes corresponding to the preset circuit model, thereby reducing the number of nodes of the RC network to be analyzed and reducing the complexity of the circuit, so that the analysis can be completed in a shorter time, improving the efficiency of the analysis.

[0088] In some embodiments, the conductivity matrix is ​​a symmetric non-negative definite matrix, and the capacitance matrix is ​​a diagonal matrix composed of capacitances to ground.

[0089] In some embodiments, S21, determining the conductivity matrix and capacitance matrix of the sub-network to be compressed includes:

[0090] According to the number of ports and circuit structure information of the sub-network to be compressed, a linear time-independent system equation corresponding to the sub-network to be compressed is determined, wherein the linear time-independent system equation includes a conductance matrix and a capacitance matrix of the sub-network to be compressed.

[0091] Among them, according to the circuit structure information, the following linear time-invariant system equation (Linear Time-invariant, LTI) is generated for each sub-network to be compressed:

[0092]

[0093] in, is the conductivity matrix, a symmetric non-negative definite matrix, represents the node voltage, is a diagonal matrix of ground capacitance (i.e., capacitance matrix), is the current at the input port, is the association matrix of the input port current and nodes, p is the number of ports, in the equation of the two-port network p=2, n is equal to the number of nodes, and t represents time.

[0094] In some embodiments, the linear time-independent system equations can be transformed into the frequency domain and expressed as follows:

[0095]

[0096] Where s represents the independent variable in the frequency domain. After conversion to the frequency domain, the equation is expressed more simply, which can further simplify the calculation process. When converted to the frequency domain, the conductance matrix and the capacitance matrix remain unchanged.

[0097] In some embodiments, S22, performing order reduction processing on the conductance matrix and the capacitance matrix based on a preset circuit model to determine compressed first circuit information of the sub-network to be compressed includes:

[0098] The conductance matrix and the capacitance matrix are reduced in order according to the projection matrix;

[0099] Determine the admittance matrix function corresponding to the reduced-order conductance matrix and capacitance matrix;

[0100] The compressed first circuit information of the sub-network to be compressed is determined according to the admittance matrix function.

[0101] In some embodiments, determining the second circuit information of the compressed network according to the compressed first circuit information of each sub-network to be compressed includes:

[0102] Determine circuit structure information corresponding to a preset circuit model according to the first circuit information;

[0103] The second circuit information of the compressed network is determined according to the circuit structure information of the preset circuit model corresponding to each sub-network to be compressed.

[0104] Among them, the projection matrix is ​​used to reduce the order of the conductance matrix and the capacitance matrix. Therefore, after reducing the order of the conductance matrix and the capacitance matrix, the admittance matrix function The order is also reduced, and then the information in the reduced-order admittance matrix function can be extracted as the first circuit information. In this embodiment, the information in the reduced-order admittance matrix function used as the first circuit information includes conductance value and capacitance value.

[0105] According to the information of the admittance matrix function, the circuit structure information corresponding to the preset circuit model can be determined. The circuit structure information corresponding to the preset circuit model is equivalent to the compressed circuit structure information of the sub-network to be compressed.

[0106] In some embodiments, to further reduce the complexity of calculation, S22 performs order reduction processing on the conductance matrix and the capacitance matrix based on a preset circuit model, and before determining the compressed first circuit information of the sub-network to be compressed, the method further includes:

[0107] The elements in the conductance matrix and the capacitance matrix are rearranged so that the elements describing the internal nodes of the sub-network to be compressed in the conductance matrix and the capacitance matrix are located in a first preset area in the corresponding matrix, and the elements describing the port nodes of the sub-network to be compressed in the conductance matrix and the capacitance matrix are located in a second preset area in the corresponding matrix.

[0108] After rearranging the conductivity matrix and capacitance matrix, the system equation expression is as follows:

[0109]

[0110] in, is an internal node, is a port node, , , , is the sub-matrix that needs to be compressed, , is the sub-matrix that does not need to be compressed, , O stands for dimensional zero matrix.

[0111] When rearranging the conductance matrix and the capacitance matrix, the elements describing the port nodes are found according to the port numbers and rearranged, and the positions of the remaining elements in the matrix are adjusted accordingly, so that the elements describing the port nodes and the elements describing the internal nodes are respectively concentrated in the corresponding areas of the matrix, for example, the elements describing the port nodes are adjusted to the corner positions of the matrix, and the elements describing the internal nodes are adjusted to other areas outside the corner positions.

[0112] After rearranging the conductance matrix and the capacitance matrix, the expression of the projection matrix and the process of reducing the conductance matrix and the capacitance matrix can be simplified. It can be understood that based on the technical concept of the present application, even if the conductance matrix and the capacitance matrix are not rearranged, the calculation complexity will only be increased to a certain extent relative to the rearrangement process, but as long as a suitable projection matrix is ​​constructed, the conductance matrix and the capacitance matrix can also be reduced in order, which will not be repeated here.

[0113] In some embodiments, after rearranging the conductivity matrix and the capacitance matrix, the constructed projection matrix V can be expressed as follows:

[0114]

[0115] in, , is the unit matrix. Apply the projection matrix V to both ends of the rearranged conductivity matrix and capacitance matrix to obtain the reduced-order conductivity matrix and capacitor matrix :

[0116]

[0117] remember ,but:

[0118]

[0119] After that, the reduced-order admittance matrix function can be obtained, which has the following Dimensional form:

[0120]

[0121] in, , is the reciprocal of resistance, , is the capacitance.

[0122] Afterwards, the circuit structure information corresponding to the preset circuit model is calculated according to the information of the admittance matrix function, that is, the compressed circuit structure information of the sub-network to be compressed is obtained. Specifically, the above-mentioned reduced-order circuit equation (matrix) is "restored", that is, circuit synthesis is performed to obtain the circuit structure information of the small-scale RC circuit, and the small-scale RC circuit is the compressed sub-network.

[0123] by Figure 2 The double-T model with five unknown elements (three resistors and two capacitors) is shown as an example of a reduced-order circuit with the same properties as the original circuit, where R1>0, Rm>0, R2>0, C1>0, C2>0 are required. Using the admittance function data can be satisfied Figure 2 Circuit information for the circuit model shown:

[0124]

[0125]

[0126]

[0127]

[0128]

[0129] in,

[0130]

[0131]

[0132]

[0133]

[0134] Where k can take any value that satisfies the following conditions:

[0135]

[0136] Usually, you can take .

[0137] At this point, the first circuit information of one of the sub-networks to be compressed is obtained, and the series of sub-networks obtained by division are processed according to the above steps, and finally a series of compressed circuit models are obtained, and then they are combined into a new compressed network, and the netlist file corresponding to the compressed network can be used to perform the required analysis.

[0138] Next, taking the RC network to be analyzed as a power supply network as an example, the calculation process of the circuit processing method for analyzing circuit performance of the present application is illustrated.

[0139] First, extract the RC Spice model of the power supply network and the ground network as follows:

[0140] .subckt VDD_0_arc 1 25

[0141] R1 6 1 1.7094193

[0142] R2 2 3 6.5406294

[0143] R3 4 5 6.5406294

[0144] R4 6 7 1.7094193

[0145] <h2 style=";text-align:left;direction:ltr">R5 8 9 1.0920632<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0146] <h2 style=";text-align:left;direction:ltr"> R6 10 11 1.0920632<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0147] <h2 style=";text-align:left;direction:ltr"> R7 12 13 1.0920632<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0148] <h2 style=";text-align:left;direction:ltr"> R8 14 15 1.0920632<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0149] <h2 style=";text-align:left;direction:ltr"> R9 16 17 1.0920632<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0150] <h2 style=";text-align:left;direction:ltr"> R10 18 19 1.0899954<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0151] <h2 style=";text-align:left;direction:ltr"> R11 20 21 1.0899954<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0152] <h2 style=";text-align:left;direction:ltr"> R12 22 23 1.0899954<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0153] <h2 style=";text-align:left;direction:ltr"> R13 24 25 0.2930939<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0154] <h2 style=";text-align:left;direction:ltr"> R14 2 7 1.0899954<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0155] <h2 style=";text-align:left;direction:ltr"> R15 3 8 1.0899954<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0156] <h2 style=";text-align:left;direction:ltr"> R16 9 4 1.0899954<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0157] <h2 style=";text-align:left;direction:ltr"> R17 5 10 0.2930939<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0158] <h2 style=";text-align:left;direction:ltr"> R18 12 11 0.2930939<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0159] <h2 style=";text-align:left;direction:ltr"> R19 14 13 0.2930939<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0160] <h2 style=";text-align:left;direction:ltr"> R20 16 15 0.2930939<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0161] <h2 style=";text-align:left;direction:ltr"> R21 18 17 0.2930939<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0162] <h2 style=";text-align:left;direction:ltr"> R22 19 20 0.2930939<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0163] <h2 style=";text-align:left;direction:ltr"> R23 21 22 1.4245161<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0164] <h2 style=";text-align:left;direction:ltr"> R24 23 24 0.09495385<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0165] <h2 style=";text-align:left;direction:ltr"> C1 1 02.388319e-14<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0166] <h2 style=";text-align:left;direction:ltr"> C2 3 0 1.1778861e-14<h2 style=";text-align:left;direction:ltr"> <h2 style=";text-align:left;direction:ltr">

[0167] <h2 style=";text-align:left;direction:ltr"> C3 6 0 4.599731e-15

[0168] C4 9 0 5.2077555e-15

[0169] C5 10 0 1.2396841e-14

[0170] C6 12 0 5.4866686e-15

[0171] C7 18 0 2.0988753e-13

[0172] C8 21 0 2.0741826e-13

[0173] C9 25 0 2.0741826e-13

[0174] .ends

[0175] Among them, taking R1 6 1 1.7094193 as an example, R1 is the name of the resistor, 6 and 1 are the node numbers corresponding to R1, and 1.7094193 is the resistance value (unit: ohm). Taking C1 1 02.388319e-14 as an example, C1 is the name of the resistor, 1 and 0 are the node numbers corresponding to C1, 0 represents ground, and 2.388319e-14 is the capacitance value (unit: farad).

[0176] Next, select the io ports to be retained: 1, 25. It can be seen that the network has only one two-port network, so there is no need to divide the network, and directly generate the conductance matrix and capacitance matrix based on the netlist information. Among them, the conductance matrix is ​​as follows Figure 5 As shown, the capacitance matrix is Figure 6 shown.

[0177] After that, the conductivity matrix and capacitance matrix are rearranged according to the port numbers. The rearrangement result of the conductivity matrix is ​​as follows: Figure 7 As shown, the rearrangement of the capacitance matrix is ​​as follows Figure 8 According to the division results, we can get , , ,Right now is the submatrix consisting of rows 1 to 23 and columns 1 to 23 of G, is the submatrix consisting of rows 1 to 23 and columns 24 to 25 of G, is the submatrix consisting of rows 24 to 25 and columns 1 to 23 of G, The submatrix consisting of rows 24 to 25 and columns 24 to 25 of G can be obtained similarly; , , , .

[0178] Next, the order reduction process is performed and the constructed projection matrix is ​​as follows Fig. 9 As shown. The reduced-order admittance matrix function can be calculated, where the conductance value and the capacitance value are the first circuit information:

[0179]

[0180] like Figure 2 The double-T model shown in the figure can calculate the compressed circuit structure information based on the information of the reduced-order admittance function matrix as follows:

[0181] R1 = 13.50991857;

[0182] Rm = 17.18914469;

[0183] R2 = 1.37244980;

[0184] C1 = 1.29439360e-13;

[0185] C2 = 5.58637737e-13.

[0186] Finally, taking power consumption analysis as an example, the compressed circuit is simulated, and the simulation results are as follows: Fig.10 and Fig.11 As shown, Fig.10 The two curves in the figure coincide, indicating that the simulation results are correct. Fig.11 The maximum error of the two curves is 0.019%, and the simulation results are within an acceptable range.

[0187] like Fig.12 As shown, the present application also provides a circuit processing device for analyzing circuit performance, comprising:

[0188] A sub-network determination module 11, configured to divide the RC network to be analyzed into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed, wherein the sub-network has a preset number of ports, and the preset circuit model is a circuit model having a preset number of ports;

[0189] The compression module 12 is used to compress at least one sub-network based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed.

[0190] In some embodiments, the apparatus further comprises an analysis module for performing power consumption analysis on the compression network.

[0191] In some embodiments, when the RC network to be analyzed is divided into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed, the sub-network determination module 11 is used to:

[0192] According to the circuit connectivity relationship of the RC network to be analyzed, the parts of the RC network to be analyzed that are not connected to each other are respectively taken as a sub-network to obtain at least one sub-network.

[0193] In some embodiments, the compression module 12 is used to:

[0194] Compressing the sub-network to be compressed based on a preset circuit model, and determining compressed first circuit information of the sub-network to be compressed;

[0195] The second circuit information of the compressed network is determined according to the compressed first circuit information of each sub-network to be compressed.

[0196] In some embodiments, when compressing the sub-network to be compressed based on the preset circuit model and determining the compressed first circuit information of the sub-network to be compressed, the compression module 12 is used to:

[0197] Determining the conductance matrix and the capacitance matrix of the subnetwork to be compressed;

[0198] The conductance matrix and the capacitance matrix are reduced in order based on a preset circuit model to determine compressed first circuit information of the sub-network to be compressed.

[0199] In some embodiments, when determining the conductance matrix and the capacitance matrix of the sub-network to be compressed, the compression module 12 is used to:

[0200] According to the number of ports and circuit structure information of the sub-network to be compressed, a linear time-independent system equation corresponding to the sub-network to be compressed is determined, wherein the linear time-independent system equation includes a conductance matrix and a capacitance matrix of the sub-network to be compressed.

[0201] In some embodiments, when performing order reduction processing on the conductance matrix and the capacitance matrix based on a preset circuit model to determine the compressed first circuit information of the sub-network to be compressed, the compression module 12 is used to:

[0202] The conductance matrix and the capacitance matrix are reduced in order according to the projection matrix;

[0203] Determine the admittance matrix function corresponding to the reduced-order conductance matrix and capacitance matrix;

[0204] The compressed first circuit information of the sub-network to be compressed is determined according to the admittance matrix function.

[0205] In some embodiments, the compression module 12 determines the second circuit information of the compressed network according to the compressed first circuit information of each sub-network to be compressed, and is used to:

[0206] Determine circuit structure information corresponding to a preset circuit model according to the first circuit information;

[0207] The second circuit information of the compressed network is determined according to the circuit structure information of the preset circuit model corresponding to each sub-network to be compressed.

[0208] In some embodiments, the apparatus further includes a rearrangement module, which is used to reduce the order of the conductance matrix and the capacitance matrix based on a preset circuit model to determine the compressed first circuit information of the sub-network to be compressed before:

[0209] Rearranging the elements in the conductance matrix and the capacitance matrix so that the elements describing the internal nodes of the subnetwork to be compressed in the conductance matrix and the capacitance matrix are located in a first preset area in the corresponding matrix, and the elements describing the port nodes of the subnetwork to be compressed in the conductance matrix and the capacitance matrix are located in a second preset area in the corresponding matrix;

[0210] And / or, the device further comprises a conversion module, which is used for: before rearranging the conductivity matrix and the capacitance matrix:

[0211] Transform the linear time-independent system equations into the frequency domain.

[0212] In some embodiments, after converting the linear time-independent system equation to the frequency domain and rearranging the elements in the conductance matrix and the capacitance matrix, the system equation is expressed as follows:

[0213]

[0214] in, is an element that describes an internal node. is an element describing a port node, , , , is the sub-matrix that needs to be compressed, , is the sub-matrix that does not need to be compressed, , O represents dimensional zero matrix, is the current at the input port;

[0215] The projection matrix is ​​expressed as follows:

[0216]

[0217] in, , is the identity matrix;

[0218] The conductivity matrix is ​​reduced in order based on the projection matrix to obtain a reduced-order conductivity matrix. It is expressed as follows:

[0219]

[0220] The capacitance matrix is ​​reduced in order based on the projection matrix to obtain a reduced capacitance matrix. It is expressed as follows:

[0221]

[0222] in, ;

[0223] The admittance matrix function corresponding to the reduced-order conductance matrix and capacitance matrix has the following Dimensional form:

[0224]

[0225] in, , is the reciprocal of resistance, , is the capacitance.

[0226] For the specific implementation process of the steps executed by each module in the circuit processing device for analyzing circuit performance, please refer to the description of the method embodiment, which will not be repeated here.

[0227] The present application also provides an electronic device, including a storage medium and a controller, wherein the storage medium stores a computer program, and when the computer program is executed by the controller, the steps of the circuit processing method for analyzing circuit performance as described in the above embodiment are implemented.

[0228] The present application also provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the circuit processing method for analyzing circuit performance as described in the above embodiment are implemented.

[0229] The circuit processing method, electronic device and storage medium for analyzing circuit performance of the present application include the following steps: dividing the RC network to be analyzed into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed; compressing at least one sub-network based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed, wherein the sub-network has a preset number of ports, and the preset circuit model is a circuit model with a preset number of ports. The technical solution of the present application compresses the RC network to be analyzed based on the circuit connectivity relationship, reduces the complexity of the RC network to be analyzed, and improves the efficiency of analyzing circuit performance. At the same time, by compressing the sub-network based on the preset circuit model, the RC network is compressed, which can ensure the accuracy of analyzing circuit performance.

[0230] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A circuit processing method for analyzing circuit performance, characterized in that: The method comprises the following steps: According to the circuit connectivity relationship of the RC network to be analyzed, the RC network to be analyzed is divided into at least one sub-network, wherein the sub-network has a preset number of ports; Compressing at least one of the sub-networks based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed includes: Compressing the sub-network to be compressed based on the preset circuit model, and determining the compressed first circuit information of the sub-network to be compressed, wherein the preset circuit model is a circuit model with the preset number of ports, and the first circuit information refers to mathematical information generated during the compression process for describing the circuit, including capacitance and conductance; Determine circuit structure information corresponding to the preset circuit model according to the first circuit information; According to the circuit structure information of the preset circuit model corresponding to each of the sub-networks to be compressed, the second circuit information of the compressed network is determined, where the second circuit information is the circuit structure information.

2. The method according to claim 1, characterized in that The method further comprises: A power consumption analysis is performed on the compression network.

3. The method according to claim 1, characterized in that The step of dividing the RC network to be analyzed into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed includes: According to the circuit connectivity relationship of the RC network to be analyzed, the parts of the RC network to be analyzed that are not connected to each other are respectively taken as a sub-network to obtain at least one sub-network.

4. The method according to claim 1, characterized in that The compressing the sub-network to be compressed based on the preset circuit model to determine the compressed first circuit information of the sub-network to be compressed includes: Determining the conductivity matrix and the capacitance matrix of the sub-network to be compressed; The conductance matrix and the capacitance matrix are subjected to order reduction processing based on the preset circuit model to determine compressed first circuit information of the sub-network to be compressed.

5. The method according to claim 4, characterized in that The determining of the conductivity matrix and the capacitance matrix of the sub-network to be compressed comprises: According to the number of ports and circuit structure information of the sub-network to be compressed, a linear time-independent system equation corresponding to the sub-network to be compressed is determined, wherein the linear time-independent system equation includes a conductance matrix and a capacitance matrix of the sub-network to be compressed.

6. The method according to claim 5, characterized in that Before performing order reduction processing on the conductance matrix and the capacitance matrix based on the preset circuit model to determine the compressed first circuit information of the sub-network to be compressed, the method further includes: Rearranging the elements in the conductance matrix and the capacitance matrix so that the elements describing the internal nodes of the subnetwork to be compressed in the conductance matrix and the capacitance matrix are located in a first preset area in the corresponding matrix, and the elements describing the port nodes of the subnetwork to be compressed in the conductance matrix and the capacitance matrix are located in a second preset area in the corresponding matrix; And / or, before rearranging the elements of the conductivity matrix and the capacitance matrix, the method further comprises: The linear time-independent system equations are transformed into the frequency domain.

7. The method according to claim 5, characterized in that The step of performing order reduction processing on the conductance matrix and the capacitance matrix based on the preset circuit model to determine the compressed first circuit information of the sub-network to be compressed includes: Performing order reduction processing on the conductance matrix and the capacitance matrix based on the projection matrix; Determine the admittance matrix function corresponding to the reduced-order conductance matrix and capacitance matrix; The compressed first circuit information of the sub-network to be compressed is determined according to the admittance matrix function.

8. The method according to claim 7, characterized in that Before performing order reduction processing on the conductance matrix and the capacitance matrix based on the preset circuit model to determine the compressed first circuit information of the sub-network to be compressed, the method further includes: Rearranging the elements in the conductance matrix and the capacitance matrix so that the elements describing the internal nodes of the subnetwork to be compressed in the conductance matrix and the capacitance matrix are located in a first preset area in the corresponding matrix, and the elements describing the port nodes of the subnetwork to be compressed in the conductance matrix and the capacitance matrix are located in a second preset area in the corresponding matrix; And / or, before rearranging the elements of the conductivity matrix and the capacitance matrix, the method further comprises: The linear time-independent system equations are transformed into the frequency domain.

9. The method according to claim 8, characterized in that After converting the linear time-independent system equation to the frequency domain and rearranging the elements in the conductance matrix and the capacitance matrix, the system equation expression is as follows: ， in, is an element that describes an internal node. is an element describing a port node, , , , , , , , , , , is the sub-matrix that needs to be compressed, , is the sub-matrix that does not need to be compressed, , O represents dimensional zero matrix, is the current at the input port; The projection matrix is ​​expressed as follows: ， in, , is the identity matrix; The conductivity matrix is ​​reduced in order based on the projection matrix to obtain a reduced-order conductivity matrix. It is expressed as follows: ， The capacitance matrix is ​​reduced in order based on the projection matrix to obtain a reduced capacitance matrix. , which is expressed as follows: ， in, ; The admittance matrix function corresponding to the reduced-order conductance matrix and capacitance matrix has the following Dimensional form: ， in, , is the reciprocal of resistance, , is the capacitance.

10. A circuit processing device for analyzing circuit performance, characterized in that: include: A sub-network determination module, used to divide the RC network to be analyzed into at least one sub-network according to the circuit connectivity relationship of the RC network to be analyzed, wherein the sub-network has a preset number of ports; A compression module, used for compressing at least one of the sub-networks based on a preset circuit model to obtain a compressed network corresponding to the RC network to be analyzed, comprising: Compressing the sub-network to be compressed based on the preset circuit model, and determining the compressed first circuit information of the sub-network to be compressed, wherein the preset circuit model is a circuit model with the preset number of ports, and the first circuit information refers to mathematical information generated during the compression process for describing the circuit, including capacitance and conductance; Determine circuit structure information corresponding to the preset circuit model according to the first circuit information; According to the circuit structure information of the preset circuit model corresponding to each of the sub-networks to be compressed, the second circuit information of the compressed network is determined, where the second circuit information is the circuit structure information.

11. An electronic device, comprising a storage medium and a controller, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the controller, the steps of the circuit processing method for analyzing circuit performance according to any one of claims 1 to 9 are implemented.

12. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the circuit processing method for analyzing circuit performance according to any one of claims 1 to 9 are implemented.

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